Display device

Abstract

To provide a display device with reduced variations in luminance among pixels.SOLUTION: The display device includes a transistor, first to fourth switches, first and second capacitors, a light-emitting element, and first to fifth wirings. The transistor comprises a first gate and a second gate. A first terminal of the transistor is connected to the third wiring. The first switch controls a conduction state between the first wiring and the first gate, the second switch controls a conduction state between the second wiring and the second gate, the third switch controls a conduction state between the first gate and a second terminal of the transistor, and the fourth switch controls a conduction state between the fifth wiring and the second terminal of the transistor. The first capacitor retains a potential difference between the first gate and the second terminal of the transistor, and the second capacitor retains a potential difference between the first gate and the second gate. The first terminal of the light-emitting element is connected to the second terminal of the transistor, and the second terminal of the light-emitting element is connected to the fourth wiring.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manu facture, or a composition (composition of matter). Further, one aspect of the present invention relates to a semiconductor device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device, a display device including an oxide semiconductor, or a light-emitting device.

[0003] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A display device, an electro-optical device, a semiconductor circuit, and an electronic device may have a semiconductor device.

Background Art

[0004] Although the configurations of active matrix type display devices using light-emitting elements specifically proposed vary depending on the manufacturer, usually, at least a light-emitting element, a transistor (switching transistor) that controls the input of a video signal to a pixel, and a transistor (driving transistor) that controls the current value supplied to the light-emitting element are provided in each pixel. By making all the transistors provided in the pixel have the same polarity, in the manufacturing process of the transistor, steps such as adding an impurity element that imparts a single conductivity to the semiconductor film can be partially

[0005] omitted. Patent Document 1 below describes a light-emitting element type display in which pixels are configured only with n-channel type transistors. ​​​​​​​​

[0006] An active matrix type display device using a light emitting element controls the current value supplied to the light emitting element according to an image signal, and the variation in the threshold voltage of a transistor (driving transistor) is likely to be reflected in the luminance of the light emitting element. A circuit configuration for preventing the influence of the variation in the threshold voltage on the luminance of the light emitting element is described in Patent Document 2 below. The variation in the threshold voltage of the transistor (driving transistor) that controls the current value supplied to the light emitting element according to the image signal is likely to be reflected in the luminance of the light emitting element. A circuit configuration for preventing the influence of the variation in the threshold voltage on the luminance of the light emitting element is described in Patent Document 2 below.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] Pixels that can correct the threshold voltage of the driving transistor have a large number of transistors in their configuration. Therefore, it is difficult to achieve high definition, and in the case of a bottom emission structure (a structure in which light is extracted through a substrate provided with transistors), the light of the light emitting element is blocked by the transistors, resulting in a small aperture ratio. In the case of a bottom emission structure (a structure in which light is extracted through a substrate provided with transistors), the light of the light emitting element is blocked by the transistors, resulting in a small aperture ratio.

[0009] Based on the above technical background, one aspect of the present invention aims to provide a display device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed. Another aspect of the present invention aims to provide a high-definition display device. Another aspect of the present invention aims to provide a display device with a high aperture ratio.

[0010] ​​​​​​Another aspect of the present invention is to provide a novel display device or a novel semiconductor device. One of the problems is to provide such.

[0011] Note that the description of a plurality of problems does not prevent the existence of each other's problems. One aspect of the present invention does not necessarily have to solve all of these problems. Also, problems other than those listed will naturally become apparent from the descriptions in the specification, drawings, claims, etc., and these problems can also be problems of one aspect of the present invention.

Means for Solving the Problems

[0012] One aspect of the present invention is a display device having a transistor, first and second capacitor elements, and a light-emitting element. The transistor has a first gate and a second gate. The first gate and the second gate of the transistor preferably have an overlapping region with each other with the channel formation region of the transistor interposed therebetween. The first terminal of the transistor is supplied with a first potential. The first terminal of the first capacitor element is electrically connected to the first gate. The second terminal of the first capacitor element is electrically connected to the second terminal of the transistor. The first terminal of the second capacitor element is electrically connected to the first gate. The second terminal of the second capacitor element is electrically connected to the second gate. The first terminal of the light-emitting element is electrically connected to the second terminal of the transistor. The second terminal of the light-emitting element is supplied with a second potential.

[0013] In the above aspect, the transistor is preferably an n-channel type.

[0014] In the above aspect, it is preferable that the first potential is higher than the second potential.

[0015] In the above aspect, the channel formation region preferably has an oxide semiconductor.

[0016] One embodiment of the present invention is a semiconductor device including a transistor, first to fourth switches, and first and second capacitors. The display device has a first gate electrode, a second gate electrode, a light emitting element, and first to fifth wirings. and a second gate. The first gate and the second gate are disposed in a channel forming region of the transistor. The first terminal of the transistor is preferably a first terminal having a first region therebetween. , and the third wiring. The first switch is in a conductive state between the first wiring and the first gate. The second switch has a function of controlling the conduction state between the second wiring and the second gate. The third switch controls the conduction state between the first gate and the second terminal of the transistor. The fourth switch has a function of controlling the conduction state between the fifth wiring and the second terminal of the transistor. The first terminal of the first capacitance element is electrically connected to the first gate. The second terminal of the first capacitance element is electrically connected to the second terminal of the transistor. A first terminal of the capacitive element is electrically connected to the first gate. A second terminal of the second capacitive element is electrically connected to the first gate. The first terminal of the light emitting element is electrically connected to the second terminal of the transistor. The second terminal of the light emitting element is electrically connected to the fourth wire.

[0017] In the above embodiment, the transistor is preferably an n-channel type.

[0018] In the above embodiment, the channel formation region preferably contains an oxide semiconductor.

[0019] In the above embodiment, the first to fourth switches each have an oxide semiconductor layer in a channel forming region. It is preferable that the transistor has a conductor.

[0020] One aspect of the present invention is a display device including a transistor, first to third switches, first and second capacitive elements, , a light-emitting element, and first to fifth wirings. The transistor has a first gate and a second gate. It is preferable that the first gate and the second gate have an overlapping region with each other with a channel formation region of the transistor interposed therebetween. A first terminal of the transistor is electrically connected to the third wiring. The first switch has a function of controlling a conduction state between the first wiring and the first gate. The second switch has a function of controlling a conduction state between the second wiring and the second gate . The third switch has a function of controlling a conduction state between the fifth wiring and a second terminal of the transistor . A first terminal of the first capacitive element is electrically connected to the first gate . A second terminal of the first capacitive element is electrically connected to the second terminal of the transistor. A first terminal of the second capacitive element is electrically connected to the first gate. A second terminal of the second capacitive element is electrically connected to the second gate . A first terminal of the light-emitting element is electrically connected to the second terminal of the transistor . A second terminal of the light-emitting element is electrically connected to the fourth wiring

[0021] In the above aspect, the transistor is preferably an n-channel type

[0022] In the above aspect, the channel formation region preferably has an oxide semiconductor

[0023] In the above aspect, the first to third switches are preferably transistors each having an oxide semiconductor in its respective channel formation region

[0024] One aspect of the present invention is a display device including a transistor, first to third switches, first and second capacitive elements, ​, a display device having a light-emitting element and first to fourth wirings. The transistor has a first gate and a second gate. The first gate and the second gate preferably have an overlapping region with each other with a channel formation region of the transistor therebetween. The first terminal of the transistor is electrically connected to the third wiring. The first switch has a function of controlling the conduction state between the first wiring and the first gate. The second switch has a function of controlling the conduction state between the second wiring and the second gate . The third switch has a function of controlling the conduction state between the first gate and the second terminal of the transistor. The first terminal of the first capacitor is electrically connected to the first gate . The second terminal of the first capacitor is electrically connected to the second terminal of the transistor. The first terminal of the second capacitor is electrically connected to the first gate. The second terminal of the second capacitor is electrically connected to the second gate. The first terminal of the light-emitting element is electrically connected to the second terminal of the transistor . The second terminal of the light-emitting element is electrically connected to the fourth wiring.

[0025] In the above aspect, the transistor is preferably an n-channel type.

[0026] In the above aspect, the channel formation region preferably has an oxide semiconductor.

[0027] In the above aspect, the first to third switches are preferably transistors having an oxide semiconductor in their respective channel formation regions .

[0028] One aspect of the present invention is a display device having a transistor, first and second switches, first and second capacitors , a light-emitting element, and first to fourth wirings. The transistor has a first gate It has a first gate and a second gate. The first gate and the second gate preferably have overlapping regions with a channel formation region of the transistor interposed therebetween. A first terminal of the transistor is electrically connected to a third wiring. The first switch has a function of controlling a conduction state between a first wiring and the first gate. The second switch has a function of controlling a conduction state between a second wiring and the second gate. A first terminal of the first capacitor element is electrically connected to the first gate. A second terminal of the first capacitor element is electrically connected to a second terminal of the transistor. A first terminal of the second capacitor element is electrically connected to the first gate. A second terminal of the second capacitor element is electrically connected to the second gate. A first terminal of the light-emitting element is electrically connected to the second terminal of the transistor. A second terminal of the light-emitting element is electrically connected to a fourth wiring. In the above aspect, it is preferable that the transistor is an n-channel type. In the above aspect, it is preferable that the channel formation region has an oxide semiconductor. In the above aspect, it is preferable that the first and second switches are transistors having an oxide semiconductor in their respective channel formation regions. One aspect of the present invention is an electronic device including the display device described in the above aspect and at least one of a microphone, a speaker, and an operation key. According to one aspect of the present invention, it is possible to provide a display device in which variations in luminance between pixels due to variations in the threshold voltage of a driving transistor are suppressed. Further, according to one aspect of the present invention

[0029]

[0030]

[0031]

[0032]

Effects of the Invention

[0033] ​​​​​​​​​​​ It becomes possible to provide a high-precision display device. According to one aspect of the present invention, a display device with a high aperture ratio can be provided.

[0034] According to one aspect of the present invention, it becomes possible to provide a novel display device or to provide a novel semiconductor device.

[0035] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be obvious from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0036]

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Embodiments for Carrying Out the Invention

[0037] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not to be construed as being limited to the description content of the following embodiments.

[0038] Also, this specification can appropriately combine the following embodiments and examples. Moreover, when a plurality of configuration examples are shown in one embodiment or example, the configuration examples can be appropriately combined with each other.

[0039] Also, in the drawings, sizes, layer thicknesses, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The drawings are merely schematic illustrations and are not limited to the shapes or values shown in the drawings.

[0040] In the present specification and the like, when describing the connection relationship of a transistor, is expressed as "one of the source and drain" (or the first electrode, or the first terminal), and the source The other of the source and drain is called the "other of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of a transistor are This is because it changes depending on the operating conditions. In this case, the term source (drain) terminal, source (drain) electrode, etc. should be used appropriately depending on the situation. It can be replaced.

[0041] In this specification, unless otherwise specified, the on-current is the current when a transistor is in the on-state. The drain current when the transistor is in the on state is an n-channel transistor unless otherwise specified. In a transistor, the voltage difference between the gate and source (V GS ) is the transistor threshold voltage (V t h ) above, for p-channel transistors, V GS V th This refers to the following state. Examples For example, the on-current of an n-channel transistor is V GS V th Slave at the above time The on-current of a transistor is the voltage between the drain and source. Pressure (V DS ) may be dependent on

[0042] In this specification, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state. The off state, unless otherwise specified, for an n-channel transistor means a state where V is lower than V GS , and for a p-channel transistor means a state where V th is higher than V GS and V th . For example, the off-current of an n-channel transistor may refer to the drain current when V G S is lower than V th . The off-current of a transistor may depend on V GS . Therefore, when it is stated that the off-current of a transistor is less than 10 -21 A, it may mean that there exists a value of V for which the off-current of the transistor is less than 10 -21 A and V GS has a certain value.

[0043] Also, the off-current of a transistor may depend on V DS . In this specification, unless otherwise specified, the off-current may represent the off-current at an absolute value of V of 0.1V, 0.8V, 1V, 1.2V DS , 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Or it may represent the off-current at V when used in a semiconductor device or the like that includes the transistor. at which it is used. DS

[0044] Note that in this specification, the high power supply voltage may be referred to as the H level (or V DD ), and the low power supply voltage may be referred to as the L level (or GND).

[0045] (Embodiment 1) In this embodiment, a configuration example of a display device according to one aspect of the present invention will be described.

[0046] 〈Basic Configuration〉 Fig. 1 shows the basic configuration of a pixel included in a display device according to one aspect of the present invention. Pixel 1 shown in Fig. 1 0 has a transistor M1, a capacitor element C1, a capacitor element C2, and a light-emitting element EL1. do.

[0047] The transistor M1 has a first gate and a second gate. The first gate and the second gate have an overlapping region with each other with the channel formation region of the transistor M1 interposed therebetween. Also the transistor M1 has a first terminal that functions as one of a source or a drain, and a second terminal that functions as the other of the source or the drain. do.

[0048] The transistor M1 preferably has amorphous silicon, polycrystalline silicon, single-crystalline silicon, an oxide semiconductor (OS: Oxide Semiconductor), an organic semiconductor, or the like in its channel formation region. In particular, a transistor having OS in its channel formation region (hereinafter referred to as an OS transistor) is preferable because there is little variation from element to element due to the manufacturing process. do. do.

[0049] The light-emitting element EL1 includes elements whose luminance is controlled by current or voltage, such as an LED (Light Emitting Diode) or an OLED ( Organic Light Emitting Diode). For example, an OLED has at least an EL ( Electroluminescence) layer, an anode, and a cathode. do. The EL layer is composed of a single layer or a plurality of layers provided between the anode and the cathode, and these It contains at least a light-emitting layer containing a light-emitting substance among the layers. The EL layer is between the cathode and the anode. When the potential difference therebetween becomes equal to or higher than the threshold voltage of the light-emitting element EL1, electroluminescence is obtained by the current supplied. Hereinafter, the above-mentioned threshold voltage of the light-emitting element EL1 is denoted as V E L Electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state.

[0050] Also, one of the anode and the cathode of the light-emitting element EL1 functions as a pixel electrode, and the other functions as a common electrode. In FIG. 1, a configuration in which the anode of the light-emitting element EL1 is used as a pixel electrode and the cathode of the light-emitting element EL1 is used as a common electrode is illustrated.

[0051] A potential V ANO is applied to the first terminal of the transistor M1. The first terminal of the capacitor element C1 is electrically connected to the first gate, and the second terminal of the capacitor element C1 is the second terminal of the transistor M1 and is electrically connected thereto. The first terminal of the capacitor element C2 is electrically connected to the first gate and the second terminal of the capacitor element C2 is electrically connected to the second gate. The first terminal (anode) of the light-emitting element EL1 is electrically connected to the second terminal of the transistor M1, and the second terminal (cathode) of the light-emitting element EL1 is applied with a potential V CAT .

[0052] In FIG. 1, a case where the transistor M1 is an n-channel type is illustrated. V ANO is preferably at a higher potential than V C AT In particular, the threshold voltage of the transistor M1 is V t hWhen expressed as V ANO is V CAT to V EL and V th is preferably higher than the voltage obtained by adding and

[0053] When V ANO is applied to the first terminal of the transistor M1 and V CA T is applied to the second terminal of the light-emitting element EL1, the value of the drain current of the transistor M1 is determined according to the image signal applied to the first gate. When the above drain current is supplied to the light-emitting element EL1, the light-emitting element EL1 enters a light-emitting state.

[0054] The capacitor element C1 has a function of holding the potential difference between the first gate and the second terminal of the transistor M1. That is, the capacitor element C1 has a function of holding the potential difference between the first gate and the source of the transistor M1. Also, the capacitor element C2 has a function of holding the potential difference between the first gate and the second gate.

[0055] In one aspect of the present invention, before determining the value of the drain current of the transistor M1 according to the image signal, the threshold voltage of the transistor M1 is corrected to prevent the threshold voltage from varying between different pixels. Also, by applying a potential corresponding to the image signal to the second gate, the transistor M1 can perform Dual-Gate driving and increase the on-current.

[0056] Note that in this specification, Dual-Gate driving refers to a state in which a high potential (or a low potential) is simultaneously applied to the first gate and the second gate.

[0057] Hereinafter, a switch or the like is added to the pixel 10, and a more specific configuration of the display device according to one aspect of the present invention A conventional example will be described.

[0058] <Configuration example of pixel 20a> Fig. 2(A) shows a configuration example of a pixel 20a included in a display device according to an aspect of the present invention. Fig. 2 (A) The pixel 20a shown includes a transistor M1, a switch S1, a switch S2, an switch S3, a switch S4, a capacitive element C1, a capacitive element C2, and a light-emitting element EL1. The pixel 20a is obtained by adding switches S1 to S4 to the pixel 10. Also, the pixel 20a is electrically connected to a wiring L1, a wiring L2, a wiring L3, a wiring L4, and a wiring L5.

[0059] The switches S1 to S4 can each be configured by using one or more transistors. Alternatively, the switches S1 to S4 may use capacitive elements in addition to one or more transistors.

[0060] The first terminal of the transistor M1 is electrically connected to the wiring L3.

[0061] The switch S1 has a function of controlling the conduction state between the wiring L1 and the first gate. The switch S2 has a function of controlling the conduction state between the wiring L2 and the second gate. The switch S3 has a function of controlling the conduction state between the first gate and the second terminal of the transistor M1. The switch S4 has a function of controlling the conduction state between the wiring L5 and the second terminal of the transistor M1.

[0062] The first terminal of the light-emitting element EL1 is electrically connected to the second terminal of the transistor M1, and the second terminal of the light-emitting element EL1 is electrically connected to the wiring L4.

[0063] The wiring L1 has a function of supplying an image signal to the pixel 20a.

[0064] Fig. 2(B) shows a more specific configuration example of the pixel 20a. Fig. 2(B) is a circuit diagram when the switches S1 to S4 are replaced with n-channel transistors. The gate of the switch S1 is electrically connected to the wiring GL1, and the gate of the switch S2 is electrically connected to the wiring GL2. The gate of the switch S3 is electrically connected to the wiring GL2, and the gate of the switch S4 is electrically connected to the wiring GL3. When an H level is applied to the wirings GL1 to GL3, the switches connected thereto turn on, and when an L level is applied to the wirings GL1 to GL3, the switches connected thereto turn off.

[0065] It is preferable to use transistors with low off-current for the switches S1 to S4, for example. Here, low off-current means that at room temperature, the voltage between the source and the drain is 3V, and the normalized off-current per 1μm channel width is 10×10 -21 A or less. By using transistors with low off-current for the switches S1 to S4, it becomes possible to continuously hold the input image information in the pixel, and as long as a still image is continuously displayed, it becomes possible to reduce the rewriting frequency of the image information and achieve power saving of the display device.

[0066] Examples of transistors with low off-current include OS transistors and transistors using a wide bandgap semiconductor (a semiconductor with a bandgap of 2.2 eV or more, such as silicon carbide, gallium nitride, diamond, etc.) in the channel formation region.

[0067] For details regarding other configurations of pixel 20a, refer to the description of pixel 10.

[0068] 〈Operation Example of Pixel 20a〉 Next, an example of the operation of pixel 20a will be described with reference to FIGS. 3 to 5.

[0069] FIG. 3 shows a timing chart of the potential V applied to wiring L1, the potentials applied to wirings GL1 to GL3, and the potential applied to wiring L3. The timing chart shown in FIG. 3 has periods P1 to P4. Further, FIG. 4(A) shows the state of pixel 20a in period P1, FIG. 4(B) shows the state of pixel 20a in period P2, and FIG. 4(C) shows the state of pixel 20a in period P3. Note that in FIGS. 4(A) to (C), switches S1 to S4 are illustrated as switches respectively to clearly show the operation of pixel 20a. DATA and the potentials applied to wirings GL1 to GL3, and the timing chart of the potential applied to wiring L3. The timing chart shown in FIG. 3 has periods P1 to P4. Further, FIG. 4(A) shows the state of pixel 20a in period P1, FIG. 4(B) shows the state of pixel 20a in period P2, and FIG. 4(C) shows the state of pixel 20a in period P3. Note that in FIGS. 4(A) to (C), switches S1 to S4 are illustrated as switches respectively to clearly show the operation of pixel 20a. FIG. 3 shows a timing chart of the potential V applied to wiring L1, the potentials applied to wirings GL1 to GL3, and the potential applied to wiring L3. The timing chart shown in FIG. 3 has periods P1 to P4. Further, FIG. 4(A) shows the state of pixel 20a in period P1, FIG. 4(B) shows the state of pixel 20a in period P2, and FIG. 4(C) shows the state of pixel 20a in period P3. Note that in FIGS. 4(A) to (C), switches S1 to S4 are illustrated as switches respectively to clearly show the operation of pixel 20a. FIG. 3 shows a timing chart of the potential V applied to wiring L1, the potentials applied to wirings GL1 to GL3, and the potential applied to wiring L3. The timing chart shown in FIG. 3 has periods P1 to P4. Further, FIG. 4(A) shows the state of pixel 20a in period P1, FIG. 4(B) shows the state of pixel 20a in period P2, and FIG. 4(C) shows the state of pixel 20a in period P3. Note that in FIGS. 4(A) to (C), switches S1 to S4 are illustrated as switches respectively to clearly show the operation of pixel 20a. FIG. 3 shows a timing chart of the potential V applied to wiring L1, the potentials applied to wirings GL1 to GL3, and the potential applied to wiring L3. The timing chart shown in FIG. 3 has periods P1 to P4. Further, FIG. 4(A) shows the state of pixel 20a in period P1, FIG. 4(B) shows the state of pixel 20a in period P2, and FIG. 4(C) shows the state of pixel 20a in period P3. Note that in FIGS. 4(A) to (C), switches S1 to S4 are illustrated as switches respectively to clearly show the operation of pixel 20a. FIG. 3 shows a timing chart of the potential V applied to wiring L1, the potentials applied to wirings GL1 to GL3, and the potential applied to wiring L3. The timing chart shown in FIG. 3 has periods P1 to P4. Further, FIG. 4(A) shows the state of pixel 20a in period P1, FIG. 4(B) shows the state of pixel 20a in period P2, and FIG. 4(C) shows the state of pixel 20a in period P3. Note that in FIGS. 4(A) to (C), switches S1 to S4 are illustrated as switches respectively to clearly show the operation of pixel 20a. FIG. 3 shows a timing chart of the potential V applied to wiring L1, the potentials applied to wirings GL1 to GL3, and the potential applied to wiring L3. The timing chart shown in FIG. 3 has periods P1 to P4. Further, FIG. 4(A) shows the state of pixel 20a in period P1, FIG. 4(B) shows the state of pixel 20a in period P2, and FIG. 4(C) shows the state of pixel 20a in period P3. Note that in FIGS. 4(A) to (C), switches S1 to S4 are illustrated as switches respectively to clearly show the operation of pixel 20a.

[0070] Period P1 is a period for initializing pixel 20a. Period P2 is a period for fixing the threshold voltage of transistor M1 at 0V. Period P3 is a period for writing data to pixel 20a. Period P4 is a period during which pixel 20a emits light. Period P1 is a period for initializing pixel 20a. Period P2 is a period for fixing the threshold voltage of transistor M1 at 0V. Period P3 is a period for writing data to pixel 20a. Period P4 is a period during which pixel 20a emits light. Period P1 is a period for initializing pixel 20a. Period P2 is a period for fixing the threshold voltage of transistor M1 at 0V. Period P3 is a period for writing data to pixel 20a. Period P4 is a period during which pixel 20a emits light.

[0071] Also, in FIGS. 4(A) to (C), the node where the first gate of transistor M1 and the first terminal of capacitor element C1 are connected is shown as node N1, the node where the second gate of transistor M1 and the second terminal of capacitor element C2 are connected is shown as node N2, and the node where the second terminal of transistor M1, the second terminal of capacitor element C1, and the first terminal of light-emitting element EL1 are connected is shown as node N3. Also, in FIGS. 4(A) to (C), the node where the first gate of transistor M1 and the first terminal of capacitor element C1 are connected is shown as node N1, the node where the second gate of transistor M1 and the second terminal of capacitor element C2 are connected is shown as node N2, and the node where the second terminal of transistor M1, the second terminal of capacitor element C1, and the first terminal of light-emitting element EL1 are connected is shown as node N3. Also, in FIGS. 4(A) to (C), the node where the first gate of transistor M1 and the first terminal of capacitor element C1 are connected is shown as node N1, the node where the second gate of transistor M1 and the second terminal of capacitor element C2 are connected is shown as node N2, and the node where the second terminal of transistor M1, the second terminal of capacitor element C1, and the first terminal of light-emitting element EL1 are connected is shown as node N3. Also, in FIGS. 4(A) to (C), the node where the first gate of transistor M1 and the first terminal of capacitor element C1 are connected is shown as node N1, the node where the second gate of transistor M1 and the second terminal of capacitor element C2 are connected is shown as node N2, and the node where the second terminal of transistor M1, the second terminal of capacitor element C1, and the first terminal of light-emitting element EL1 are connected is shown as node N3.

[0072] In the following description, the potential difference between the first gate and the second terminal of the transistor M1 (the potential difference between node N 1 and node N3) is represented as V GS , and the potential difference between the second gate and the second terminal of the transistor M1 (the potential difference between node N2 and node N3) is represented as V . BGS

[0073] Throughout periods P1 to P4, V DATA is applied to the wiring L1, the potential V0 is applied to the wiring L2, V is applied to the wiring L3, V ANO is applied to the wiring L4, and the potential V1 is applied to the wiring CAT L5.

[0074] First, in period P1, the pixel 20a is initialized. The L level is applied to the wiring GL1, the H level is applied to the wiring GL2, and the H level is applied to the wiring GL3. The switches S2 to S witch S4 are turned on, and the switch S1 is turned off (Fig. 4(A)).

[0075] At this time, node N1 and node N3 become equipotential, and V GS becomes 0V. Also, V1 is applied to nodes N1 and N3, and V0 is applied to node N2. Further, in period P1 , in order not to emit light from the light-emitting element EL1, it is preferable that V1 is sufficiently small. In particular , V1 - V CAT is preferably smaller than V EL (the threshold voltage of the light-emitting element EL1).

[0076] Here, the relationship between V BGS and V th (the threshold voltage of the transistor M1) will be described with reference to Fig. 5 . Fig. 5 shows the V th dependency of V BGS . The larger V BGS is, the more...​​​ , V th is found to shift negatively. The V in period P1 BGS = V0 - V1 where the V th is taken as V th1 . To make V th1 a negative value, it is preferable that V0 - V1 is sufficiently large . When V th1 takes a negative value, the transistor M1 is in the on state at GS V = 0V .

[0077] Next, in period P2, the pixel 20a fixes the V of the transistor M1 th at 0V. The L level is applied to the wirings GL1 and GL3, and the H level is applied to the wiring GL2. The switches S1 and S4 turn off, and the switches S2 and S3 turn on (Fig. 4(B)).

[0078] A current flows through the transistor M1, and the potential of the node N3 rises. As the potential of the node N3 rises, V becomes smaller. From Fig. 5, the V of the transistor M1 BGS shifts positively from V th th 1. Since V GS is kept at 0V by the capacitive element C1, when V GS t h GS = 0V, V GS = V th , and the transistor M1 turns off, and the potential rise of the node N 3 stops.

[0079] In Fig. 5, when V BGS = 0V, taking V th as V th0 , the following relational expression holds .

[0080] V th = V th0 - αVBGS (1)

[0081] In formula (1), α is a constant determined by the capacitance value of the gate insulating film or the like. From formula (1), V th = 0, V BGS = V th0 / α can be expressed (Figure 5).

[0082] During period P2, it is preferable that no current flows through the light-emitting element EL1. Therefore, V0 - V CAT is preferably a value smaller than V th0 / α + V EL .

[0083] Next, during period P3, the pixel 20a writes data. The wiring GL1 and GL3 are given an H level, and the wiring GL2 is given an L level. The switches S1 and S4 are turned on, and the switches S2 and S3 are turned off. The node N1 is given V through the switch S1, and the node N3 is given V1 again through the switch S4 (Figure 4 DATA (C)). V GS = V DATA - V1.

[0084] At this time, the potential of the node N2 becomes V DATA + V th0 / α . Therefore, V BGS = V DATA + V th0 / α - V1. The transistor M1 has a potential dependent on V DATA applied to the first gate and the second gate. That is, the transistor M1 is in a state of being driven by Dual-Gate. A transistor driven by Dual-Gate has a larger on-current than a transistor driven by Single-Gate. DATA ​​​​

[0085] Next, in period P4, pixel 20a emits light according to the V written in period P3. Wiring GL1 to GL3 is given an L level, and switches S1 to S4 turn off. DATA according to and become. become.

[0086] In period P2, since the V of transistor M1 is corrected to the state of 0V, the light emitting element EL1 can obtain light emission independent of the V of transistor M1. Also, since transistor M1 performs Dual-Gate drive, it can pass a larger current. th is corrected to the state of 0V, so the light emission element EL1 can obtain light emission independent of the V of transistor M1. Also, th it becomes possible. Also, since transistor M1 performs Dual-Gate drive, it can pass a larger current. Also, since transistor M1 performs Dual-Gate drive, it can pass a larger current. become possible.

[0087] If transistor M1 is driven in Dual-Gate mode, transistor M1 can pass a large current with a smaller channel width, and the occupied area of transistor M1 can be reduced. If the occupied area of transistor M1 can be reduced, the occupied area of pixel 20a can be reduced, and a higher definition display device can be provided. channel width and can pass a large current, reducing the occupied area of transistor M1. If the occupied area of transistor M1 can be reduced, the occupied area of pixel 20 a can be reduced, and a higher definition display device can be provided. become possible.

[0088] Also, when the light of light emitting element EL1 is blocked by transistor M1 (when the display device has a bottom emission structure), by reducing the occupied area of transistor M1, the aperture ratio of the display device can be increased, and a display device with higher display quality can be provided. (when the display device has a bottom emission structure), by reducing the occupied area of transistor M1, the aperture ratio of the display device can be increased, and a display device with higher display quality can be provided. become possible.

[0089] Pixel 20a may supply the current I flowing through transistor M1 to an external circuit via switch S4 and wiring L5. The external circuit generates a correction signal according to the value of current I PIX to the external circuit. The external circuit generates a correction signal according to the value of current I PIX according to the value of can be supplied to the wiring L1. With the above configuration, the pixel 20a can correct not only the V of the transistor M1 but also the variation caused by the mobility of the transistor M1. of the transistor M1 th but also the variation caused by the mobility of the transistor M1. becomes possible.

[0090] By using the above-described pixel 20a in the display device, it is possible to provide a display device in which the variation in luminance between pixels is suppressed. Also, it is possible to provide a higher-definition display device. Also, it is possible to provide a display device with a higher aperture ratio. Also, it is possible to provide a display device with higher display quality. becomes possible. Also, it is possible to provide a higher-definition display device. Also, it is possible to provide a display device with a higher aperture ratio. Also, it is possible to provide a display device with higher display quality. becomes possible. Also, it is possible to provide a display device with a higher aperture ratio. Also, it is possible to provide a display device with higher display quality. becomes possible.

[0091] <Example configuration of pixel 21a> In the pixel 20a shown in FIG. 2(A), the switch S3 may be omitted. A configuration example in that case is shown in FIG. 6(A). is shown in FIG. 6(A).

[0092] A configuration example of the pixel 21a included in the display device according to one aspect of the present invention is shown in FIG. 6(A). The pixel 21a shown in FIG. 6(A) includes a transistor M1, a switch S1, a switch S2, a switch S4, a capacitive element C1, a capacitive element C2, and a light-emitting element EL1. Also, the pixel 21a is electrically connected to a wiring L1, a wiring L2, a wiring L3, a wiring L4, and a wiring L5. The transistor M1 has a first gate and a second gate. The first gate and the second gate have an overlapping region with each other with the channel formation region of the transistor M1 interposed therebetween. are shown in FIG. 6(A). The pixel 21a shown in FIG. 6(A) includes a transistor M1, a switch S1, a switch S2, a switch S4, a capacitive element C1, a capacitive element C2, and a light-emitting element EL1. Also, the pixel 21a is electrically connected to a wiring L1, a wiring L2, a wiring L3, a wiring L4, and a wiring L5. The transistor M1 has a first gate and a second gate. The first gate and the second gate have an overlapping region with each other with the channel formation region of the transistor M1 interposed therebetween. a switch S4, a capacitive element C1, a capacitive element C2, and a light-emitting element EL1. Also, the pixel 21a is electrically connected to a wiring L1, a wiring L2, a wiring L3, a wiring L4, and a wiring L5. The transistor M1 has a first gate and a second gate. The first gate and the second gate have an overlapping region with each other with the channel formation region of the transistor M1 interposed therebetween. is shown in FIG. 6(A). The pixel 21a shown in FIG. 6(A) includes a transistor M1, a switch S1, a switch S2, a switch S4, a capacitive element C1, a capacitive element C2, and a light-emitting element EL1. Also, the pixel 21a is electrically connected to a wiring L1, a wiring L2, a wiring L3, a wiring L4, and a wiring L5. The transistor M1 has a first gate and a second gate. The first gate and the second gate have an overlapping region with each other with the channel formation region of the transistor M1 interposed therebetween. is shown in FIG. 6(A). The pixel 21a shown in FIG. 6(A) includes a transistor M1, a switch S1, a switch S2, a switch S4, a capacitive element C1, a capacitive element C2, and a light-emitting element EL1. Also, the pixel 21a is electrically connected to a wiring L1, a wiring L2, a wiring L3, a wiring L4, and a wiring L5. The transistor M1 has a first gate and a second gate. The first gate and the second gate have an overlapping region with each other with the channel formation region of the transistor M1 interposed therebetween. gate and the second gate have an overlapping region with each other with the channel formation region of the transistor M1 interposed therebetween. have.

[0093] FIG. 6(B) shows a more specific configuration example of the pixel 21a. FIG. 6(B) shows a circuit diagram when the switches S1, S2, and S4 in FIG. 6(A) are replaced with n-channel type transistors. is shown when the switches S1, S2, and S4 in FIG. 6(A) are replaced with n-channel type transistors. It is. The gate of switch S1 is electrically connected to wiring GL1, and the gate of switch S2 is electrically connected to wiring GL2, and the gate of switch S4 is electrically connected thereto.

[0094] Pixel 21a is different from pixel 20a shown in FIG. 2 in that it does not have switch S3 and that the V th of transistor M1 can be set to a value outside 0V. Other configurations are the same as those of pixel 20a, and reference may be made to the description of pixel 20a.

[0095] <Example of operation of pixel 21a> Next, an example of the operation of pixel 21a will be described with reference to FIGS. 7 to 8. Note that in FIG. 8, the same reference numerals as those in FIG. 4 are used for the potential (or potential difference) to represent the same potential (or potential difference).

[0096] FIG. 7 shows a timing chart of the potential applied to wiring L1, the potentials applied to wirings GL1 to GL3, and the potential applied to wiring L3. The timing chart shown in FIG. 7 has periods P1 to P4. Further, FIG. 8(A) shows the state of pixel 21a in period P1, FIG. 8(B) shows the state of pixel 21a in period P2, and FIG. 8(C) shows the state of pixel 21a in period P3, respectively. Note that in FIGS. 8(A) to (C), switches S1, S2, and S4 are shown as switches for the sake of clearly showing the operation of pixel 21a.

[0097] Period P1 is a period for initializing pixel 21a. Period P2 is a period for fixing the threshold voltage of transistor M1 to V2 - V1. Period P3 is a period for writing data to pixel 21a. ​​​​​​It is the period of charging. Period P4 is the period during which the pixel 21a emits light.

[0098] Also, in FIGS. 8(A) to (C), the node connecting the first gate of the transistor M1, the first terminal of the capacitor element C1, and the first terminal of the capacitor element C2 is shown as node N1, and the node connecting the second gate of the transistor M1 and the second terminal of the capacitor element C2 is shown as node N2. The node connecting the second terminal of the transistor M1, the second terminal of the capacitor element C1, and the first terminal of the light-emitting element EL1 is shown as node N3.

[0099] Throughout periods P1 to P4, V0 is applied to the wiring L2, V is applied to the wiring L3, ANO is applied V is applied to the wiring L4, CAT and V1 is applied to the wiring L5.

[0100] First, in period P1, the pixel 21a is initialized. An H level is applied to the wiring GL1, an H level is applied to the wiring GL2, and an H level is applied to the wiring GL3. The switches S1, S2 and S4 are turned on (FIG. 8(A)).

[0101] At this time, an arbitrary fixed potential (potential V2) is applied to the wiring L1. V2 is applied to the node N1, V0 is applied to the node N2, and V1 is applied to the node N3. At this time, V G S = V2 - V1, V BGS = V0 - V1. Also, the threshold value of the transistor M1 is V t h1 becomes.

[0102] Next, in period P2, the pixel 21a fixes the V th of the transistor M1 to V2 - V1. An L level is applied to the wirings GL1 and GL3, and an H level is applied to the wiring GL2. ​​​​​​​ Switches S1 and S4 are turned off, and switch S2 is turned on. Node N2 is supplied with V0 (Fig. 8(B)).

[0103] At this time, a current flows through transistor M1, and the potential of node N3 rises. Since V is maintained at V2 - V1 by capacitor C1, when V = V2 - V1, V 1 GS becomes equal to V, and transistor M1 turns off, halting the potential rise of node N3. th = V2 - V1, V GS = V th and transistor M1 enters the off state, stopping the potential rise of node N3. The V BGS at this time becomes (V th0 - V2 + V1) / α (Figs. 5 and 8(B)).

[0104] Next, in period P3, pixel 21a writes data. High level is applied to wirings GL1 and GL3 and low level is applied to wiring GL2. Switches S1 and S4 are turned on, and switch S2 is turned off. Node N1 is supplied with V DATA through switch S1, and node N3 is supplied with V1 again through switch S4. At this time, V GS = V DATA - V1, V BGS = V DATA - V2 + (V th0 - V2 + V1) / α results (Fig. 8(C)).

[0105] Transistor M1 has a potential dependent on V DATA applied to its first gate and second gate That is, transistor M1 is in a state of being driven by Dual - Gate.

[0106] In period P2, since the V th of transistor M1 is corrected to the state of V2 - V1 ​, the light-emitting element EL1 can obtain light emission that does not depend on the V of the transistor M1. th Also, since the transistor M1 performs Dual-Gate driving, it becomes possible to flow a larger current. If the transistor M1 is driven in Dual-Gate mode, the transistor M1 can flow a large current with a smaller channel width, making it possible to reduce the occupied area of the transistor M1.

[0107] If the transistor M1 is driven in Dual-Gate mode, the transistor M1 can flow a large current with a smaller channel width, making it possible to reduce the occupied area of the transistor M1. If the occupied area of the transistor M1 can be reduced, it becomes possible to reduce the occupied area of the pixel 21a, making it possible to provide a higher-definition display device.

[0108] Also, when the light of the light-emitting element EL1 is blocked by the transistor M1, by reducing the occupied area of the transistor M1, it becomes possible to increase the aperture ratio of the display device, making it possible to provide a display device with higher display quality.

[0109] The pixel 21a may supply the current I flowing through the transistor M1 to an external circuit via the switch S4 and the wiring L5. PIX The external circuit can supply a correction signal to the wiring L1 according to the value of the current I. PIX With the above configuration, the pixel 21a can correct not only the V of the transistor M1, but also the variations caused by the mobility of the transistor M1. th By using the above-described pixel 21a in a display device, it becomes possible to provide a display device with reduced variation in luminance between pixels. Also, it becomes possible to provide a higher-definition display device.

[0110] By using the above-described pixel 21a in a display device, it becomes possible to provide a display device with reduced variation in luminance between pixels. Also, it becomes possible to provide a higher-definition display device. ​​This makes it possible to provide a display device with a higher aperture ratio. Also, it becomes possible to provide a display device with higher display quality. This makes it possible to provide a display device with higher display quality.

[0111] <Configuration example of pixel 22a> In the pixel 20a shown in FIG. 2(A), the switch S4 and the wiring L5 may be omitted. In that case, the configuration example is shown in FIG. 9(A).

[0112] FIG. 9(A) shows a configuration example of a pixel 22a included in a display device according to an aspect of the present invention. FIG. 9 (A) shows a pixel 22a having a transistor M1, a switch S1, a switch S2, a switch S3, a capacitive element C1, a capacitive element C2, and a light-emitting element EL1. Also, the pixel 22a is electrically connected to a wiring L1, a wiring L2, a wiring L3, and a wiring L4. The transistor M1 has a first gate and a second gate. The first gate and the second gate have an overlapping region with each other with the channel formation region of the transistor M1 therebetween.

[0113] FIG. 9(B) shows a more specific configuration example of the pixel 22a. FIG. 9(B) shows a circuit diagram when the switches S1 to S3 in FIG. 9(A) are replaced with n-channel transistors. The gate of the switch S1 is electrically connected to the wiring GL1, the gate of the switch S2 is electrically connected to the wiring GL2, and the gate of the switch S3 is electrically connected to the wiring GL3. The gate of the switch S3 is electrically connected to the wiring GL3.

[0114] The pixel 22a is different from the pixel 20a shown in FIG. 2 in that it does not have the switch S4 and the wiring L5. Other configurations are the same as those of the pixel 20a, and the description of the pixel 20a may be referred to.

[0115] <Operation example of pixel 22a> Next, an example of the operation of pixel 22a will be described with reference to FIGS. 10 and 11. Note that FIG. 11 uses the same reference numerals as FIGS. 4 or 8 for the potential (or potential difference) to represent the same potential (or potential difference).

[0116] FIG. 10 shows a timing chart of the potential applied to wiring L1, the potentials applied to wirings GL1 to GL3, and the potential applied to wiring L3. The timing chart shown in FIG. 10 has periods P1 to P4. Further, FIG. 11(A) shows the state of pixel 22a in period P1, FIG. 11(B) shows the state of pixel 22a in period P2, and FIG. 11(C) shows the state of pixel 22a in period P3. In FIGS. 11(A) to (C), for easy understanding of the operation of pixel 22a, switches S1 to S3 are each illustrated as switches.

[0117] Period P1 is a period for initializing pixel 22a. Period P2 is a period for fixing the threshold voltage of transistor M1 at 0V. Period P3 is a period for writing data to pixel 22a. Period P4 is a period during which pixel 22a emits light.

[0118] Also, in FIGS. 11(A) to (C), the node connecting the first gate of transistor M1 and the first terminal of capacitor element C1 is shown as node N1, the node connecting the second gate of transistor M1 and the second terminal of capacitor element C2 is shown as node N2, and the node connecting the second terminal of transistor M1, the second terminal of capacitor element C1, and the first terminal of light-emitting element EL1 is shown as node N3.

[0119] Throughout periods P1 to P4, V DATA is applied to wiring L1, and V0 is applied to wiring L2. ​​​​​​​​​Then, V is applied to wiring L4. CAT is applied.

[0120] First, in period P1, pixel 22a is initialized. An L level is applied to wiring GL1, and an H level is applied to wirings GL2 and GL3. Switch S1 turns off, and switches S2 and S3 turn on (Fig. 11(A)).

[0121] A low potential (potential V L ) is applied to wiring L3, and V0 is applied to node N2. Nodes N1 and N3 become equipotential. When the potentials of nodes N1 and N3 at this time are set as potential V3, then , V GS = 0V, V BGS = V0 - V3. Also, let the threshold of transistor M1 be V th2 . In period P1, by applying V L to wiring L3, current flow through transistor M1 and light-emitting element EL1 is prevented.

[0122] Next, in period P2, pixel 22a fixes V th of transistor M1 to 0V. L levels are applied to wirings GL1 and GL3, and an H level is applied to wiring GL2. Switches S1 and S3 turn off, and switch S2 turns on. Node N2 is given V0 . Also, V ANO is applied to wiring L3 (Fig. 11(B)).

[0123] At this time, current flows through transistor M1, and the potential of node N3 rises. Due to capacitor C 1, since V GS is kept at 0V, when V th = 0V, V GS = V th and transistor M1 turns off, and the potential rise of node N3 stops. The V at this time BGS becomes V th0 / α.

[0124] Next, during period P3, pixel 22a writes data. An H level is applied to wiring GL1, and an L level is applied to wirings GL2 and GL3. Switch S1 is turned on, and switches S2 and S3 are turned off. Node N1 is supplied with V . When the potential of node N3 at this time is V4, then V = V DATA is supplied. Let the potential of node N3 at this time be V4, then V GS = V DATA - V4 and V BGS = V DATA + V th0 / α - V4 (FIG. 11(C)).

[0125] Transistor M1 has a potential depending on V DATA applied to the first gate and the second gate. That is, transistor M1 is in a state of being driven by Dual-Gate.

[0126] During period P2, since the V th of transistor M1 is corrected to the 0V state, the light-emitting element EL1 can obtain light emission independent of the V th of transistor M1. Also, since transistor M1 performs Dual-Gate drive, it becomes possible to pass a larger current.

[0127] If transistor M1 is driven by Dual-Gate, transistor M1 can pass a large current with a smaller channel width, and it becomes possible to reduce the occupied area of transistor M1. If the occupied area of transistor M1 can be reduced, it becomes possible to reduce the occupied area of pixel 22 a, and it becomes possible to provide a higher-definition display device. It becomes possible.

[0128] Also, when the light of the light-emitting element EL1 is blocked by the transistor M1, by reducing the occupation area of the transistor M 1, it becomes possible to increase the aperture ratio of the display device, and it becomes possible to provide a display device with higher display quality.

[0129] By using the pixel 22a described above in the display device, it becomes possible to provide a display device in which the variation in luminance between pixels is suppressed. Also, it becomes possible to provide a higher-definition display device. Also, it becomes possible to provide a display device with a higher aperture ratio. Also, it becomes possible to provide a display device with higher display quality.

[0130] <Configuration Example of Pixel 23a> The pixel 20a shown in FIG. 2(A) may omit the switch S3, the switch S4, and the wiring L5. The circuit diagram in that case is shown in FIG. 12(A).

[0131] FIG. 12(A) shows a configuration example of a pixel 23a included in a display device according to an aspect of the present invention. The pixel 23a shown in FIG. 12(A) includes a transistor M1, a switch S1, a switch S2 , a capacitor element C1, a capacitor element C2, and a light-emitting element EL1. Also, the pixel 23a is electrically connected to a wiring L1, a wiring L2, a wiring L3, and a wiring L4. The transistor M1 has a first gate and a second gate. The first gate and the second gate have an overlapping region with each other with the channel formation region of the transistor M1 interposed therebetween.

[0132] FIG. 12(B) shows a more specific configuration example of the pixel 23a. FIG. 12(B) is FIG. 12(A The circuit when the switches S1 and S2 in are replaced with n-channel transistors is shown in the figure. The gate of switch S1 is electrically connected to the wiring GL1, and the gate of switch S2

[0133] is electrically connected to the wiring GL2. Pixel 23a is different from pixel 20a shown in Fig. 2 in that it does not have switch S3, switch S4, and wiring L5. Other configurations are the same as those of pixel 20a, and the description of pixel 20a can be referred to.

[0134] <Example of the operation of pixel 23a> Next, an example of the operation of pixel 23a will be described with reference to FIGS. 13 and 14. Note that in FIG. 14, the same reference numerals as those in FIGS. 4, 8, or 11 are used for the potential (or potential difference) to represent the same potential (or potential difference).

[0135] FIG. 13 shows a timing chart of the potential applied to wiring L1, the potentials applied to wirings GL1 to GL3, and the potential applied to wiring L3. The timing chart shown in FIG. 13 has periods P1 to P4. Also, FIG. 14(A) shows the state of pixel 23a in period P1, FIG. 14(B) shows the state of pixel 23a in period P2, and FIG. 14(C) shows the state of pixel 23a in period P3, respectively. Note that in FIGS. 14(A) to (C), for the sake of clearly showing the operation of pixel 23a, switches S1 and S2 are each illustrated as switches.

[0136] Period P1 is a period for initializing pixel 23a. Period P2 is a period for fixing the threshold voltage of transistor M1 to V2 - V5. Period P3 is a period for writing data to It is the period when it is filled. Period P4 is the period when pixel 23a emits light.

[0137] Also, in FIGS. 14(A) to (C), the node connecting the first gate of transistor M1, the first terminal of capacitor C1, and the first terminal of capacitor C2 is shown as node N1, and the node connecting the second gate of transistor M1 and the second terminal of capacitor C2 is shown as node N2. The node connecting the second terminal of transistor M1, the second terminal of capacitor C1, and the first terminal of light-emitting element EL1 is shown as node N3. The node connecting the first gate of transistor M1, the first terminal of capacitor C1, and the first terminal of capacitor C2 is shown as node N1, and the node connecting the second gate of transistor M1 and the second terminal of capacitor C2 is shown as node N2. The node connecting the second gate of transistor M1 and the second terminal of capacitor C2 is shown as node N2. The node connecting the second terminal of transistor M1, the second terminal of capacitor C1, and the first terminal of light-emitting element EL1 is shown as node N3. is shown as node N3.

[0138] Throughout periods P1 to P4, V0 is applied to wiring L2, and V is applied to wiring L4. CAT is applied .

[0139] First, in period P1, pixel 23a is initialized. H level is applied to wirings GL1 and GL2. Switches S1 and S2 are turned on (FIG. 14(A)). H level is applied to wirings GL1 and GL2. Switches S1 and S2 are turned on (FIG. 14(A)).

[0140] An arbitrary fixed potential (potential V2) is applied to wiring L1, and a low potential (potential V) is applied to wiring L3. Node N1 is given V2, and node N2 is given V0. When the potential of node N3 at this time is defined as potential V5, then V = V2 - V5, V = V0 - V5. Also, let the threshold value of transistor M1 be V. In period P1, by applying V to wiring L3, current flow through transistor M1 and light-emitting element EL1 is prevented. L is applied Node N1 is given V2, and node N2 is given V0. When the potential of node N3 at this time is defined as potential V5, then V = V2 - V5, V = V0 - V5. Node N3's potential at this time is defined as potential V5, then V = V2 - V5, V = V0 - V5. GS = V2 - V5, V BGS = V0 - V5 holds. Also, let the threshold value of transistor M1 be V. th3 In period P1, by applying V to wiring L3, current flow through transistor M1 and light-emitting element EL1 is prevented. V L to wiring L3, current flow through transistor M1 and light-emitting element EL1 is prevented.

[0141] Next, in period P2, pixel 23a fixes the V of transistor M1 to V2 - V5. th is fixed to V2 - V5. The L level is applied to the wiring GL1, and the H level is applied to the wiring GL2. Switch S1 is turned off and switch S2 is turned on. Node N2 is given V0. Line L3 has V ANO is given (Figure 14(B)).

[0142] At this time, a current flows through the transistor M1, and the potential of the node N3 rises. 1, V GS Since is kept at V2-V5, V th When V = V2-V5, V GS =V th This causes the transistor M1 to be turned off, and the potential rise at the node N3 stops. At this time, V BGS (V th0 -V2+V5) / α.

[0143] Next, in the period P3, data is written to the pixel 23a. is applied, and the L level is applied to the wiring GL2. The switch S1 is turned on, and the switch S2 is turned off. Node N1 is connected to V through switch S1. DATA is given. If the potential of node N3 at this time is V6, then V GS =V DATA -V6, V BGS =V DA TA -V2+V5+(V th0 -V2+V5) / α-V6 (Figure 14(C)).

[0144] The transistor M1 has a first gate and a second gate connected to V DATA A potential dependent on That is, the transistor M1 is driven by a dual gate.

[0145] During the period P2, the V thSince it is corrected to the states of V2 - V5 , the light-emitting element EL1 can obtain light emission that does not depend on the V th of the transistor M1. Also, since the transistor M1 performs Dual-Gate driving, it becomes possible to flow a larger current .

[0146] If the transistor M1 is driven with Dual-Gate, the transistor M1 can flow a large current with a smaller channel width, and it becomes possible to reduce the occupied area of the transistor M1 . If the occupied area of the transistor M1 can be reduced, it becomes possible to reduce the occupied area of the pixel 23 a, and it becomes possible to provide a higher-definition display device .

[0147] Also, when the light of the light-emitting element EL1 is blocked by the transistor M1, by reducing the occupied area of the transistor M 1, it becomes possible to increase the aperture ratio of the display device, and it becomes possible to provide a display device with higher display quality.

[0148] By using the above-described pixel 23a in a display device, it becomes possible to provide a display device in which the variation in luminance between pixels is suppressed . Also, it becomes possible to provide a higher-definition display device . Also, it becomes possible to provide a display device with a higher aperture ratio. Also, it becomes possible to provide a display device with higher display quality.

[0149] 〈Other pixel configuration examples〉 In the above-described pixels 20a to 23a, the first gate and the second gate of the transistor M1 may be swapped. The circuit diagrams in that case are shown in FIGS. 15(A) to (D). As shown in FIG. 15(A) Pixel 20b corresponds to pixel 20a, and pixel 21b shown in FIG. 15(B) corresponds to pixel 21a Pixel 22b shown in FIG. 15(C) corresponds to pixel 22a, and pixel 23 b shown in FIG. 15(D) corresponds to pixel 23a.

[0150] Pixels 20a to 23a described above can be replaced with the capacitance of the capacitor element C1 that the first gate of the transistor M1 has The circuit diagrams in that case are shown in FIGS. 16(A) to (D). Pixel 20c shown in FIG. 16(A) corresponds to pixel 20a, and pixel 21c shown in FIG. 16(B) corresponds to pixel 21a, pixel 22c shown in FIG. 16(C) corresponds to pixel 22a, and in FIG. 16( D), pixel 23c shown corresponds to pixel 23a. D) corresponds to pixel 23a.

[0151] For pixels 20a to 23a described above, transistors having a first gate and a second gate may be applied to switches S1 to S4 The circuit diagrams in that case are shown in FIGS. 17(A) to (D). Pixel 20d shown in FIG. 17(A) corresponds to pixel 20a, and pixel 21 d shown in FIG. 17(B) corresponds to pixel 21a, pixel 22d shown in FIG. 17(C) corresponds to pixel 22a, and in FIG. 17 d shown in FIG. 17(C) corresponds to pixel 22a, and in FIG. 17 (D), pixel 23d shown corresponds to pixel 23a. The second gates that switches S1 to S4 have may each be given a common potential V7. With the above configuration, the s witches S1 to S4 can control the threshold voltage.

[0152] Also, switches S1 to S4 shown in FIGS. 17(A) to (D) may electrically connect the first gate and the second gate The circuit diagrams in that case are shown in FIGS. 18(A) to (D). Pixel 20e shown in FIG. 18 (A) corresponds to pixel 20d, and pixel 21e shown in FIG. 18(B) corresponds to pixel 2 Corresponding to 1d, the pixel 22e shown in Fig. 18(C) corresponds to the pixel 22d, and the pixel 23e shown in Fig. 18(D) corresponds to the pixel 23d. With the above configuration, switches S1 to S4 can improve the on-current of the transistor.

[0153] For the above-described pixels 20a to 23a, the transistor M1 may be a p-channel transistor, and the positions of the anode and cathode of the light-emitting element EL1 may be swapped. The circuit diagrams in that case are shown in Figs. 19(A) to (D). The pixel 20f shown in Fig. 19(A) corresponds to the pixel 20a, the pixel 21f shown in Fig. 19(B) corresponds to the pixel 21a, the pixel 22f shown in Fig. 19(C) corresponds to the pixel 22a, and the pixel 23f shown in Fig. 19(D) corresponds to the pixel 23a. By swapping the positions of the anode and cathode of the light-emitting element EL1, V CAT is applied to the wiring L3, and it is preferable that V A NO is applied to the wiring L4.

[0154] For the above-described pixels 20a to 23a, a switch S5 may be provided between the second terminal of the capacitor element C1 and the first terminal of the light-emitting element EL1. The circuit diagrams in that case are shown in Figs. 20(A) to (D) . The pixel 20g shown in Fig. 20(A) corresponds to the pixel 20a, the pixel 2 1g shown in Fig. 20(B) corresponds to the pixel 21a, the pixel 22g shown in Fig. 20(C) corresponds to the pixel 22a, and the pixel 2 3g shown in Fig. 20(D) corresponds to the pixel 23a. Figs. 20(A) to (D) show the case where an n-channel transistor is applied as the switch S5. The gate of the switch S5 is electrically connected to the wiring GL4. The pixels 20g to 23g can control the current flowing through the light-emitting element EL1 by providing the switch S 5. By providing 5, it becomes possible to control the current flowing through the light-emitting element EL1.

[0155] The above-mentioned pixels 20a to 23a each have a switch between the first terminal of the transistor M1 and the line L3. A switch S5 may be provided. Circuit diagrams in this case are shown in Figures 21(A) to (D). 21(B) corresponds to pixel 21a. 21(C) corresponds to pixel 22a, and the pixel 22h shown in FIG. 21(D) corresponds to pixel 22a. Pixel 23h corresponds to pixel 23a. The gate of the switch S5 is connected to the wiring G By using the above configuration, the pixels 20h to 23h are electrically connected to the transistors L1 and L2. It is possible to control the current flowing through the transistor M1 and the light-emitting element EL1.

[0156] The above-mentioned pixels 20a to 23a each include a second terminal of the transistor M1 and a second terminal of the capacitance element C1. A switch S5 may be provided between the MOSFET and the power supply. Circuit diagrams in this case are shown in Figures 22(A) to 22(D). The pixel 20i shown in FIG. 22(A) corresponds to the pixel 20a, and the pixel 21 shown in FIG. 22(B) corresponds to the pixel 21. i corresponds to pixel 21a, pixel 22i shown in FIG. 22(C) corresponds to pixel 22a, and The pixel 23i shown in (D) corresponds to the pixel 23a. The gate of switch S5 is an n-channel transistor. The gate is electrically connected to the wiring GL4. 23i can control the current flowing through the transistor M1 and the light-emitting element EL1. do.

[0157] In the above-described pixels 20a to 23a, a capacitive element C3 may be connected in parallel to the light-emitting element EL1. 。The circuit diagrams in such cases are shown in FIGS. 23(A) to (D). The pixel 20j shown in FIG. 23(A) corresponds to the pixel 20a, the pixel 21j shown in FIG. 23(B) corresponds to the pixel 21a, and FIG. 23(C ) the pixel 22j shown corresponds to the pixel 22a, and the pixel 23j shown in FIG. 23(D) corresponds to the pixel 23a . With the above configuration, the pixels 20j to 23j can stabilize the potential of the first terminal of the light-emitting element EL1 .

[0158] The above-described pixels 20a to 23a may have the positions of the anode and cathode of the light-emitting element EL1 swapped . The circuit diagrams in such cases are shown in FIGS. 24(A) to (D). The pixel 20k shown in FIG. 24(A) corresponds to the pixel 20a, the pixel 21k shown in FIG. 24(B) corresponds to the pixel 21a, and FIG. 24(C ) the pixel 22k shown corresponds to the pixel 22a, and the pixel 23k shown in FIG. 24(D) corresponds to the pixel 23a . In the pixels 20k and 22k, the switch S3 has a function of controlling the conduction state between the first gate and the first terminal of the transistor M1 . Also, in the pixels 20k to 23k , the first terminal of the capacitor element C1 is electrically connected to the first gate, and the second terminal of the capacitor element C1 is electrically connected to the first terminal of the transistor M1. By swapping the positions of the anode and cathode of the light-emitting element EL1, V is applied to the wiring L3 , and it is preferable that V is applied to the wiring L4 CAT , AN O .

[0159] The above-described pixels 20a to 23a may use the transistor M1 as a p-channel type transistor . The circuit diagrams in such cases are shown in FIGS. 25(A) to (D). The pixel 20 l shown in FIG. 25(A) corresponds to the pixel 20a, the pixel 21l shown in FIG. 25(B) corresponds to the pixel 21a, and FIG. 25 The pixel 22l shown in (C) corresponds to the pixel 22a, and the pixel 23l shown in FIG. 25(D) corresponds to the pixel 2 3a. In the pixels 20l and 22l, the switch S3 has a function of controlling the conduction state between the first gate and the first terminal of the transistor M1. Also, in the pixels 20l to 23 l, the first terminal of the capacitor element C1 is electrically connected to the first gate, and the second terminal of the capacitor element C1 is electrically connected to the first terminal of the transistor M1.

[0160] <Example configuration of pixel section and selection circuit> Next, FIG. 26 shows, as an example, the configuration of a pixel section of a display device according to an aspect of the present invention.

[0161] In FIG. 26, the pixel section 40 has a plurality of pixels 20a arranged in a matrix. Also, the pixel section 40 has wirings GL1 to GL3 connected to the drive circuit 110, and wirings L1 to L3 connected to the drive circuit 1 20, a wiring L4 (not shown), and a wiring L5. In FIG. 26, the wirings GL1 to GL3 are represented by a single wiring GL. Each of the plurality of pixels 20a is electrically connected to at least one of the wirings GL1, at least one of the wirings GL2, at least one of the wirings GL3, at least one of the wirings L1, at least one of the wirings L2, at least one of the wirings L3, at least one of the wirings L4, and at least one of the wirings L5.

[0162] Note that the types and numbers of the above wirings can be determined according to the configuration, number, and arrangement of the pixels 20a. Specifically, in the case of the pixel section 40 shown in FIG. 26, the pixels 20a of m rows and n columns are electrically connected in a matrix form. And a plurality of wirings indicated by GL[1] to GL[m] The line GL, a plurality of wirings L1 indicated by wirings L1[1] to L1[n], a plurality of wirings L2 indicated by wirings L2[1] to L2[n], a plurality of wirings L3 indicated by wirings L3[1] to L3[n], and a plurality of wirings L5 indicated by wirings L5[1] to L5[n] are arranged within the pixel portion 40 are illustrated as an example.

[0163] FIG. 26 shows a configuration example of a pixel portion having the pixel 20a, but is not limited thereto. FIG. 26 can be applied to all the pixels exemplified in the present embodiment.

[0164] (Embodiment 2) In the present embodiment, a transistor (OS transistor) in which a channel formation region applicable to the transistor of the pixel described in the above embodiment is formed of an oxide semiconductor film, and a transistor (Si transistor) in which a channel formation region is formed of silicon will be described by way of example.

[0165] <Configuration Example 1 of Transistor> First, the OS transistor will be described.

[0166] FIGS. 27(A), 27(B) and 27(C) show top views (layout diagrams) of three transistors (TA1, TA2, TB1) having different device structures, and their respective circuit symbols are shown. FIG. 28 is a cross-sectional view of the transistors (TA1, TA2, TB1). Cross-sectional views of the transistor TA1 taken along lines a1-a2 and b1-b2, the transistor TA2 taken along lines a3- a4 and b3-b4, and the transistor TB1 taken along lines a5-a6, b5-b6 are shown in FIGS. 28(A) and 28(B). These transistors ​The cross-sectional structure in the channel length direction is shown in Fig. 28(A), and the cross-sectional structure in the channel width direction is shown in Fig. 28(B).

[0167] As shown in Figs. 28(A) and (B), the transistors (TA1, TA2, TB1) are integrated on the same insulating surface, and these transistors can be fabricated in the same manufacturing process . Here, for the sake of clarity of the device structure, the potential to each gate (G), source (S), and drain (D) of the transistors and the electrical connection with the wiring for supplying power are omitted.

[0168] Transistor TA1 (Fig. 27(A)) and transistor TA2 (Fig. 27(B)) are transistors having a gate electrode (G) and a back gate electrode (BG). The gate electrode corresponds to the first gate electrode, and the back gate electrode corresponds to the second gate electrode. Transistors TA1 and TA2 have a structure in which the back gate electrode is connected to the gate electrode . Transistor TB1 (Fig. 27(C)) is a transistor without a back gate electrode. As shown in Fig. 28, these transistors (TA1, TA2, TB1) are formed on the substrate 30. Hereinafter, with reference to Figs. 27 and 28, the configurations of these transistors will be described.

[0169] [Transistor TA1] Transistor TA1 has a gate electrode GE1, a source electrode SE1, a drain electrode DE1, a back gate electrode BGE1, and an oxide semiconductor film OS1.

[0170] Also, in this embodiment, the channel length of the OS transistor is between the source electrode and the drain electrode Let the distance be between them. Also, the channel width of the OS transistor is the width of the source electrode or the drain electrode in the region where the oxide semiconductor film and the gate electrode overlap. The channel length of transistor TA1 is La1, and the channel width is Wa1.

[0171] The oxide semiconductor film OS1 overlaps with the gate electrode GE1 via the insulating film 34. A pair of electrodes (SE1, DE1) are formed in contact with the upper surface and the side surface of the oxide semiconductor film OS1. As shown in Fig. 27(A), the oxide semiconductor film OS1 has a portion that does not overlap with the gate electrode GE1 and the pair of electrodes (SE1, DE1). The oxide semiconductor film OS1 has a length in the channel length direction that is longer than the channel length La1, and a length in the channel width direction that is longer than the channel width Wa1.

[0172] An insulating film 35 is formed covering the oxide semiconductor film OS1, the gate electrode GE1, the source electrode SE1, and the drain electrode DE1. A back gate electrode BGE1 is formed on the insulating film 35. The back gate electrode BGE1 is provided so as to overlap with the oxide semiconductor film OS1 and the gate electrode G E1. Here, as an example, the back gate electrode BGE1 is provided to have the same shape as the gate electrode GE1 and to be arranged at the same position. The back gate electrode BGE1 is in contact with the gate electrode GE1 at the opening CG1 that penetrates the insulating film 34, the insulating film 35, and the insulating film 36. With this structure, the gate electrode of the transistor TA1 and the back gate electrode are electrically connected.

[0173] By connecting the back gate electrode BGE1 to the gate electrode GE1, the ​​​​​​​The on-current can be increased. By providing the back gate electrode BGE1, the strength of the transistor TA1 can be improved. Against deformation such as bending of the substrate 30, the back gate electrode BGE1 serves as a reinforcing member to make the transistor TA1 less likely to break. The oxide semiconductor film OS1 including the channel formation region has a multilayer structure. Here, as an example, it has a three-layer structure composed of three oxide semiconductor films 31, 32, and 33. The oxide semiconductor films constituting the oxide semiconductor film OS1 are preferably metal oxide films containing at least one same metal element, and particularly preferably contain In. Examples of the metal oxide containing In that can form the semiconductor film of the transistor include In-Ga oxide film and In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd). Also, films obtained by adding other elements or materials to such metal oxide films can be used. In the transistor TA1, by forming a channel in the oxide semiconductor film 32, the channel formation region can be prevented from contacting the insulating films 34 and 35.

[0174]

[0175]

[0176] ​​​​​​​​​​​​​​​The oxide semiconductor films 31 to 33 are made of metal oxide films containing at least one same metal element. In this way, at the interfaces between the oxide semiconductor film 32 and the oxide semiconductor film 31, and between the oxide semiconductor film 32 and the oxide semiconductor film 33, interface scattering can be made difficult to occur. As a result, the field-effect mobility of the transistor TA1 can be made higher than that of the transistor TA2 or the transistor TB1, and also the drain current (on-current) in the on-state can be increased.

[0177] [Transistor TA2] The transistor TA2 has a gate electrode GE2, a source electrode SE2, a drain electrode DE2, a back gate electrode BGE2, and an oxide semiconductor film OS2. The back gate electrode BGE2 is in contact with the gate electrode GE2 at an opening CG2 that penetrates the insulating films 34 to 36. The transistor TA2 is a modified example of the transistor TA1. It is different from the transistor TA1 in that the oxide semiconductor film OS2 has a single-layer structure in which the oxide semiconductor film is 33, and is otherwise the same. Here, the channel length La2 and the channel width Wa2 of the transistor TA2 are made equal to the channel length La1 and the channel width Wa1 of the transistor TA1.

[0178] [Transistor TB1] The transistor TB1 has a gate electrode GE3, a source electrode SE3, a drain electrode DE3, and an oxide semiconductor film OS3. The transistor TB1 is a modified example of the transistor TA2. Similar to the transistor TA2, the oxide semiconductor film OS3 has a single-layer structure in which the oxide semiconductor film is 33. It is different from the transistor TA2 in that it does not have a back gate electrode. ​​​​​​​This is also the case for the layout of the oxide semiconductor film OS3 and the electrodes (GE3, SE3, DE3). They are different. As shown in Fig. 27(C), the oxide semiconductor film OS3 does not overlap with the gate electrode GE3, and the region that does not overlap is overlapped with either the source electrode SE3 or the drain electrode DE3. Therefore, the channel width Wb1 of the transistor TB1 is determined by the width of the oxide semiconductor film OS3. The channel length Lb1 is determined by the distance between the source electrode SE3 and the drain electrode DE3, similar to the transistor TA2. Here, the channel length La2 of the transistor TA2 is made longer.

[0179] [Insulating film] The insulating films 34, 35, and 36 are films formed over the entire region where the transistors TA1, TA2, and TB1 are formed on the substrate 30. The insulating films 34, 35, and 36 are formed of a single-layer or multiple-layer insulating film. The insulating film 34 is a film that constitutes the gate insulating film of the transistors TA1, TA2, and TB1. Also, the insulating films 35 and 36 are films that constitute the gate insulating film on the back-channel side of the transistors TA1, TA2, and TB1. Further, the topmost insulating film 36 is preferably formed of a material that functions as a protective film for the transistors formed on the substrate 30. The insulating film 36 may be provided as appropriate. To insulate the third-layer electrode (BGE1) from the second-layer electrodes (SE1, DE1), at least one insulating film may be present between them.

[0180] The insulating films 34 to 36 can be formed of a single-layer insulating film or a multi-layer insulating film of two or more layers. As the insulating films constituting these insulating films 34 to 36, aluminum oxide ​​​​​​​​​​​Magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. are given as examples of the film. These insulating films can be formed by sputtering, CVD, MBE, ALD or PLD methods.

[0181] [Oxide semiconductor film] Here, the oxide semiconductor film constituting the semiconductor film of the OS transistor will be described. When the semiconductor film has a multilayer structure like the oxide semiconductor film OS1, the oxide semiconductor films constituting these are preferably metal oxide films containing at least one same metal element, and preferably contain In.

[0182] For example, when the oxide semiconductor film 31 is an In-Ga oxide film, the atomic ratio of In is made smaller than the atomic ratio of Ga. In the case of an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), the atomic ratio of In is made smaller than the atomic ratio of M. In this case, the atomic ratio of Zn can be made the largest.

[0183] For example, when the oxide semiconductor film 32 is an In-Ga oxide film, the atomic ratio of In is made larger than the atomic ratio of Ga. In the case of an In-M-Zn oxide film, the atomic ratio of In is made larger than the atomic ratio of M. In the In-M-Zn oxide film, it is preferable that the atomic ratio of In is larger than the atomic ratios of M and Zn.

[0184] For example, when the oxide semiconductor film 33 is an In-Ga oxide film, the atomic ratio of In is made larger than the atomic ratio of Ga. ​​​​​​​Make it the same as or smaller than the numerical ratio. In the case of the In-M-Zn oxide film, the atomic ratio of In is made the same as the atomic ratio of M. In this case, the atomic ratio of Zn can be larger than those of In and M . Here, the oxide semiconductor film 33 also forms the channel formation regions of the transistors TA2 and transistor TB1.

[0185] When forming the oxide semiconductor films 31 to 33 by sputtering, the atomic ratio of the constituent materials of the target can be adjusted. Also, when forming the films by CVD, it can be achieved by adjusting the flow rate ratio of the source gases . Hereinafter, taking the case of forming an In-M-Zn oxide film by sputtering as an example of the oxide semiconductor films 31 to 33, the targets used for film formation will be described. To form these films, targets made of In-M-Zn oxide are used.

[0186] Assuming that the atomic ratio of the metal elements of the target for the oxide semiconductor film 31 is In:M:Zn = x1:y1: z1, then 、 x1 / y1 is preferably 1 / 6 or more and less than 1. Also, z1 / y 1 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less.

[0187] Typical examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:2, In :M:Zn = 1:3:4, In:M:Zn = 1:3:6, In:M:Zn = 1:3:8, In:M:Zn = 1:4:4, In:M:Zn = 1:4:5, In:M:Zn = 1:4: 6, In:M:Zn = 1:4:7, In:M:Zn = 1:4:8, In:M:Zn = 1: 5:5, In:M:Zn = 1:5:6, In:M:Zn = 1:5:7, In:M:Zn = ​There are cases such as 1:5:8, In:M:Zn = 1:6:8, etc.

[0188] Regarding the atomic ratio of the metal elements of the target of the oxide semiconductor film 32 as In:M:Zn = x2:y2: when it is set as 、 x2 / y2 is preferably greater than 1 and equal to or less than 6. Also, z2 / y2 is preferably greater than 1 and equal to or less than 6. As representative examples of the atomic ratio of the metal elements of the target, In:M:Zn = 2:1:1.5, In:M:Zn = 2:1:2.3, I n:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 3:1:3 There are cases such as In:M:Zn = 3:1:4, etc.

[0189] Regarding the atomic ratio of the metal elements of the target of the oxide semiconductor film 33 as In:M:Zn = x3:y3: when it is set as 、 x3 / y3 is preferably 1 / 6 or more and 1 or less. Also, z3 / y 3 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. As representative examples of the atomic ratio of the metal elements of the target, In:M:Zn = 1:1:1, In:M:Zn = 1 :1:1.2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M: Zn = 1:3:6, In:M:Zn = 1:3:8, In:M:Zn = 1:4:4, In: M:Zn = 1:4:5, In:M:Zn = 1:4:6, In:M:Zn = 1:4:7, I n:M:Zn = 1:4:8, In:M:Zn = 1:5:5, In:M:Zn = 1:5:6 There are cases such as In:M:Zn = 1:5:7, In:M:Zn = 1:5:8, In:M:Zn = 1:6 :8, etc.

[0190] In the target for forming the In-M-Zn oxide film, the atomic ratio of the metal elements is In:M: When Zn = x:y:z, it is preferable to set 1 ≤ z / y ≤ 6 because it facilitates the formation of the CAAC-OS film as the In-M-Zn oxide film. The CAAC-OS film will be described later. For the CAAC-OS film, it will be described later. For the CAAC-OS film, it will be described later.

[0191] As the oxide semiconductor films 31 to 33, an oxide semiconductor film with a low carrier density is used. For example, as the oxide semiconductor films 31 to 33, the carrier density is 1×10 17 per cm 3 or less , preferably 1×10 15 per cm 3 or less, more preferably 1×10 13 per cm 3 or less of the oxide semiconductor film is used. In particular, as the oxide semiconductor films 31 to 33, the carrier density is less than 8×10 11 per cm 3 , more preferably less than 1×10 11 per cm 3 , still more preferably less than 1×10 per cm 10 and is preferably 1×10 3 per cm -9 or more 3 of the oxide semiconductor film is preferably used. By using an oxide semiconductor film with a low impurity concentration and a low defect level density as the oxide semiconductor films 31 to 33, a transistor with even more excellent electrical characteristics can be fabricated. Here, an oxide semiconductor with a low impurity concentration and a low defect level density (low oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has few carrier generation sources, there are cases where the carrier density can be lowered. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film

[0192] By using an oxide semiconductor film with a low impurity concentration and a low defect level density as the oxide semiconductor films 31 to 33, a transistor with even more excellent electrical characteristics can be fabricated. Here, an oxide semiconductor with a low impurity concentration and a low defect level density (low oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has few carrier generation sources, there are cases where the carrier density can be lowered. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film By using an oxide semiconductor film with a low impurity concentration and a low defect level density as the oxide semiconductor films 31 to 33, a transistor with even more excellent electrical characteristics can be fabricated. Here, an oxide semiconductor with a low impurity concentration and a low defect level density (low oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has few carrier generation sources, there are cases where the carrier density can be lowered. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film By using an oxide semiconductor film with a low impurity concentration and a low defect level density as the oxide semiconductor films 31 to 33, a transistor with even more excellent electrical characteristics can be fabricated. Here, an oxide semiconductor with a low impurity concentration and a low defect level density (low oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has few carrier generation sources, there are cases where the carrier density can be lowered. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film By using an oxide semiconductor film with a low impurity concentration and a low defect level density as the oxide semiconductor films 31 to 33, a transistor with even more excellent electrical characteristics can be fabricated. Here, an oxide semiconductor with a low impurity concentration and a low defect level density (low oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has few carrier generation sources, there are cases where the carrier density can be lowered. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film By using an oxide semiconductor film with a low impurity concentration and a low defect level density as the oxide semiconductor films 31 to 33, a transistor with even more excellent electrical characteristics can be fabricated. Here, an oxide semiconductor with a low impurity concentration and a low defect level density (low oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has few carrier generation sources, there are cases where the carrier density can be lowered. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film will be It is less likely to have electrical characteristics (also referred to as normally off) where the threshold voltage is negative. . Further, an oxide semiconductor film that is of high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, so the trap level density may also be low. Further, an oxide semiconductor film that is of high-purity intrinsic or substantially high -purity intrinsic has an extremely small off-current, and even for an element with a channel width of 1×10 6 μ m and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current can be below the measurement limit of a semiconductor parameter analyzer, i.e., 1×10 -13 A or less. Therefore, , a transistor in which a channel region is formed in the oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Impurities include hydrogen, nitrogen, alkali metals, , or alkaline earth metals, etc.

[0193] Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to form water, and at the same time, oxygen vacancies are formed in the lattice from which oxygen has desorbed (or the part from which oxygen has desorbed). When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Also, in some cases, a part of hydrogen binds to oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally off characteristics. Therefore, it is preferable that the oxide semiconductor films 31 to 33 have as little hydrogen as possible along with oxygen vacancies. Specifically, in the oxide semiconductor films 31 to 33, secondary ion mass spectrometry

[0194] For this reason, it is preferable that the oxide semiconductor films 31 to 33 have as little hydrogen as possible along with oxygen vacancies. Specifically, in the oxide semiconductor films 31 to 33, secondary ion mass The hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 5×10 or less, more preferably 19 atoms / cm 3 1×10 or less, more preferably 5×10 19 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 less, more preferably 1×10 18 atoms / cm 3 or less, more preferably 5×10 1 7 atoms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or less.

[0195] When the oxide semiconductor films 31 to 33 contain silicon or carbon, which is one of the Group 14 elements, the oxygen deficiency in the films increases, and these films become n-type. Therefore, the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) in the oxide semiconductor films 3 1 to 33 is 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0196] Also, in the oxide semiconductor films 31 to 33, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. Alkali metals and alkaline earth metals ​A genus may generate carriers when combined with an oxide semiconductor, which may increase the off-current of a transistor. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor films 31 to 33. When nitrogen is contained in the oxide semiconductor films 31 to 33, electrons as carriers are generated, the carrier density increases, and it tends to be n-type. Therefore, a transistor using an oxide semiconductor containing nitrogen tends to have normal-on characteristics, so the nitrogen content of the oxide semiconductor films 31 to 33 is preferably reduced as much as possible. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5×10 or less.

[0197] As described above for the oxide semiconductor films 31 to 33, the present invention is not limited thereto, and an oxide semiconductor film having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics and electrical characteristics of the required transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor films 31 to 33 are preferably made appropriate. As described above for the oxide semiconductor films 31 to 33, the present invention is not limited thereto, and an oxide semiconductor film having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics and electrical characteristics of the required transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor films 31 to 33 are preferably made appropriate. Since the transistor TA1 has a channel formed in the oxide semiconductor film 32 in which the atomic ratio of In is larger than the atomic ratio of Ga or M (M is Al, Ga, Y, Zr, La, Ce, or Nd), the field effect mobility can be increased. Typically, the field effect mobility is greater than 10 cm 18 / Vs and less than 60 cm 3 / Vs.

[0198] As described above for the oxide semiconductor films 31 to 33, the present invention is not limited thereto, and an oxide semiconductor film having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics and electrical characteristics of the required transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor films 31 to 33 are preferably made appropriate. As described above for the oxide semiconductor films 31 to 33, the present invention is not limited thereto, and an oxide semiconductor film having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics and electrical characteristics of the required transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor films 31 to 33 are preferably made appropriate. As described above for the oxide semiconductor films 31 to 33, the present invention is not limited thereto, and an oxide semiconductor film having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics and electrical characteristics of the required transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor films 31 to 33 are preferably made appropriate. As described above for the oxide semiconductor films 31 to 33, the present invention is not limited thereto, and an oxide semiconductor film having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics and electrical characteristics of the required transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor films 31 to 33 are preferably made appropriate. As described above for the oxide semiconductor films 31 to 33, the present invention is not limited thereto, and an oxide semiconductor film having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics and electrical characteristics of the required transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor films 31 to 33 are preferably made appropriate. As described above for the oxide semiconductor films 31 to 33, the present invention is not limited thereto, and an oxide semiconductor film having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics and electrical characteristics of the required transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor films 31 to 33 are preferably made appropriate.

[0199] The transistor TA1 has a channel formed in the oxide semiconductor film 32 in which the atomic ratio of In is larger than the atomic ratio of Ga or M (M is Al, Ga, Y, Zr, La, Ce, or Nd), so the field effect mobility can be increased. Typically, the field effect mobility is greater than 10 cm / Vs and less than 60 cm 2 / Vs. 2Less than / Vs, preferably 15 cm 2 Greater than or equal to / Vs 50 cm 2 It is less than / Vs. Therefore, when the transistor TA1 is used in the circuit of the active matrix display device, it is suitable for a drive circuit that requires high-speed operation.

[0200] Also, the transistor TA1 is preferably provided in a shaded area. Also, by providing the transistor TA1 having a high field-effect mobility in the drive circuit, the drive frequency can be increased, so that a higher-definition display device can be realized.

[0201] The transistors TA2 and TB1 whose channel formation regions are formed of the oxide semiconductor film 33 have a lower field-effect mobility than the transistor TA1, and their size is 3 cm 2 Greater than or equal to / Vs and 10 cm 2 Less than or equal to / Vs. Since the transistors TA2 and TB1 do not have the oxide semiconductor film 32, they are less likely to be deteriorated by light than the transistor TA1, and the increase amount of the off-current due to light irradiation is small. Therefore, the transistors TA2 and TB1 whose channel formation regions are formed of the oxide semiconductor film 33 are suitable for pixel portions where light is irradiated.

[0202] Compared with the transistors TA2 and TB1 that do not have the oxide semiconductor film 32, the transistor TA1 is more likely to increase the current in the off state when irradiated with light. This is one of the reasons why the transistor TA1 is more suitable for the peripheral drive circuit where the influence of light is less than that in the pixel portion where sufficient light shielding cannot be achieved. Also, of course, transistors having the same configuration as the transistors TA2 and TB1 can also be provided in the drive circuit.

[0203] As described above, transistors TA1, TA2, TB1 and oxide semiconductor films 31 to 33 have been described. However, the present invention is not limited thereto, and the configuration of the transistor may be changed according to the required semiconductor characteristics and electrical characteristics of the transistor. For example, the presence or absence of a back gate electrode, the laminated structure of the oxide semiconductor film, the shapes of the oxide semiconductor film, the gate electrode, the source electrode, and the drain electrode, and the arrangement and the like can be appropriately changed.

[0204] [Structure of Oxide Semiconductor] Next, the structure of the oxide semiconductor will be described.

[0205] In the present specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0206] In the present specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system.

[0207] The oxide semiconductor film can be divided into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. Alternatively, the oxide semiconductor can be divided into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor.

[0208] Note that, as the non-single crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide There are semiconductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, etc. Also, as crystalline oxide semiconductors there are single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, etc.

[0209] First, the CAAC-OS film will be described.

[0210] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction.

[0211] By using a transmission electron microscope (TEM: Transmission Electron Micro scope), a plurality of crystal parts can be confirmed by observing a composite analysis image of a bright-field image and a diffraction pattern of the CAAC-OS film ( also referred to as a high-resolution TEM image).) On the other hand, even by a high-resolution TEM image, a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary), cannot be confirmed. Therefore, it can be said that the CAAC-OS film is less likely to cause a decrease in electron mobility due to grain boundaries.

[0212] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction substantially parallel to the sample surface, in the crystal part, it can be confirmed that metal atoms are arranged in layers. Each layer of metal atoms is a shape that reflects the unevenness of the surface (also referred to as the film-forming surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the film-forming surface or the upper surface of the CAAC-OS film.

[0213] On the other hand, when observing a high-resolution TEM image of the plane of the CAAC-OS film from a direction substantially perpendicular to the sample surface, in the crystal part, it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape.​​​ It can be cut. However, no regularity is observed in the arrangement of metal atoms between different crystal parts.

[0214] When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) device for example, in the out-of-plane method analysis of a CAAC-OS film having InGaZnO4 crystals peaks may appear near a diffraction angle (2θ) of 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal Therefore, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0215] In addition, in the out-of-plane method analysis of a CAAC-OS film having InGaZnO4 crystals in addition to the peak near 2θ of 31°, peaks may also appear near 2θ of 36°. The peak near 2θ of 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation. It is preferable that the CAAC-OS film shows a peak near 2θ of 31° and does not show a peak near 2θ of 36°.

[0216] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, transition metal elements, etc. In particular, elements with a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, such as silicon will disrupt the atomic arrangement of the oxide semiconductor film and reduce the crystallinity by taking oxygen from the oxide semiconductor film. Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they will (or molecular radius), so when contained inside the oxide semiconductor film, they will It disrupts the atomic arrangement and becomes a factor in reducing crystallinity. Note that impurities contained in the oxide semiconductor film may serve as carrier traps or carrier generation sources.

[0217] Also, the CAAC-OS film is an oxide semiconductor film with a low density of defect levels. For example, oxygen deficiencies in the oxide semiconductor film may serve as carrier traps or become carrier generation sources by capturing hydrogen.

[0218] A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier traps of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0219] Also, a transistor using the CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0220] Next, the microcrystalline oxide semiconductor film will be described.

[0221] In a high-resolution TEM image, the microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is called an nc- OS (nanocrystalline Oxide Semiconductor) film. Also, in a high-resolution TEM image, for example, the nc-OS film may not clearly show crystal grain boundaries. The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, there is no orientation in the whole film. Therefore, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal parts, no peak indicating a crystal plane is detected in the out-of-plane method analysis.

[0222] Also, when performing electron diffraction (also called limited field of view electron diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal parts (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, for the nc-OS film, when using a nano-beam electron beam with a probe diameter close to or smaller than the size of the crystal parts, a diffraction pattern is observed. However, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal parts, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, when performing electron diffraction (also called limited field of view electron diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal parts (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, for the nc-OS film, when using a nano-beam electron beam with a probe diameter close to or smaller than the size of the crystal parts, a diffraction pattern is observed. When performing electron diffraction (also called limited field of view electron diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal parts (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, for the nc-OS film, when using a nano-beam electron beam with a probe diameter close to or smaller than the size of the crystal parts, a diffraction pattern is observed. When diffraction is performed, spots are observed. Also, when nano-beam electron diffraction is performed on the nc-OS film, bright regions may be observed in a circular (ring-shaped) pattern. Also, when nano-beam electron diffraction is performed on the nc-OS film, multiple spots may be observed within the ring-shaped region.

[0223] The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect energy levels than the amorphous oxide semiconductor film. However, the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, the nc-O S film has a higher density of defect energy levels than the CAAC-OS film.

[0224] Next, the amorphous oxide semiconductor film will be described.

[0225] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal parts. An example is an oxide semiconductor film having an amorphous state such as quartz.

[0226] In a high-resolution TEM image, crystal parts cannot be confirmed in the amorphous oxide semiconductor film.

[0227] When structural analysis is performed on the amorphous oxide semiconductor film using an XRD apparatus, no peaks indicating crystal planes are detected in the out-of-plane method analysis. Also, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Also, when nano-beam electron diffraction is performed on the amorphous oxide semiconductor film, no spots are observed and a halo pattern is observed. When nano-beam electron diffraction is performed on the amorphous oxide semiconductor film, no spots are observed and a halo pattern is observed.

[0228] Note that the oxide semiconductor film may have a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film. In some cases, voids may be observed in the high-resolution TEM image of the a-like OS film. Also, in the high-resolution TEM image, there are regions where crystal parts can be clearly confirmed and regions where crystal parts cannot be confirmed. The a-like OS film may undergo crystallization and crystal growth may be observed by a small amount of electron irradiation at the level of observation by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization by a small amount of electron irradiation at the level of observation by TEM is hardly observed.

[0229]

[0230] Note that the size of the crystal parts of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, the crystal of InGaZnO4 has a layered structure and has two Ga-Zn-O layers between In-O layers. The unit cell of the crystal of InGaZnO4 has three In-O layers and six Ga-Zn-O layers, for a total of nine layers stacked in a layered manner in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice plane spacing (also referred to as the d value) of the (009) plane, and the value has been determined to be 0.29 nm from crystal structure analysis. Therefore, by focusing on the lattice fringes in the high-resolution TEM image, at locations where the distance between the lattice fringes is 0.28 nm or more and 0.30 nm or less, each lattice fringe corresponds to the a-b plane of the crystal of InGaZnO4.​​​​​​​​​​​​​​​​

[0231] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the membrane is known, the density can be determined by comparing it with that of a single crystal of the same composition. The structure of the oxide semiconductor film can be estimated. The density of the OS-like film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film was 92.3% or more. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is The film formation itself is difficult.

[0232] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor film that satisfies the [number ratio], single crystal InGaZnO4 with a rhombohedral crystal structure The density of is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1 In the oxide semiconductor film that satisfies the atomic ratio, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1: In the oxide semiconductor film that satisfies the atomic ratio of 1, the density and CAAC- The density of the OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0233] In some cases, single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. , it may be calculated using a weighted average. However, the density is preferably calculated by combining as few types of single crystals as possible. It is preferable to calculate by combining.

[0234] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. It may be a laminated film having two or more of them.

[0235] As described above, the OS transistor can achieve extremely excellent off-current characteristics.

[0236] [Substrate 30] As the substrate 30, various substrates can be used and are not limited to specific ones. As an example of the substrate 30, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), a SO I substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate , a substrate having a stainless steel foil, a tungsten substrate, a tungsten foil substrate, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film There are films and the like. As an example of the glass substrate, there are barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of the flexible substrate, the laminated film, the base film, etc. include the following. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES) and other plastics. Or, as an example, there are synthetic resins such as acrylic. Or, as an example, there are polypropylene, polyester, polyvinyl fluoride , or polyvinyl chloride. Or, as an example, there are polyamide, poly . Or, as an example, there are polypropylene, polyester, polyvinyl fluoride or polyvinyl chloride. Or, as an example, there are polyamide, poly vinyl chloride, or polyvinyl chloride. Or, as an example, there are polyamide, poly There are imides, aramids, epoxies, inorganic vapor deposition films, or papers, etc. In particular, for manufacturing transistors by using a semiconductor substrate, a single crystal substrate, or a SOI substrate, etc., transistors with less variation in characteristics, size, or shape, high current capacity, and small size can be manufactured. By configuring a circuit with such transistors, low power consumption of the circuit or high integration of the circuit can be achieved.

[0237] Before forming the gate electrodes GE1 to GE3, a base insulating film may be formed on the substrate 30. Examples of the base insulating film include silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, etc. Note that by using silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, etc. as the base insulating film, impurities (typically alkali metals, water, hydrogen, etc.) can be prevented from diffusing from the substrate 30 into the oxide semiconductor films OS1 to OS3. (Typically, alkali metals, water, hydrogen, etc.) diffusion can be suppressed.

[0238] [Gate electrodes GE1, GE2, GE3] The gate electrodes GE1 to GE3 are a single-layer conductive film or a film having a multilayer structure in which two or more conductive films are laminated. The conductive film formed as the gate electrodes GE1 to GE3 is a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements, etc. can be used for formation. Also, one or more metal elements selected from manganese and zirconium may be used. Further, titanium, tantalum, or tungsten may be added to aluminum. ​An alloy film or a nitride film composed of one or more selected from tungsten, molybdenum, chromium, neodymium, and scandium may be used. Also, a conductive material having translucency such as indium tin oxide, indium oxide containing tantalum tungsten, indium zinc oxide containing tantalum tungsten, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon oxide, etc. can be applied. For example, as the gate electrodes GE1 to GE3, an aluminum film containing silicon can be formed. When the gate electrodes GE1 to GE3 have a two-layer structure, for example, a titanium film is formed on an aluminum film, a titanium film is formed on a titanium nitride film, a tungsten film is formed on a titanium nitride film, or a tungsten film is formed on a tantalum nitride film or a tungsten nitride film. When the gate electrodes GE1 to GE3 have a three-layer structure, for example, a titanium film, an aluminum film is laminated on the titanium film, and then a titanium film is formed thereon. The gate electrodes GE1 to GE3 are formed by a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. In addition, the tungsten film can be formed by a film forming apparatus using ALD. In this case, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then a tungsten film is formed using WF6 gas and H2 gas. Note that SiH4 gas may be used instead of B2H6 gas.

[0239] For example, as the gate electrodes GE1 to GE3, an aluminum film containing silicon can be formed. When the gate electrodes GE1 to GE3 have a two-layer structure, for example, a titanium film is formed on an aluminum film, a titanium film is formed on a titanium nitride film, a tungsten film is formed on a titanium nitride film, or a tungsten film is formed on a tantalum nitride film or a tungsten nitride film. When the gate electrodes GE1 to GE3 have a three-layer structure, for example, a titanium film, an aluminum film is laminated on the titanium film, and then a titanium film is formed thereon. The gate electrodes GE1 to GE3 are formed by a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. In addition, the tungsten film can be formed by a film forming apparatus using ALD. In this case, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then a tungsten film is formed using WF6 gas and H2 gas. Note that SiH4 gas may be used instead of B2H6 gas. For example, as the gate electrodes GE1 to GE3, an aluminum film containing silicon can be formed. When the gate electrodes GE1 to GE3 have a two-layer structure, for example, a titanium film is formed on an aluminum film, a titanium film is formed on a titanium nitride film, a tungsten film is formed on a titanium nitride film, or a tungsten film is formed on a tantalum nitride film or a tungsten nitride film.

[0240] The gate electrodes GE1 to GE3 are formed by a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. In addition, the tungsten film can be formed by a film forming apparatus using ALD. In this case, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then a tungsten film is formed using WF6 gas and H2 gas. Note that SiH4 gas may be used instead of B2H6 gas.

[0241] In addition, the tungsten film can be formed by a film forming apparatus using ALD. In this case, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then a tungsten film is formed using WF6 gas and H2 gas. Note that SiH4 gas may be used instead of B2H6 gas. In this case, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then a tungsten film is formed using WF6 gas and H2 gas. Note that SiH4 gas may be used instead of B2H6 gas. In addition, the tungsten film can be formed by a film forming apparatus using ALD. In this case, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then a tungsten film is formed using WF6 gas and H2 gas. Note that SiH4 gas may be used instead of B2H6 gas.

[0242] In addition to the above-described formation method, the gate electrodes GE1 to GE3 can be formed by an electrolytic plating method, a printing method, an inkjet method, or the like.

[0243] [Insulating film 34 (gate insulating film)] An insulating film 34 is formed to cover the gate electrodes GE1 to GE3. The insulating film 34 is a single-layer insulating film or an insulating film having a multilayer structure of two or more layers. The insulating film formed as the insulating film 34 includes an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitroxide insulating film. In this specification, an oxynitride is a material having a higher oxygen content than nitrogen, and a nitride oxide is a material having a higher nitrogen content than oxygen.

[0244] Examples of the insulating film formed as the insulating film 34 include an insulating film made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or a Ga-Zn-based metal oxide. Also, as such an insulating film, a film made of a high-k material such as hafnium silicate (HfSiO x ) in which nitrogen is added to hafnium silicate (HfSi x O y N z ), hafnium aluminate (Hf Al x O y N z ) in which nitrogen is added, hafnium oxide, yttrium oxide, or the like can be formed. By using a high-k material, the gate leakage of the transistor can be reduced.

[0245] The insulating film 34 has a function as a gate insulating film. The oxide semiconductor films OS1 to OS3 and the gate In order to improve the interface characteristics with the gate insulating film, in the insulating film 34, the region in contact with the oxide semiconductor films OS1 to OS3 is preferably formed of an oxide insulating film or a silicon oxynitride insulating film. For example, the topmost film of the insulating film 34 may be a silicon oxide film or a silicon oxynitride film.

[0246] The thickness of the insulating film 34 may be, for example, 5 nm or more and 400 nm or less. The thickness is preferably 10 nm or more and 300 nm or less, and more preferably 50 nm or more and 250 nm or less.

[0247] When forming the oxide semiconductor films OS1 to OS3 by sputtering, a power supply device for generating plasma can be appropriately used, such as an RF power supply device, an AC power supply device, or a DC power supply device.

[0248] As the sputtering gas, a noble gas (typically argon), oxygen, or a mixed gas of a noble gas and oxygen can be appropriately used. In the case of a mixed gas of a noble gas and oxygen, it is preferable to increase the gas ratio of oxygen with respect to the noble gas.

[0249] Also, the target may be appropriately selected according to the composition of the oxide semiconductor films OS1 to OS3 to be formed.

[0250] When using sputtering to form the oxide semiconductor films OS1 to OS3, by setting the substrate temperature to 150°C or more and 750°C or less, preferably 150°C or more and 450°C or less, and more preferably 200°C or more and 350°C or less, a CAA-C-OS film can be formed as the oxide semiconductor films 31 to 33.

[0251] In addition, in order to form the CAAC-OS film, it is preferable to apply the following conditions.

[0252] By suppressing the incorporation of impurities during film formation, it is possible to suppress the disruption of the crystal state by the impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber may be reduced. Also, the impurity concentration in the film formation gas may be reduced. Specifically, a film formation gas with a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0253] In addition, it is preferable to reduce the plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the power. The oxygen ratio in the film formation gas is preferably 30% by volume or more, more preferably 100% by volume.

[0254] By forming the film while heating the oxide semiconductor film, or by performing a heat treatment after forming the oxide semiconductor film, the hydrogen concentration in the oxide semiconductor film can be made 2×10 20 atoms / cm 3 19 atoms / cm 3 19 at oms / cm 3 18 atoms / cm 3 18 atoms / cm 3 17 atoms / c m 3 16 atoms / cm 3 or less, and more preferably 1×10

[0255] ​​​​​​​​​​​​​Note that the heat treatment is carried out at a temperature higher than 350°C and not higher than 650°C, preferably 450°C or higher and 600°C or lower, so that the CAAC conversion rate described later is 70% or higher and less than 100%, preferably 80% or higher and less than 100%, preferably 90% or higher and less than 100%, more preferably 95% or higher and 98 % or lower, and an oxide semiconductor film can be obtained. Further, an oxide semiconductor film with a reduced content of hydrogen, water, etc. can be obtained. That is, an oxide semiconductor film with a low impurity concentration and a low defect level density can be formed.

[0256] An oxide semiconductor film can be formed by a film forming apparatus using ALD. For example, when forming an InG aZnO X (X>0) film, In(CH3)3 gas and O3 gas are sequentially introduced repeatedly to form an InO2 layer, and then, Ga(CH3)3 gas and O3 gas are used to form a GaO layer, and further, Zn(CH3)2 gas and O3 gas are used to form a ZnO layer . Note that the order of these layers is not limited to this example. Also, these gases can be mixed to form a mixed compound layer such as an InGaO2 layer, an InZnO2 layer, a GaInO layer, a ZnInO layer, a GaZnO layer. Note that instead of O3 gas, H 2O gas bubbled with an inert gas such as Ar can be used, but it is preferable to use O3 gas not containing H. Also, instead of In( CH3)3 gas, In(C2H5)3 gas can be used. Also, instead of Ga(CH3 )3 gas, Ga(C2H5)3 gas can be used. Also, Zn(CH3)2 gas can be used.

[0257] The oxide semiconductor film 32 and the oxide semiconductor film 33 are formed with a transistor channel It is a film, and its film thickness can be 3 nm or more and 200 nm or less. These thicknesses are , preferably 3 nm or more and 100 nm or less, and more preferably 30 nm or more and 50 nm or less. The film thickness of the oxide semiconductor film 31 can be, for example, 3 nm or more and 100 nm or less and is preferably 3 nm or more and 30 nm or less, and more preferably 3 nm or more and 15 nm or less. The oxide semiconductor film 31 is preferably formed thinner than the oxide semiconductor film 32 and the oxide semiconductor film 33.

[0258] Here, as the oxide semiconductor films 31 to 33, an In-Ga-Zn film is formed by sputtering. The atomic ratio of the metal elements of the target used for these film formations (In:Ga: Zn) is, for example, 1:3:6 for the oxide semiconductor film 31, 3: 1:2 for the oxide semiconductor film 32, and the oxide semiconductor film 33 can be 1:1:1.2 or 1:1:1. Also, the thicknesses of the oxide semiconductor films 31, 32, and 33 can be 5 nm, 35 nm, and 35 nm, respectively.

[0259] [Source electrode, drain electrode] The source electrode and the drain electrode (SE1, DE1, SE2, DE2, SE3, DE3) can be formed in the same manner as the gate electrodes GE1 to GE3.

[0260] For example, by laminating these films in the order of a copper-manganese alloy film with a thickness of 50 nm, a copper film with a thickness of 400 nm, and a copper-manganese alloy film with a thickness of 100 nm by sputtering, a source electrode and a drain electrode having a three-layer structure can be formed.

[0261] [Insulating films 35, 36] As the insulating film 35, an insulating film having a two-layer structure can be formed. Here, the first-layer film of the insulating film 35 will be referred to as the insulating film 35a, and the second-layer film will be referred to as the insulating film 35b.

[0262] As the insulating film 35a, for example, an oxide insulating film made of silicon oxide or the like, or an oxide insulating film containing nitrogen and having a small amount of defects can be formed. Representative examples of the oxide insulating film containing nitrogen and having a small amount of defects include a silicon oxynitride film and an aluminum oxynitride film and the like.

[0263] In the spectrum obtained by measuring with an ESR of 100 K or less, the oxide insulating film with few defects has a first signal with a g value of 2.037 or more and 2.039 or less, a second signal with a g value of 2.001 or more and 2. 003 or less, and a third signal with a g value of 1.964 or more and 1.966 or less is observed. Note that the split widths of the first signal and the second signal, and the split widths of the second signal and the third signal are approximately 5 mT in the X-band ESR measurement . Also, the sum of the spin densities of the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the third signal with a g value of 1.964 or more and 1.96 6 or less is less than 1×10 18 spins / cm 3 and typically is 1×10 17 spins / cm or more and less than 1×10 3 spins / cm 18 3

[0264] m 3 .

[0264] Note that in the ESR spectrum at 100 K or less, the g value is 2.037 or more and 2.039 or less The first signal, the second signal with a g-value of 2.001 or more and 2.003 or less, and the third signal with a g-value of 1 .964 or more and 1.966 or less correspond to signals caused by nitrogen oxides (NOx, where x is greater than 0 and less than or equal to 2, preferably 1 or more and 2 or less). Representative examples of nitrogen oxides include nitric oxide, nitrogen dioxide, etc. That is, the first signal with a g-value of 2.037 or more and 2.039 or less, the second signal with a g-value of 2.001 or more and 2.003 or less, and the third signal with a g-value of 1.964 or more and 1.966 or less, the smaller the total spin density of the signals, the lower the content of nitrogen oxides contained in the oxide insulating film can be said.

[0265] Since the insulating film 35a is a film with a low content of nitrogen oxides, it is possible to reduce the carrier trap at the interface between the insulating film 35a and the oxide semiconductor films OS1 to OS3. As a result, it is possible to reduce the shift of the threshold voltage of the transistor, and the variation in the electrical characteristics of the transistor can be reduced.

[0266] Also, for improving the reliability of the transistor, the insulating film 35a preferably has a nitrogen concentration measured by SIMS (Secondary Ion Mass Spectrometry) of 6×10 2 0 / cm 3 or less. This is because it is difficult for nitrogen oxides to be generated in the insulating film 35 a during the manufacturing process of the transistor.

[0267] As an example of an oxide insulating film containing nitrogen and having a small amount of defects as the insulating film 35a, a silicon oxynitride film can be formed by the CVD method. In this case, as the source gas, It is preferable to use a depositable gas and an oxidizing gas containing silicon. The depositable gas containing silicon Examples of the depositable gas include silane, disilane, trisilane, silicon fluoride, etc. As the oxidizing gas, there are nitrous oxide, nitrogen dioxide, etc.

[0268] Also, the flow rate of the oxidizing gas is made more than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, compared to the flow rate of the depositable gas, and the pressure in the processing chamber is made less than 100 Pa, preferably 50 Pa or less. By using the CVD method, as the insulating film 35a, an oxide insulating film containing nitrogen and having a small defect amount can be formed.

[0269] As the insulating film 35b, for example, an oxide insulating film containing more oxygen (excess oxygen ) than oxygen satisfying the stoichiometric composition can be used. In the oxide insulating film containing the above excess oxygen a part of oxygen desorbs by heating. In the oxide insulating film containing the above excess oxygen, by TDS analysis the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 3.0×10 20 atoms / cm 3 or more. Note that during the above TDS analysis the surface temperature of the film is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 500°C or less.

[0270] As the insulating film 35b, silicon oxide, silicon oxynitride, etc. having a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 4 00 nm or less can be used. When using a silicon oxynitride film containing excess oxygen as the insulating film 35 b, it can be formed by using the CVD method.

[0271] ​​​ When forming a silicon oxide film or a silicon oxynitride film as the insulating film 35b, film formation can be carried out under the following conditions. A substrate placed in the evacuated processing chamber of a plasma CVD apparatus is held at 180°C or higher and 280°C or lower, more preferably 200°C or higher and 240°C or lower. A source gas is introduced into the processing chamber to set the pressure in the processing chamber to 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower. High-frequency power of 0.17 W / cm or higher and 0.5 W / cm or lower, more preferably 0.25 W / cm or higher and 0.35 W / cm or lower is supplied to the electrode provided in the processing chamber. 2 2 2 2

[0272] As the insulating film 36, at least a film having a blocking effect on hydrogen and oxygen is used. Further, preferably, it has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Typically, a nitride insulating film such as silicon nitride may be formed. In addition to the silicon nitride film, a silicon oxynitride film, an aluminum nitride film, an aluminum oxynitride film, etc. can also be used.

[0273] Further, an oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc. may be provided as the film constituting the insulating film 36. Examples of such an oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc.

[0274] Also, the thickness of the insulating film 36 may be 50 nm or more and 300 nm or less, preferably 100​​​​​​​​​​​It is 200 nm or less and more than 200 nm. By forming the insulating film 36 having a blocking effect against oxygen, hydrogen, water, etc., diffusion of oxygen from the oxide semiconductor films 31 to 33 to the outside is prevented. and intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor films 31 to 33 can be prevented.

[0275] When forming a silicon nitride film by plasma CVD as the insulating film 36, it is preferable to use a silicon-containing depositable gas, nitrogen, and ammonia as source gases. By using these source gases, ammonia dissociates in the plasma and active species are generated. The active species break the bonds between silicon and hydrogen contained in the silicon-containing depositable gas and the triple bond of nitrogen. As a result, the bond between silicon and nitrogen is promoted, the bond between silicon and hydrogen is reduced, the defects are reduced, and a dense silicon nitride film can be formed. On the other hand, if the amount of ammonia relative to nitrogen in the source gas is large, the decomposition of the silicon-containing depositable gas and nitrogen respectively does not proceed, the silicon and hydrogen bonds remain, and the defects increase, and a rough silicon nitride film is formed. For these reasons, in the source gas, it is preferable to set the flow rate ratio of nitrogen to ammonia to 5 or more and 50 or less, preferably 10 or more and 50 or less. After forming the insulating film 35, a heat treatment may be performed. The temperature of the heat treatment is typically 150 °C or more and less than the substrate distortion point, preferably 200 °C or more and 450 °C or less, more preferably 3 00 °C or more and 450 °C or less. By the heat treatment, oxygen contained in the oxide insulating film constituting the second layer of the insulating film 35 is moved to the oxide semiconductor films 31 to 33 and contained therein.

[0276] The resulting oxygen deficiency can be reduced. The heat treatment may be performed, for example, in a mixed gas atmosphere containing nitrogen and oxygen at a heating temperature of 350°C and a heating time of 1 hour. The heat treatment may be performed, for example, in a mixed gas atmosphere containing nitrogen and oxygen at a heating temperature of 350°C and a heating time of 1 hour.

[0277] Further, after forming the insulating film 36, heat treatment may be performed for the purpose of releasing hydrogen or the like from the oxide semiconductor films 31 to 33. This heat treatment may be performed, for example, in a mixed gas atmosphere containing nitrogen and oxygen at a heating temperature of 350°C and a heating time of 1 hour. Further, after forming the insulating film 36, heat treatment may be performed for the purpose of releasing hydrogen or the like from the oxide semiconductor films 31 to 33. This heat treatment may be performed, for example, in a mixed gas atmosphere containing nitrogen and oxygen at a heating temperature of 350°C and a heating time of 1 hour. The heat treatment may be performed, for example, in a mixed gas atmosphere containing nitrogen and oxygen at a heating temperature of 350°C and a heating time of 1 hour.

[0278] [Back Gate Electrode] The back gate electrodes BGE1 and BGE2 can be formed in the same manner as the gate electrodes GE1 to GE3. The back gate electrodes BGE1 and BGE2 can be formed in the same manner as the gate electrodes GE1 to GE3.

[0279] Hereinafter, some other configuration examples of the transistor will be shown.

[0280] (Transistors TA3, TA4) Top views (layout diagrams) of the transistor TA3 and the transistor TA4, and their circuit symbols are shown in FIGS. 29(A) and (B), respectively. Cross-sectional views taken along lines a7-a8 and b7-b8 of the transistor TA3, and cross-sectional views taken along lines a9-a10 and b9-b10 of the transistor TA4 are shown in FIGS. 30(A) and (B). (Layout diagrams) of the transistor TA3 and the transistor TA4, and their circuit symbols are shown in FIGS. 29(A) and (B), respectively. Cross-sectional views taken along lines a7-a8 and b7-b8 of the transistor TA3, and cross-sectional views taken along lines a9-a10 and b9-b10 of the transistor TA4 are shown in FIGS. 30(A) and (B). The transistor TA3 has a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, a drain electrode DE4, and a back gate electrode BGE4. The transistor TA3 is a modified example of the transistor TA1. The difference from the transistor TA1 is that the back gate electrode BGE4 is in contact with the gate electrode GE4 at two openings CG4 and CG5. Otherwise, it is the same as the transistor TA1. As shown in FIG. 30(B), in the channel width direction, the acid The transistor TA3 has a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, a drain electrode DE4, and a back gate electrode BGE4. The transistor TA3 is a modified example of the transistor TA1. The difference from the transistor TA1 is that the back gate electrode BGE4 is in contact with the gate electrode GE4 at two openings CG4 and CG5. Otherwise, it is the same as the transistor TA1. As shown in FIG. 30(B), in the channel width direction, the acid

[0281] The transistor TA3 has a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, a drain electrode DE4, and a back gate electrode BGE4. The transistor TA3 is a modified example of the transistor TA1. The difference from the transistor TA1 is that the back gate electrode BGE4 is in contact with the gate electrode GE4 at two openings CG4 and CG5. Otherwise, it is the same as the transistor TA1. As shown in FIG. 30(B), in the channel width direction, the acid The transistor TA3 has a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, a drain electrode DE4, and a back gate electrode BGE4. The transistor TA3 is a modified example of the transistor TA1. The difference from the transistor TA1 is that the back gate electrode BGE4 is in contact with the gate electrode GE4 at two openings CG4 and CG5. Otherwise, it is the same as the transistor TA1. As shown in FIG. 30(B), in the channel width direction, the acid The transistor TA3 has a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, a drain electrode DE4, and a back gate electrode BGE4. The transistor TA3 is a modified example of the transistor TA1. The difference from the transistor TA1 is that the back gate electrode BGE4 is in contact with the gate electrode GE4 at two openings CG4 and CG5. Otherwise, it is the same as the transistor TA1. As shown in FIG. 30(B), in the channel width direction, the acid The transistor TA3 has a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, a drain electrode DE4, and a back gate electrode BGE4. The transistor TA3 is a modified example of the transistor TA1. The difference from the transistor TA1 is that the back gate electrode BGE4 is in contact with the gate electrode GE4 at two openings CG4 and CG5. Otherwise, it is the same as the transistor TA1. As shown in FIG. 30(B), in the channel width direction, the acid The transistor TA3 has a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, a drain electrode DE4, and a back gate electrode BGE4. The transistor TA3 is a modified example of the transistor TA1. The difference from the transistor TA1 is that the back gate electrode BGE4 is in contact with the gate electrode GE4 at two openings CG4 and CG5. Otherwise, it is the same as the transistor TA1. As shown in FIG. 30(B), in the channel width direction, the acid The oxide semiconductor film OS4 is surrounded by the gate electrode GE4 and the back gate electrode BGE4, and the intensity of the transistor TA3 can be further improved.

[0282] The transistor TA4 has a gate electrode GE5, an oxide semiconductor film OS5, a source electrode SE5, a drain electrode DE5, and a back gate electrode BGE5. The transistor TA4 is a modified example of the transistor TA2, and the back gate electrode BGE5 is not connected to the gate electrode GE5, and different signals or potentials can be input to the back gate electrode BGE5 with respect to the gate electrode GE5. For example, a signal for controlling the conduction state of the transistor TA4 is input to the gate electrode GE5, and a signal or potential for correcting the threshold voltage of the transistor TA4 can be input to the back gate electrode BGE5.

[0283] (Transistors TC1, TB2, TD1) FIGS. 31(A) to (C) show top views (layout diagrams) of the transistors TC1, TB2, and TD1, respectively, and their circuit symbols. FIGS. 32(A) , (B) show cross-sectional views of the transistor TC1 taken along lines a11 - a12 and b11 - b12, cross-sectional views of the transistor TB2 taken along lines a13 - a14 and b13 - b14, and cross-sectional views of the transistor TD1 taken along lines a15 - a16 and b15 - b16.

[0284] The transistor TC1 has a gate electrode GE6, an oxide semiconductor film OS6, a source electrode SE6, a drain electrode DE6, and a back gate electrode BGE6. The back gate electrode BGE 6 is in contact with the gate electrode GE6 at the opening CG6. The transistor TC1 is a ​This is a modified example of transistor TA1, where the oxide semiconductor film OS6 has a two-layer structure. The oxide semi- conductor film OS6 consists of an oxide semiconductor film 32 and an oxide semiconductor film 33. Transistor TC 1, similar to transistor TA1, is a transistor in which the channel formation region is composed of the oxide semiconductor film 32. Therefore, transistor TC1 is also a transistor with a high field-effect mobility comparable to that of transistor TA1. Typically, the field-effect mobility is greater than 10 cm 2 / V s and less than 60 cm 2 / Vs, preferably greater than or equal to 15 cm 2 / Vs and less than 50 cm 2 / Vs . Thus, transistor TC1 is also suitable for transistors that operate at high speeds, such as in driver circuits, similar to transistor TA1.

[0285] Transistor TB2 has a gate electrode GE7, an oxide semiconductor film OS7, a source electrode SE7, a drain electrode DE7, and a back gate electrode BGE7. The back gate electrode BG E7 is in contact with the gate electrode GE7 at the opening CG7. Transistor TB2 is a modified example of transistor TB1 and is different from transistor TB1 in that it has a back gate electrode BGE7. Since transistor TB2 has a back gate electrode BGE7 connected to the gate electrode GE7, it has a higher on-current and improved mechanical strength compared to transistor TB1.

[0286] Transistor TD1 has a gate electrode GE8, an oxide semiconductor film OS8, a source electrode SE8, and a drain electrode DE8. Transistor TD1 is a modified example of transistor TB1 where the entire oxide semiconductor film OS8 overlaps the gate electrode GE8, and the gate electrode G It does not have a portion outside the end of E8. In this way, since the oxide semiconductor film OS8 of the transistor TD1 has a structure that is less exposed to light than the transistor TB1, it is suitable for the transistors in the pixel portion.

[0287] In addition, like the transistors TA1, TA2, TA3, TC1, and TB2, in the cross-sectional view in the channel width direction, a structure in which the channel formation region (active layer region) is electrically surrounded by the electric fields of the upper and lower gate electrodes is called an s-channel (surrounded channel ) structure. The s-channel structure can allow a large current to flow between the source and drain of the transistor, and can increase the on-current of the transistor.

[0288] Also, an s-channel transistor having an oxide semiconductor in the channel formation region has a small threshold variation for each transistor. In addition, the transistor is resistant to NGBT (Negative Gate Bias Temperature) stress and PGBT ( Positive Gate Bias Temperature) stress. Also, the transistor suppresses DIBL (Drain Induced Barrier Lowering) and is less affected by the short-channel effect. Also, the transistor has a high drain breakdown voltage and shows good saturation characteristics in the Id (drain current)-Vd (drain voltage) characteristics. Also, the transistor has good switching characteristics and has a small subthreshold coefficient in the Id-Vg (gate voltage) characteristics. For a transistor used in a driving circuit of a light-emitting device or the like, a transistor that operates at high speed

[0289] ​ In the case of the STA, it is preferable to shorten the channel length, such as the transistors TA1 and TA2, or the transistors TA3, TA4, and TC1. The channel length of such transistors is preferably less than 2.5 μm. For example, it may be 2.2 μm or less. In the transistors of the present embodiment, since the channel length is determined by the distance between the source electrode and the drain electrode, the minimum value of the channel length is restricted by the accuracy of processing the conductive film serving as the source electrode and the drain electrode. In the transistors of the present embodiment, for example, the channel length can be 0.5 μm or more, or 1.0 μm or more.

[0290] <Example Configuration 2 of Transistor> The transistor used in the display device according to one aspect of the present invention may have a channel formation region on a semiconductor film or a semiconductor substrate such as amorphous, microcrystalline, polycrystalline or single crystal silicon or germanium. When forming a transistor using a thin film of silicon, the thin film may use amorphous silicon produced by a vapor phase growth method such as plasma CVD or sputtering, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single crystal silicon obtained by implanting hydrogen ions or the like into a single crystal silicon wafer and peeling off the surface layer portion, and the like.

[0291] Cross-sectional views of transistors using a silicon film of a thin film that can be used in the display device according to one aspect of the present invention are illustrated in FIGS. 33(A) and (B). In FIGS. 33(A) and (B), an n-channel type transistor 70 and a p-channel type transistor 71 are shown.

[0292] The transistor 70 has, on a substrate 72 having an insulating surface, a conductive film that functions as a gate electrode 73, an insulating film 74 on the conductive film 73, a semi conductor film 75 that overlaps the conductive film 73 with the insulating film 74 interposed therebetween, an insulating film 76 on the semiconductor film 75, and a conductive film 77a and a conductive film 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and that also function as a gate electrode and an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and a conductive film 80 and a conductive film 81 that are electrically connected to the semiconductor film 75 at an opening provided in the insulating films 78 and 79 and that function as a source or a drain The conductive film 77b has a width in the channel length direction that is shorter than that of the conductive film 77a, and the conductive films 77a and 77b are stacked in order from the insulating film 76 side. Further, the semiconductor film 75 has a channel formation region 82 at a position that overlaps the conductive film 77b, a pair of LDD (Light Doped Drain) regions 83 positioned so as to sandwich the channel formation region 82 therebetween, and a pair of impurity regions 84 positioned so as to sandwich the channel formation region 82 and the LDD regions 83 therebetween The pair of impurity regions 84 function as a source region or a drain region. Also, the LDD regions 83 and the impurity regions 84 are doped with an impurity element that imparts an n-type conductivity type to the semiconductor film 75, for example, boron (B), aluminum (Al), gallium (Ga), etc The transistor 71 has, on a substrate 72 having an insulating surface, a conductive film 85 that functions as a gate electrode, an insulating film 74 on the conductive film 85, and a semi

[0293] conductor film that overlaps the conductive film 85 with the insulating film 74 interposed therebetween The conductive film 77b has a width in the channel length direction that is shorter than that of the conductive film 77a, and the conductive films 77a and 77b are stacked in order from the insulating film 76 side. Also, the semiconductor film 75 has a channel formation region 82 at a position that overlaps the conductive film 77b, a pair of LDD (Light Doped Drain) regions 83 positioned so as to sandwich the channel formation region 82 therebetween, and a pair of impurity regions 84 positioned so as to sandwich the channel formation region 82 and the LDD regions 83 therebetween The pair of impurity regions 84 function as a source region or a drain region. Also, the LDD regions 83 and the impurity regions 84 are doped with an impurity element that imparts an n-type conductivity type to the semiconductor film 75, for example, boron (B), aluminum (Al), gallium (Ga), etc The transistor 71 has, on a substrate 72 having an insulating surface, a conductive film 85 that functions as a gate electrode, an insulating film 74 on the conductive film 85, and a semi conductor film that overlaps the conductive film 85 with the insulating film 74 interposed therebetween The pair of impurity regions 84 function as a source region or a drain region. Also, the LDD regions 83 and the impurity regions 84 are doped with an impurity element that imparts an n-type conductivity type to the semiconductor film 75, for example, boron (B), aluminum (Al), gallium (Ga), etc The pair of impurity regions 84 function as a source region or a drain region. Also, the LDD regions 83 and the impurity regions 84 are doped with an impurity element that imparts an n-type conductivity type to the semiconductor film 75, for example, boron (B), aluminum (Al), gallium (Ga), etc The pair of impurity regions 84 function as a source region or a drain region. Also, the LDD regions 83 and the impurity regions 84 are doped with an impurity element that imparts an n-type conductivity type to the semiconductor film 75, for example, boron (B), aluminum (Al), gallium (Ga), etc The pair of impurity regions 84 function as a source region or a drain region. Also, the LDD regions 83 and the impurity regions 84 are doped with an impurity element that imparts an n-type conductivity type to the semiconductor film 75, for example, boron (B), aluminum (Al), gallium (Ga), etc

[0294] The transistor 71 has, on a substrate 72 having an insulating surface, a conductive film 85 that functions as a gate electrode, an insulating film 74 on the conductive film 85, and a semi conductor film that overlaps the conductive film 85 with the insulating film 74 interposed therebetween The semiconductor film 86 to be formed, the insulating film 76 on the semiconductor film 86, and the conductive films 87a and 87b that overlap the semiconductor film 86 with the insulating film 76 interposed therebetween and function as gate electrodes. And the insulating film 78 on the conductive films 87a and 87b, the insulating film 79 on the insulating film 78, and the conductive films 88 and 89 that are electrically connected to the semiconductor film 86 at the openings provided in the insulating film 78 and the insulating film 79 and function as source or drain. The width of the conductive film 87b in the channel length direction is shorter than that of the conductive film 87a, and the conductive films 87a and 87b are laminated in order from the insulating film 76 side. Also, the semiconductor film 75 has a channel formation region 90 at a position overlapping the conductive film 87b, and a pair of impurity regions 91 positioned so as to sandwich the channel formation region 90 therebetween. The pair of impurity regions 91 function as source regions or drain regions. Also, the impurity regions 91 are doped with impurity elements, such as phosphorus (P), arsenic (As), etc., that impart a p-type conductivity type to the semiconductor film 86. Note that the semiconductor film 75 or the semiconductor film 86 may be crystallized by various techniques. As various crystallization methods, there are a laser crystallization method using a laser beam and a crystallization method using a catalyst element.

[0295] Alternatively, it is also possible to use a combination of the crystallization method using a catalyst element and the laser crystallization method. Also, when using a substrate 72 having excellent heat resistance such as quartz, a thermal crystallization method using an electric furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalyst element, or a crystallization method combining a high-temperature annealing at about 950 °C may be used.

[0296]

[0297] ​​​​​​​​​​​Note that in FIG. 33(A), a configuration having conductive films 77a and 77b that function as gate electrodes and a conductive film 73 that functions as a back gate electrode is shown, but other configurations are also possible. For example, as shown in FIG. 33(B), the conductive film 73 that functions as a back gate electrode may be omitted. Also, in FIG. 33(A), a configuration having conductive films 87a and 87b that function as gate electrodes and a conductive film 85 that functions as a back gate electrode is shown, but other configurations are also possible. For example, as shown in FIG. 33(B), the conductive film 85 that functions as a back gate electrode may be omitted. Note that the structure of FIG. 33(B) is applicable to an OS transistor.

[0298] Also, FIG. 34(A) shows a top view of a transistor 70A corresponding to the n-channel transistor 70 shown in FIG. 33(A). FIG. 34(B) is a cross-sectional view taken along line L1-L2 representing the channel length direction of the transistor 70A. FIG. 34(C) is a cross-sectional view taken along line W1-W2 representing the channel width direction of the transistor 70A.

[0299] In FIG. 34(A), conductive films 77, 73, a semiconductor film 75, conductive films 80, 81, openings 93, 94, 95, and 96 are shown. The conductive film 77 functions as a gate electrode. The conductive film 73 functions as a back gate electrode. In the description of FIG. 34(A), for the details of the configurations with the same reference numerals, since they are the same as the description in FIG. 33(A), they are omitted here. The openings 93 and 94 are openings for connecting the semiconductor film 75 to the conductive films 80 and 81. The openings 95 and 96 are openings for electrically connecting the conductive film 77 to the conductive film 73.

[0300] ​​​​​​​​​​​​ In FIG. 34(B), on a substrate 72, a conductive film 73, an insulating film 74, a semiconductor film 75 that overlaps the conductive film 73 with the insulating film 74 interposed therebetween, an insulating film 76 on the semiconductor film 75, and a conductive film 77a and a conductive film 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and function as gate electrodes, an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. In the description of FIG. 34(B), since the details of the configurations denoted by the same reference numerals are the same as those in the description of FIG. 33(A), they are omitted here. On a substrate 72, a conductive film 73, an insulating film 74, a semiconductor film 75 that overlaps the conductive film 73 with the insulating film 74 interposed therebetween, an insulating film 76 on the semiconductor film 75, and a conductive film 77a and a conductive film 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and function as gate electrodes, an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. The semiconductor film 75 has a channel formation region 82, a pair of LDD regions 83, and a pair of impurity regions 84. The pair of impurity regions 84 function as a source region or a drain region. In the description of FIG. 34(B), since the details of the configurations denoted by the same reference numerals are the same as those in the description of FIG. 33(A), they are omitted here. with the insulating film 74 interposed therebetween, a semiconductor film 75 that overlaps the conductive film 73, an insulating film 76 on the semiconductor film 75, and a conductive film 77a and a conductive film 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and function as gate electrodes, an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. and a conductive film 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and function as gate electrodes, an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. insulating film 79, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. In the description of FIG. 34(B), since the details of the configurations denoted by the same reference numerals are the same as those in the description of FIG. 33(A), they are omitted here. In the description of FIG. 34(B), since the details of the configurations denoted by the same reference numerals are the same as those in the description of FIG. 33(A), they are omitted here.

[0301] In FIG. 34(B), on a substrate 72, a conductive film 73, an insulating film 74, a semiconductor film 75 that overlaps the conductive film 73 with the insulating film 74 interposed therebetween, an insulating film 76 on the semiconductor film 75, and a conductive film 77a and a conductive film 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and function as gate electrodes, an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. On a substrate 72, a conductive film 73, an insulating film 74, a semiconductor film 75 that overlaps the conductive film 73 with the insulating film 74 interposed therebetween, an insulating film 76 on the semiconductor film 75, and a conductive film 77a and a conductive film 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and function as gate electrodes, an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. with the insulating film 74 interposed therebetween, a semiconductor film 75 that overlaps the conductive film 73, an insulating film 76 on the semiconductor film 75, and a conductive film 77a and a conductive film 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and function as gate electrodes, an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. and a conductive film 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and function as gate electrodes, an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. insulating film 79, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. electrically connected to the semiconductor film 75 at openings 93 and 94 provided in the insulating films 78 and 79 and function as a source or a drain. The semiconductor film 75 has a channel formation region 82, a pair of LDD regions 83, and a pair of impurity regions 84. The semiconductor film 75 has a channel formation region 82, a pair of LDD regions 83, and a pair of impurity regions 84. The pair of impurity regions 84 function as a source region or a drain region. The pair of impurity regions 84 function as a source region or a drain region. In the description of FIG. 34(B), since the details of the configurations denoted by the same reference numerals are the same as those in the description of FIG. 33(A), they are omitted here.

[0302] In FIG. 34(C), on the substrate 72, there are a conductive film 73, an insulating film 74, a channel formation region 82 , an insulating film 76, and conductive films 77a and 77b that are electrically connected to the conductive film 73 at the openings 95 and 96 , an insulating film 78 on the conductive films 77a and 77b, and an insulating film 79 on the insulating film 7 8. In the description of FIG. 34(C), since the details of the components with the same reference numerals are the same as those in the description of FIG. 33(A), they are omitted here.

[0303] The structures of the top view and cross-sectional view shown in FIGS. 34(A) to (C) are such that the conductive film 77 and the conductive film 73 electrically connected to the conductive film 77 electrically surround the channel width direction of the channel formation region 82 of the semiconductor film 75 to form an s-channel structure. The s-channel structure can surround the channel formation region from the top, bottom, and side surfaces of the channel formation region. Therefore, the on-current can be increased, and the size reduction in the channel width direction can be achieved. Also, since the channel formation region is surrounded by a conductive film, the light shielding of the channel formation region can be easily performed, and the photoexcitation caused by the unintended light irradiation on the channel formation region can be suppressed.

[0304] Also, in the structures of the top view and cross-sectional view shown in FIGS. 34(A) to (C), the conduction state due to the unintended increase in conductivity at the side ends in the W1-W2 direction in the semiconductor film 75 can be suppressed. Also, the influence of the variation in the distribution of the impurity elements added in the semiconductor film 75 can be reduced.

[0305] Also, in the structures of the top view and cross-sectional view shown in FIGS. 34(A) to (C), between the gate electrode and the back gate It is configured to electrically connect to the boost electrode, but a configuration with separate voltages is also effective. The configuration is particularly effective for a circuit composed only of n-channel types. That is, by applying a voltage to the back gate electrode , the threshold voltage of the transistor can be controlled. Therefore, a logic circuit such as an inverter circuit can be configured with ED-MOS transistors having different threshold voltages. By applying such a logic circuit to a drive circuit for driving pixels, the area occupied by the drive circuit can be reduced, so that a narrow bezel of the display device can be realized. Also, by setting the voltage of the back gate electrode to a voltage at which the transistor turns off, the off-current when the transistor is turned off can be made smaller. Therefore, even if the refresh frequency of the display device is reduced, the written voltage can be continuously held. Therefore, it is possible to expect power consumption reduction of the display device by reducing the number of write operations. Note that the top views and cross-sectional views shown in FIGS. 34(A) to (C) are examples, and other configurations are possible. For example, FIGS. 35(A) to (C) show top views and cross-sectional views different from FIGS. 34(A) to (C). The difference between the configuration shown in FIGS. 35(A) to (C) and the configuration shown in FIGS. 34(A) to (C)

[0306] is that the conductive film 77 serving as the gate electrode is formed as a single layer. Also, the positions of the openings 95 and 96 are closer to the channel formation region 82 side. By doing so, an electric field can be easily applied to the channel formation region from the top surface, bottom surface, and side surface of the channel formation region. Also, with this configuration, the same effects as those of FIGS. 34(A) to (C) can be obtained.

[0307] The difference between the configuration shown in FIGS. 35(A) to (C) and the configuration shown in FIGS. 34(A) to (C) is that the conductive film 77 serving as the gate electrode is formed as a single layer. Also, the positions of the openings 95 and 96 are closer to the channel formation region 82 side. By doing so, an electric field can be easily applied to the channel formation region from the top surface, bottom surface, and side surface of the channel formation region. Also, with this configuration, the same effects as those of FIGS. 34(A) to (C) can be obtained. Also, with this configuration, the same effects as those of FIGS. 34(A) to (C) can be obtained. It is possible.

[0308] As another configuration, FIGS. 36(A) to (C) show top views and cross-sectional views different from those of FIGS. 34(A) to (C) and FIGS. 35( A) to (C).

[0309] The configuration shown in FIGS. 36(A) to (C) is different from the configurations shown in FIGS. 34(A) to (C) and FIGS. 35(A) to (C) in that the conductive film 73 serving as the back gate electrode is composed of the conductive film 73a and the conductive film 73b, and the conductive film 73b is surrounded by the conductive film 73a. Even with this configuration, the same effects as those of FIGS. 34(A) to (C) can be achieved.

[0310] In addition, in the configuration of FIGS. 36(A) to (C), even when a mobile element (for example, copper ( Cu)) is used for the conductive film 73b, it is possible to prevent the mobile element from penetrating into the semiconductor film and deteriorating the semiconductor film.

[0311] As the material of the conductive film 73a that functions as a barrier film on the surface where the wiring is to be formed, high melting point materials such as tungsten (W), molybdenum (Mo), chromium (Cr), titanium (Ti ), tantalum (Ta), any of their alloys (for example, W-Mo, Mo-Cr, ) Ta-Mo), or their nitrides (for example, tungsten nitride, titanium nitride, tantalum nitride, TiSiNx), etc. can be used. As the formation method, a sputtering method, a CVD method etc. can be used. As the material of the conductive film 73b, copper (Cu) is preferable, but it is not particularly limited as long as it is a low resistance material. For example, silver (Ag), aluminum (Al), gold ( Au), and their alloys, etc. can also be used. As the method for forming the conductive film 73b, Although the sputtering method is preferred, the CVD method can also be used by selecting conditions that do not damage the resist mask. 、CVD method can also be used.

[0312] The transistors shown in FIGS. 34 to 36 have an s-channel structure. An s-channel transistor having silicon in the channel formation region has a high on-current and a small threshold variation for each transistor. Also, the transistor has suppressed DIBL and is less affected by the short-channel effect. Also, the transistor is less affected by impact ions and has a high drain breakdown voltage. Therefore, in the Id-Vd characteristics, it shows good saturation characteristics. Also, the transistor has good switching characteristics and a small subthreshold coefficient in the Id-Vg (gate voltage) characteristics. (gate voltage) characteristics, the subthreshold coefficient is small.

[0313] <Regarding the manufacturing process of the transistor> Next, a cross-sectional view of the above-described transistor, here particularly the transistor having a back gate electrode described in FIGS. 33 to 36, and a light-emitting element provided on the transistor is shown, and an example of the manufacturing process thereof will be described. an example of the manufacturing process will be described.

[0314] First, as shown in FIG. 37(A), a conductive film 502 that functions as a back gate electrode is provided on the insulating surface of the substrate 501. The conductive film 502 can be formed of a conductive material selected from one or more of Al, W, Mo, Ti, and Ta and can be formed of a conductive material selected from one or more of Al, W, Mo, Ti, and Ta. In the present embodiment, tungsten is used, but a laminate of tungsten on tantalum nitride may be used as the conductive film 502 and can be used. Also, it may be composed of a plurality of layers instead of a single layer. and can be used. Also, it may be composed of a plurality of layers instead of a single layer. and can be used. Also, it may be composed of a plurality of layers instead of a single layer.

[0315] For the substrate 501, for example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, quartz substrates, ceramic substrates, etc. can be used. Also, those obtained by forming an insulating film on the surface of a metal substrate or a silicon substrate may be used. Substrates made of a synthetic resin having flexibility such as plastic generally tend to have a lower heat-resistant temperature compared to the above substrates but can be used if they can withstand the processing temperature in the manufacturing process.

[0316] Next, an insulating film 503 is provided so as to cover the conductive film 502. The insulating film 503 is provided by laminating an insulating film 503 a and an insulating film 503b. As an example, the insulating film 503a uses a silicon oxynitride film As an example, the insulating film 503b uses a silicon oxide film or a silicon oxynitride film. Note that the insulating film 503 is not limited to this configuration and may be formed of a single-layer insulating film or formed of three or more layers of insulating films. Also, the material is not limited to this.

[0317] The surface of the insulating film 503 (here, the surface of the insulating film 503b) may have irregularities caused by the previously formed conductive film 502. In this case, it is desirable to provide a step for flattening the irregularities. In this embodiment, flattening is performed using CMP (Chemical-Mechanical Pol ishing).

[0318] Next, an amorphous semiconductor film 504 is formed on the insulating film 503 by plasma CVD. Although it depends on the hydrogen content of the amorphous semiconductor film 504, it is preferably heated at 400 to 550 °C for several hours to perform dehydrogenation treatment so that the hydrogen content is 5 atomic% or less, and it is desirable to perform a crystallization step. Also, the amorphous semiconductor film can be formed by other manufacturing methods such as sputtering and evaporation ​​​​​​Although it may be achieved, it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film. It is desirable.

[0319] The semiconductor to be used is not limited to silicon only. For example, silicon germanium can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 at omic%.

[0320] In addition, when both the insulating film 503 and the amorphous semiconductor film 504 are formed by the plasma CVD method, these two films may be continuously formed without exposing them to the atmosphere. By continuously forming the film, surface contamination by the atmosphere can be suppressed as much as possible, and thus the variation in the characteristics of the manufactured transistors can be reduced.

[0321] Next, a catalyst is added to the amorphous semiconductor film 504. In this embodiment, a nickel acetate solution containing 1 to 100 ppm of nickel in terms of weight was applied by a spinner. In addition, in order to improve the wettability of the nickel acetate solution, a very thin oxide film is formed by treating the surface of the amorphous semiconductor film 504 with an ozone-containing aqueous solution, and the oxide film is etched with a mixed solution of hydrofluoric acid and hydrogen peroxide solution to form a clean surface, and then treated again with an ozone-containing aqueous solution to form a very thin oxide film. Since the surface of the semiconductor film is inherently hydrophobic, by forming the oxide film in this way, the nickel acetate solution can be uniformly applied. The above is the description of Fig. 37 (A). (A).

[0322] Of course, the addition of the catalyst to the amorphous semiconductor film is not limited to the above method, and it may be added using a sputtering method, an evaporation method, a plasma treatment, etc. It may be added.

[0323] Next, heat treatment is performed at 500 to 650 °C for 4 to 24 hours, for example, at 570 °C for 14 hours. By performing the heat treatment, crystallization proceeds in the nickel-containing layer 505, and a highly crystalline semiconductor film is formed.

[0324] As the heat treatment method, a furnace annealing method using an electric furnace, or an RTA method using a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, a high-pressure mercury lamp, etc. can be used. Alternatively, it is also possible to use an RTA of a gas heating method using a heated inert gas.

[0325] When performing by the RTA method, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source can be arbitrary, but the amorphous semiconductor film 504 is instantaneously heated to 600 to 1000 °C, preferably about 650 to 750 °C. Even at such a high temperature, the semiconductor film is only instantaneously heated, and the substrate 501 itself does not warp or deform.

[0326] When using the furnace annealing method as another method, prior to the heat treatment, a heat treatment is performed at 500 °C for about 1 hour to release the hydrogen contained in the amorphous semiconductor film 504. Then, using an electric furnace, a heat treatment is performed at 550 °C or higher and 600 °C or lower, preferably at 580 °C for 4 hours in a nitrogen atmosphere to crystallize the amorphous semiconductor film 504.

[0327] In this embodiment, nickel (Ni) is used as the catalyst element, but in addition to that, , germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb) , elements such as cobalt (Co), platinum (Pt), copper (Cu), and gold (Au) may also be used .

[0328] Next, the gettering of the catalyst element present in the crystalline semiconductor film 506 will be described. By crystallization using a catalyst element, in the crystalline semiconductor film 506, the catalyst element (here nickel) is considered to remain at an average concentration exceeding 1×10 / cm 19 . 3 Since the remaining catalyst element may have an adverse effect on the characteristics of the transistor, it is necessary to provide a step for reducing the catalyst element concentration.

[0329] Although there are various gettering methods, in this embodiment, an example of gettering performed before patterning the crystalline semiconductor film 506 will be described. First, as shown in FIG. 37(B), a barrier layer 507 is formed on the surface of the crystalline semiconductor film 506. The barrier layer 507 is provided to prevent the crystalline semiconductor film 506 from being etched when removing the gettering site later.

[0330] The thickness of the barrier layer 507 is set to about 1 to 10 nm. A chemical oxide formed by treatment with ozone water may be used as the barrier layer. Also, a chemical oxide can be formed in the same manner by treating with an aqueous solution obtained by mixing sulfuric acid, hydrochloric acid, nitric acid, etc. with hydrogen peroxide water. Alternatively, a method of plasma treatment in an oxidizing atmosphere or a method of performing an oxidation treatment by generating ozone by ultraviolet irradiation in an oxygen-containing atmosphere may be used. Also,ク ​​​​​​​​​​Using a lean oven, heat to about 200 to 350 °C to form a thin oxide film as a barrier layer is also acceptable. Alternatively, an oxide film of about 1 to 5 nm may be deposited by plasma CVD method, sputtering method, evaporation method, etc. as a barrier layer. In any case, during the gettering process, the catalyst element can move to the gettering site side, and during the removal process of the gettering site, a film (e.g., protecting the crystalline semiconductor film 506 from the etching solution) that does not allow the etching solution to penetrate, for example, a chemical oxide film formed by treating with ozone water, a silicon oxide film (SiOx), or a porous film may be used. For example, a chemical oxide film formed by treating with ozone water, a silicon oxide film (SiOx), or a porous film may be used.

[0331] Next, as a gettering site 508 on the barrier layer 507 by sputtering, a semiconductor film for gettering containing a rare gas element in the film at a concentration of 1×10 / cm 20 or more (typically 3 an amorphous silicon film) is formed with a thickness of 25 to 250 nm. The gettering site 508 to be removed later preferably forms a film with a low density in order to increase the etching selectivity with the crystalline semiconductor film 506. The gettering site 508 to be removed later preferably forms a film with a low density in order to increase the etching selectivity with the crystalline semiconductor film 506. Since the rare gas element is inert in the semiconductor film itself, it has no adverse effect on the crystalline semiconductor film 506. Also, as the rare gas element, one or more selected from helium (He), neon (Ne )、argon (Ar), krypton (Kr), and xenon (Xe) are used.

[0332] Since the rare gas element is inert in the semiconductor film itself, it has no adverse effect on the crystalline semiconductor film 506. Also, as the rare gas element, one or more selected from helium (He), neon (Ne )、argon (Ar), krypton (Kr), and xenon (Xe) are used. )、argon (Ar), krypton (Kr), and xenon (Xe) are used. A plurality of species are used.

[0333] Next, gettering is performed by heat treatment (Fig. 37(B)). The heat treatment is performed by furnace annealing method or RTA method. When performing by furnace annealing method, in a nitrogen atmosphere When performing by furnace annealing method, in a nitrogen atmosphere Perform a heat treatment at 450 to 600 °C for 0.5 to 12 hours in the air. Also, in the case of using the RTA method When using, turn on the lamp light source for heating for 1 to 60 seconds, preferably 30 to 60 seconds and repeat it 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary but make sure that the semiconductor film is instantaneously heated to 600 to 1000 °C, preferably 700 to about 750 °C.

[0334] By the heat treatment, the catalyst element in the crystalline semiconductor film 506 is released by thermal energy and moves to the gettering site 508 by diffusion as shown by the arrow. Therefore, gettering depends on the treatment temperature, and the higher the temperature, the faster the gettering proceeds in a shorter time.

[0335] After the gettering process is completed, selectively etch and remove the gettering site 508 . As the etching method, dry etching without using plasma with ClF3, or wet etching with an alkaline solution such as hydrazine or an aqueous solution containing tetramethylammonium hydroxide (chemical formula (CH3) 4NOH) can be performed. At this time, the barrier layer 507 functions as an etch stopper. Also, the barrier layer 507 is then removed with hydrofluoric acid (Fig. 37(C)).

[0336] Next, pattern the crystalline semiconductor film 506 after removing the barrier layer 507 to form island-shaped semiconductor films 509 and 510 (Fig. 37(D)). The film thickness of the semiconductor films 509 and 510 is 25 to 100 nm (preferably 30 to 60 nm). Next, form an insulating film 511 so as to cover the semiconductor films 509 and 510. The insulating film 511 will later function as an electrode for the gate electrode In the dry etching performed to form it, since the film thickness decreases by about 10 to 40 nm, it is desirable to set the film thickness taking into account the decrease. Specifically, an insulating film 511 is formed to a thickness of about 40 to 150 nm (more preferably 60 to 120 nm). Since it decreases, it is desirable to set the film thickness taking into account the amount of decrease. Specifically, an insulating film 511 is formed to a thickness of about 40 to 150 nm (more preferably 60 to 120 nm). For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed. For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed.

[0337] For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed. For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed. For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed. For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed. For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed. For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed. For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed. 2 For the insulating film 511, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. In this embodiment, the insulating film 511 is composed of a single-layer insulating film, but it may be composed of a plurality of two or more insulating films. Also, as the film formation method, a plasma CVD method, a sputtering method, etc. can be used. For example, when forming the insulating film 511 with silicon oxide using the plasma CVD method, a gas mixture of TEOS (Tetraethyl Orthosilicate) and O2 is used, with a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 °C, and a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm², and film formation is performed.

[0338] Also, aluminum nitride can be used as the insulating film 511. Aluminum nitride has a relatively high thermal conductivity and can efficiently dissipate the heat generated in the transistor. Also, after forming silicon oxide or silicon oxynitride that does not contain aluminum, a laminated structure of aluminum nitride can be used as the insulating film 511. Also, aluminum nitride can be used as the insulating film 511. Aluminum nitride has a relatively high thermal conductivity and can efficiently dissipate the heat generated in the transistor. Also, after forming silicon oxide or silicon oxynitride that does not contain aluminum, a laminated structure of aluminum nitride can be used as the insulating film 511. Also, aluminum nitride can be used as the insulating film 511. Aluminum nitride has a relatively high thermal conductivity and can efficiently dissipate the heat generated in the transistor. Also, after forming silicon oxide or silicon oxynitride that does not contain aluminum, a laminated structure of aluminum nitride can be used as the insulating film 511. Also, aluminum nitride can be used as the insulating film 511. Aluminum nitride has a relatively high thermal conductivity and can efficiently dissipate the heat generated in the transistor. Also, after forming silicon oxide or silicon oxynitride that does not contain aluminum, a laminated structure of aluminum nitride can be used as the insulating film 511.

[0339] Next, a conductive film is formed on the insulating film 511 (Fig. 37(E)). In this embodiment, a conductive film 512a made of tantalum nitride is formed to a thickness of 20 to 100 nm, and a conductive film 512b made of tungsten is formed to a thickness of 100 to 400 nm. Specifically, for the conductive film 512a, Next, a conductive film is formed on the insulating film 511 (Fig. 37(E)). In this embodiment, a conductive film 512a made of tantalum nitride is formed to a thickness of 20 to 100 nm, and a conductive film 512b made of tungsten is formed to a thickness of 100 to 400 nm. Specifically, for the conductive film 512a, Next, a conductive film is formed on the insulating film 511 (Fig. 37(E)). In this embodiment, a conductive film 512a made of tantalum nitride is formed to a thickness of 20 to 100 nm, and a conductive film 512b made of tungsten is formed to a thickness of 100 to 400 nm. Specifically, for the conductive film 512a, The tantalum nitride was formed by using Ta with a purity of 99.99% as the target, setting the temperature in the chamber to room temperature, the flow rate of Ar to 50 ml / min, the flow rate of N2 to 10 ml / min, the pressure in the chamber to 0.6 Pa, and the film-forming power to 1 kW, with a film-forming rate of approximately 40 nm / min. Also, the tungsten used for the conductive film 512b was formed by using tungsten with a purity of 99.99% as the target, setting the temperature in the chamber to 230 °C, the flow rate of Ar to 100 ml / min, the pressure in the chamber to 1.5 Pa, and the film-forming power to 6 kW, with a film-forming rate of approximately 390 nm / min. In this embodiment, an example of forming an electrode that functions as a gate electrode using two conductive films will be described. However, the conductive film may be a single layer, or may be formed of a plurality of layers of three or more layers. Also, the material of each conductive layer is not limited to those shown in this embodiment.

[0340] Specifically, each conductive film can be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, or an alloy or compound having the above-mentioned element as a main component. For example, the first layer is tantalum and the second layer is tungsten, or the first layer is tantalum nitride and the second layer is aluminum, or the first layer is tantalum nitride and the second layer is copper. Combinations such as these are conceivable. Also, an alloy of silver, palladium, and copper may be used for either the first layer or the second layer. A three-layer structure in which tungsten, an alloy of aluminum and silicon (Al-Si), and titanium nitride are sequentially laminated may also be used. Instead of tungsten, tungsten nitride may be used, instead of the alloy of aluminum and silicon (Al-Si), an alloy film of aluminum and titanium (Al-Ti) may be used, or instead of titanium nitride, titanium may be used. However, when forming a plurality of conductive films

[0341] ​​​​​​​​​​ If you want to create a difference in the width of the conductive film of each layer in the channel length direction after etching, Use materials with different etching selectivity to each other.

[0342] Note that it is important to appropriately select the optimal etching gas according to the material of the conductive film.

[0343] Next, a mask 514 is formed, and the conductive film 512a and the conductive film 512 b are etched as shown in Fig. 38(A) (first etching process). In this embodiment, ICP (Induct ively Coupled Plasma: inductively coupled plasma) etching method is used to perform. As the etching gas, a gas mixture of Cl2, CF4, and O2 is used, and the pressure of the etching gas in the chamber is set to 1.0 Pa. Then, 500 W of high-frequency (RF) power at 13.56 MHz is applied to the coil-shaped electrode to generate plasma. Also, the substrate is placed on the stage (lower electrode) and 150 W of high-frequency (RF) power at 13.56 MHz is applied to it, thereby applying a self-bias voltage to the substrate. After that, the etching gas is changed to Cl 2 and CF4, and the total pressure is set to 1.0 Pa. Also, 500 W of high-frequency (13.56 MHz) power is applied to the coil-shaped electrode, and 20 W of high frequency (13.56 MHz) power is applied to the substrate side (sample stage).

[0344] When CF4 and Cl2 are used as the etching gas, the etching rates of tantalum nitride which is the conductive film 512a and tungsten which is the conductive film 512b become almost equal, and both are etched to the same extent.

[0345] By this first etching process, a first structure composed of a lower layer 515a and an upper layer 515b ​A conductive film 515 in a [specific shape] and a conductive film 516 in the first shape composed of a lower layer 516a and an upper layer 516b are formed. In this first etching process, the side surfaces of the lower layers 515a and 516a and the upper layers 515b and 516b become slightly tapered. Also, when etching is performed so as not to leave residues of the conductive film, the surface of the insulating film 5 11 that is not covered by the conductive films 515 and 516 in the first shape may be etched by about 5 to 10 nm or more.

[0346] Next, as shown in FIG. 38(B), using the mask 514 whose surface has been etched and whose width has become smaller in the first etching process, the conductive films 515 and 516 in the first shape are etched (the second etching process). In the second etching process, the same IC P etching method as in the first etching process is used. As the etching gas, a gas mixture of SF6, Cl2, and O2 is used , and the pressure of the etching gas in the chamber is set to 1.3 Pa. Then, high-frequency power of 700 W and 13.56 MHz is applied to the coil-type electrode to generate plasma. Also, high-frequency power of 10 W and 13.56 MHz is applied to the stage (lower electrode) on which the substrate is placed , and a self-bias voltage is applied to the substrate thereby.

[0347] By adding O2 to the gas mixture of SF6 and Cl2, in the conductive films 515 and 51 6 in the first shape, the etching rate of tungsten increases, and the etching rate of tantalum nitride extremely decreases, so that a selectivity can be obtained.

[0348] By the second etching process, a conductive film 517 in the second shape (lower layer 517a, upper layer 517 b) and a conductive film 518 in the second shape (lower layer 518a, upper layer 518b) are formed. The upper layer ​​​​The widths of 517b and 518b in the channel length direction are shorter than those of the lower layers 517a and 518a. Note that by the second etching process, the surface of the insulating film 511 not covered by the conductive films 517 and 51 8 of the second shape is etched by about 5 to 10 nm or more.

[0349] Next, as shown in Fig. 38(C), using the conductive films 517 and 518 of the second shape as masks, impurities for imparting n-type conductivity are added to the semiconductor films 509 and 510 (first doping process). Doping is performed by the ion implantation method. The doping is carried out with a dose amount of 1×10 13 to 5×10 14 atoms / cm 2 and an acceleration voltage of 40 to 80 kV. Impurity elements for imparting n-type are 5-group atoms such as P, As, and Sb that function as donors, and 6-group atoms such as S, Te and Se. In this embodiment, P is used. By the first doping process, self-aligned impurity regions 520 and 521 are formed. The impurity regions 520 and 521 are doped with impurity elements for imparting n-type in the concentration range of 1×10 18 to 1×10 20 atoms / cm 3 .

[0350] Subsequently, a second doping process is performed to obtain the state of Fig. 38(D). The second doping process is carried out with an acceleration voltage of 50 to 100 kV and a dose amount of 1×10 15 to 1×10 17 atoms / cm 2 . By the first doping process and the second doping process, impurity regions 522 and 523 overlapping with the lower layers 517a and 518a, and impurity regions 524 and 52 ​​5 is formed. The impurity regions 522 and 523 are doped with an impurity element that imparts an n-type in a concentration range of 1×10 18 to 5×10 19 ato ms / cm 3 The impurity regions 524 and 5 25 are doped with an impurity element that imparts an n-type in a concentration range of 1×10 19 to 5×10 21 atoms / cm 3 The impurity regions 522 and 523 are formed inside the impurity regions 524 and 525, and the impurity regions 522 and 523 function as LDD regions, and the impurity regions 524 and 525 function as source / drain regions. Of course, by setting an appropriate acceleration voltage, the first doping process and the second doping process can be completed in a single doping process to form a low-concentration impurity region and a high-concentration impurity region.

[0351] Of course, by setting an appropriate acceleration voltage, the first doping process and the second doping process can be completed in a single doping process to form a low-concentration impurity region and a high-concentration impurity region. Of course, by setting an appropriate acceleration voltage, the first doping process and the second doping process can be completed in a single doping process to form a low-concentration impurity region and a high-concentration impurity region. function as

[0352] Of course, by setting an appropriate acceleration voltage, the first doping process and the second doping process can be completed in a single doping process to form a low-concentration impurity region and a high-concentration impurity region. process, and it is also possible to form a low-concentration impurity region and a high-concentration impurity region. process, and it is also possible to form a low-concentration impurity region and a high-concentration impurity region.

[0353] In the above steps, impurity regions are formed in each island-shaped semiconductor film.

[0354] Next, an interlayer insulating film 530 is formed to cover the island-shaped semiconductor films 509 and 510, the insulating film 511, and the conductive films 517 and 518 (Fig. 39(A)). The interlayer insulating film 530 can be an insulating film such as silicon-containing silicon oxide, silicon nitride, or silicon oxynitride, and its thickness is set to about 100 to 200 nm. is set to about 100 to 200 nm.

[0355] Next, a heat treatment is performed to activate the impurity elements added to the island-shaped semiconductor films 509 and 510. This step uses a thermal annealing method using a furnace annealing furnace or a laser annealing method using a furnace annealing furnace or a laser annealing The thermal annealing method or rapid thermal annealing method (RTA method) can be used. For example, when activation is performed by the thermal annealing method, it is carried out in a nitrogen atmosphere with an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 700 °C (preferably 500 to 600 °C). Furthermore, a step of heat-treating in an atmosphere containing 3 to 100% hydrogen at 300 to 450 °C for 1 to 12 hours to hydrogenate the island-shaped semiconductor film is performed. This step is carried out for the purpose of terminating dangling bonds with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. Also, the activation treatment may be performed before forming the interlayer insulating film 530. When activation is performed by the thermal annealing method, it is carried out in a nitrogen atmosphere with an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. at 400 to 700 °C (preferably 500 to 600 °C). Furthermore, a heat treatment is performed in an atmosphere containing 3 to 100% hydrogen at 300 to 450 °C for 1 to 12 hours to hydrogenate the island-shaped semiconductor film. This step is carried out for the purpose of terminating dangling bonds with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. Also, the activation treatment may be performed before forming the interlayer insulating film 530.

[0356] By the above series of steps, the transistor 531 and the transistor 532 can be formed. In this embodiment, the transistors 531 and 532 are treated as n-channel transistors, but the transistor 531 or the transistor 532 may be treated as a p-channel transistor. In that case, in the first doping treatment and the second doping treatment, a p-type impurity may be doped. Or, the first doping treatment and the second doping treatment may be completed with a single doping treatment of a p-type impurity. Examples of the impurity element for imparting a p-type include B. The impurity regions 522 and 523 are doped with an impurity element for imparting a p-type in a concentration range of 1×10 to 5×10 atoms / cm, and the impurity regions 524 and 525 are doped with an impurity element for imparting a p-type in a concentration range of 1×10 to 5×1 0 atoms / cm. 18 to 5×10 19 atoms / cm 3 to impart a p-type, and the impurity regions 524 and 525 are doped with an impurity element for imparting a p-type in a concentration range of 1×10 to 5×1 19 0 0 21 atoms / cm 3An impurity element that imparts a p-type within the concentration range may be added.

[0357] Also, a first doping process may be performed between the first etching process and the second etching process. After performing the first doping process, the upper layer is etched in the channel length direction to be shortened by the second etching process, and by performing the second doping process, impurity regions 522, 523 and impurity regions 524, 525 may be formed.

[0358] Note that the above plasma etching is not limited to the ICP etching method. For example, ECR (Electron Cyclotron Resonance) etching method, RIE etching method, helicon wave etching method, helical resonance etching method, pulse modulation etching method, or other plasma etching methods may be used. lectron Cyclotron Resonance: electron cyclotron resonance etching method, RIE etching method, helicon wave etching method, helical resonance etching method, pulse modulation etching method, or other plasma etching methods may be used.

[0359] In this embodiment, an example using only the crystallization method by a catalyst element is shown, but it is not limited thereto. After crystallization is performed using a catalyst element, in order to further enhance crystallinity, pulsed laser light irradiation may be performed. Also, the gettering process described above is not limited to the method shown in this embodiment. Other methods may be used to reduce the catalyst element in the semiconductor film.

[0360] Next, an interlayer insulating film 533 and an interlayer insulating film 534 are formed so as to cover the interlayer insulating film 530. In this embodiment, the interlayer insulating film 533 is formed using an organic resin, for example, non-photosensitive acrylic. The interlayer insulating film 534 uses a film that is less likely to transmit substances that cause deterioration of the OLED, such as moisture and oxygen, compared to other insulating films. Typically, for example, DLC ​ It is desirable to use a film, a carbon nitride film, a silicon nitride film formed by RF sputtering method, etc.

[0361] Next, the insulating film 511, the interlayer insulating film 530, the interlayer insulating film 533, and the interlayer insulating film 534 are etched to form openings. Then, wirings 535 to 538 that form contacts with the island-shaped semiconductor films 509 and 510 are formed. Next, a transparent conductive film is formed covering the interlayer insulating film 534 and the wirings 535 to 538, and by patterning, a pixel electrode (anode) 540 connected to the wiring 538 connected to the island-shaped semiconductor film 510 of the transistor 532 is formed (FIG. 39(B)). As the transparent conductive film used for the pixel electrode 540, not only ITO (indium tin oxide), but also a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide may be used. The surface of the pixel electrode 540 may be polished by CMP method or wiping using a porous body of polyvinyl alcohol so as to be flattened. Also, after polishing using the CMP method, ultraviolet irradiation, oxygen plasma treatment, etc. may be performed on the surface of the pixel electrode 540. Next, an organic resin film 541 used as a partition is formed on the interlayer insulating film 534. The organic resin film 541 is made to have an opening in the region overlapping with the pixel electrode 540. The organic resin film 541 is heated in a vacuum atmosphere in order to remove adsorbed moisture, oxygen, etc. before forming the electroluminescent layer next. Specifically, heat treatment is performed in a vacuum atmosphere at 100°C to 200°C for about 0.5 to 1 hour. Preferably, it is set to 3×10 Torr or less, and if possible, 3×10

[0362] Next, a transparent conductive film is formed covering the interlayer insulating film 534 and the wirings 535 to 538, and by patterning, a pixel electrode (anode) 540 connected to the wiring 538 connected to the island-shaped semiconductor film 510 of the transistor 532 is formed (FIG. 39(B)). The transparent conductive film used for the pixel electrode 540 may be not only ITO (indium tin oxide), but also a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide. The pixel electrode 540 may be polished by CMP method or wiping using a porous body of polyvinyl alcohol so that its surface is flattened. Also, after polishing using the CMP method, ultraviolet irradiation, oxygen plasma treatment, etc. may be performed on the surface of the pixel electrode 540. Next, a transparent conductive film is formed covering the interlayer insulating film 534 and the wirings 535 to 538, and by patterning, a pixel electrode (anode) 540 connected to the wiring 538 connected to the island-shaped semiconductor film 510 of the transistor 532 is formed (FIG. 39(B)). The transparent conductive film used for the pixel electrode 540 may be not only ITO (indium tin oxide), but also a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide. The pixel electrode 540 may be polished by CMP method or wiping using a porous body of polyvinyl alcohol so that its surface is flattened. Also, after polishing using the CMP method, ultraviolet irradiation, oxygen plasma treatment, etc. may be performed on the surface of the pixel electrode 540. Next, a transparent conductive film is formed covering the interlayer insulating film 534 and the wirings 535 to 538, and by patterning, a pixel electrode (anode) 540 connected to the wiring 538 connected to the island-shaped semiconductor film 510 of the transistor 532 is formed (FIG. 39(B)). The transparent conductive film used for the pixel electrode 540 may be not only ITO (indium tin oxide), but also a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide. The pixel electrode 540 may be polished by CMP method or wiping using a porous body of polyvinyl alcohol so that its surface is flattened. Also, after polishing using the CMP method, ultraviolet irradiation, oxygen plasma treatment, etc. may be performed on the surface of the pixel electrode 540. Next, a transparent conductive film is formed covering the interlayer insulating film 534 and the wirings 535 to 538, and by patterning, a pixel electrode (anode) 540 connected to the wiring 538 connected to the island-shaped semiconductor film 510 of the transistor 532 is formed (FIG. 39(B)). The transparent conductive film used for the pixel electrode 540 may be not only ITO (indium tin oxide), but also a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide. The pixel electrode 540 may be polished by CMP method or wiping using a porous body of polyvinyl alcohol so that its surface is flattened. Also, after polishing using the CMP method, ultraviolet irradiation, oxygen plasma treatment, etc. may be performed on the surface of the pixel electrode 540. Next, a transparent conductive film is formed covering the interlayer insulating film 534 and the wirings 535 to 538, and by patterning, a pixel electrode (anode) 540 connected to the wiring 538 connected to the island-shaped semiconductor film 510 of the transistor 532 is formed (FIG. 39(B)). The transparent conductive film used for the pixel electrode 540 may be not only ITO (indium tin oxide), but also a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide. The pixel electrode 540 may be polished by CMP method or wiping using a porous body of polyvinyl alcohol so that its surface is flattened. Also, after polishing using the CMP method, ultraviolet irradiation, oxygen plasma treatment, etc. may be performed on the surface of the pixel electrode 540. Next, a transparent conductive film is formed covering the interlayer insulating film 534 and the wirings 535 to 538, and by patterning, a pixel electrode (anode) 540 connected to the wiring 538 connected to the island-shaped semiconductor film 510 of the transistor 532 is formed (FIG. 39(B)). The transparent conductive film used for the pixel electrode 540 may be not only ITO (indium tin oxide), but also a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide. The pixel electrode 540 may be polished by CMP method or wiping using a porous body of polyvinyl alcohol so that its surface is flattened. Also, after polishing using the CMP method, ultraviolet irradiation, oxygen plasma treatment, etc. may be performed on the surface of the pixel electrode 540. Next, a transparent conductive film is formed covering the interlayer insulating film 534 and the wirings 535 to 538, and by patterning, a pixel electrode (anode) 540 connected to the wiring 538 connected to the island-shaped semiconductor film 510 of the transistor 532 is formed (FIG. 39(B)). The transparent conductive film used for the pixel electrode 540 may be not only ITO (indium tin oxide), but also a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide. The pixel electrode 540 may be polished by CMP method or wiping using a porous body of polyvinyl alcohol so that its surface is flattened. Also, after polishing using the CMP method, ultraviolet irradiation, oxygen plasma treatment, etc. may be performed on the surface of the pixel electrode 540. Next, a transparent conductive film is formed covering the interlayer insulating film 534 and the wirings 535 to 538, and by patterning, a pixel electrode (anode) 540 connected to the wiring 538 connected to the island-shaped semiconductor film 510 of the transistor 532 is formed (FIG. 39(B)). The transparent conductive film used for the pixel electrode 540 may be not only ITO (indium tin oxide), but also a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide. The pixel electrode 540 may be polished by CMP method or wiping using a porous body of polyvinyl alcohol so that its surface is flattened. Also, after polishing using the CMP method, ultraviolet irradiation, oxygen plasma treatment, etc. may be performed on the surface of the pixel electrode 540.

[0363] Then, an organic resin film 541 used as a partition is formed on the interlayer insulating film 534. The organic resin film 541 is made to have an opening in the region overlapping with the pixel electrode 540. The organic resin film 541 is heated in a vacuum atmosphere in order to remove adsorbed moisture, oxygen, etc. before forming the electroluminescent layer next. Specifically, heat treatment is performed in a vacuum atmosphere at 100°C to 200°C for about 0.5 to 1 hour. Preferably, it is set to 3×10 Torr or less, and if possible, 3×10 Then, an organic resin film 541 used as a partition is formed on the interlayer insulating film 534. The organic resin film 541 is made to have an opening in the region overlapping with the pixel electrode 540. The organic resin film 541 is heated in a vacuum atmosphere in order to remove adsorbed moisture, oxygen, etc. before forming the electroluminescent layer next. Specifically, heat treatment is performed in a vacuum atmosphere at 100°C to 200°C for about 0.5 to 1 hour. Preferably, it is set to 3×10 Torr or less, and if possible, 3×10 Then, an organic resin film 541 used as a partition is formed on the interlayer insulating film 534. The organic resin film 541 is made to have an opening in the region overlapping with the pixel electrode 540. The organic resin film 541 is heated in a vacuum atmosphere in order to remove adsorbed moisture, oxygen, etc. before forming the electroluminescent layer next. Specifically, heat treatment is performed in a vacuum atmosphere at 100°C to 200°C for about 0.5 to 1 hour. Preferably, it is set to 3×10 Torr or less, and if possible, 3×10 Then, an organic resin film 541 used as a partition is formed on the interlayer insulating film 534. The organic resin film 541 is made to have an opening in the region overlapping with the pixel electrode 540. The organic resin film 541 is heated in a vacuum atmosphere in order to remove adsorbed moisture, oxygen, etc. before forming the electroluminescent layer next. Specifically, heat treatment is performed in a vacuum atmosphere at 100°C to 200°C for about 0.5 to 1 hour. Preferably, it is set to 3×10 Torr or less, and if possible, 3×10 Then, an organic resin film 541 used as a partition is formed on the interlayer insulating film 534. The organic resin film 541 is made to have an opening in the region overlapping with the pixel electrode 540. The organic resin film 541 is heated in a vacuum atmosphere in order to remove adsorbed moisture, oxygen, etc. before forming the electroluminescent layer next. Specifically, heat treatment is performed in a vacuum atmosphere at 100°C to 200°C for about 0.5 to 1 hour. Preferably, it is set to 3×10 Torr or less, and if possible, 3×10 -7 Torr or less, and if possible, 3×10 Torr or less, and if possible, 3×10 -8It is most desirable to be below Torr. And for the organic resin film 54 When forming the electroluminescent layer after heat-treating 1 in a vacuum atmosphere, keep it in a vacuum atmosphere until immediately before film formation, the reliability can be further enhanced.

[0364] At the end in the opening of the organic resin film 541, it is desirable to make it rounded so that no holes are formed in the electroluminescent layer to be formed later at that end. Specifically, it is desirable that the radius of curvature of the curve depicting the cross-section of the organic resin film 541 in the opening is about 0.2 to 2 μm.

[0365] In FIG. 39(C), an example using a positive photosensitive acrylic resin as the organic resin film 541 is shown. Photosensitive organic resins include a positive type in which the exposed portions of energy rays such as light, electrons, and ions are removed, and a negative type in which the exposed portions remain. In the present invention, a negative type organic resin film may be used. Also, the organic resin film 541 may be formed using a photosensitive polyimide.

[0366] When forming the organic resin film 541 using a negative acrylic, the end at the opening has an S-shaped cross-sectional shape. At this time, it is desirable that the radius of curvature at the upper and lower ends of the opening is 0.2 to 2 μm.

[0367] With the above configuration, the coverage of the electroluminescent layer and the cathode to be formed later can be made good, and it is possible to prevent the pixel electrode 540 and the cathode from short-circuiting in the holes formed in the electroluminescent layer. Also, by relaxing the stress of the electroluminescent layer, it is possible to reduce the shrinkage in which the light-emitting region decreases and reduce the defects caused thereby, and improve the reliability.

[0368] ​​​​​​​​​​​ Next, a light-emitting layer 542 is formed on the pixel electrode 540. The light-emitting layer 542 may be composed of one or more layers and may include not only organic substances but also inorganic layers.

[0369] Next, a cathode 543 is formed to cover the light-emitting layer 542. As the cathode 543, other known materials can be used as long as they are conductive films with a small work function. For example, Ca, Al, MgAg, AlLi, etc. are desirable. AlLi, etc. are desirable.

[0370] The pixel electrode 540, the light-emitting layer 542, and the cathode 543 overlap at the opening of the organic resin film 541, and the overlapping portion corresponds to the light-emitting element 544.

[0371] Next, a protective film 545 is formed on the organic resin film 541 and the cathode 543. Similar to the interlayer insulating film 534, the protective film 5 45 uses a film that is less permeable to substances that cause deterioration of the light-emitting element, such as moisture and oxygen, compared to other insulating films. Typically, for example, a DL C film, a carbon nitride film, a silicon nitride film formed by RF sputtering, etc. are preferably used. Also, it is also possible to stack a film that is less permeable to substances such as moisture and oxygen described above and a film that is more permeable to substances such as moisture and oxygen than the former film and use it as a protective film. It is also possible to stack a film that is less permeable to substances such as moisture and oxygen described above and a film that is more permeable to substances such as moisture and oxygen than the former film and use it as a protective film. It is also possible to stack a film that is less permeable to substances such as moisture and oxygen described above and a film that is more permeable to substances such as moisture and oxygen than the former film and use it as a protective film.

[0372] Note that FIG. 39(C) shows a configuration in which the light emitted from the light-emitting element is irradiated toward the substrate 501 side, but a light-emitting element having a structure in which the light travels to the side opposite to the substrate may also be used.

[0373] In practice, when it is completed up to FIG. 39(C), a highly airtight and low outgassing protective film (such as a laminate film or an ultraviolet curable resin film) is used so that it is not further exposed to the outside air. In practice, when it is completed up to FIG. 39(C), a highly airtight and low outgassing protective film (such as a laminate film or an ultraviolet curable resin film) is used so that it is not further exposed to the outside air. It is preferable to package (enclose) with a light-transmissive cover material. At this time, if an inert atmosphere is provided inside the cover material, or a hygroscopic material (for example, barium oxide) is disposed inside, the reliability of the display device having the light-emitting element is improved. By using the manufacturing method described above, a transistor having a back gate electrode and a light-emitting element provided on the transistor can be formed on the same substrate.

[0374]

[0375] (Embodiment 3) In this embodiment, an example of a method for manufacturing a display device will be described with reference to FIGS. 40 to 42. In particular, in this embodiment, a method for manufacturing a flexible display device will be described.

[0376] <Manufacturing method 1 of display device> First, an insulating film 420 is formed on a substrate 462, and a first element layer 410 is formed on the insulating film 420 (see FIG. 40(A)). A semiconductor element is provided in the first element layer 410. Alternatively, in addition to the semiconductor element, a part of a display element such as a display element or a pixel electrode may be provided in the first element layer 410.

[0377] The substrate 462 needs to have at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 462.

[0378] When a glass substrate is used as the substrate 462, it is preferable to form an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film between the substrate 462 and the insulating film 420 to prevent contamination from the glass substrate.

[0379] For the insulating film 420, for example, an organic resin film such as an epoxy resin, an aramid resin, an acrylic resin, a polyimide resin, a polyamide resin, or a polyamideimide resin can be used. Among these, using a polyimide resin is preferable because of its high heat resistance. When using a polyimide resin as the insulating film 420, for example, the film thickness of the polyimide resin is 3 nm or more and 20 μm or less, preferably 500 nm or more and 2 μm or less. When using a polyimide resin as the insulating film 420, it can be formed by a spin coating method, a dip coating method, a doctor blade method, etc. For example, when using a polyimide resin as the insulating film 420, by removing a part of the film using the polyimide resin by the doctor blade method, an insulating film 420 having a desired thickness can be obtained. It should be noted that the first element layer 410 preferably has a temperature in the manufacturing process of room temperature or higher and 300 °C or lower. For example, the insulating film or conductive film using an inorganic material contained in the first element layer 410 is preferably formed at a film formation temperature of 150 °C or higher and 300 °C or lower, more preferably 200 °C or higher and 270 °C or lower. Also, the insulating film using an organic resin material contained in the first element layer 410 is preferably formed at a film formation temperature of room temperature or higher and 100 °C or lower.

[0380] In addition, for the oxide semiconductor film of the transistor contained in the first element layer 410, it is preferable to use the aforementioned CAAC-OS. When using CAAC-OS for the oxide semiconductor film of the transistor, for example, when folding the display device, it is difficult for cracks or the like to enter the channel formation region, and it is possible to enhance the resistance to bending.

[0381]

[0382] ​​​​​​​Further, as the conductive film included in the first element layer 410, indium added with silicon oxide tin oxide is used, and when the display device is bent, cracks and the like are less likely to occur in the conductive film which is preferable.

[0383] Next, the first element layer 410 and the temporary support substrate 466 are adhered using the peeling adhesive 464 and the insulating film 420 and the first element layer 410 are peeled off from the substrate 462. Thereby, the insulating film 420 and the first element layer 410 are provided on the side of the temporary support substrate 466 (see FIG. 40(B)) .

[0384] As the temporary support substrate 466, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, etc. can be used. Also, a plastic substrate having heat resistance capable of withstanding the processing temperature of the present embodiment may be used, or a flexible substrate such as a film may be used .

[0385] As the peeling adhesive 464, an adhesive that can be separated chemically or physically from the temporary support substrate 466 and the first element layer 410 when necessary, such as one soluble in water or a solvent or one that can be plasticized by irradiation with ultraviolet rays or the like, is used.

[0386] Note that various methods can be appropriately used for the step of transferring to the temporary support substrate 466. For example , by irradiating the insulating film 420 with the laser light 468 from the side of the substrate 462 where the insulating film 420 is not formed, that is, the lower side shown in FIG. 40(B) , the insulating film 420 can be made brittle to peel off the substrate 462 and the insulating film 420. Also, by adjusting the energy density of the irradiation of the laser light 468, a region where the adhesion between the substrate 462 and the insulating film 420 is high and the base ​It may be possible to separate the board 462 after creating and separating an area with low adhesion between the insulating film 420 and the board 462.

[0387] In this embodiment, a method of peeling at the interface between the substrate 462 and the insulating film 420 has been exemplified, but the method is not limited thereto. For example, peeling may be performed at the interface between the insulating film 420 and the first element layer 410. For example, peeling may be performed at the interface between the insulating film 420 and the first element layer 410. It may be peeled off.

[0388] Further, a liquid may be infiltrated into the interface between the substrate 462 and the insulating film 420 to peel the insulating film 420 from the substrate 462. Alternatively, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating a liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. Further, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating a liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. It may be peeled off. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating a liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. For example, water, a polar solvent, or the like can be used. By infiltrating a liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. Specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. Specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. It is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410.

[0389] Next, the first substrate 401 is adhered to the insulating film 420 using the adhesive layer 418 (see FIG. 40(C)). See).

[0390] Next, the peeling adhesive 464 is dissolved or plasticized to remove the peeling adhesive 464 and the temporary support substrate 466 from the first element layer 410 (see FIG. 40(D)). Remove.

[0391] Note that it is preferable to remove the peeling adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed. It is preferable.

[0392] Thus, the first element layer 410 can be formed on the first substrate 401.

[0393] Next, by a forming method similar to the steps shown in FIGS. 40(A) to 40(D), a second substrate 4 05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and a second element layer 411 are formed (see FIG. 41(A)). A semiconductor element is provided in the second element layer 411. Alternatively, in addition to the semiconductor element, a display element, or a part of a display element such as a pixel electrode may be provided in the second element layer 411.

[0394] As the insulating film 440 included in the second element layer 411, a material similar to the insulating film 420, here it can be formed using an organic resin.

[0395] Next, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first element layer 410 and the second element layer 411 are bonded together (see FIG. 41(B)).

[0396] With the sealing layer 432, for example, solid sealing can be achieved. However, as the sealing layer 432 a configuration having flexibility is preferable. As the sealing layer 432, for example, a glass material such as glass frit or a curable resin that cures at room temperature such as a two-component mixed resin, a photo-curable resin or a resin material such as a thermosetting resin can be used.

[0397] As described above, a display device can be manufactured.

[0398] <Manufacturing Method 2 of Display Device> Next, another manufacturing method of the display device will be described with reference to FIG. 42. In FIG. 42 a configuration using an inorganic insulating film as the insulating film 420 will be described.

[0399] First, a release layer 463 is formed on the substrate 462. Next, an insulating film 420 is formed on the release layer 463, and a first element layer 410 is formed on the insulating film 420 (see Fig. 42(A)).

[0400] As the release layer 463, for example, an element selected from tungsten, molybdenum, titanium, tantalum, niobium , nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium , iridium, silicon, an alloy material containing the element, or a compound material containing the element can be included, and a single-layer or laminated structure can be used. Also, in the case of a layer containing silicon , the crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, polycrystalline , and single crystal.

[0401] The release layer 463 can be formed by a sputtering method, a PECVD method, a coating method, a printing method, etc. . Note that the coating method includes a spin coating method, a droplet discharge method, and a dispense method.

[0402] When the release layer 463 has a single-layer structure, it is preferable to form a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum . Also, a layer containing an oxide or oxynitride of tungsten, a layer containing an oxide or oxynitride of molybdenum, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum can be formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum .

[0403] Also, when forming a laminated structure of a layer containing tungsten and a layer containing an oxide of tungsten as the release layer 463 , a layer containing tungsten is formed, and an oxide is formed on the upper layer By forming an insulating layer, it may be utilized that a layer containing tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. Also, the surface of the layer containing tungsten may be treated with a strongly oxidizing solution such as thermal acidification treatment, oxygen plasma treatment, nitrous oxide (N2O) plasma treatment, or ozone water to form a layer containing tungsten oxide. Further, the plasma treatment or heat treatment may be performed in an atmosphere of oxygen, nitrogen, nitrous oxide alone, or a mixed gas of the gas and other gases. By changing the surface state of the release layer 463 by the above plasma treatment or heat treatment, it is possible to control the adhesion between the release layer 463 and the insulating film 420 formed later. For the insulating film 420, for example, an inorganic insulating film with low moisture permeability such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or an aluminum oxide film can be used. The above inorganic insulating film can be formed using, for example, a sputtering method, a PECVD method, or the like. Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the release layer 463. Thereby, the insulating film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 42(B)). Note that various methods can be appropriately used for the transfer process to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization, and the insulating film 420 can be peeled from the release layer 463. Also, the plasma treatment and heat treatment may be performed in an atmosphere of oxygen, nitrogen, nitrous oxide alone, or a mixed gas of the gas and other gases. By changing the surface state of the release layer 463 by the above plasma treatment or heat treatment, it is possible to control the adhesion between the release layer 463 and the insulating film 420 formed later. By forming an insulating layer, it may be utilized that a layer containing tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. Also, the surface of the layer containing tungsten may be treated with a strongly oxidizing solution such as thermal acidification treatment, oxygen plasma treatment, nitrous oxide (N2O) plasma treatment, or ozone water to form a layer containing tungsten oxide. For the insulating film 420, for example, an inorganic insulating film with low moisture permeability such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or an aluminum oxide film can be used. The above inorganic insulating film can be formed using, for example, a sputtering method, a PECVD method, or the like. Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the release layer 463. Thereby, the insulating film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 42(B)).

[0404] For the insulating film 420, for example, an inorganic insulating film with low moisture permeability such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or an aluminum oxide film can be used. The above inorganic insulating film can be formed using, for example, a sputtering method, a PECVD method, or the like. Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the release layer 463. Thereby, the insulating film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 42(B)). Note that various methods can be appropriately used for the transfer process to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization, and the insulating film 420 can be peeled from the release layer 463. Also, the plasma treatment and heat treatment may be performed in an atmosphere of oxygen, nitrogen, nitrous oxide alone, or a mixed gas of the gas and other gases. By changing the surface state of the release layer 463 by the above plasma treatment or heat treatment, it is possible to control the adhesion between the release layer 463 and the insulating film 420 formed later.

[0405] Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the release layer 463. Thereby, the insulating film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 42(B)). Note that various methods can be appropriately used for the transfer process to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization, and the insulating film 420 can be peeled from the release layer 463. Also, the plasma treatment and heat treatment may be performed in an atmosphere of oxygen, nitrogen, nitrous oxide alone, or a mixed gas of the gas and other gases. By changing the surface state of the release layer 463 by the above plasma treatment or heat treatment, it is possible to control the adhesion between the release layer 463 and the insulating film 420 formed later. By forming an insulating layer, it may be utilized that a layer containing tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. Also, the surface of the layer containing tungsten may be treated with a strongly oxidizing solution such as thermal acidification treatment, oxygen plasma treatment, nitrous oxide (N2O) plasma treatment, or ozone water to form a layer containing tungsten oxide.

[0406] Note that various methods can be appropriately used for the transfer process to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization, and the insulating film 420 can be peeled from the release layer 463. For the insulating film 420, for example, an inorganic insulating film with low moisture permeability such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or an aluminum oxide film can be used. The above inorganic insulating film can be formed using, for example, a sputtering method, a PECVD method, or the like. Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the release layer 463. Thereby, the insulating film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 42(B)). Moreover, when the release layer 463 is formed of a tungsten film, the tungsten film may be etched with a mixed solution of aqueous ammonia and hydrogen peroxide water while performing the release. The release may be performed while etching the tungsten film with a mixed solution of aqueous ammonia and hydrogen peroxide water.

[0407] Also, a liquid may be infiltrated into the interface between the release layer 463 and the insulating film 420 to release the insulating film 420 from the release layer 463. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface for releasing the insulating film 420, specifically, the interface between the release layer 463 and the insulating film 420, it is possible to suppress the influence of static electricity or the like generated due to the release applied to the first element layer 410. The insulating film 420 may be released by infiltrating a liquid such as water or a polar solvent into the interface between the release layer 463 and the insulating film 420. By infiltrating the liquid into the interface for releasing the insulating film 420, specifically, the interface between the release layer 463 and the insulating film 420, it is possible to suppress the influence of static electricity or the like generated due to the release applied to the first element layer 410. The interface for releasing the insulating film 420, specifically, the interface between the release layer 463 and the insulating film 420 By infiltrating a liquid, it is possible to suppress the influence of static electricity or the like generated due to the release applied to the first element layer 410. The influence of static electricity or the like generated due to the release applied to the first element layer 410 can be suppressed.

[0408] Next, the first substrate 401 is adhered to the insulating film 420 using the adhesive layer 418 (see FIG. 42(C)). See FIG. 42(C).

[0409] Next, the release adhesive 464 is dissolved or plasticized, and the release adhesive 464 and the temporary support substrate 466 are removed from the first element layer 410 (see FIG. 42(D)). See FIG. 42(D).

[0410] Note that it is preferable to remove the release adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed. It is preferable to remove the release adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed.

[0411] As described above, the first element layer 410 can be formed on the first substrate 401.

[0412] As described above, a display device can be manufactured.

[0413] (Embodiment 4) In this embodiment, a display device according to an aspect of the present invention and an electronic device having an input device attached thereto will be described with reference to FIGS. 43 to 48. See FIGS. 43 to 48.

[0414] <Touch panel explanation> In the present embodiment, an electronic device that combines a display device and an input device is used as an example of the electronic device. The touch panel 2000 will be described. In addition, as an example of an input device, a touch sensor The case where the above formula is used will be described.

[0415] 43(A) and (B) are perspective views of the touch panel 2000. 2, representative components of touch panel 2000 are shown for clarity.

[0416] The touch panel 2000 includes a display device 2501 and a touch sensor 2595 (see FIG. 43). The touch panel 2000 also includes a substrate 2510, a substrate 2570, and a substrate The substrate 2510, the substrate 2570, and the substrate 2590 are all However, any of the substrates 2510, 2570, and 2590 is flexible. Alternatively, one or all of the components may be configured to have no flexibility.

[0417] The display device 2501 includes a plurality of pixels on a substrate 2510 and a display device that can supply signals to the pixels. The plurality of wirings 2511 are arranged around the periphery of the substrate 2510. The wire is routed through a wire loop, part of which constitutes the terminal 2519. The terminal 2519 is an FPC 2509 (1) and electrically connect it.

[0418] The substrate 2590 includes a touch sensor 2595 and a plurality of electrodes electrically connected to the touch sensor 2595. The plurality of wirings 2598 are routed around the periphery of the substrate 2590. A part of the terminal is electrically connected to the FPC2509(2). This is the case. In FIG. 43(B), for clarity, the electrodes, wirings, etc. of the touch sensor 2595 provided on the back side of the substrate 2590 (the side facing the substrate 2510) are shown by solid lines. The electrodes and wirings of the touch sensor 2595 provided on the back side of the substrate 2590 (the side facing the substrate 2510) are shown by solid lines for clarity.

[0419] As the touch sensor 2595, for example, a capacitance type touch sensor can be applied. As the capacitance type method, there are a surface capacitance type method, a projected capacitance type method, etc.

[0420] As the projected capacitance type method, mainly due to the difference in the driving method, there are a self - capacitance method, a mutual - capacitance method, etc. Using the mutual - capacitance method is preferable because simultaneous multi - point detection becomes possible.

[0421] Note that the touch sensor 2595 shown in FIG. 43(B) is a configuration applying a projected capacitance type touch sensor. is a configuration applying a projected capacitance type touch sensor.

[0422] Note that various sensors capable of detecting the proximity or contact of a detection target such as a finger can be applied to the touch sensor 2595. can be applied to the touch sensor 2595.

[0423] The projected capacitance type touch sensor 2595 has an electrode 2591 and an electrode 2592. The electrode 2591 is electrically connected to any one of a plurality of wirings 2598, and the electrode 2592 is electrically connected to any other one of the plurality of wirings 2598. is electrically connected to any other one of the plurality of wirings 2598.

[0424] As shown in FIGS. 43(A) and (B), the electrode 2592 has a shape in which a plurality of quadrilaterals repeatedly arranged in one direction are connected at the corners. has a shape in which a plurality of quadrilaterals repeatedly arranged in one direction are connected at the corners.

[0425] The electrode 2591 is quadrilateral and is repeatedly arranged in a direction intersecting the direction in which the electrode 2592 extends. is repeatedly arranged in a direction intersecting the direction in which the electrode 2592 extends.

[0426] The wiring 2594 is electrically connected to two electrodes 2591 sandwiching the electrode 2592. At this time , a shape in which the area of the intersection of the electrode 2592 and the wiring 2594 is as small as possible is preferable. Thereby, the area of the region where no electrode is provided can be reduced, and the variation in transmittance can be reduced . As a result, the variation in the luminance of the light transmitted through the touch sensor 2595 can be reduced .

[0427] Note that the shapes of the electrode 2591 and the electrode 2592 are not limited to this, and various shapes can be taken . For example, a plurality of electrodes 2591 are arranged so that gaps are not generated as much as possible, and a plurality of electrodes 2592 are provided with an insulating layer in between and separated so that a region where they do not overlap with the electrode 2591 is formed . At this time, it is preferable to provide a dummy electrode that is electrically insulated from these two adjacent electrodes 2592, because the area of the regions with different transmittances can be reduced . .

[0428] Note that as materials that can be used for conductive films such as the electrode 2591, the electrode 2592, and the wiring 2598, that is, the wirings and electrodes constituting the touch panel , transparent conductive films having indium oxide, tin oxide, zinc oxide, etc. (for example, ITO, etc.) can be mentioned. Further, as materials that can be used for the wirings and electrodes constituting the touch panel , for example, it is preferable that the resistance value is low . As an example, silver, copper, aluminum, carbon nanotubes, graphene, metal halides (such as silver halide), etc. may be used . Further, metal nanowires composed of a plurality of very thin conductors (for example, with a diameter of several nanometers) may be used . Or, a metal mesh in which the conductor is in a mesh shape may be used. As an example, Ag nano . . Non-wire, Cu nanowire, Al nanowire, Ag mesh, Cu mesh, Al mesh, etc. may be used. For example, when using Ag nanowires for the wiring or electrodes constituting the touch panel, the transmittance in visible light can be 89% or more, and the sheet resistance value can be 40 Ω / cm or more and 1 00 Ω / cm 2 or less. Also, metal nanowires, metal meshes, carbon nanotubes, graphene, etc., which are examples of materials that can be used for the wiring or 2 electrodes constituting the above-mentioned touch panel, have a high transmittance in visible light, and thus may be used as electrodes (for example, pixel electrodes or common electrodes, etc.) for display elements. <Explanation of display device> Next, the details of the display device 2501 will be described with reference to FIGS. 44(A) and (B). FIGS. 4 4(A) and (B) correspond to a cross-sectional view between the dashed-dotted lines X1-X2 shown in FIG. 43(B).

[0429] The display device 2501 has a plurality of pixels arranged in a matrix. Each pixel has a display element and a pixel circuit for driving the display element.

[0430]

[0431] Note that in the cross-sectional view shown in FIG. 44(A), the case where an EL element that emits white light is applied as the display element is illustrated, but the EL element is not limited to this. For example, as shown in FIG. 44( B), it is also possible to adopt a configuration in which EL elements with different emission colors are painted for each pixel so that the colors of the light emitted for each adjacent pixel are different. In the following description, the case where an EL element that emits white light is applied as the display element will be taken as an example for explanation.

[0432] ​​​​​​As the substrates 2510 and 2570, for example, materials having a water vapor transmission rate of 10 -5 g / (m 2 ·day) or less, preferably 10 -6 g / (m 2 ·day) or less and having flexibility can be preferably used. Alternatively, it is preferable to use a material in which the coefficient of thermal expansion of the substrate 2510 and the coefficient of thermal expansion of the substrate 2570 are approximately equal. For example, a material having a linear expansion coefficient of 1×10 / K or less, preferably 5×10 / K or less, more preferably 1×10 - 3 / K or less can be preferably used. -5 / K or less, more preferably 1×10 -5 / K or less and can be preferably used.

[0433] Note that the substrate 2510 is a laminate having an insulating layer 2510a that prevents diffusion of impurities into the EL element, a flexible substrate 2510b, and an adhesive layer 2 510c that bonds the insulating layer 2510a and the flexible substrate 2510b. Further, the substrate 2570 is a laminate having an insulating layer 2570a that prevents diffusion of impurities into the EL element, a flexible substrate 2570b, and an adhesive layer 2570c that bonds the insulating layer 2570a and the flexible substrate 2570b. Note that the substrate 2510 is a laminate having an insulating layer 2510a that prevents diffusion of impurities into the EL element, a flexible substrate 2510b, and an adhesive layer 2 510c that bonds the insulating layer 2510a and the flexible substrate 2510b. Further, the substrate 2570 is a laminate having an insulating layer 2570a that prevents diffusion of impurities into the EL element, a flexible substrate 2570b, and an adhesive layer 2570c that bonds the insulating layer 2570a and the flexible substrate 2570b. board 2570b.

[0434] As the adhesive layers 2510c and 2570c, for example, materials containing polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, or a resin having a siloxane bond can be used for the adhesive layer. As the adhesive layers 2510c and 2570c, for example, materials containing polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, or a resin having a siloxane bond can be used for the adhesive layer. As the adhesive layers 2510c and 2570c, for example, materials containing polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, or a resin having a siloxane bond can be used for the adhesive layer. As the adhesive layers 2510c and 2570c, for example, materials containing polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, or a resin having a siloxane bond can be used for the adhesive layer.

[0435] Further, a sealing layer 2560 is provided between the substrate 2510 and the substrate 2570. The sealing layer 2560 , it preferably has a refractive index greater than that of air. Also, as shown in Fig. 44(A), when extracting light on the side of the sealing layer 2560, the sealing layer 2560 can also serve as an optical element.

[0436] Moreover, a sealing material may be formed on the outer peripheral portion of the sealing layer 2560. By using the sealing material , a configuration can be adopted in which the EL element 2550 is provided in the region surrounded by the substrate 2510, the substrate 2570, the sealing layer 2560, and the sealing material. Note that as the sealing layer 2560, an inert gas (such as nitrogen or argon) may be filled. Also, a drying material may be provided in the inert gas to adsorb moisture and the like. Moreover, as the above-mentioned sealing material, for example , it is preferable to use an epoxy-based resin or glass frit. Also, as the material used for the sealing material , it is suitable to use a material that does not permeate moisture or oxygen.

[0437] Also, the display device 2501 shown in Fig. 44(A) has pixels 2505. Also, the pixel 25 05 has a light-emitting module 2580, an EL element 2550, and a transistor 2502t that can supply power to the EL element 2550. Note that the transistor 2502 t functions as part of the pixel circuit.

[0438] Also, the light-emitting module 2580 has an EL element 2550 and a coloring layer 2567. Also , the EL element 2550 has a lower electrode, an upper electrode, and an EL layer between the lower electrode and the upper electrode.

[0439] Also, when the sealing layer 2560 is provided on the side where light is extracted, the sealing layer 2560 is in contact with the EL element 2550 and the coloring layer 2567. Note that the coloring layer 2567 has EL elements with different emission colors. When the child is painted separately for each pixel, it can also be omitted as shown in Fig. 44(B). 。

[0440] The coloring layer 2567 is located at a position overlapping the EL element 2550. As a result, a part of the light emitted by the EL element 255 0 passes through the coloring layer 2567 and is emitted outside the light emitting module 2580 in the direction of the arrow shown in the figure.

[0441] In addition, the display device 2501 is provided with a light shielding layer 2568 in the direction of light emission. The light shielding layer 2568 is provided so as to surround the coloring layer 2567.

[0442] The coloring layer 2567 only needs to have a function of transmitting light in a specific wavelength band. For example a color filter that transmits light in the red wavelength band, a color filter that transmits light in the green wavelength band, a color filter that transmits light in the blue wavelength band, a color filter that transmits light in the yellow wavelength band, etc. can be used. Each color filter can be formed using various materials by printing methods, inkjet methods, etching methods using photolithography techniques, etc. and formed by printing methods, inkjet methods, etching methods using photolithography techniques, etc.

[0443] In addition, the display device 2501 is provided with an insulating layer 2521. The insulating layer 2521 covers the transistor 2502t, etc. Note that the insulating layer 2521 has a function of flattening the unevenness caused by the pixel circuit and may also be provided with a function of suppressing the diffusion of impurities. Thereby, a decrease in the reliability of the transistor 2502t, etc. due to the diffusion of impurities can be suppressed.

[0444] In addition, the EL element 2550 is formed above the insulating layer 2521. Also, the EL element 255 ​​​​​A partition wall 2528 that overlaps with the end of the lower electrode is provided on the lower electrode of 0. Note that A spacer for controlling the distance between the substrate 2510 and the substrate 2570 may be formed on the partition wall 2528. That's okay.

[0445] Also, the gate line driving circuit 2504 includes a transistor 2503t and a capacitive element 2503c. Note that the driving circuit can be formed on the same substrate in the same process as the pixel circuit. .

[0446] Also, a wiring 2511 for supplying signals is provided on the substrate 2510. Also, a terminal 2519 is provided on the wiring 2511. Further, an FPC 2509(1) is electrically connected to the terminal 2519. Also, the FPC25 09(1) has a function of supplying a video signal, a clock signal, a start signal, a reset signal, etc. Note that an FPC25 09(1) may have a printed wiring board (PWB) attached thereto.

[0447] Note that either one or both of the transistor 2502t and the transistor 2503t may be applied with the transistor shown in the previous embodiment. The transistor used in this embodiment has an oxide semiconductor film with high purity and high crystallinity. The transistor can reduce the current value (off-current value) in the off state. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the writing interval can also be set longer in the power-on state. Thus, the frequency of the refresh operation can be reduced, and the effect of suppressing power consumption is achieved. Note that the details of the refresh operation will be described later. That's okay.

[0448] In addition, since the transistor used in this embodiment can obtain a relatively high field-effect mobility, it can be driven at high speed. For example, by using such a transistor capable of high-speed driving in a display device 2501, the switching transistor of the pixel circuit and the driver transistor used in the driving circuit can be formed on the same substrate. That is, since there is no need to use a semiconductor device formed by a separate driving circuit and a silicon wafer or the like, the number of components of the semiconductor device can be reduced. Also, in the pixel circuit, by using a transistor capable of high-speed driving, a high-quality image can be provided.

[0449] <Explanation of the touch sensor> Next, with reference to FIG. 45, the details of the touch sensor 2595 will be described. FIG. 45 corresponds to a cross-sectional view between the dashed-dotted line X3-X4 shown in FIG. 4 3(B).

[0450] The touch sensor 2595 includes electrodes 2591 and 2592 arranged in a staggered pattern on a substrate 2590, an insulating layer 2593 covering the electrodes 2591 and 2592, and a wiring 2594 that electrically connects adjacent electrodes 2 591.

[0451] The electrodes 2591 and 2592 are formed using a conductive material having translucency. As the conductive material having translucency, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide added with gallium can be used. In addition, a film containing graphene can also be used. The film containing graphene can be formed, for example, by reducing a film containing graphene oxide formed in a film shape. Examples of the reduction method include a method of applying heat. ​

[0452] For example, a conductive material having translucency is formed on a substrate 2590 by a sputtering method. Thereafter, unnecessary portions are removed by various patterning techniques such as photolithography to form electrode 2591 and electrode 2592.

[0453] In addition, as the material used for the insulating layer 2593, for example, resins such as acrylic and epoxy, resins having a siloxane bond, and inorganic insulating materials such as silicon oxide, silicon oxynitride, and aluminum oxide can also be used.

[0454] An opening reaching electrode 2591 is provided in insulating layer 2593, and wiring 2594 is electrically connected to adjacent electrode 2591. Since the translucent conductive material can increase the aperture ratio of the touch panel, it can be suitably used for wiring 2594. In addition, a material having higher conductivity than electrode 2591 and electrode 2592 can reduce the electrical resistance, so it can be suitably used for wiring 2594.

[0455] Electrode 2592 extends in one direction, and a plurality of electrodes 2592 are provided in a stripe shape. In addition, wiring 2594 is provided to intersect electrode 2592.

[0456] A pair of electrodes 2591 are provided with one electrode 2592 interposed therebetween. In addition, wiring 2594 electrically connects a pair of electrodes 2591.

[0457] Note that the plurality of electrodes 2591 do not necessarily have to be arranged in a direction perpendicular to one electrode 2592, and they may be arranged at an angle greater than 0 degrees and less than 90 degrees.

[0458] Further, the wiring 2598 is electrically connected to the electrode 2591 or the electrode 2592. Also, A part of the wiring 2598 functions as a terminal. As the wiring 2598, for example, aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum, iron, cobalt ruth, copper, or a metal material such as palladium, or an alloy material containing the metal material can be used.

[0459] Note that an insulating layer covering the insulating layer 2593 and the wiring 2594 may be provided to protect the touch sensor 2595.

[0460] Also, the connection layer 2599 electrically connects the wiring 2598 and the FPC 2509(2).

[0461] As the connection layer 2599, an anisotropic conductive film (ACF: Anisotropic Conductive Film) or an anisotropic conductive paste (ACP: Anisotropic Conductive Paste) can be used.

[0462] <Explanation of the touch panel> Next, the details of the touch panel 2000 will be described with reference to FIG. 46(A). FIG. 46( A) corresponds to a cross-sectional view between the dashed-dotted lines X5 - X6 shown in FIG. 43(A).

[0463] The touch panel 2000 shown in FIG. 46(A) has a configuration in which the display device 2501 described in FIG. 44(A) and the touch sensor 2595 described in FIG. 45 are bonded together.

[0464] Also, the touch panel 2000 shown in FIG. 46(A) has, in addition to the configuration described in FIGS. 44(A) and 45, an adhesive layer 2597 and an antireflection layer 2569.

[0465] ​​​​​ The adhesive layer 2597 is provided in contact with the wiring 2594. Note that the adhesive layer 2597 touches the substrate 2590 to the substrate 2570 so that the touch sensor 2595 overlaps the display device 2501. Also, the adhesive layer 2597 preferably has light transmissibility. Further, as the adhesive layer 25 97, a thermosetting resin or an ultraviolet curable resin can be used. For example, an a cryl resin, a urethane resin, an epoxy resin, or a siloxane resin can be used.

[0466] The antireflection layer 2569 is provided at a position overlapping the pixel. As the antireflection layer 2569, for example, a circular polarizing plate can be used.

[0467] Next, a touch panel having a configuration different from that shown in FIG. 46(A) will be described with reference to FIG. 46(B).

[0468] FIG. 46(B) is a cross-sectional view of the touch panel 2001. The touch panel 2001 shown in FIG. 46(B) differs from the touch panel 2000 shown in FIG. 46(A) in the position of the touch sensor 2595 with respect to the display device 2501. Here, different configurations will be described in detail, and parts where the same configurations can be used will refer to the description of the touch panel 2000.

[0469] The coloring layer 2567 is located below the EL element 2550. Also, the EL element 2550 shown in FIG. 46(B) emits light toward the side where the transistor 2502t is provided. As a result, a part of the light emitted by the EL element 2550 passes through the coloring layer 2567 and is emitted outside the light emitting module 2580 in the direction of the arrow shown in the figure.

[0470] ​​​​Further, the touch sensor 2595 is provided on the substrate 2510 side of the display device 2501.

[0471] The adhesive layer 2597 is between the substrate 2510 and the substrate 2590, and bonds the display device 2501 and the touch sensor 2595.

[0472] As shown in FIGS. 46(A) and (B), the light emitted from the light-emitting element may be emitted through either one or both of the substrate 2510 and the substrate 2570.

[0473] <Explanation of the driving method of the touch panel> Next, an example of the driving method of the touch panel will be described with reference to FIG. 47.

[0474] FIG. 47(A) is a block diagram showing the configuration of a mutual capacitance type touch sensor. FIG. 47( A) shows a pulse voltage output circuit 2601 and a current detection circuit 2602. In FIG. 47(A), the electrodes 2621 to which a pulse voltage is applied are denoted as X1-X6, and the electrodes 2622 for detecting the change in current are denoted as Y1-Y6, and are each illustrated by six wirings. Also FIG. 47(A) shows the capacitance 2 603 formed by the superposition of the electrode 2621 and the electrode 2622. Note that the functions of the electrode 2621 and the electrode 2622 may be mutually replaced .

[0475] The pulse voltage output circuit 2601 is a circuit for sequentially applying a pulse voltage to the wirings X1-X6. By applying a pulse voltage to the wirings X1-X6, an electric field is generated between the electrode 2621 and the electrode 2622 that form the capacitance 2603. Utilizing the fact that the electric field generated between these electrodes causes a change in the mutual capacitance of the capacitance 2603 due to shielding or the like, the proximity of the object to be detected, or also the contact of the object to be detected can be detected. the contact of the object to be detected can be detected by utilizing the fact that the electric field generated between these electrodes causes a change in the mutual capacitance of the capacitance 2603 due to shielding or the like. can detect contact.

[0476] The current detection circuit 2602 is a circuit for detecting a change in current in the wirings of Y1 to Y6 due to a change in mutual capacitance in the capacitor 2603. In the wirings of Y1 to Y6, there is no change in the current value detected when there is no proximity or contact of the object to be detected, but a change in the current value is detected when the proximity or contact of the object to be detected causes a decrease in mutual capacitance. Note that the current detection may be performed using an integration circuit or the like.

[0477] Next, FIG. 47(B) shows a timing chart of the input / output force waveforms in the mutual capacitance type touch sensor shown in FIG. 47(A). In FIG. 47(B), it is assumed that the object to be detected is detected in each matrix during one frame period. Also, in FIG. 47(B), two cases are shown: when the object to be detected is not detected (non-touch) and when the object to be detected is detected (touch). Note that for the wirings of Y1 - Y6, waveforms corresponding to the detected current values are shown.

[0478] Pulse voltages are sequentially applied to the wirings of X1 - X6, and the waveforms in the wirings of Y1 - Y 6 change according to the pulse voltages. When there is no proximity or contact of the object to be detected, the waveforms of Y1 - Y6 change uniformly in response to the change in the voltage of the wirings of X1 - X6. On the other hand, at the location where the object to be detected is in proximity or contact, since the current value decreases, the waveform of the corresponding voltage value also changes.

[0479] In this way, by detecting a change in mutual capacitance, the proximity or contact of the object to be detected can be detected.

[0480] <Explanation of the sensor circuit> In addition, in FIG. 47(A), a capacitive matrix type touch sensor is shown in which only the capacitor 2603 is provided at the intersection of the wirings as the touch sensor. However, it may also be an active matrix type touch sensor having a transistor and a capacitor. An example of the sensor circuit included in the active matrix type touch sensor is shown in FIG. 48.

[0481] The sensor circuit shown in FIG. 48 includes a capacitor 2603, a transistor 2611, a transistor 2612, and a transistor 2613.

[0482] A signal G2 is applied to the gate of the transistor 2613, a voltage VRES is applied to one of the source or the drain, and the other is electrically connected to one electrode of the capacitor 2603 and the gate of the transistor 2611. One of the source or the drain of the transistor 2611 is electrically connected to one of the source or the drain of the transistor 2612, and a voltage VSS is applied to the other. A signal G1 is applied to the gate of the transistor 2612, and the other of the source or the drain is electrically connected to the wiring ML. A voltage VSS is applied to the other electrode of the capacitor 2603.

[0483] Next, the operation of the sensor circuit shown in FIG. 48 will be described. First, when a potential that turns on the transistor 2613 is applied as the signal G2, a potential corresponding to the voltage VRES is applied to the node n to which the gate of the transistor 2611 is connected. Next, when a potential that turns off the transistor 2613 is applied as the signal G2, the potential of the node n is maintained.

[0484] Subsequently, due to the proximity or contact of a detected object such as a finger, the mutual capacitance of capacitor 2603 changes. Accordingly, the potential of node n changes from VRES.

[0485] For the read operation, a potential that turns on transistor 2612 is applied to signal G1. The current flowing through transistor 2611, that is, the current flowing through wiring ML, changes according to the potential of node n. By detecting this current, the proximity or contact of the detected object can be detected.

[0486] The transistors 2611, 2612, and 2613 can be applied with the transistors shown in the previous embodiments. In particular, by applying the transistor shown in the previous embodiments to transistor 2613, the potential of node n can be held for a long period of time, and the frequency of the operation of supplying VRES to node n again (refresh operation) can be reduced.

[0487] (Embodiment 5) In this embodiment, an example of the appearance of a display device having the pixels described in the above embodiment and an electronic device including the display device will be described.

[0488] <Appearance of Display Device> FIG. 49(A) is a perspective view showing an example of the appearance of a display device. The display device shown in FIG. 49(A) includes a panel 1601, a circuit board 1602 provided with a controller, a power supply circuit, an image processing circuit, an image memory, a CPU, etc., and a connection portion 1603. The panel 1601 includes a pixel portion 1604 provided with a plurality of pixels, a drive circuit 1605 that selects a plurality of pixels row by row, and a drive circuit 1606 that controls the input of a data voltage to the pixels in the selected row. ​ It has

[0489] From the circuit board 1602, various signals and the potential of the power supply are input into the panel 1601 via the connection part 1603. For the connection part 1603, an FPC (Flexible Printed Circuit), etc. can be used. What has a chip mounted on the FPC is called a CO F tape. When using a COF tape, mounting with a higher density can be achieved in a smaller area . Also, when using a COF tape for the connection part 1603, a part of the circuit within the circuit board 1602, or a part of the drive circuit 1605 or drive circuit 1606 that the panel 1601 has, etc. are formed on a separately prepared chip, and it may be connected to the COF tape using the COF (Chip On Film) method.

[0490] Also, a perspective view showing an example of the appearance of a display device using a COF tape 1607 is shown in Fig. 49(B) .

[0491] The chip 1608 is a semiconductor bare chip (such as an IC or LSI) having terminals such as bumps on its surface. Further, CR components can also be mounted on the COF tape 1607, and the reduction of the area of the circuit board 1602 can also be achieved. The wiring patterns of the flexible substrate are formed in a plurality corresponding to the terminals of the chips to be mounted. The chip 1608 is positioned and arranged on a flexible substrate having a wiring pattern by a bonder device or the like, and is mounted by thermocompression bonding.

[0492] Fig. 49(B) shows an example of one COF tape 1607 on which one chip 1608 is mounted, but it is not particularly limited. A plurality of rows of chips can be mounted on one side or both sides of one COF tape 1607. Although P can be implemented, in order to reduce costs, it is preferable to arrange the chips to be implemented in a single row, and more preferably, it is desirable to use only one chip. For this reason, it is preferably arranged in a single row, and more preferably, it is desirable to use only one chip.

[0493] <Configuration Example of Electronic Device> Next, an electronic device including a display device will be described.

[0494] A display device according to an aspect of the present invention can be used in a display device, a notebook personal computer, and an image playback device including a recording medium (typically a device having a display capable of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying its image). In addition, as an electronic device that can use the display device according to an aspect of the present invention, there are a mobile phone, a portable game machine, a portable information terminal, an e-book terminal, a video camera, a digital still camera, etc., a camera such as a digital still camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copying machine, a facsimile machine, a printer, a printer multifunction machine, a cash dispenser (ATM), a vending machine, and the like. Specific examples of these electronic devices are shown in FIG. 50. In addition, as an electronic device that can use the display device according to an aspect of the present invention, there are a mobile phone, a portable game machine, a portable information terminal, an e-book terminal, a video camera, a digital still camera, etc., a camera such as a digital still camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copying machine, a facsimile machine, a printer, a printer multifunction machine, a cash dispenser (ATM), a vending machine, and the like. Specific examples of these electronic devices are shown in FIG. 50. In addition, as an electronic device that can use the display device according to an aspect of the present invention, there are a mobile phone, a portable game machine, a portable information terminal, an e-book terminal, a video camera, a digital still camera, etc., a camera such as a digital still camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copying machine, a facsimile machine, a printer, a printer multifunction machine, a cash dispenser (ATM), a vending machine, and the like. Specific examples of these electronic devices are shown in FIG. 50.

[0495] FIG. 50(A) is a display device, which includes a housing 5001, a display unit 5002, a support base 5003, etc. A display device according to an aspect of the present invention can be used for the display unit 5002. Note that the display device includes all information display devices for personal computers, TV broadcast rece...

Claims

【Claim 1】 A transistor, a first capacitive element, a second capacitive element, and a light-emitting element, wherein the transistor has a first gate and a second gate, the first gate and the second gate have an overlapping region with the channel formation region of the transistor interposed therebetween, a first terminal of the transistor is supplied with a first potential, a first terminal of the first capacitive element is electrically connected to the first gate, a second terminal of the first capacitive element is electrically connected to a second terminal of the transistor, a first terminal of the second capacitive element is electrically connected to the first gate, a second terminal of the second capacitive element is electrically connected to the second gate, a first terminal of the light-emitting element is electrically connected to the second terminal of the transistor, and a second terminal of the light-emitting element is supplied with a second potential. A display device characterized by the above.

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