Semiconductor device

Abstract

To reduce a circuit scale of a semiconductor device or improve drive capability of the semiconductor device.SOLUTION: An oxide semiconductor uses a transistor in which a channel region is formed as a pull-down transistor. The oxide semiconductor has a band gap of 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Therefore, hot carrier deterioration in the transistor can be suppressed. As a result, a circuit scale of the semiconductor device having the pull-down transistor can be reduced. Also, a gate of a pull-up transistor is brought into a floating state by switching the transistor. Furthermore, by highly purifying the oxide semiconductor, an off-state current of the transistor can be reduced to 1aA / μm(1×10-18A / μm) or less. As a result, the drive capability of the semiconductor device can be improved.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to a display device. For example, a liquid crystal display device is exemplified. A display device in which pixels are selected by a pixel signal line and a source signal line to display an image is classified into a technical category. Also, semiconductor devices such as driver circuits used in display devices, display devices, etc. Electronic devices using this technology are also included as one of the technical fields. [Background technology]

[0002] A gate made of amorphous silicon transistors (also called a-Si TFTs) The development of gate driver circuits is currently underway. A transistor (pull-down transistor) that maintains the potential of the The problem is that the threshold voltage of the transistor (also called a transistor) shifts, causing malfunction. In order to solve this problem, during the period in which the potential of the gate line is kept low, A gate driver circuit is opened, in which the pull-down transistor is repeatedly turned on and off. As a result, the pull-down transistor This shortens the time that the pull-down transistor is on, which reduces the degradation of the pull-down transistor. It can be suppressed.

[0003] In addition, the gate driver circuit, which is made up of amorphous silicon transistors, A transistor that controls the timing of outputting a high voltage to the output line (a pull-up transistor A pull-up transistor has one of its source and drain connected to a clock signal. The other of the source and drain is connected to a gate signal line. The potential of the gate of the pull-up transistor is raised to a value higher than the potential of the H level of the clock signal by capacitive coupling. A driving method is used to raise it to an even higher value. To achieve this, it is necessary to put the gate of the pull-up transistor in a floating state. Therefore, it is necessary to turn off all the transistors connected to the gate of the pull-up transistor.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the conventional technology, in order for the pull-down transistor to repeatedly turn on and off, a circuit for controlling the conduction state of the pull-down transistor is required. Therefore, there is a limit to reducing the circuit scale of the semiconductor device. Also, even when all the transistors connected to the gate of the pull-up transistor are turned off, due to the off-current of the transistor, the charge held by the gate of the pull-up transistor was lost over time. Therefore, it was difficult to lower the driving frequency of semiconductor devices such as gate driver circuits. Also, the range of driving frequencies at which the semiconductor device can operate has become narrow. As a result, there is a limit to improving the driving ability of the semiconductor device.

[0006] In view of the above problems, one aspect of the present invention aims to reduce the circuit scale of the semiconductor device as one of the problems. ​​​​​​​​​Another object of one embodiment of the present invention is to improve the driving capability of a semiconductor device. Note that it is not necessary for one embodiment of the present invention to achieve all of the above-described objects. . [Means for solving the problem]

[0007] The above-mentioned problem is solved by using an oxide as the pull-up transistor or the pull-down transistor. This can be solved by applying a transistor in which the channel region is formed from a nitride semiconductor. Note that the oxide semiconductor can be formed by removing impurities (such as hydrogen or water) that serve as electron donors (donors). ) is thoroughly removed to produce a highly purified oxide semiconductor.

[0008] The oxide semiconductor has a polarization constant of 2.0 eV or more, preferably 2.5 eV or more, and more preferably 3. Therefore, the oxide semiconductor has a band gap of 0 eV or more. In a transistor in which this is formed, impact ionization and avalanche breakdown are unlikely to occur. In other words, the carriers (electrons) in the oxide semiconductor are not easily accelerated. In a transistor in which the channel region is formed from a nitride semiconductor, the gate of carriers (electrons) Shift in the threshold voltage of transistors due to implantation into the insulating layer (so-called hot capacitance) This can suppress rear deterioration.

[0009] In addition, in a transistor in which a channel region is formed using the oxide semiconductor, Therefore, the off-current per 1 μm of channel width is 1 aA (1 × 10 -18 A) or less (this is expressed as 1 aA / μm).

[0010] That is, one aspect of the present invention includes a plurality of gate signal lines, a plurality of source signal lines, pixels respectively disposed in the intersection regions of the gate signal lines and the source signal lines, and a gate driver circuit electrically connected to the plurality of gate signal lines. The gate driver circuit includes a first transistor, a second transistor, and an inverter circuit. A first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a second wiring. A first terminal of the second transistor is electrically connected to a third wiring, and a second terminal of the second transistor is electrically connected to the second wiring. An input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is electrically connected to the gate of the second transistor. The first transistor and the second transistor have channel regions formed of an oxide semiconductor, and the off-currents of the first transistor and the second transistor are 1 aA / μm or less. The display device is as described above. That is, an output terminal of the inverter circuit is electrically connected to the gate of the second transistor. The first transistor and the second transistor have channel regions formed of an oxide semiconductor, and the off-currents of the first transistor and the second transistor are 1 aA / μm or less. The display device is as described above. That is, one aspect of the present invention includes a plurality of gate signal lines, a plurality of source signal lines, pixels respectively disposed in the intersection regions of the gate signal lines and the source signal lines, and a gate driver circuit electrically connected to the plurality of gate signal lines. The gate driver circuit includes a first transistor, a second transistor, and an inverter circuit. A first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a second wiring. A first terminal of the second transistor is electrically connected to a third wiring, and a second terminal of the second transistor is electrically connected to the second wiring. An input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is electrically connected to the gate of the second transistor. The first transistor and the second transistor have channel regions formed of an oxide semiconductor, and the off-currents of the first transistor and the second transistor are 1 aA / μm or less. The display device is as described above.

[0011] Also, one aspect of the present invention includes a plurality of gate signal lines, a plurality of source signal lines, pixels respectively disposed in the intersection regions of the gate signal lines and the source signal lines, and a gate driver circuit electrically connected to the plurality of gate signal lines. The gate driver circuit includes a first transistor, a second transistor, and an inverter circuit. The first terminal of the first transistor is electrically connected to the first wiring, and the second terminal of the first transistor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the third wiring, and the second terminal of the first transistor is electrically connected to the second wiring. The input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and the output terminal of the inverter circuit is electrically connected to the gate of the second is electrically connected to the wiring, and the second terminal of the second transistor is electrically connected to the gate of the first transistor. The input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and the output terminal of the inverter circuit is electrically connected to the gate of the second transistor. The first transistor and the second transistor have channel regions formed of an oxide semiconductor, and the display device has an off-current of 1 aA / μm or less for the first transistor and the second transistor. is electrically connected to the gate of the first transistor. The input terminal of the inverter circuit is electrically connected to the gate of the first transistor. is electrically connected to the gate of the first transistor, and the output terminal of the inverter circuit is electrically connected to the gate of the second transistor. is electrically connected to the gate of the second transistor. The first transistor and the second transistor have channel regions formed of an oxide semiconductor. The off-current of the first transistor and the second transistor is 1 aA / μm or less.

[0012] Also, one aspect of the present invention includes a plurality of gate signal lines, a plurality of source signal lines, pixels respectively disposed in the intersection regions of the gate signal lines and the source signal lines, and a gate driver circuit electrically connected to the plurality of gate signal lines. The gate driver circuit includes a first transistor, a second transistor, a third transistor, and an inverter circuit. The first terminal of the first transistor is electrically connected to a first wiring, the second terminal of the first transistor is electrically connected to a second wiring, the first terminal of the second transistor is electrically connected to a third wiring, the second terminal of the second transistor is electrically connected to the second wiring, the first terminal of the third transistor is electrically connected to a fourth wiring, the second terminal of the third transistor is electrically connected to the gate of the first transistor, the gate of the third transistor is electrically connected to the fourth wiring, the input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and the output terminal of the inverter circuit is electrically connected to the gate of the second transistor. The first terminal of the first transistor is electrically connected to a first wiring, and the second terminal of the first transistor is electrically connected to a second wiring. The gate driver circuit includes a first transistor, a second transistor, a third transistor, and an inverter circuit. The first terminal of the first transistor is electrically connected to a first wiring, and the second terminal of the first transistor is electrically connected to a second wiring. The first terminal of the first transistor is electrically connected to a first wiring, and the second terminal of the first transistor is electrically connected to a second wiring. The second terminal of the first transistor is electrically connected to a second wiring. The first terminal of the second transistor is electrically connected to a third wiring. The second terminal of the second transistor is electrically connected to the second wiring. The first terminal of the third transistor is electrically connected to a fourth wiring. The second terminal of the second transistor is electrically connected to the second wiring. The first terminal of the third transistor is electrically connected to a fourth wiring. The second terminal of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the fourth wiring. The input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and the output terminal of the inverter circuit is electrically connected to the gate of the second transistor. The input terminal of the inverter circuit is electrically connected to the gate of the first transistor. The output terminal of the inverter circuit is electrically connected to the gate of the second transistor. electrically connected to the gate, and the first transistor to the third transistor are a channel region is formed of an oxide semiconductor, and the first transistor to the third transistor has an off-current of 1 aA / μm or less.

[0013] Further, one aspect of the present invention includes a plurality of gate signal lines, a plurality of source signal lines, pixels respectively disposed in intersection regions of the gate signal lines and the source signal lines, and a gate driver circuit electrically connected to the plurality of gate signal lines. The gate driver circuit includes a first transistor, a second transistor, a third transistor, and an inverter circuit. A first terminal of the first transistor is electrically connected to a first wiring, a second terminal of the first transistor is electrically connected to a second wiring, a first terminal of the second transistor is electrically connected to a third wiring, a second terminal of the second transistor is electrically connected to the second wiring, a first terminal of the third transistor is electrically connected to the third wiring, a second terminal of the third transistor is electrically connected to a gate of the first transistor, a gate of the third transistor is electrically connected to a fourth wiring, an input terminal of the inverter circuit is electrically connected to a gate of the first transistor, an output terminal of the inverter circuit is electrically connected to a gate of the second transistor, and the first transistor to the third transistor are a channel region is formed of an oxide semiconductor, and the first transistor to the third transistor has an off-current of 1 aA / μm or less. transistor is electrically connected to a gate of the first transistor, a gate of the third transistor is electrically connected to a fourth wiring, an input terminal of the inverter circuit is electrically connected to a gate of the first transistor, an output terminal of the inverter circuit is electrically connected to a gate of the second transistor, and the first transistor to the third transistor are a channel region is formed of an oxide semiconductor, and the first transistor to the third transistor has an off-current of 1 aA / μm or less. transistor has an off-current of 1 aA / μm or less.

[0014] In addition, one aspect of the present invention includes a plurality of gate signal lines, a plurality of source signal lines, pixels respectively disposed in the intersection regions of the gate signal lines and the source signal lines, and a gate driver circuit electrically connected to the plurality of gate signal lines. The gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter circuit. A first terminal of the first transistor is electrically connected to a first wiring, a second terminal of the first transistor is electrically connected to a second wiring, a first terminal of the second transistor is electrically connected to a third wiring, a second terminal of the second transistor is electrically connected to the second wiring, a first terminal of the third transistor is electrically connected to a fourth wiring, a second terminal of the third transistor is electrically connected to the gate of the first transistor, the gate of the third transistor is electrically connected to the fourth wiring, a first terminal of the fourth transistor is electrically connected to the third wiring, a second terminal of the fourth transistor is electrically connected to the gate of the first transistor, the gate of the fourth transistor is electrically connected to a fifth wiring, an input terminal of the inverter circuit is electrically connected to the gate of the first transistor, an output terminal of the inverter circuit is electrically connected to the gate of the second transistor, and the first transistor to the fourth transistor have channel regions formed of an oxide semiconductor. The display device has an off-current of 1 aA / μm or less for the first transistor to the fourth transistor. and pixels respectively disposed in the intersection regions of the gate signal lines and the source signal lines, and a gate driver circuit electrically connected to the plurality of gate signal lines. The gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter circuit. A first terminal of the first transistor is electrically connected to a first wiring, a second terminal of the first transistor is electrically connected to a second wiring, a first terminal of the second transistor is electrically connected to a third wiring, a second terminal of the second transistor is electrically connected to the second wiring, a first terminal of the third transistor is electrically connected to a fourth wiring, a second terminal of the third transistor is electrically connected to the gate of the first transistor, the gate of the third transistor is electrically connected to the fourth wiring, a first terminal of the fourth transistor is electrically connected to the third wiring, a second terminal of the fourth transistor is electrically connected to the gate of the first transistor, the gate of the fourth transistor is electrically connected to a fifth wiring, an input terminal of the inverter circuit is electrically connected to the gate of the first transistor, an output terminal of the inverter circuit is electrically connected to the gate of the second transistor, and the first transistor to the fourth transistor have channel regions formed of an oxide semiconductor. A first terminal of the first transistor is electrically connected to a first wiring, a second terminal of the first transistor is electrically connected to a second wiring, a first terminal of the second transistor is electrically connected to a third wiring, a second terminal of the second transistor is electrically connected to the second wiring, a first terminal of the third transistor is electrically connected to a fourth wiring, a second terminal of the third transistor is electrically connected to the gate of the first transistor, the gate of the third transistor is electrically connected to the fourth wiring, a first terminal of the fourth transistor is electrically connected to the third wiring, a second terminal of the fourth transistor is electrically connected to the gate of the first transistor, the gate of the fourth transistor is electrically connected to a fifth wiring, an input terminal of the inverter circuit is electrically connected to the gate of the first transistor, an output terminal of the inverter circuit is electrically connected to the gate of the second transistor, and the first transistor to the fourth transistor have channel regions formed of an oxide semiconductor. The display device has an off-current of 1 aA / μm or less for the first transistor to the fourth transistor.

[0015] An electronic device including the above-described display device and an operation switch for operating an image of the display device is also an aspect of the present invention. This is also an aspect of the present invention.

[0016] In this specification and the like, for those explicitly described as singular, it is desirable to be singular. However, it is not limited thereto, and it is also possible to be plural. Similarly, for those explicitly described as plural, it is desirable to be plural. However, it is not limited thereto, and it is also possible to be singular. However, it is not limited to this, and it is also possible to be plural. Similarly, for those explicitly described as plural, it is desirable to be plural. However, it is not limited to this, and it is also possible to be singular. However, it is not limited thereto, and it is also possible to be singular. In this specification and the like, terms such as first, second, and third are used to describe various elements, members, regions, layers, and sections separately from others. Therefore, terms such as first, second, and third do not limit the number of elements, members, regions, layers, sections, etc. Further, for example, it is possible to replace "first" with "second" or "third", etc.

[0017] In this specification and the like, terms such as first, second, and third are used to distinguish various elements, members, regions, layers, and sections from others. Therefore, terms such as first, second, and third do not limit the number of elements, members, regions, layers, and sections. Further, for example, it is possible to replace "the first" with "the second" or "the third", etc. Thus, terms such as first, second, and third do not limit the number of elements, members, regions, layers, and sections. Further, for example, it is possible to replace "the first" with "the second" or "the third", etc. That is, terms such as first, second, and third do not limit the number of elements, members, regions, layers, and sections. Further, for example, it is possible to replace "the first" with "the second" or "the third", etc.

Advantages of the Invention

Advantages of the Invention

[0018] One aspect of the present invention applies a transistor in which a channel region is formed by an oxide semiconductor as a pull-down transistor. Thereby, hole carrier degradation in the pull-down transistor can be suppressed. Therefore, the number of transistors functioning as pull-down transistors can be reduced. Further, accordingly, the scale of a circuit for controlling the switching of the pull-down transistor can be reduced. As a result, the circuit scale of a semiconductor device having the pull-down transistor can be reduced. Thereby, hole carrier degradation in the pull-down transistor can be suppressed. Therefore, the number of transistors functioning as pull-down transistors can be reduced. Further, accordingly, the scale of a circuit for controlling the switching of the pull-down transistor can be reduced. As a result, the circuit scale of a semiconductor device having the pull-down transistor can be reduced. As a result, the circuit scale of a semiconductor device having the pull-down transistor can be reduced. As a result, the circuit scale of a semiconductor device having the pull-down transistor can be reduced.

[0019] Also, one aspect of the present invention is to use an oxide semiconductor for the gate of a pull-up transistor. It is made to be in a floating state by the switching of a transistor in which a NEL region is formed. As a result, the charge held by the gate of the pull-up transistor can be held over a long period of time. Therefore, the driving frequency of the semiconductor device having the pull-up transistor can be lowered. Also, the range of the driving frequency at which the semiconductor device can operate can be widened. As a result, the driving ability of the semiconductor device can be improved.

Brief Description of the Drawings

[0020]

Figure 1

Figure 2

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Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Mode for Carrying Out the Invention

[0021] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the description of the embodiments should not be construed as being limited thereto. In the configurations described below, the same parts or parts having similar functions are denoted by common reference numerals in different drawings, and detailed descriptions of the same parts or parts having similar functions are omitted. In the drawings to be referred to, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0022] (Embodiment 1) In the present embodiment, a circuit related to a display device which is an aspect of the present invention will be described.

[0023] FIG. 1(A) shows a configuration example of a circuit having transistors 101, 102, 103, transistors 104, 105, and a circuit 200. The transistors constituting the circuit shown in FIG. 1( A) are of N-channel type. The transistors of N-channel type A transistor turns on when the potential difference between the gate and the source is greater than the threshold voltage. It is a transistor.

[0024] Note that an oxide semiconductor can be used as the semiconductor layer of the transistor constituting the circuit shown in Fig. 1(A). This oxide semiconductor has a sufficiently low hydrogen concentration and is highly purified, and has a sufficiently small carrier density, being intrinsic (i-type) or substantially intrinsic (i-type). This can reduce the S value of the transistor. The off-current of the transistor can be reduced. The breakdown voltage of the transistor can be improved. The temperature characteristics of the transistor can be improved. Deterioration of the transistor can be suppressed. Specifically, the shift amount of the threshold voltage of the transistor can be reduced.

[0025]

[0025] Note that the above oxide semiconductor can be used as the semiconductor layer of some transistors, and semiconductors other than the above oxide semiconductor (for example, silicon (amorphous silicon, microcrystalline silicon or polycrystalline silicon, etc.), organic semiconductors, etc.) can be used as the semiconductor layers of the other transistors. However, the above oxide semiconductor is used as the semiconductor layer of at least the transistor whose source or drain is connected to the gate of the transistor 101.

[0026] The connection relationship of the circuit shown in Fig. 1(A) will be described. The first terminal of the transistor 101 is connected to the wiring 111. The second terminal of the transistor 101 is connected to the wiring 112. The first terminal of the transistor 102 is connected to the wiring 113. The second terminal of the transistor 102 is connected to the wiring 112. The first terminal of the transistor 103 is connected to the wiring 1 It is connected to 13. The second terminal of transistor 103 is connected to the gate of transistor 101 and connected. The gate of transistor 103 is connected to the gate of transistor 102 . The first terminal of transistor 104 is connected to wiring 114. The second terminal of transistor 104 is connected to the gate of transistor 101. The gate of transistor 104 is connected to wiring 114. The first terminal of transistor 105 is connected to wiring 113 and connected. The second terminal of transistor 105 is connected to the gate of transistor 101. The gate of transistor 105 is connected to wiring 115. The input terminal of circuit 200 is connected to the gate of transistor 101. The output terminal of circuit 200 is connected to the gate of transistor 102 . Note that the gate of transistor 101 is shown as node 11, and the gate of transistor 102 is shown as node 12. Note that circuit 200 can be connected to any wiring or any node according to its configuration. For example, circuit 200 can be connected to one or more of wiring 111 , wiring 112, wiring 113, wiring 114, wiring 115, node 11, and node 12.

[0027] Note that since the source and drain of a transistor change depending on the structure and operating conditions of the transistor, etc., it is difficult to specify which is the source or drain. Therefore , in this document, one of the source and drain is denoted as the first terminal, and the other of the source and drain is denoted as the second terminal and distinguished.

[0028] An example of the configuration of circuit 200 will be described with reference to FIG. 1(B). Circuit 200 is a ​​It has transistor 201, transistor 202, transistor 203, and transistor 204. The first terminal of transistor 201 is connected to wiring 116. Transistor 20 The second terminal of 1 is connected to node 12. The first terminal of transistor 202 is connected to the wiring 113. The second terminal of transistor 202 is connected to node 12. The t The gate of transistor 202 is connected to node 11. The first terminal of transistor 203 is connected to wiring 116. The second terminal of transistor 203 is connected to the gate of transistor 20 1. The gate of transistor 203 is connected to wiring 116. The t The first terminal of transistor 204 is connected to wiring 113. The second terminal of transistor 204 is connected to the gate of transistor 201. The gate of transistor 204 is connected to node 11.

[0029] A clock signal is input to wiring 111. An output signal of the circuit of this embodiment is input to wiring 112 A voltage V2 is supplied to wiring 113. A start pulse is input to wiring 114. A reset signal is input to wiring 115. A voltage V1 is supplied to wiring 116. Here, for the sake of convenience, the potential of the H level of the signals input to wiring 111, wiring 112, wiring 114, and wiring 115 is defined as potential V1, and the potential of the L level of the signals input to wiring 111, wiring 112, wiring 114, and wiring 115 is defined as potential V2 for the sake of convenience. Wiring 111 is a wiring for transmitting signals such as a clock signal from an external circuit such as a controller to the circuit of this embodiment, and has a function as a signal line or a clock signal line. The wiring 111, wiring 112, wiring 114, and wiring 115, the potential of the H level of the signals input to wiring 111, wiring 112, wiring 114, and wiring 115 is defined as potential V1 for the sake of convenience, and the potential of the L level of the signals input to wiring 111, wiring 112, wiring

[0030] 114, and wiring 115 is defined as potential V2 for the sake of convenience. 111 is a wiring for transmitting signals such as a clock signal from an external circuit such as a controller to the circuit of this embodiment, and has a function as a signal line or a clock signal line. The wiring Line 112 is a wiring for transmitting the output signal of the circuit of the present embodiment to a circuit such as a pixel circuit or a demultiplexer, and has a function as a signal line or a gate signal line. Wiring 113 is a wiring for supplying a power supply voltage such as voltage V2 from an external circuit such as a power supply circuit to the circuit of the present embodiment, and has a function as a power supply line, a negative power supply line, or a ground line. Wiring 11 is a wiring for supplying a power supply voltage such as voltage V2 from an external circuit such as a power supply circuit to the circuit of the present embodiment, and has a function as a power supply line, a negative power supply line, or a ground line. Wiring 11 is a wiring for supplying a power supply voltage such as voltage V2 from an external circuit such as a power supply circuit to the circuit of the present embodiment, and has a function as a power supply line, a negative power supply line, or a ground line. Wiring 11 4 is a wiring for transmitting a start signal from an external circuit such as a timing controller or another circuit to the circuit of the present embodiment, and has a function as a signal line. Wiring 115 is a wiring for transmitting a reset signal from an external circuit such as a timing controller or another circuit to the circuit of the present embodiment, and has a function as a signal line. Wiring 116 is a wiring for transmitting a reset signal from an external circuit such as a timing controller or another circuit to the circuit of the present embodiment, and has a function as a signal line. Wiring 116 is a wiring for supplying a power supply voltage such as voltage V1 from an external circuit such as a power supply circuit to the circuit of the present embodiment, and has a function as a power supply line or a positive power supply line. a wiring for supplying a power supply voltage such as voltage V1 from an external circuit such as a power supply circuit to the circuit of the present embodiment, and has a function as a power supply line or a positive power supply line. Transistor 101 has a function as a switch for controlling the conduction state between wiring 111 and wiring 112. Also, transistor 101 has a function of controlling the timing for raising the potential of node 11 by capacitive coupling between the second terminal and the gate. Transistor 10

[0031] has a function as a switch for controlling the conduction state between wiring 113 and wiring 112. has a function as a switch for controlling the conduction state between wiring 113 and wiring 112. has a function as a switch for controlling the conduction state between wiring 113 and wiring 112. 2 has a function as a switch for controlling the conduction state between wiring 113 and wiring 112. Transistor 103 has a function as a switch for controlling the conduction state between wiring 113 and node 11. Transistor 104 has a function as a switch for controlling the conduction state between wiring 114 and node 11. Also, transistor 104 has a function as a diode with its input terminal connected to wiring 114 and its output terminal connected to node 11. Transistor 103 has a function as a switch for controlling the conduction state between wiring 113 and node 11. Transistor 104 has a function as a switch for controlling the conduction state between wiring 114 and node 11. Also, transistor 104 has a function as a diode with its input terminal connected to wiring 114 and its output terminal connected to node 11. Transistor 103 has a function as a switch for controlling the conduction state between wiring 113 and node 11. Transistor 104 has a function as a switch for controlling the conduction state between wiring 114 and node 11. Also, transistor 104 has a function as a diode with its input terminal connected to wiring 114 and its output terminal connected to node 11. Transistor 103 has a function as a switch for controlling the conduction state between wiring 113 and node 11. Transistor 104 has a function as a switch for controlling the conduction state between wiring 114 and node 11. Also, transistor 104 has a function as a diode with its input terminal connected to wiring 114 and its output terminal connected to node 11. Transistor 103 has a function as a switch for controlling the conduction state between wiring 113 and node 11. Transistor 104 has a function as a switch for controlling the conduction state between wiring 114 and node 11. Also, transistor 104 has a function as a diode with its input terminal connected to wiring 114 and its output terminal connected to node 11. Transistor 105 functions as a switch for controlling the conduction state between wiring 113 and node 11. Transistor 201 functions as a switch for controlling the conduction state between wiring 116 and node 12. In addition, transistor 201 has a function of controlling the timing for raising the potential of node 21 by capacitive coupling between the second terminal and the gate. Transistor 202 functions as a switch for controlling the conduction state between wiring 113 and node 12. Transistor 203 functions as a switch for controlling the conduction state between wiring 116 and node 12. In addition, transistor 203 has a function as a diode with its input terminal connected to wiring 116 and its output terminal connected to node 21. Transistor 204 functions as a switch for controlling the conduction state between wiring 113 and node 21. Circuit 200 has a function as a control circuit for controlling the potential of node 12 and the conduction states of transistors 102 and 103. In addition, circuit 200 has a function as an inverter circuit for inverting the potential of node 11 and outputting it to node 12. Next, an example of the operation of the circuit shown in FIGS. 1(A) and 1(B) will be described with reference to the timing chart shown in FIG. 2(A). Here, the circuit shown in FIG. 1(B) will be taken as an example for explanation.

[0032] The timing chart shown in FIG. 2(A) has periods A, B, C, and D. In period A, the potential of wiring 111 (denoted as potential V111) becomes V2, and the potential of wiring 114 becomes V3.

[0033] Next, an example of the operation of the circuit shown in FIGS. 1(A) and 1(B) will be described with reference to the timing chart shown in FIG. 2(A). Here, the circuit shown in FIG. 1(B) will be taken as an example for explanation. The timing chart shown in FIG. 2(A) has periods A, B, C, and D. In period A, the potential of wiring 111 (denoted as potential V111) becomes V2, and the potential of wiring 114 becomes V3.

[0034] In period A, the potential of wiring 111 (denoted as potential V111) becomes V2, and the potential of wiring 114 (Denoted as potential V114) becomes V1, and the potential of wiring 115 (denoted as potential V115) becomes V2. As a result, transistor 104 turns on, and wiring 114 and node 11 become conductive. Transistor 105 turns off. At this time, circuit 200 sets the potential of node 12 (denoted as potential V12) to V2. As a result, transistor 102 turns off, and wiring 113 and wiring 112 become non-conductive. Transistor 103 turns off, and wiring 113 and node 11 become non-conductive. Therefore, the potential of node 11 is supplied with the potential of wiring 114, and the potential of node 11 (denoted as potential V11) begins to rise. Eventually, the potential of node 11 becomes higher than V2 + Vth101 (Vth101 is the threshold voltage of transistor 10 1). As a result, transistor 101 turns on, and wiring 111 and wiring 112 become conductive. Therefore, the potential of wiring 111 is supplied to wiring 112, and the potential of wiring 112 (denoted as potential V112) becomes equal to V2 (see Fig. 2(B)).

[0035] After that, the potential of node 11 continues to rise. Eventually, the potential of node 11 reaches V1 - Vth104 (Vth104 is the threshold voltage of transistor 104). As a result, transistor 104 turns off, and wiring 114 and node 11 become non-conductive. Therefore, node 11 becomes floating, and the potential of node 11 maintains a value equal to V1 - Vth104 (V 1 - Vth104 is a value higher than V2 + Vth101) (see Fig. 3( A)).

[0036] During period B, the potential of wiring 111 becomes V1, the potential of wiring 114 becomes V2, and the potential of wiring 11 The potential of the transistor 104 remains at V2. Therefore, the wiring 114 and the node 11 remain in a non-conductive state. The transistor 105 is in an off state. In this case, the wiring 113 and the node 11 remain in a non-conductive state. 00 leaves the potential of node 12 equal to V2. This causes transistor 102 The transistor remains in the off state, and the wiring 113 and the wiring 112 remain in a non-conducting state. The transistor 103 remains in an off state, and the wiring 113 and the node 11 remain in a non-conducting state. Therefore, since node 11 remains floating, the potential of node 11 is V1-Vt h104 remains equal to h104. This allows transistor 101 to remain on. The wiring 111 and the wiring 112 remain in a conductive state. Therefore, the potential of the wiring 112 starts to rise. Then, the node 11 becomes floating. Since the transistor 101 is in the ON state, the potential of the node 11 is The potential at node 11 starts to rise due to parasitic capacitance. Eventually, the potential at node 11 becomes V1 + Vth101 + V a (Va is a positive potential). As a result, the potential of the wiring 112 reaches a value equal to V1. (See Fig. 3(B)). This type of operation is called bootstrap operation. say.

[0037] In the period C, the potential of the wiring 111 becomes V2, the potential of the wiring 114 remains at V2, and The potential of the line 115 becomes V1. This causes the transistor 104 to remain in the off state. Therefore, the wiring 114 and the node 11 remain in a non-conductive state. The transistor 105 is in an on state. Therefore, the wiring 113 and the node 11 are electrically connected to each other. A potential of 3 is supplied, and the potential of node 11 becomes equal to V2. As a result, the transistor 101 turns off, and the wiring 111 and the wiring 112 become non-conductive. At this time, the circuit 200 makes the potential of node 12 equal to V1. As a result, the transistor 102 turns on, and the wiring 113 and the wiring 112 become conductive. The transistor 103 turns on, and the wiring 113 and the node 11 become conductive. Therefore, since the potential of the wiring 113 is supplied to the wiring 112, the potential of the wiring 112 becomes V2 (see Fig. 4(A)).

[0038] During period D, the potential of the wiring 111 repeatedly alternates between V1 and V2, the potential of the wiring 114 remains V 2, and the potential of the wiring 115 becomes V2. As a result, the transistor 104 remains off, and the wiring 114 and the node 11 remain non-conductive. The transistor 105 turns off, and the wiring 113 and the node 11 become non-conductive. At this time, the circuit 200 keeps the potential of node 12 at V1. As a result, the transistor 102 remains on, and the wiring 113 and the wiring 112 remain conductive. The transistor 103 remains on, and the wiring 113 and the node 11 remain conductive . Therefore, since the potential of the wiring 113 is continuously supplied to the node 11, the potential of the node 11 remains V2. As a result, the transistor 101 remains off, so the wiring 111 and the wiring 112 remain non-conductive. Therefore, since the potential of the wiring 113 is continuously supplied to the wiring 112, the potential of the wiring 112 remains V2 (see Fig. 4 (B)). (B)). (B)).

[0039] ​Next, the operation of circuit 200 will be specifically described. For example, the potential of node 11 is V2 +Vth202 (Vth202 is the threshold voltage of transistor 202) or higher, and V2 +Vth204 (Vth204 is the threshold voltage of transistor 204) or higher. Thus transistor 202 turns on, and wiring 113 and node 12 become conductive . Transistor 204 turns on, and wiring 113 and node 21 become conductive . At this time, transistor 203 turns on, and wiring 116 and node 21 become conductive . Therefore, the potential of wiring 116 and the potential of wiring 113 are supplied to node 21 , and the potential of node 21 (denoted as potential V21) is higher than V2 and lower than V1 . The potential of this node 21 depends on the current supply capabilities of transistor 203 (such as channel length, channel width, mobility, etc.) and transistor 204 . Here, the potential of node 21 is set to a value lower than V2 + Vth201 (Vth201 is the threshold voltage of transistor 2 01). Thereby, transistor 201 turns off , and wiring 116 and node 12 become non-conductive. Therefore, the potential of wiring 113 is supplied to node 12 , and the potential of node 12 becomes equal to V2 (for example, during period A and period B). On the other hand, for example, assume that the potential of node 11 is less than V2 + Vth202 and less than V2 + Vth

[0040] 204. Thereby, transistor 202 turns off, and wiring 11 3 and node 12 become non-conductive. Transistor 204 turns off, and wiring 11 3 and node 21 become non-conductive. At this time, transistor 203 turns on . At this time, transistor 203 turns on , the wiring 116 and the node 21 are in a conductive state. Therefore, the potential of the wiring 116 is supplied to the node 21, and the potential of the node 21 rises. And the potential of the node 21 finally becomes V1 + Vth201 + Vb (Vb is a positive potential). As a result, the transistor 201 turns on, and the wiring 116 and the node 12 are in a conductive state. Therefore, the potential of the wiring 116 is supplied to the node 12, and the potential of the node 12 becomes V1 (for example, in periods C and D).

[0041] As described above, the circuits shown in FIGS. 1(A) and 1(B) can make the potential of the wiring 112 equal to the potential of the wiring 111 by using the bootstrap operation. Furthermore, in period B, since the potential difference (Vgs) between the gate and the source of the transistor 101 can be increased, the rise time of V112 can be shortened.

[0042] In the conventional technology, the S value of the transistor was large. Therefore, the time from when the potential of the wiring 11 4 becomes V1 until the transistor 104 turns on is long. Also, since it is necessary to lengthen period A, it is difficult to increase the driving frequency . Also, the rise time of V112 was long (the rise time of the output signal was long). Also, the load that can be connected to the wiring 112 was small. Also, the channel width of the transistor 101 was large. Also, the layout area was large .

[0043] In contrast, in this embodiment, the S value of the transistor is small. Therefore, the driving ability can be improved. For example, since the S value of the transistor 104 is small, the wiring 1 The time from when the potential of 14 becomes V1 until the transistor 104 turns on can be shortened. Therefore, the time of period A can be shortened. As a result, the driving frequency can be improved. As another example, since the S value of the transistor 101 is small, the rise time of V112 can be shortened. Also, even if a large negative load is connected to the wiring 112, the load can be driven. Further, since the channel width of the transistor 101 can be reduced, the layout area can be reduced. Note that in the conventional technology, the off-current of the transistor was large. Therefore, the amount of charge lost from the node 11 increased with the passage of time. Also, the potential of the node 11 was low.

[0044] Also, the time during which the transistor 101 could maintain the potential of the node 11 above the potential at which it turns on was short. Further, it was difficult to lower the driving frequency. Moreover, the range of the driving frequency at which it could operate was narrow.

[0045] On the other hand, in this embodiment, the off-current of the transistor is small. Therefore, the driving ability can be improved. For example, since the off-currents of the transistor 103, the transistor 104, and the transistor 105 are small, the amount of charge lost from the node 11 can be reduced. Therefore, the decrease in the potential of the node 11 can be suppressed. That is, the time during which the potential of the node 11 can be maintained above the potential at which the transistor 101 turns on can be lengthened. As a result, the driving frequency can be lowered, so the range of the driving frequency at which it can operate can be widened. ​

[0046] In the conventional technology, transistors are prone to deterioration, and the shift amount of the threshold voltage of the transistors was large. Therefore, the transistors were driven to repeat the on state and the off state. Also, two transistors were connected in parallel, and these two transistors were alternately turned on. Also, the circuit for controlling the conduction state of the transistors was complicated. Also, the number of transistors was increasing. Also, in order to suppress the deterioration of the transistors, it was necessary to increase the channel width of the transistors. Also, in order to suppress the deterioration of the transistors,

[0047] it was necessary to increase the channel length of the transistors. Also, the layout area was large. On the other hand, in the present embodiment, the shift amount of the threshold voltage of the transistors is small. Therefore, it is possible to improve the driving ability. For example, since the shift amount of the threshold voltages of transistor 102 and transistor 103 is small, the time for these transistors to turn on can be lengthened. Therefore, the circuit for controlling the conduction states of transistor 102 and transistor 103 can be simplified. As a result, the number of transistors can be reduced, so that the layout area can be reduced. Also, since the shift amount of the threshold voltages

[0048] The circuit related to the display device according to one aspect of the present invention is not limited to the circuits shown in FIGS. 1(A) and 1(B), and circuits with various other configurations can also be used. An example thereof will be described below. For example, in the circuits shown in FIGS. 1(A) and 1(B), as shown in FIG. 5(A), the input terminal of circuit 200 can be connected to wiring 112. Specifically, the gate of transistor 202 is connected to wiring 112, and the gate of transistor 204 can be connected to wiring 112. Note that FIG. 5(A) is a diagram showing the configuration when the input terminal of circuit 200 in the circuit shown in FIG. 1(A) is connected to wiring 112.

[0049] As another example, in the circuits shown in FIGS. 1(A), 1(B), and 5(A), as shown in FIG. 5(B), the first terminal of transistor 103 is connected to wiring 112, and the gate of transistor 103 can be connected to wiring 111. By doing so, the time during which transistor 103 is on can be shortened, so that the deterioration of transistor 103 can be suppressed. Also, in period B, it is possible to prevent the potential of node 11 from becoming too high, so that the destruction or deterioration suppression of transistors (for example, transistor 101, transistor 104, transistor 105, or transistors constituting circuit 200, etc.) electrically connected to node 11 can be achieved. Note that FIG. 5(B) is a diagram showing the configuration when the first terminal of transistor 103 is connected to wiring 112 and the gate of transistor 103 is connected to wiring 111 in the circuit shown in FIG. 1(A). 00 can be connected to wiring 112. Specifically, the gate of transistor 202 is connected to wiring 112, and the gate of transistor 204 can be connected to wiring 112. Note that FIG. 5(A) is a diagram showing the configuration when the input terminal of circuit 200 in the circuit shown in FIG. 1(A) is connected to wiring 112. to wiring 112. Note that FIG. 5(A) is a diagram showing the configuration when the input terminal of circuit 200 in the circuit shown in FIG. 1(A) is connected to wiring 112. to wiring 112. Note that FIG. 5(A) is a diagram showing the configuration when the input terminal of circuit 200 in the circuit shown in FIG. 1(A) is connected to wiring 112. 00 is connected to wiring 112.

[0050] As another example, in the circuits shown in FIGS. 1(A), 1(B), and 5(A), as shown in FIG. 5(B), the first terminal of transistor 103 is connected to wiring 112, and the gate of transistor 103 can be connected to wiring 111. By doing so, the time during which transistor 103 is on can be shortened, so that the deterioration of transistor 103 can be suppressed. Also, in period B, it is possible to prevent the potential of node 11 from becoming too high, so that the destruction or deterioration suppression of transistors (for example, transistor 101, transistor 104, transistor 105, or transistors constituting circuit 200, etc.) electrically connected to node 11 can be achieved. Note that FIG. 5(B) is a diagram showing the configuration when the first terminal of transistor 103 is connected to wiring 112 and the gate of transistor 103 is connected to wiring 111 in the circuit shown in FIG. 1(A). to wiring 111. By doing so, the time during which transistor 103 is on can be shortened, so that the deterioration of transistor 103 can be suppressed. Also, in period B, it is possible to prevent the potential of node 11 from becoming too high, so that the destruction or deterioration suppression of transistors (for example, transistor 101, transistor 104, transistor 105, or transistors constituting circuit 200, etc.) electrically connected to node 11 can be achieved. Note that FIG. 5(B) is a diagram showing the configuration when the first terminal of transistor 103 is connected to wiring 112 and the gate of transistor 103 is connected to wiring 111 in the circuit shown in FIG. 1(A). a diagram showing the configuration when the first terminal of transistor 103 is connected to wiring 112 and the gate of transistor 103 is connected to wiring 111 in the circuit shown in FIG. 1(A). In the circuit shown in FIG. 1(A), the first terminal of transistor 103 is connected to wiring 112, and the gate of transistor 103 is connected to wiring 111. Note that FIG. 5(B) is a diagram showing the configuration when the first terminal of transistor 103 is connected to wiring 112 and the gate of transistor 103 is connected to wiring 111 in the circuit shown in FIG. 1(A). Note that FIG. 5(B) is a diagram showing the configuration when the first terminal of transistor 103 is connected to wiring 112 and the gate of transistor 103 is connected to wiring 111 in the circuit shown in FIG. 1(A).

[0051] As another example, in the circuits shown in FIGS. 1(A), 1(B), 5(A), and 5(B), as shown in FIG. 5(C), the first terminal of transistor 104 can be connected to wiring 116. Note that FIG. 5(C) is a diagram showing the configuration when the first terminal of transistor 104 is connected to wiring 116 in the circuit shown in FIG. 1(A).

[0052] The circuits shown in FIGS. 1(A), 1(B), 5(A), 5(B), and 5(C) can be provided with various elements such as transistors or capacitive elements. An example thereof will be described below. For example, in the circuits shown in FIGS. 1(A), 1(B), 5(A), 5(B), and 5(C), as shown in FIG. 6(A), a transistor 121 can be provided in which the first terminal is connected to wiring 113, the second terminal is connected to wiring 112, and the gate is connected to wiring 115.

[0053] Transistor 121 turns on during period C, and the potential of wiring 113 is supplied to wiring 112. Therefore, the fall time of V112 can be shortened. Note that FIG. 6(A) is a diagram showing the configuration when transistor 121 is provided in the circuit shown in FIG. 1(A).

[0054] As another example, in the circuits shown in FIGS. 1(A), 1(B), 5(A), 5(B), 5(C), and 6(A), as shown in FIG. 6(B), a transistor 122 can be provided in which the first terminal is connected to wiring 113, the second terminal is connected to node 12, and the gate is connected to wiring 114.

[0054] Transistor 122 turns on during period A, and the potential of wiring 113 is supplied to node 12. As a result, during period A, V12 is connected, the second terminal is connected to node 12, and the gate is connected to wiring 114. 122 can be provided. Transistor 122 turns on during period A, and the potential of wiring 113 is supplied to node 12. becomes high. The fall time of can be shortened, and the timing when the transistor 103 turns off can be advanced. Therefore, the timing at which the potential of node 11 reaches V1 - Vth104 can be advanced, so that period A can be shortened. As a result, the driving frequency can be increased. Note that FIG. 6(B) is a diagram showing a configuration when a transistor 122 is provided in the circuit shown in FIG. 1(A).

[0055] As another example, in the circuits shown in FIGS. 1(A), 1(B), 5(A), 5(B), 5(C), 6( A), and 6(B), as shown in FIG. 6(C), a first terminal is connected to wiring 1 16, a second terminal is connected to node 12, and a gate is connected to wiring 115 It is possible to provide a transistor 123. The transistor 123 is in an on state during period C, and the potential of wiring 116 is supplied to node 12. Thereby, during period C the rise time of V12 can be shortened. Therefore, the timing at which the transistors 102 and 103 turn on can be advanced. As a result the timing at which the potential of wiring 113 is supplied to wiring 112 can be advanced, so that the fall time of V112 can be shortened. Note that FIG. 6(C) is a diagram showing a configuration when a transistor 123 is provided in the circuit shown in FIG. 1(A).

[0056] As another example, in the circuits shown in FIGS. 1(A), 1(B), 5(A), 5(B), 5(C), 6( A), 6(B), and 6(C), as shown in FIG. 7(A), a first terminal is connected to wiring 111, a second terminal is connected to wiring 117, and a gate is connected to node 11 a transistor 124 having a first terminal connected to the wiring 113 and a second terminal connected to the a transistor 125 connected to the wiring 117 and having a gate connected to the node 12; In this way, the potential of the wiring 117 can be changed at the time when the potential of the wiring 112 changes. For example, the wiring 112 and the wiring 11 One end of the wiring 112 and the wiring 117 may be connected to a load, and the other end of the wiring 112 and the wiring 117 may be connected to another circuit. Note that the transistor 125 can be omitted. 1 shows a configuration in which a transistor 124 and a transistor 125 are provided in the circuit shown in A). FIG.

[0057] As another example, Figs. 1(A), 1(B), 5(A), 5(B), 5(C), and 6( In the circuits shown in Figs. 6(A), 6(B), 6(C) and 7(A), In this way, a capacitor 126 is provided between the gate and the second terminal of the transistor 101. It is possible to provide a capacitor 12 between the gate and the second terminal of the transistor 124. 7B, a capacitor element 1 can be provided in the circuit shown in FIG. FIG. 2 is a diagram showing a configuration in which the second filter 26 is provided.

[0058] The circuit 200 is not limited to the configuration shown in FIG. 1B and may have various other configurations. Another example of the configuration will be described. For example, as shown in FIG. The transistor 201 and the transistor 202 can be omitted. In circuit 200, as shown in FIG. 8B, the gate of transistor 203 is connected to node 1 2. In the circuit 200 shown in FIG. ) As shown in ), the gate of the transistor 203 can be connected to the wiring 118. The wiring 118 receives an inverted signal (inverted clock signal) of the signal input to the wiring 111, or a signal whose phase is shifted from the signal input to the wiring 111 (for example, a phase-shifted signal such as 180°, 90°, 45°, etc.). Therefore, the wiring 118 is assumed to have a function as a signal line, a clock signal line, or an inverted clock signal line. However, the circuit 200 is not limited to the above-described configuration as long as the functions of the circuit 200 can be realized.

[0059] The above circuit is not limited to the timing chart shown in Fig. 2(A), and various other timing charts can also be used. An example thereof will be described. For example, as shown in Fig. 9(A), the signal input to the wiring 111 can be unbalanced. From this, in the period C, since the timing at which the potential of the wiring 115 becomes V1 can be made later than the timing at which the potential of the wiring 111 becomes V2, the fall time of V112 can be shortened. As another example, as shown in Fig. 9(B), the signal input to the wiring 111 can be a multi-phase clock signal. Thereby, power consumption can be reduced. Fig. 9(B) is a diagram showing an example of a timing chart when a 4-phase clock signal is input to the wiring 111.

[0060] The W / L (W: channel width, L: channel length) ratio of the transistor 101 is preferably larger than the W / L ratios of the transistors 102, 103, 104, and 105. In particular, the W / L ratio of the transistor 101 is that of the transistor 104. It is preferably 1.5 times or more and 10 times or less of the W / L ratio. More preferably, it is 1.8 times or more and 7 times or less. Even more preferably, it is 2 times or more and 4 times or less. Also, the W / L ratio of the transistor 102 is preferably larger than the W / L ratio of the transistor 103. This is because the load of the transistor 103 (for example, the node 11) is smaller than the load of the transistor 102 (for example, the wiring 112). In particular, the W / L ratio of the transistor 102 is preferably 1.5 times or more and 8 times or less of the W / L ratio of the transistor 103. More preferably, it is 2 times or more and 6 times or less. Even more preferably, it is 2 times or more and 5 times or less . Also, at least one of the channel length of the transistor 102 and the channel length of the transistor 103 is preferably larger than the channel length of the transistor 105. In particular , at least one of the channel length of the transistor 102 and the channel length of the transistor 103 is preferably larger than 1 times and 4 times or less of the channel length of the transistor 105 . More preferably, it is 1.3 times or more and 3 times or less. Even more preferably, it is 1.8 times or more and 2.5 times or less.

[0061] The wiring width of the wiring 111 is preferably smaller than at least one of the channel widths of the transistor 101, the channel width of the transistor 102 and the channel width of the transistor 104. Also, the wiring width of the wiring 111 preferably includes a portion larger than at least a part of the wiring width of the wiring 116 .

[0062] As the circuit described in this embodiment, the following configuration is included as one aspect of the present invention. A semiconductor device having a transistor 101, a transistor 102, and a circuit 200 (FIG. 10(A)) . A semiconductor device having transistor 101, transistor 103, and circuit 200 (see reference). (See FIG. 10(B)). A semiconductor device having transistor 101, transistor 102, and transistor 103, and circuit 200 (see FIG. 10(C)). A semiconductor device having transistor 101, transistor 102, transistor 104, and circuit 200 (see FIG. 10 (D)).

[0063] (Embodiment 2) In this embodiment, a shift register circuit related to a display device, which is an aspect of the present invention, will be described. The shift register circuit of this embodiment can include the circuit described in Embodiment 1 . Further, the shift register circuit of this embodiment can be used in a driving circuit of a display device such as a gate driver circuit and / or a source driver circuit.

[0064] FIG. 11 is a diagram showing a configuration example of a shift register circuit having N (N is a natural number) circuits 301 (denoted as circuits 301_1 to 301_N). As the circuit 301, the circuit described in Embodiment 1 can be used. FIG. 11 shows an example in the case where the circuit shown in FIG. 1(A) is used as the circuit 301 .

[0065] The connection relationship of the shift register circuit shown in FIG. 11 will be described. The connection relationship of circuit 301_i (i is a natural number greater than or equal to 2 and less than N - 1) will be described as an example. Circuit 301_i is connected to one of wiring 31 1_i, wiring 311_i - 1, wiring 311_i + 1, wiring 312, and wiring 313 , and wiring 314. Specifically, in circuit 301_i, wiring 112 is connected to wiring 311_i, wiring 114 is connected to wiring 311_i - 1, and wiring 115 is connected to wiring ​It is connected to 311_i + 1, and wiring 111 is connected to one of wiring 312 and wiring 313. Wiring 113 is connected to wiring 314. In circuit 301_i, when wiring 111 is connected to wiring 312, in circuit 301_i + 1 and circuit 301_i - 1, wiring 111 is connected to wiring 313. Note that circuit 301_1 is different from circuit 301_i in that wiring 114 is connected to wiring 315. Also, circuit 301_N is different from circuit 301_i in that wiring 115 is connected to the output terminal of the dummy circuit (shown as circuit 301_D). Note that as circuit 301_D, a configuration similar to that of circuit 301 can

[0066] The operation of the shift register circuit shown in FIG. 11 will be described with reference to the timing chart shown in FIG. 12.

[0067] The operation of circuit 301_i will be described as an example. First, the potential of wiring 311_i - 1 (denoted as potential V311_i - 1) becomes V1. Then, circuit 301_i performs the operation in period A described in Embodiment 1, and the potential of wiring 311_i (denoted as potential V311_i) becomes V2. After that, the potential of wiring 312 (denoted as potential V312) and the potential of wiring 313 (denoted as potential V313) are inverted. Then, circuit 301_i performs the operation in period B described in Embodiment 1, and the potential of wiring 311_i becomes V1. After that, the potential of wiring 312 and the potential of wiring 1_i performs the operation during the period D described in Embodiment 1 until the potential of the wiring 311_i-1 becomes V1 again, and the potential of the wiring 311_i remains at V2. However, the circuit 301_1 performs an operation different from that of the circuit 301_i when the potential of the wiring 315 (denoted as potential V315) becomes V1 during the period A. Also, the circuit 301_N performs an operation different from that of the circuit 301_i when the output signal of the circuit 301_D becomes V1 during the period C. As described above, the potential of the wiring 311_1 (denoted as potential V311_1) to the potential of the wiring 311_N (denoted as potential V311_N) can be sequentially set to V1. And by being configured by the circuit described in Embodiment 1, the shift register circuit shown in FIG. 11 can obtain the same advantages as the circuit described in Embodiment 1.

[0068] The output signal of the shift register circuit is input to the wiring 311 (one of the wirings 311_1 to 311_N). A clock signal is input to the wiring 312. To the wiring 313 is input a clock signal having a phase different from that of the clock signal input to the wiring 312, or an inverted signal of the clock signal input to the wiring 312. A voltage V2 is supplied to the wiring 314. A start signal is input to the wiring 315.

[0069] The wiring 311 is a wiring for transmitting the output signal of the shift register circuit to a circuit such as a pixel circuit or a demultiplexer, and has a function as a signal line or a gate signal line. The wiring 31 2 and the wiring 313 are from an external circuit such as a controller to the shift register circuit of the present embodiment

[0070] is a wiring for transmitting signals such as a clock signal, and functions as a signal line or a clock signal line. The wiring 314 is a wiring for supplying a power supply voltage such as voltage V2 from an external circuit such as a power supply circuit to the shift register circuit of the present embodiment, and functions as a power supply line, a negative power supply line, or a ground line. The wiring 315 is a wiring for transmitting a start signal from an external circuit such as a controller to the shift register circuit of the present embodiment, and functions as a signal line.

[0071] (Embodiment 3) In the present embodiment, an example of a transistor constituting the circuit described in Embodiment 1 or 2 will be described. Specifically, an example of the structure and manufacturing process of a transistor in which a channel region is formed of an oxide semiconductor will be described.

[0072] As the oxide semiconductor, a quaternary metal oxide In-Sn-Ga-Zn-O-based oxide semiconductor, a ternary metal oxide In-Ga-Zn-O-based oxide semiconductor, In-Sn-Zn -O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, or Sn-Al-Zn-O-based oxide semiconductor, or a binary metal oxide In-Zn-O-based oxide semiconductor, Sn-Zn- O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, S n-Mg-O-based oxide semiconductor, In-Mg-O-based oxide semiconductor, In-O-based oxide semiconductor , Sn-O-based oxide semiconductor, or Zn-O-based oxide semiconductor can be used. Further, an oxide semiconductor obtained by adding SiO2 to the above oxide semiconductor may also be used.

[0073] ​​​​​​​ In addition, the oxide semiconductor can use a substance represented by InMO3(ZnO) m (m > 0 and m is not a natural number). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co . For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. Among the oxide semiconductors represented by InMO3(ZnO) (m > 0 and m is not a natural number), an oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O oxide semiconductor, and its thin film is also referred to as an In-Ga-Zn-O film m (m > 0 and m is a natural number). Among the oxide semiconductors represented by InMO3(ZnO) (m > 0 and m is not a natural number), an oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O oxide semiconductor, and its thin film is also referred to as an In-Ga-Zn-O film . Also, the oxide semiconductor material represented by In-Ga-Zn-O in this specification is InGaO3(ZnO) (m > 0 and m is not a natural number), and the fact that m m is not a natural number can be confirmed by using ICP-MS analysis or RBS analysis .

[0074] A form of a method for manufacturing a transistor in which a channel region is formed of an oxide semiconductor will be described with reference to FIG. 13

[0075] FIGS. 13(A) to (D) are diagrams showing an example of the cross-sectional structure of a transistor. The transistor 410 shown in FIG. 13(D ) is one of the bottom gate structures called the channel etch type .

[0076] Also, FIG. 13(D) shows a single gate structure transistor, but if necessary, it can be a multi-gate structure transistor having a plurality of channel regions

[0077] Hereinafter, using FIGS. 13(A) to (D), the process of manufacturing the transistor 410 on the substrate 400 ​Describe the process.

[0078] First, after forming a conductive film on a substrate 400 having an insulating surface, a gate electrode layer 411 is formed by a first photolithography process.

[0079] There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance to withstand subsequent heat treatment. For example, it is possible to use a glass substrate such as barium borosilicate glass or aluminoborosilicate glass. Also, when the temperature of the subsequent heat treatment is high, it is advisable to use a glass substrate with a strain point of 730 °C or higher.

[0080] An insulating film serving as an underlayer may be provided between the substrate 400 and the gate electrode layer 411. The underlayer has a function of preventing the diffusion of impurity elements from the substrate 400 and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0081] Also, the gate electrode layer 411 can be formed as a single layer or by lamination using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material having these as main components.

[0082] Next, a gate insulating layer 402 is formed on the gate electrode layer 411.

[0083] The gate insulating layer 402 is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed by using a plasma CVD method, a sputtering method, etc. ​​​​​​The gate insulating layer may be formed of a single layer or a stacked layer. High-k materials such as hafnium (HfOx) and tantalum oxide (TaOx) can also be used. The thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. For example, the first gate insulating layer has a thickness of 50 nm or more and 200 nm or less, and the first gate insulating layer has a thickness of 50 nm or more and 200 nm or less. A second gate insulating layer having a thickness of 5 nm to 300 nm is laminated on the edge layer.

[0084] In this embodiment, the gate insulating layer 402 is formed by a plasma CVD method to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0085] In addition, a silicon oxynitride layer is formed as the gate insulating layer 402 by using a high density plasma device. Here, the high-density plasma device is 1×10 11 / cm 3 Plasma density above For example, a microwave power of 3kW to 6kW can be applied to the device. The insulating layer formed by the high density plasma device is Since it is possible to form a film of a constant thickness, it has excellent step coverage. The insulating layer obtained by this arrangement can be precisely controlled to a thin film thickness.

[0086] The insulating layer obtained by the high-density plasma device is different from that obtained by the conventional parallel plate type PCVD device. The film quality is significantly different from that of the insulating layer, and the etching rates are compared using the same etchant. In comparison, the insulating layer obtained by the parallel plate PCVD equipment is 10% or more The etching rate is slower than 0.0%, and the insulating layer obtained by the high-density plasma device can be said to be a dense layer. do.

[0087] Note that an oxide semiconductor that is or substantially is i-typed in a later process (a highly purified oxide semiconductor) is extremely sensitive to interface levels and interface charges. Therefore, the interface with the gate insulating layer is important. Therefore, the gate insulating layer (GI) in contact with the highly purified oxide semiconductor is required to be of high quality. Therefore, high-density plasma CVD using microwaves (2.45 GHz) is preferred because it can form a high-quality insulating layer that is dense and has a high breakdown voltage. By closely contacting the highly purified oxide semiconductor with the high-quality gate insulating layer, the interface levels can be reduced and the interface characteristics can be made good because of this. Needless to say, it is important that the film quality as the gate insulating layer is good, and it is important to reduce the interface level density with the oxide semiconductor and form a good interface is important. Next, an oxide semiconductor film 43 0 with a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 402. The oxide semiconductor film 430 can be any oxide semiconductor film such as an In-Ga-Zn-O system or an In-Zn-O system. In this embodiment, as the oxide semiconductor film 430, a film is formed by sputtering using an In-Ga-Zn-O system oxide semiconductor target. The cross-sectional view at this stage

[0088] corresponds to Fig. 13(A). Also, the oxide semiconductor film 430 can be formed by sputtering in an inert gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of an inert gas (typically argon) and oxygen. Here, a metal oxide target containing In, Ga, and Zn (In2O3:Ga2O3 :ZnO = 1:1:1 [mole ratio]) is used, and the distance between the substrate and the target is 10 cm. The cross-sectional view at this stage corresponds to Fig. 13(A). Also, the oxide semiconductor film 430 can be formed by sputtering in an inert gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of an inert gas (typically argon) and oxygen. Typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of an inert gas (typically argon) and oxygen. can be formed by sputtering.

[0089] Here, a metal oxide target containing In, Ga, and Zn (In2O3:Ga2O3 :ZnO = 1:1:1 [mole ratio]) is used, and the distance between the substrate and the target is 10 0 mm, pressure 0.2 Pa, DC power supply 0.5 kW, in an atmosphere of argon and oxygen (argon: oxygen = 30 sccm:20 sccm, oxygen flow rate ratio 40%), a film is formed. Note that, when using a pulsed DC power supply, the powdery substances generated during film formation can be reduced, and the film thickness distribution is also preferred because it becomes uniform. The film thickness of the In-Ga-Zn-O-based film is 5 nm or more and 200 nm or less. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O-based metal oxide target is used to form an In-Ga-Zn-O-based film with a film thickness of 20 nm by sputtering. Next, the oxide semiconductor film 430 is processed into island-shaped oxide semiconductor layers by a second photolithography process.

[0090] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or more and 750°C or less, preferably less than the strain point of the substrate at 400°C or more. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without being exposed to the atmosphere, the mixing of water and hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 431 is obtained (see Fig. 13(B)). Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, RTA (Rapid Thermal Annealing) apparatuses such as GRTA (Gas Rapid Thermal Annealing) apparatuses and LRTA (Lamp Ra pid Thermal Annealing) apparatuses can be used. The LRTA apparatus is a halogen lamp

[0091] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, RTA (Rapid Thermal Annealing) apparatuses such as GRTA (Gas Rapid Thermal Annealing) apparatuses and LRTA (Lamp Ra pid Thermal Annealing) apparatuses can be used. The LRTA apparatus is a halogen lamp mal Annealing) apparatuses can be used. The LRTA apparatus is a halogen lamp ​Lamps such as incandescent lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lithium lamps, high-pressure mercury lamps, etc., are devices that heat the object to be treated by the radiation of light (electromagnetic waves) emitted from the lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. In the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. For example, as the first heat treatment, the substrate is moved and placed in an inert gas heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and then the GRTA may be performed to move the substrate out of the inert gas heated to a high temperature. Using GRTA enables high-temperature heat treatment in a short time.

[0092] In the atmosphere of the first heat treatment, it is preferably not to contain water, hydrogen, etc. in nitrogen, or rare gases such as helium, neon, argon, or dry air. For example, the purity of nitrogen or rare gases such as helium, neon, argon, etc. introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0093] In addition, the first heat treatment of the oxide semiconductor layer can also be performed on the oxide semiconductor film 430 before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device, and the second photolithography process is performed.

[0094] When forming an opening in the gate insulating layer 402, the process is performed on the oxide semiconductor film 430.

[0095] It may be performed before or after the dehydration or dehydrogenation treatment.

[0096] Note that the etching of the oxide semiconductor film 430 here is not limited to wet etching and dry etching may be used.

[0097] As the etching gas for the oxide semiconductor film 430 used in dry etching, a gas containing chlorine (for example, chlorine (Cl2), boron trichloride (BCl3), etc.) is preferable.

[0098] As the etching solution for the oxide semiconductor film 430 used in wet etching, a solution obtained by mixing phosphoric acid, acetic acid and nitric acid, aqueous ammonia peroxide (31 wt% hydrogen peroxide water: 28 wt% ammonia water: water = 5: 2: 2), etc. can be used. Further, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0099] Next, a metal conductive film is formed on the gate insulating layer 402 and the oxide semiconductor layer 431. The metal conductive film may be formed by sputtering or vacuum evaporation. As the material of the metal conductive film, a element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti) , molybdenum (Mo), tungsten (W), neodymium (Nd), scandium (Sc) , an alloy containing the above-described elements as components, or an alloy obtained by combining the above-described elements and the like can be mentioned. Further, a nitride film of the above-described elements may be used. Also, manganese (Mn ), magnesium (Mg), zirconium (Zr), beryllium (Be), yttrium (Y) or a material selected from any one or more of them may be used. Further, the metal conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon A single-layer structure of the mu film, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer structure in which an aluminum film is laminated on a titanium film and then a titanium film is laminated on the aluminum film, etc. can be mentioned. When a heat treatment is performed after forming the metal conductive film, it is preferable to give the metal conductive film heat resistance to withstand this heat treatment. It can be mentioned.

[0100] When a heat treatment is performed after forming the metal conductive film, it is preferable to give the metal conductive film heat resistance to withstand this heat treatment. It is preferable to give it to the metal conductive film.

[0101] A resist mask is formed on the metal conductive film by the third photolithography process, and after selectively etching to form the source electrode layer 415a and the drain electrode layer 415b, the resist mask is removed (see Fig. 13(C)). After selectively etching to form the source electrode layer 415a and the drain electrode layer 415b, the resist mask is removed (see Fig. 13(C)). Mask is removed (see Fig. 13(C)).

[0102] In this embodiment, a titanium film is used as the metal conductive film, an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layer 431, and an ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide solution) is used as the etchant. -Ga-Zn-O-based oxide is used, and ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide solution) is used as the etchant. A mixed solution of water and hydrogen peroxide solution) is used.

[0103] In the third photolithography process, only a part of the oxide semiconductor layer 431 may be etched to form an oxide semiconductor layer having a groove portion (recess). It may become an oxide semiconductor layer having a groove portion (recess).

[0104] In addition, in order to reduce the number of photomasks and processes used in the photolithography process, an etching process may be performed using a resist mask formed by a multi-tone mask, which is an exposure mask in which the transmitted light has a plurality of intensities. The resist mask formed by a multi-tone mask, which is an exposure mask in which the transmitted light has a plurality of intensities, has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing ashing. It can be used in a plurality of etching processes for processing into different patterns because it can be further deformed by performing ashing. The resist mask formed using a multi-tone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing ashing. Therefore, it can be used in a plurality of etching processes for processing into different patterns. Therefore, with a single multi-tone mask, it is possible to form a resist mask corresponding to at least two or more different patterns. Thus, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, enabling the simplification of the process. Next, plasma treatment is performed using a gas such as nitrous oxide (N2O), nitrogen (N2), or argon (Ar). This plasma treatment removes adsorbed water and the like adhering to the surface of the exposed oxide semiconductor layer. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon. After the plasma treatment, without being exposed to the atmosphere, an oxide insulating layer 416 serving as a protective insulating layer in contact with a part of the oxide semiconductor layer 431 is formed.

[0105] The oxide insulating layer 416 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the oxide insulating layer 416, such as a sputtering method. If hydrogen is contained in the oxide insulating layer 416, the hydrogen will penetrate into the oxide semiconductor layer, causing the back channel of the oxide semiconductor layer 431 to have a lower resistance (N-type), and a parasitic channel will be formed. Therefore, it is important not to use hydrogen in the film formation method so that the oxide insulating layer 416 becomes a film that contains as little hydrogen as possible. In this embodiment, a silicon oxide film with a film thickness of 200 nm is formed as the oxide insulating layer 416 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is set to 100°C. The film formation of the silicon oxide film by the sputtering method is typically performed using a rare gas.

[0106] After the plasma treatment, without being exposed to the atmosphere, an oxide insulating layer 416 serving as a protective insulating layer in contact with a part of the oxide semiconductor layer 431 is formed.

[0107] The oxide insulating layer 416 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the oxide insulating layer 416, such as a sputtering method. If hydrogen is contained in the oxide insulating layer 416, the hydrogen will penetrate into the oxide semiconductor layer, causing the back channel of the oxide semiconductor layer 431 to have a lower resistance (N-type), and a parasitic channel will be formed. Therefore, it is important not to use hydrogen in the film formation method so that the oxide insulating layer 416 becomes a film that contains as little hydrogen as possible. In this embodiment, a silicon oxide film with a film thickness of 200 nm is formed as the oxide insulating layer 416 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is set to 100°C. The film formation of the silicon oxide film by the sputtering method is typically performed using a rare gas.

[0108] In this embodiment, a silicon oxide film with a film thickness of 200 nm is formed as the oxide insulating layer 416 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is set to 100°C. The film formation of the silicon oxide film by the sputtering method is typically performed using a rare gas. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is set to 100°C. The film formation of the silicon oxide film by the sputtering method is typically performed using a rare gas. ​​​​​​It can be carried out in an argon atmosphere, an oxygen atmosphere, or an atmosphere of a noble gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, a silicon oxide film can be formed by sputtering in an atmosphere of oxygen and nitrogen. Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is carried out in an inert gas atmosphere, a dry air atmosphere, or an oxygen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is carried out in a nitrogen atmosphere. When the second heat treatment is carried out, a part (channel region) of the oxide semiconductor layer is heated in contact with the oxide insulating layer 416. Thereby, oxygen is supplied to a part (channel region) of the oxide semiconductor layer.

[0109] After the heat treatment for dehydration or dehydrogenation of the oxide semiconductor layer is carried out through the above steps, a part (channel region) of the oxide semiconductor layer is selectively made in an oxygen-excessive state. The transistor 410 is formed through the above steps.

[0110]

[0111]

[0112] Furthermore, a heat treatment may be carried out in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. In this embodiment, a heat treatment is carried out at 150°C for 10 hours. This heat treatment may be carried out while maintaining a constant heating temperature, or the temperature may be raised from room temperature to a heating temperature of 100°C or higher and 200°C or lower and then lowered from the heating temperature to room temperature multiple times.

[0112] A protective insulating layer may be further formed on the oxide insulating layer 416. For example, the RF sputtering method may be used. is used to form a silicon nitride film. Since the RF sputtering method has good mass productivity, it is preferred as a method for forming the protective insulating layer. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH - and uses an inorganic insulating film that blocks these from entering from the outside. For example, a silicon nitride film, aluminum nitride film, silicon oxynitride film, aluminum oxynitride film, etc. are used. In this embodiment, the protective insulating layer 403 is formed using a silicon nitride film as the protective insulating layer (refer to Fig. 13(D ). )

[0113] In this embodiment, the oxide semiconductor layer of the transistor 410 has hydrogen, which is an n-type impurity, removed from the oxide semiconductor, and is highly purified so that impurities are not contained as much as possible other than the main components of the oxide semiconductor, thereby making it intrinsic (i-type) or substantially intrinsic. That is, instead of adding impurities to make it i-type, impurities such as hydrogen and water are removed as much as possible, characterized by being highly purified to i-type (intrinsic semiconductor) or approaching it. By doing so, the Fermi level (E ) can be made the same level as the intrinsic Fermi level (E ). f ) i

[0114] The bandgap (Eg) of the oxide semiconductor is 3.15 eV, and the electron affinity (χ) is said to be 4. 3 eV. The work function of titanium (Ti ) that constitutes the source electrode layer and the drain electrode layer is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons.

[0115] For example, in an element where the channel width W of the transistor is 1×10 4 μm and the channel length L is 3 μm Even if the off-state current is less than 10 -13 A or less, and the S value is 0.1V / dec ade (gate insulating layer thickness 100 nm).

[0116] In this way, it is possible to highly purify the oxide semiconductor so that it contains as few impurities as possible other than the main component. As a result, the transistor 410 can operate satisfactorily.

[0117] In order to suppress fluctuations in electrical characteristics, the oxide semiconductor described above is made to be free of hydrogen, moisture, and other factors that cause fluctuations. Impurities such as hydroxyl groups or hydrides (also called hydrogen compounds) are intentionally excluded, and impurities The oxygen, which is the main component of the oxide semiconductor, is reduced at the same time by the removal process. Since the oxide semiconductor is supplied to the semiconductor substrate, it is highly purified and electrically i-type (intrinsic) oxide semiconductor.

[0118] Therefore, the less hydrogen there is in the oxide semiconductor, the better. There are very few carriers in semiconductors (close to zero), with a carrier density of 1×10 12 / c m 3 Less than 1 x 10 11 / cm 3 That is, the carrier of the oxide semiconductor layer is less than 1000 nm. The carrier density is close to zero. Since there are very few carriers in the oxide semiconductor layer, In a transistor, the off-state current can be reduced. The smaller the off-state current, the better. The transistor has a current value of 100 aA or less per 1 μm of channel width (w). Preferably, it is 10 zA (zeptoamperes) or less, and more preferably, it is 1 zA or less. In addition, there is no pn junction and no hot carrier degradation, so the electrical characteristics of the transistors are Gender is not affected.

[0119] By thoroughly removing hydrogen contained in the oxide semiconductor layer in this way, a highly purified transistor using an oxide semiconductor in the channel region can make the off-current extremely small. That is, in the non-conducting state of the transistor, the oxide semiconductor layer can be regarded as an insulator and circuit design can be performed. On the other hand, in the conducting state of the transistor, the oxide semiconductor layer can be expected to have a higher current supply capacity than a semiconductor layer formed of amorphous silicon.

[0120] Also, in a transistor having low-temperature polysilicon, compared with a transistor fabricated using an oxide semiconductor, the design is made assuming that the off-current is about 10,000 times larger. Therefore, in a transistor having an oxide semiconductor, when the holding capacitance is equivalent (about 0.1 pF) compared with a transistor having low-temperature polysilicon, the voltage holding period can be extended about 10,000 times. As an example, when video display is performed at 60 frames per second, the holding period by one signal write can be made about 160 seconds, which is 10,000 times. And even with a small number of write times of image signals, display of a still image on the display unit can be performed.

[0121] (Embodiment 4) In this embodiment, an example of a display device according to an aspect of the present invention will be described.

[0122] FIG. 14(A) shows an example of a display device in which the shift register circuit of Embodiment 2 is used. The display device shown in FIG. 14(A) includes a timing controller 5360, a source driver circuit 5362, a gate driver circuit 5363_1, and a gate driver circuit 5363_2. It has a driving circuit 5361 and a pixel section 5364. In the pixel section 5364, a plurality of source signal lines 5371 extend from a source driver circuit 5362 and are arranged, and a plurality of gate signal lines 5372 extend from a gate driver circuit 5363_1 and a gate driver circuit 5363_2 and are arranged. In the intersection region of the plurality of source signal lines 5371 and the plurality of gate signal lines 5372, pixel 5367 are arranged in a matrix respectively.

[0123] Note that the display device can have a lighting device and its control circuit, etc. In this case, the pixel 5367 may have a liquid crystal element.

[0124] Note that one of the gate driver circuit 5363_1 and the gate driver circuit 5363_2 can be omitted.

[0125] The timing controller 5360 is a circuit having a function of controlling the operation of the driving circuit 5361 by supplying a control signal to the driving circuit 5361. For example, the timing controller 5360 supplies control signals such as a start signal SSP, a clock signal SCK, an inverted clock signal SCKB, a video signal DATA, and a latch signal LAT to the source driver circuit 5362. Also, the timing controller 5360 supplies control signals such as a start signal GSP, a clock signal GCK, and an inverted clock signal GCKB to the gate driver circuit 5363_1 and the gate driver circuit 5363_2.

[0126] The source driver circuit 5362 is a circuit having a function of outputting video signals to the plurality of source signal lines 5371 respectively, and can be called a driving circuit or a signal line driving circuit, etc. The video ​​​​​​The image signal is input to pixel 5367, and the display element constituting pixel 5367 assumes a gradation corresponding to the video signal. It becomes a gradation corresponding to the video signal.

[0127] The gate driver circuits 5363_1 and 5363_2 are circuits having a function of sequentially selecting the pixels 5 367 in each row, and can be called a driving circuit or a scanning line driving circuit. The control of the timing for selecting pixel 5367 is performed by the gate driver circuits 5363 _1 and 5363_2 outputting a gate signal to the gate signal line 5372. This is done by the gate driver circuits 5363_1 and 5363_2 outputting a gate signal to the gate signal line 5372.

[0128] In the display device shown in FIG. 14(A), the gate driver circuits 5363_1 and 5363_2 can be formed on the same substrate as the pixel portion 5364. FIG. 14(B) shows an example in which the gate driver circuits 5363_1 and 5363_2 are formed on the same substrate (shown as substrate 5380) as the pixel portion 5364. Incidentally 14(B) shows an example in which the gate driver circuits 5363_1 and 5363_2 are formed on the same substrate (shown as substrate 5380) as the pixel portion 5364. Incidentally, the substrate 5380 and the external circuit are connected via the terminal 5381. the substrate 5380 and the external circuit are connected via the terminal 5381.

[0129] In the display device shown in FIG. 14(A), a part of the source driver circuit 5362 (for example a switch, a multiplexer, a shift register circuit, a decoder circuit, an inverter circuit, a buffer circuit, and / or a level shifter circuit, etc.) can be formed on the same substrate as the pixel portion 5364. FIG. a switch, a multiplexer, a shift register circuit, a decoder circuit, an inverter circuit, a buffer circuit, and / or a level shifter circuit, etc.) can be formed on the same substrate as the pixel portion 5364. FIG. 14(C) shows that on the same substrate (shown as substrate 5380) as the pixel portion 5364 the gate driver circuits 5363_1 and 5363_2 and a part of the source driver circuit 5362 (shown as 5362a) are formed, and a part of the source driver circuit 5362 Another portion (designated 5362b) is shown formed on a substrate different from substrate 5380. vinegar.

[0130] The shift register described in the second embodiment may be used as a driving circuit or a part of the driving circuit of the display device. In particular, the display device may be driven by a transistor circuit as described in the third embodiment. When the transistors are used, the shift register circuit described in the second embodiment is used. By doing so, it is possible to improve the driving capability of the driving circuit. Alternatively, the resolution of the display device can be improved. Since the layout area of the circuit can be reduced, the frame of the display device can be made smaller. can be done.

[0131] (Embodiment 5) In this embodiment, an example of an electronic device will be described.

[0132] 15(A) to 15(H) and 16(A) to 16(D) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, and an LED. A lamp 5004, an operation key 5005 (including a power switch or an operation switch), a connection terminal Child 5006, sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (has the function of measuring flow rate, humidity, gradient, vibration, odor or infrared rays), microphone 5008, etc.

[0133] FIG. 15A shows a mobile computer, which includes, in addition to the above, a switch 5009, It can have an infrared port 5010, etc. FIG. 15(B) is a portable type image playback device (for example, a DVD playback device). In addition to the above-described components, it can have a second display unit 5002, a recording medium reading unit 5011, etc. FIG. 15(C) is a goggle type display. In addition to the above-described components, it can have a second display unit 5002, a support unit 5012, earphones 5013, etc. FIG. 15(D) is a portable game machine. In addition to the above described components, it can have a recording medium reading unit 5011, etc. FIG. 15(E) is a p rojector. In addition to the above-described components, it can have a light source 5033, a projection lens 5034, etc. FIG. 15(F) is a portable game machine. In addition to the above-described components, it can have a second display unit 5002, a recording medium reading unit 5011, etc. FIG. 15(G) is a television receiver. In addition to the above-described components, it can have a tuner, an image processing unit, etc. FIG. 15(H) is a portable television receiver. In addition to the above-described components, it can have a charger 5017 capable of transmitting and receiving signals FIG. 16(A) is a display. In addition to the above-described components, it can have a support stand 5018, etc. FIG. 16(B) is a camera and, in addition to the above-described components, it can have an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 16(C) is a computer. In addition to the above-described components it can have a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 16(D) is a mobile phone. In addition to the above-described components it can have an antenna, a one-seg (one-segment partial reception service for mobile phones and mobile terminals) tuner, etc.

[0134]

[0134] The electronic devices shown in FIGS. 15(A) to 15(H) and FIGS. 16(A) to 16(D) can have various functions. For example, functions such as displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, displaying a calendar, date, or time, etc., controlling processing by various software (programs), a wireless communication function, connecting to various computer networks using the wireless communication function, transmitting or receiving various data using the wireless communication function, reading a program or data recorded on a recording medium and displaying it on the display unit, etc. can be provided. Furthermore, in an electronic device having a plurality of display units, a function of mainly displaying image information on one display unit and mainly displaying character information on another display unit, or a function of displaying a three-dimensional image by displaying an image considering parallax on a plurality of display units, etc. can be provided. Furthermore, in an electronic device having an imaging unit, functions such as taking a still image, taking a moving image, automatically or manually correcting the taken image, saving the taken image on a recording medium (external or built into the camera), and displaying the taken image on the display unit, etc. can be provided . Note that the functions that the electronic devices shown in FIGS. 15(A) to 15(H) and FIGS. 16(A) to 16(D) can have are not limited to these, and they can have various functions.

[0135] FIG. 16(E) shows an example in which a display device is provided integrally with a building. FIG. 16(E) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, a speaker 50 25, etc. The display device is wall-mounted and integrated with the building, and has a large installation space It can be installed without the need for

[0136] Fig. 16(F) shows another example in which a display device is provided integrally with a building inside the building. . The display panel 5026 is attached integrally with the unit bath 5027, and the bather can view the display panel 5026.

[0137] In the present embodiment, a wall and a unit bath are exemplified as the building, but the present embodiment is not limited to this, and the display device can be installed in various buildings.

[0138] Next, an example in which the display device is provided integrally with a moving body will be shown.

[0139] Fig. 16(G) is a diagram showing an example in which a display device is provided in an automobile. The display panel 5 028 is attached to the vehicle body 5029 of the automobile, and the operation of the vehicle body or information input from inside and outside the vehicle body can be displayed on demand. Note that it may have a navigation function.

[0140] Fig. 16(H) is a diagram showing an example in which a display device is provided integrally with a passenger aircraft. Fig. 16(H) is a diagram showing the shape in use when a display panel 5031 is provided on the ceiling 5030 above the seat of a passenger aircraft. The display panel 5031 is integrally attached to the ceiling 503 0 via a hinge portion 5032, and the passenger can view the display panel 5031 by the expansion and contraction of the hinge portion 5032. The display panel 5031 has a function of displaying information by being operated by the passenger.

[0141] In the present embodiment, the moving body is exemplified by an automobile body and an aircraft body. ​​is not limited to this, and can be installed on various vehicles such as motorcycles, four-wheel vehicles (including automobiles, buses, etc.), trains (including monorails, railways, etc.), ships, etc. It can be installed on various vehicles such as motorcycles, four-wheel vehicles (including automobiles, buses, etc.), trains (including monorails, railways, etc.), ships, etc.

[0142] It is preferable to mount the shift register circuit of Embodiment 2 on the electronic device shown in this embodiment. In particular, it is preferable to mount the shift register circuit of Embodiment 2 as a circuit for driving the display unit of the electronic device. By mounting the shift register circuit of Embodiment 2 as a circuit for driving the display unit of the electronic device, the area of the driving circuit can be reduced, and the display unit can be enlarged. In addition, the resolution of the display unit can be improved.

Explanation of Signs

[0143] 11 Node 12 Node 21 Node 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 118 Wiring 121 Transistor 122 Transistor 123 Transistor 124 Transistor 125 Transistor 126 Capacitor 200 Circuit 201 Transistor 202 Transistor 203 Transistor 204 Transistor 301 Circuit 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 400 Substrate 402 Gate Insulating Layer 403 Protection Insulating Layer 410 Transistor 411 Gate Electrode Layer 415a Source Electrode Layer 415b Drain Electrode Layer 416 Oxide Insulating Layer 430 Oxide Semiconductor Film 431 Oxide Semiconductor Layer 5000 Housing 5001 Display Unit 5002 Second Display Unit 5003 Speaker 5004 LED Lamp 5005 Operation Key 5006 Connection Terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared Port 5011 Recording Medium Reading Unit 5012 Support Unit 5013 Earphone 5015 Shutter Button 5016 Image Receiving Unit 5017 Charger 5018 Support Stand 5019 External Connection Port 5020 Pointing Device 5021 Reader / Writer 5022 Housing 5023 Display Unit 5024 Remote Control Device 5025 Speaker 5026 Display Panel 5027 Unit Bus 5028 display panel 5029 vehicle body 5030 ceiling 5031 display panel 5032 hinge part 5360 timing controller 5361 circuit 5362 circuit 5362a circuit 5362b circuit 5363_1 circuit 5363_2 circuit 5364 pixel section 5367 pixel 5371 source signal line 5372 gate signal line 5380 substrate 5381 terminal

Claims

1. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a first signal line; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the first wiring; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the power supply line; a gate of the tenth transistor is always electrically connected to the first signal line; When the other of the source or the drain of the second transistor is in a conductive state with the gate signal line at least via a channel formation region of the second transistor, the potential of the other of the source or the drain of the second transistor is input to the gate signal line at least via a channel formation region of the second transistor.

2. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a first signal line; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the first wiring; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the power supply line; a gate of the tenth transistor is always electrically connected to the first signal line; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, a W (W is a channel width) / L (L is a channel length) ratio of the first transistor is greater than a W / L ratio of the second transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the fifth transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the sixth transistor; A semiconductor device in which the W / L ratio of the first transistor is greater than the W / L ratio of the seventh transistor.

3. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a first signal line; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the first wiring; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the power supply line; a gate of the tenth transistor is always electrically connected to the first signal line; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, the clock signal line has a region whose wiring width is smaller than the channel width of the first transistor, the clock signal line has a region whose wiring width is smaller than the channel width of the second transistor, the clock signal line has a region whose wiring width is smaller than the channel width of the sixth transistor, The clock signal line has a region with a wiring width greater than that of the first wiring.

4. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a first signal line; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the first wiring; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the power supply line; a gate of the tenth transistor is always electrically connected to the first signal line; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, a W (W is a channel width) / L (L is a channel length) ratio of the first transistor is greater than a W / L ratio of the second transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the fifth transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the sixth transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the seventh transistor; the clock signal line has a region whose wiring width is smaller than the channel width of the first transistor, the clock signal line has a region whose wiring width is smaller than the channel width of the second transistor, the clock signal line has a region whose wiring width is smaller than the channel width of the sixth transistor, The clock signal line has a region with a wiring width greater than that of the first wiring.

5. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a first signal line; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the first wiring; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the power supply line; a gate of the tenth transistor is always electrically connected to the first signal line; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, At least one of the first to tenth transistors includes an oxide semiconductor in a channel formation region.

6. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a first signal line; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the first wiring; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the power supply line; a gate of the tenth transistor is always electrically connected to the first signal line; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, at least one of the first to tenth transistors has an oxide semiconductor in a channel formation region; a W (W is a channel width) / L (L is a channel length) ratio of the first transistor is greater than a W / L ratio of the second transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the fifth transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the sixth transistor; A semiconductor device in which the W / L ratio of the first transistor is greater than the W / L ratio of the seventh transistor.

7. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a first signal line; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the first wiring; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the power supply line; a gate of the tenth transistor is always electrically connected to the first signal line; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, at least one of the first to tenth transistors has an oxide semiconductor in a channel formation region; the clock signal line has a region whose wiring width is smaller than the channel width of the first transistor, the clock signal line has a region whose wiring width is smaller than the channel width of the second transistor, the clock signal line has a region whose wiring width is smaller than the channel width of the sixth transistor, The clock signal line has a region with a wiring width greater than that of the first wiring.

8. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to an output signal line; the other of the source and the drain of the third transistor is always electrically connected to the clock signal line; a gate of the third transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a first signal line; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to a first wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the first wiring; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the power supply line; a gate of the tenth transistor is always electrically connected to the first signal line; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, at least one of the first to tenth transistors has an oxide semiconductor in a channel formation region; a W (W is a channel width) / L (L is a channel length) ratio of the first transistor is greater than a W / L ratio of the second transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the fifth transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the sixth transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the seventh transistor; the clock signal line has a region whose wiring width is smaller than the channel width of the first transistor, the clock signal line has a region whose wiring width is smaller than the channel width of the second transistor, the clock signal line has a region whose wiring width is smaller than the channel width of the sixth transistor, The clock signal line has a region with a wiring width greater than that of the first wiring.

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