Sample holder and superconducting quantum computer

Abstract

To more increase a resonance frequency of resonance occurring when a signal of a specific frequency is input to a chip when the chip is mounted on a sample holder.SOLUTION: A sample holder includes a pedestal and a printed circuit board (PCB) in contact with the pedestal. The PCB includes: a dielectric 8; a front surface ground (GND) 9 formed on a front surface of the dielectric 8; a back surface GND 11 formed on a back surface of the dielectric 8; a through hole 4 that penetrates from the front surface GND 9 to the back surface GND 11 and in which a chip is stored; and a conductor 14 that conducts the front surface GND 9 and the back surface GND 11 to an end surface of the through hole 4. A cavity is provided in at least part of a lower side of the through hole 4 in the pedestal, and a support structure is provided that supports a surface of the chip and being conducted to the pedestal in the cavity.SELECTED DRAWING: Figure 11E

Description

Technical Field

[0001] The present disclosure relates to a sample holder and the like.

Background Art

[0002] A superconducting quantum circuit is formed on a substrate such as a silicon substrate using a superconducting material such as Nb (niobium) or Al (aluminum). Here, an object obtained by forming a superconducting quantum circuit on a substrate is called a chip. The superconducting quantum circuit is mounted on a sample holder and operated. There are various structures for the sample holder. As a method of mounting the chip, there are a method of mounting the chip on a printed circuit board without turning over the circuit surface of the chip as described in Non-Patent Document 1, and a method of mounting the chip on a printed circuit board by turning over the circuit surface of the chip (flip chip mounting) as described in Patent Document 1. In the following description, the former mounting method will be described on the premise.

[0003] For example, there is a structure in which a printed circuit board (Printed Circuit Board, hereinafter PCB) is installed on a metal pedestal. A through hole is provided near the center of the PCB, the chip is placed in the through hole, and the pads of the chip and the PCB, and the ground of the chip and the ground of the PCB are electrically connected by bonding wires such as Al. In such a case, the back surface of the chip is in contact with the metal pedestal.

[0004] When a chip is mounted on the sample holder as described above, resonance occurs when a signal of a specific frequency is input to the chip. Here, this resonance is referred to as resonance in the chip mode. When the resonance in the chip mode couples with the superconducting quantum circuit on the chip, decoherence of the superconducting quantum circuit is caused. In order to reduce the influence of this decoherence, the resonance frequency in the chip mode should be made as high as possible. For example, Non-Patent Document 1 describes that in order to suppress the influence of the chip mode, in the above-described structure, a cavity is formed directly under the chip by cutting out a part of the metal pedestal directly under the chip.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Non-Patent Documents

[0006]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] When a chip is mounted on a sample holder, it is required to make the resonance frequency of the resonance that occurs when a signal of a specific frequency is input to the chip higher than the technique described in Non-Patent Document 1.

[0008] An example of the object of the present disclosure is to provide a sample holder or the like that makes the resonance frequency of the resonance that occurs when a signal of a specific frequency is input to a chip higher when the chip is mounted on the sample holder.

Means for Solving the Problems

[0009] A sample holder according to one aspect of the present disclosure includes a pedestal and a PCB in contact with the pedestal. The PCB includes a dielectric, a surface ground formed on the surface of the dielectric, a back surface ground formed on the back surface of the dielectric, a through hole penetrating from the surface ground to the back surface ground for storing a chip, and a conductor for connecting the surface ground and the back surface ground to the end face of the through hole. At least a part of the lower side of the through hole in the pedestal has a cavity, and the cavity has a support structure that is connected to the pedestal and supports the surface of the chip. In the support structure, at least a part of the portion that supports the chip is not parallel to the surface of the chip.

[0010] A superconducting quantum computer according to one aspect of the present disclosure includes a sample holder and a chip on which a superconducting quantum circuit is formed and stored in the sample holder. The sample holder includes a pedestal and a PCB in contact with the pedestal. The PCB includes a dielectric, a surface ground formed on the surface of the dielectric, a back surface ground formed on the back surface of the dielectric, a through hole penetrating from the surface ground to the back surface ground for storing the chip, and a conductor for connecting the surface ground and the back surface ground to the end face of the through hole. At least a part of the lower side of the through hole in the pedestal has a cavity, and the cavity has a support structure that is connected to the pedestal and supports the surface of the chip. In the support structure, at least a part of the portion that supports the chip is not parallel to the surface of the chip.

Advantages of the Invention

[0011] According to the present disclosure, when a chip is mounted on a sample holder, the resonance frequency of resonance that occurs when a signal of a specific frequency is input to the chip is increased.

Brief Description of the Drawings

[0012]

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Mode for Carrying Out the Invention

[0013] Hereinafter, with reference to the drawings, embodiments of a sample holder and a superconducting quantum computer according to the present disclosure will be described in detail. However, the drawings schematically represent the configurations in the embodiments of the present disclosure. Further, the embodiments of the present disclosure described below are examples, and can be appropriately changed within the range where their essence is the same. Also, in the description of the following drawings, the same or similar parts are denoted by the same or similar reference numerals. Also, in the following drawings, elements not used in the description are appropriately omitted from the illustration. Also, in the following description, the ground may be represented as GND. For example, the surface ground is represented as surface GND. For example, the back ground is represented as back GND.

[0014] To more clearly clarify the effects of the sample holders according to the embodiments, the results of modeling and simulating a sample holder with a cavity formed in the pedestal directly below the chip are compared with the results of modeling and simulating the sample holders according to the embodiments. Therefore, before the detailed description of each embodiment, first, the problem of the chip mode in the superconducting quantum circuit will be described in more detail. Then, the results of modeling and simulating the sample holder to be compared with the sample holders according to the embodiments will be described. Note that the sample holder to be compared is one in which a PCB is installed on a metal pedestal. Further, this sample holder is provided with a through hole near the center of the PCB. Further, in this sample holder, a part of the metal pedestal directly below the chip is hollowed out, and a cavity is formed directly below the chip.

[0015] Also, in each drawing, in order to clarify each direction, the x-axis, y-axis, and z-axis are used as a three-dimensional coordinate system for explanation.

[0016] FIG. 1A is an explanatory diagram showing an example of a sample holder for storing a chip on which a superconducting quantum circuit is formed. FIG. 1B is a side view of the sample holder 101 shown in FIG. 1A. As shown in FIG. 1A, the sample holder 101 has a configuration in which a PCB 103 is placed on a metal pedestal 102. In FIG. 1A, the shape of the pedestal 102 is a rectangular parallelepiped or a cube. A through hole 104 penetrating the PCB 103 is provided near the center of the PCB 103.

[0017] An example of the PCB 103 is shown in FIGS. 2A to 2E. FIG. 2A is a top view of the PCB 103. FIG. 2B is a bottom view of the PCB 103. FIG. 2C is a side view of the PCB 103. FIG. 2D is a perspective view of the PCB 103. FIG. 2E is an enlarged view of the vicinity of the through hole 104 of the PCB 103.

[0018] As shown in FIGS. 2A to 2E, the PCB 103 has a structure in which, for example, a surface GND 109 and a coplanar waveguide core wire 110 are formed on one surface of a plate-shaped dielectric 108 extending parallel to the xy plane, and a back surface GND 111 is formed on the other surface of the dielectric 108. The core wire 110, the surface GND 109, and the back surface GND 111 are conductors, for example, metals. Here, the coplanar waveguide is composed of a central conductor (hereinafter abbreviated as the central conductor), and two GND planes arranged on both side surfaces of the central conductor with a gap therebetween in the xy plane, and the central conductor and the two GND planes are arranged on substantially the same plane. The two GND planes of the coplanar waveguide shown in FIGS. 2A and 2E are formed by the surface GND 109. In the PCB 103 shown in FIGS. 2A to 2E, the core wire 110 corresponds to the central conductor. In the PCB 103 shown in FIGS. 2A to 2E, a coplanar waveguide is formed by forming the surface GND 109 with a gap in the xy plane on both side surfaces of the core wire 110. In the example shown in FIGS. 2A to 2E, eight coplanar waveguides are formed on the PCB 103. As shown in FIG. 2D, a plurality of through holes 112 are provided in the PCB 103. These through holes 112 penetrate the dielectric 108 and electrically connect the surface GND 109 and the back surface GND 111. For example, after forming a hole penetrating the dielectric 108, the through hole 112 is fabricated by plating the inside of the hole with metal. In FIGS. 1A and 1B, the back surface GND 111 of the PCB 103 is in contact with the pedestal 102. Therefore, the metal pedestal 102, the back surface GND 111 of the PCB 103, the through hole 112 of the PCB 103, and the surface GND 109 of the PCB 103 are electrically connected. Also, the through hole 104 provided near the center of the PCB 103 has, for example, the same shape as the chip of the superconducting quantum circuit mounted on the sample holder 101, that is, a rectangular or square shape. Also, in order for the chip to fit inside the through hole 104, the area of the through hole 104 is larger than the area of the chip.

[0019] Next, FIGS. 3A and 3B show the configuration when the chip 107 of the superconducting quantum circuit is mounted on the sample holder 101 shown in FIGS. 1A and 1B. FIG. 3A is a perspective view showing the configuration when the chip 107 of the superconducting quantum circuit is mounted on the sample holder 101 shown in FIGS. 1A and 1B. FIG. 3B is an end view of the configuration when the chip 107 of the superconducting quantum circuit is mounted on the sample holder 101 shown in FIGS. 1A and 1B, cut along a plane parallel to the xz plane including the cutting line A-AA shown in FIG. 3A. In FIGS. 3A and 3B, the PCB 103 shown in FIGS. 2A to 2E is used. As shown in FIGS. 3A and 3B, the chip 107 is placed inside the through hole 104 of the PCB 103 and placed on the pedestal 102. The pads of the chip 107 and the core wires 110 of the PCB 103 are electrically connected by bonding wires 113 such as Al (aluminum), and the GND plane of the chip 107 and the surface GND 109 of the PCB are electrically connected by bonding wires 113 such as Al. Here, the pads of the chip 107 are the terminals for signal input / output formed on the chip 107. In the example shown in FIGS. 3A and 3B, the back surface of the chip 107 (the lower surface of the chip 107 in FIG. 3B) is in contact with the metal pedestal 102.

[0020] When a signal of a specific frequency is input to the chip 107 when the chip 107 is mounted on the sample holder 101 shown in FIGS. 1A and 1B, resonance occurs. In order to identify the cause of this chip-mode resonance, a simulation is performed using electromagnetic field analysis software. Here, the simulation is performed using ANSYS (registered trademark) HFSS manufactured by ANSYS Japan Co., Ltd. The same tool will be used for the subsequent simulations.

[0021] The chip is shown in FIGS. 4A and 4B. FIG. 4A is a top view of the chip 107 used in the simulation. FIG. 4B is an enlarged view of the vicinity of the tip of the first coplanar waveguide 71. As shown in FIG. 4A, the chip 107 has a rectangular or square shape, and let the lengths of the sides of the chip 107 be v and w respectively. In the following description of the simulation, the shape of the chip 107 is a square, and the lengths of the sides of the chip 107 are v = w = 5 [mm] (millimeters). Also, on the chip 107 used in the simulation, a metal film with a thickness of 200 [nm] (nanometers) is laminated on a silicon substrate with a thickness of 380 [μm] (micrometers), and a circuit pattern is formed by removing a predetermined portion of the metal film. In the chip 107 shown in FIGS. 4A and 4B, a first coplanar waveguide 71 and a second coplanar waveguide 72 are formed. The first coplanar waveguide 71 and the second coplanar waveguide 72 have the same shape. The characteristic impedance of the first coplanar waveguide 71 and the second coplanar waveguide 72 is designed to be 50 [Ω] (ohms), and the length is 1 [mm]. FIG. 4B shows an enlarged view of the vicinity of the tip of the first coplanar waveguide 71. As shown in FIG. 4B, the tip of the first coplanar waveguide 71 is not in contact with the GND plane 73. As shown in FIG. 4A, the first coplanar waveguide 71 and the second coplanar waveguide 72 are not connected. Similarly, the tip of the second coplanar waveguide 72 is also not in contact with the GND plane 73. One end of the first core wire 74 is connected to the first pad 76, and one end of the second core wire 75 is connected to the second pad 77.

[0022] Examples of mounting the chip 107 shown in FIGS. 4A and 4B on the sample holder 101 shown in FIGS. 1A and 1B are shown in FIGS. 5A and 5B. FIG. 5A is a perspective view showing an example of mounting the chip 107 shown in FIGS. 4A and 4B on the sample holder 101 shown in FIGS. 1A and 1B. FIG. 5B is an enlarged view of the vicinity of the chip 107. As shown in FIGS. 5A and 5B, the first pad 76 of the chip 107 is electrically connected to the first core wire 110a of the PCB 103 by an Al bonding wire 113. Also, the second pad 77 of the chip 107 is electrically connected to the second core wire 110b of the PCB 103 by an Al bonding wire 113, and the GND plane 73 of the chip 107 is electrically connected to the surface GND 109 of the PCB 103 by an Al bonding wire 113. As shown in FIG. 5A, one end of the first core wire 110a of the PCB 103, which is different from the end connected to the first pad 76 of the chip 107, is defined as Port1. On the other hand, one end of the second core wire 110b of the PCB 103, which is different from the end connected to the second pad 77 of the chip 107, is defined as Port2. In the simulation, for example, when a high-frequency signal is input from Port1, the reflection to Port1 and the transmission to Port2 are calculated. Here, the reflection to Port1 is denoted as S11, and the transmission to Port2 is denoted as S21.

[0023] The simulation results when a high-frequency signal is input from Port1 shown in FIG. 5A are shown in FIGS. 6A and 6B. FIG. 6A is an explanatory diagram showing the reflection (S11) to Port1 when a high-frequency signal is input from Port1 shown in FIG. 5A. FIG. 6B is an explanatory diagram showing the transmission (S21) to Port2 when a high-frequency signal is input from Port1 shown in FIG. 5A. In FIGS. 6A and 6B, the horizontal axis represents the frequency (unit [GHz] (gigahertz)). S11 and S21 on the vertical axis are displayed in decibels ([dB]). That is, S11 and S21 on the vertical axis are displayed logarithmically. In the description of the subsequent simulation results as well, the horizontal axis represents the frequency (unit [GHz]), and S11 and S21 on the vertical axis are displayed in decibels ([dB]).

[0024] As shown in FIGS. 6A and 6B, when signals of some specific frequencies are input, S21 becomes very large and S11 becomes very small. As shown in FIGS. 4A and 4B, the first coplanar waveguide 71 and the second coplanar waveguide 72 of the chip 107 are not connected. Therefore, even if a signal is input to Port1, it is expected that the signal will not be transmitted to Port2. However, as shown by the simulation results in FIG. 6B, when signals of some specific frequencies are input from Port1, S21 becomes very large. For example, according to the simulation results in FIG. 6B, when a signal of 8.9 [GHz] is input from Port1, S21 is about -1.9 [dB]. That is, about 65% of the energy of the signal input from Port1 is transmitted to Port2. At such specific frequencies where S21 becomes very large, it can be seen from the simulation results shown in FIG. 6A that S11 becomes very small.

[0025] From the above, according to the simulation results shown in FIGS. 6A and 6B, the following can be understood. That is, in a system in which the chip 107 of a superconducting quantum circuit is mounted on the sample holder 101 as shown in FIGS. 5A and 5B, the space sandwiched between the GND plane 73 on the surface of the chip 107 and the metal pedestal 102, that is, the silicon substrate, forms a cavity resonator. And the first coplanar waveguide 71 and the second coplanar waveguide 72 of the chip 107 are coupled to this cavity resonator. Therefore, when a signal having a frequency equal to the resonance frequency of this cavity resonator is input to the chip from, for example, Port1, the resonance of the cavity resonator is excited. Then, a standing wave is formed in the silicon substrate and the energy of the electromagnetic field is accumulated. Since the second coplanar waveguide 72 of the chip 107 is also coupled to this cavity resonator, a part of the energy of the electromagnetic field accumulated in the silicon substrate is transmitted through the second coplanar waveguide 72 of the chip 107 to Port2.

[0026] Such a phenomenon can occur in the system shown in Figures 3A and 3B regardless of the type of circuit formed on chip 107. This phenomenon can occur not only when coplanar waveguides 71 and 72 as shown in Figures 4A and 4B are formed on chip 107, but also when any superconducting quantum circuit is formed on chip 107. In the mounting system shown in Figure 3, the space between GND plane 73 on the surface of chip 107 and metal base 102, i.e., the silicon substrate, forms a cavity resonator, and this resonance is referred to as chip mode resonance in this specification.

[0027] In the simulation results of FIG. 6A and FIG. 6B, some specific frequencies at which S21 becomes very large and S11 becomes very small are referred to as the resonant frequency of the chip mode hereinafter. When a signal having a frequency equal to or close to the resonant frequency of the chip mode is input to the chip 107, the chip mode resonates. According to the simulation results of FIG. 6A and FIG. 6B, in the system shown in FIG. 5A and FIG. 5B, the lowest resonant frequency of the chip mode is 8.9 [GHz]. In the system shown in FIG. 3A and FIG. 3B in which the chip 107 on which the superconducting quantum circuit is formed is mounted on the sample holder 101 shown in FIG. 1A and FIG. 1B, when the chip mode is coupled with the superconducting quantum circuit formed on the chip 107, it causes decoherence of the superconducting quantum circuit. It is known that in order to reduce the effect of this decoherence, it is necessary to make the resonant frequency of the chip mode as high as possible.

[0028] For this reason, there is a demand for technology to increase the resonance frequency of the tip mode. For example, in the comparative sample holder 101, the influence of the tip mode can be reduced by hollowing out a part of the part of the base 102 directly below the tip 107 to form a cavity directly below the tip 107.

[0029] An enlarged view of the vicinity of the through-hole 104 of the PCB 103 in the sample holder 101 with a cavity formed in the pedestal 102 is shown in FIGS. 7A to 7C. FIG. 7A is a perspective view of the sample holder 101 with a cavity formed in the pedestal. FIG. 7B is a top view of the sample holder 101 with a cavity formed in the pedestal. FIG. 7C is an end view of the sample holder 101 with a cavity formed in the pedestal, cut along a plane parallel to the xz plane including the cutting line B-BB shown in FIG. 7B. As shown in FIGS. 7A to 7C, a cavity 105 is formed in the pedestal 102 at a portion directly below the through-hole 104 of the PCB 103. In other words, as shown in FIGS. 7A to 7C, a cavity 105 is formed in the pedestal 102 at a portion directly below the chip 107 when the chip 107 is mounted on the sample holder 101. Further, in FIGS. 7A to 7C, the cavity 105 has a shape of a quadrangular prism having a bottom surface with the same area as the area of the chip 107. And the pedestal 102 has a structure in which columns 106 are left at the four corners of the cavity 105. The columns 106 are made of, for example, metal. Note that in FIG. 7C, the chip 107 is mounted on the sample holder 101 with bonding wires 113.

[0030] In FIGS. 7A, 7B, and 7C, in order to clearly show the columns 106, the columns 106 are represented by a pattern different from that of the pedestal 102. The metal columns 106 at the four corners are integrated with the pedestal 102 and constitute a part of the pedestal 102. The upper bottom surface of the two bottom surfaces of the metal columns 106 at the four corners shown in FIGS. 7A to 7C contacts the back surface of the chip 107. Also, in FIGS. 7A and 7B, the bottom surface of the metal column 106 is a right-angled isosceles triangle. As shown in FIG. 7C, with the length of the equal sides of the bottom surface of this column 106 being 1 [mm] (millimeter) and the height of the cavity 105 being 3 [mm], a simulation is performed for the case where the chips 107 of FIGS. 4A and 4B are mounted on the sample holder 101 of FIG. 7.

[0031] FIG. 8 is an explanatory diagram showing a simulation result of reflection (S11) at Port1 when a high-frequency signal is input to Port1 shown in FIG. 5A when the chip 107 shown in FIGS. 4A and 4B is mounted on the sample holder 101 shown in FIGS. 7A, 7B, and 7C with bonding wires 113. According to the simulation result of FIG. 8, when the chip 107 shown in FIGS. 4A and 4B is mounted on the sample holder 101 having the cavity 105 formed in the pedestal 102 in FIG. 7 with bonding wires 113, it can be seen that the lowest resonance frequency of the chip mode can be increased to 19.9 [GHz]. In the simulation results (FIGS. 6A and 6B) when the cavity 105 is not formed in the pedestal 102, the lowest resonance frequency of the chip mode is 8.9 [GHz]. From this, it can be seen that by using the sample holder 101 having the cavity 105 formed in the pedestal 102 in FIGS. 7A, 7B, and 7C, the resonance frequency of the chip mode can be significantly increased.

[0032] The reason why the resonance frequency of the chip mode can be increased by forming the cavity 105 in the pedestal 102 is that when the cavity 105 is formed directly below the chip 107, the inside of the cavity resonator formed by the space sandwiched between the GND plane 73 on the surface of the chip 107 and the pedestal 102 (in this case, the bottom of the cavity 105) is presumed to be silicon (thickness 380 [μm] in the simulation) and vacuum (thickness 3 [mm] in the simulation). As a result, it is presumed that this is because the effective dielectric constant inside the cavity resonator decreases compared to the case where the cavity 105 is not formed in the pedestal 102 (that is, when the inside of the cavity resonator is almost only silicon). Note that the relative dielectric constant of vacuum is 1, while the relative dielectric constant of silicon is very high at 11.9. Also, the resonance frequency of the cavity resonator generally has the property that it becomes higher as the dielectric constant of the medium filling the inside of the cavity resonator is lower.

[0033] Thus, by using the sample holder 101 with the cavity 105 formed in the pedestal 102, the resonance frequency of the chip mode can be increased. However, in order to reduce the influence on the superconducting quantum circuit in the chip mode, it is required to increase the resonance frequency of the chip mode as much as possible. In addition, as the number of qubits integrated on the chip 107 increases towards the practical application of quantum computers, it is predicted that a chip 107 with an area larger than 5 [mm] × 5 [mm] will be required. The larger the area of the chip 107, the lower the resonance frequency of the chip mode. This is because the larger the area of the chip 107, the larger the dimensions of the bottom surface of the cavity resonator formed by the space sandwiched between the GND plane 73 on the surface of the chip 107 and the pedestal 102. Therefore, even when using the sample holder 101 with the cavity 105 formed in the pedestal 102 as shown in FIGS. 7A to 7C, it is predicted that the larger the area of the chip 107, the lower the resonance frequency of the chip mode and the greater the influence on the quantum circuit. From the above, it is required to develop a technology that can make the resonance frequency of the chip mode even higher than when using the sample holder 101 with the cavity 105 formed in the pedestal 102 as much as possible.

[0034] Therefore, each embodiment capable of making the resonance frequency of the chip mode higher will be described.

[0035] (First Embodiment) In the first embodiment, an example will be described in which the PCB in contact with the pedestal has a dielectric, a surface GND formed on the surface of the dielectric, a back GND formed on the back surface of the dielectric, a through hole penetrating from the surface GND to the back GND in which the chip is stored, and a conductor for conducting the surface GND and the back GND on the end surface of the through hole. And in the first embodiment, an example will be described in which there is a cavity in at least a part of the lower side of the through hole in the pedestal, and there is a support structure that conducts to the pedestal and supports the surface of the chip in the cavity.

[0036] FIG. 9 is an explanatory diagram showing a sample holder according to the first embodiment. As shown in FIG. 9, the sample holder 1 of the first embodiment has a configuration in which a PCB 3 is placed on a metal pedestal 2. A through hole 4 penetrating the PCB 3 is provided near the center of the PCB 3. The shape of the pedestal 2 is not particularly limited. For example, the shape of the pedestal 2 may be a rectangular parallelepiped or a cube. The sample holder 1 has a cavity 5 in a portion of the pedestal 2 that corresponds directly below the through hole 4 of the PCB 3.

[0037] By making the height of the circuit surface of the chip and the height of the surface of the PCB 3 as close as possible, it is possible to facilitate wire bonding and shorten the bonding wire. Note that the shorter the bonding wire, the better the electrical characteristics. Also, by forming the through hole 4 in the PCB 3, the resonance frequency of the chip mode can be increased. If a dielectric or conductor exists on the back surface of the chip (the surface opposite to the circuit surface), the resonance frequency of the chip mode will decrease. Therefore, in order to increase the resonance frequency of the chip mode, the back surface of the chip should be in contact with a vacuum as much as possible. If the chip is placed on the PCB 3 without forming the through hole 4 in the PCB 3, the dielectric or conductor of the PCB 3 will contact the back surface of the chip, so the resonance frequency of the chip mode cannot be increased. Therefore, in the first embodiment, the through hole 4 is formed in the PCB 3, the chip is placed in the through hole 4, and further, the cavity 5 is formed in the pedestal 2 directly below the chip, so that as large an area as possible of the back surface of the chip is in contact with a vacuum.

[0038] An enlarged view of the vicinity of the through hole 4 of the PCB 3 of the sample holder 1 of the first embodiment is shown in FIGS. 10A to 10C. FIG. 10A is a perspective view showing the sample holder 1 of the first embodiment. FIG. 10B is a top view of the sample holder 1 of the first embodiment. FIG. 10C is an end view of the sample holder 1 of the first embodiment cut along a plane parallel to the xz plane including the cutting line C-CC shown in FIG. 10B. Note that in FIG. 10C, the chip 7 is mounted on the sample holder 1 of the first embodiment with bonding wires 13.

[0039] The sample holder 1 has a cavity 5 in at least a part of the lower side of the pedestal 2 below the through hole 4. In FIGS. 10A to 10C, the sample holder 1 has a cavity 5 in a part of the pedestal 2 that corresponds to directly below the through hole 4 of the PCB 3. In other words, in FIGS. 10A to 10C, the sample holder 1 has a cavity 5 in a part of the pedestal 2 that corresponds to directly below the chip 7 when the chip 7 is mounted on the sample holder 1 with the bonding wire 13. The shape of the cavity 5 is not particularly limited. For example, the bottom surface of the cavity 5 may be a flat surface or a non-flat surface. The side surface of the cavity 5 may be a flat surface or a non-flat surface. For example, there may be depressions or the like on the side surface or the bottom surface of the cavity 5. In FIGS. 10A to 10C, the cavity 5 is in the shape of a quadrangular prism. More specifically, in FIGS. 10A to 10C, the cavity 5 has a bottom surface in the shape of a quadrilateral with side lengths a and b, and is in the shape of a quadrangular prism with a height of d. Further, the cavity 5 has a support structure that supports the surface of the chip 7 and is electrically connected to the pedestal. The material of the support structure is, for example, made of metal. Specifically, the material of the support structure may be, for example, a mixture containing metal such as a resin mixed with metal particles or fillers.

[0040] Also, the shape of the support structure is not particularly limited. For example, in FIGS. 10A to 10C, the support structure may be the pillar 6. Although not shown, the support structure may be, for example, a protrusion extending from the side surface of the cavity 5. Or, although not shown, the support structure may be, for example, a non-linear three-point support. Or, although not shown, the support structure may be a structure that extends like a pincushion from the bottom surface of the cavity 5.

[0041] Here, as an example of the support structure, the pillar 6 shown in FIGS. 10A to 10C will be described. The number and shape of the pillar 6 are not particularly limited. The same applies to the following embodiments. In FIGS. 10A to 10C, a plurality of pillars 6 are provided in the cavity 5. More specifically, pillars 6 that are conductors are arranged at the four corners of the cavity 5.

[0042] In FIGS. 10A to 10C, in order to clearly show the pillar 6, the pillar 6 is shown in a pattern different from that of the pedestal 2. The cavity 5 in FIGS. 10A to 10C has the same structure as the cavity 105 shown in FIGS. 7A to 7C. That is, the bottom surface of the pillar 6 at the four corners is in the shape of a right-angled isosceles triangle. The length of the two equal sides (equilateral sides) of the bottom surface of this pillar 6 is s. The height of the pillar 6 is d. The conductive pillars 6 at the four corners are in electrical contact with the pedestal 2. The four conductive pillars 6 shown in FIGS. 10A to 10C may be separate from the pedestal 2. Or the pillar 6 shown in FIGS. 10A to 10C may be made of the same material as the pedestal 2. That is, the pedestal 2 and the pillar 6 may be integrated. When the chip 7 is mounted on the sample holder 1 with the bonding wire 13, the upper bottom surface of the pillar 6 at the four corners contacts the back surface of the chip 7.

[0043] Here, the effects of using the pillar 6 will be described. When there is no pillar 6, there is a concern that the chip 7 may fall into the cavity 5. The chip 7 and the PCB 3 are connected by bonding wires. Therefore, even without the pillar 6, there is a possibility that the chip 7 will not fall into the cavity 5, but there is a risk that the chip 7 may fall into the cavity 5 due to vibration or the like, or some of the bonding wires may come off, causing the chip 7 to fall into the cavity 5. Therefore, by providing the metal pillar 6, it is possible to prevent the chip 7 from falling into the cavity 5 and prevent the bonding wires from coming off. In addition, the metal pillar 6 can strengthen the heat path between the chip 7 and the pedestal 2. The chip 7 of the superconducting quantum circuit is cooled to about 10 [mK] (millikelvin) by a refrigerator and operated. Generally, the pedestal 2 is in thermal contact with the cold stage (the coldest part) of the refrigerator. That is, the pedestal 2 reaches a very low temperature. And the stronger the heat path between the pedestal 2 and the chip 7, in other words, the smaller the thermal resistance between the pedestal 2 and the chip 7, the better the chip 7 cools. If the chip 7 does not cool well, the good performance of the quantum circuit formed on the chip 7 cannot be obtained, so it is desirable to cool the chip 7 to the lowest possible temperature. Therefore, it is preferable that the thermal resistance between the pedestal 2 and the chip 7 is as small as possible. And the metal pillar 6 can reduce the thermal resistance between the pedestal 2 and the chip 7.

[0044] For example, a structure in which no cavity 5 is formed in the pedestal 2 can be considered to most strongly reinforce the heat path between the chip 7 and the pedestal 2. However, when the cavity 5 is not formed in the pedestal 2, there is a chip mode problem. Therefore, when the cavity 5 is formed in the pedestal 2 to solve the chip mode problem, a part of the upper surface of the pillar 6 is made parallel to the back surface of the chip 7. That is, at least a part of the portion that supports the chip 7 in the support structure is parallel to the back surface of the chip 7. Thereby, the thermal resistance can be reduced.

[0045] FIG. 11A is a top view of the PCB 3 used in the sample holder 1 of the first embodiment. FIG. 11B is a bottom view of the PCB 3 used in the sample holder 1 of the first embodiment. FIG. 11C is a side view of the PCB 3 used in the sample holder 1 of the first embodiment. FIG. 11D is a perspective view of the PCB 3 used in the sample holder 1 of the first embodiment. FIG. 11E is an enlarged view of the vicinity of the through hole 4 of the PCB 3 used in the sample holder 1 of the first embodiment.

[0046] As shown in FIGS. 11A and 11E, the PCB 3 has, for example, a plate-shaped dielectric 8 extending parallel to the xy plane. The PCB 3 has a structure in which a surface GND 9 and a coplanar waveguide core wire 10 are formed on one surface (front surface) of the dielectric 8. The PCB 3 has a structure in which a back surface GND 11 is formed on the other surface (back surface) of the dielectric 8. The core wire 10, the surface GND 9, and the back surface GND 11 are conductors, for example, metals. Examples of the metal include Cu (copper) and Cu plated with Au plating (gold plating). In FIG. 11A, eight coplanar waveguides are formed on the PCB 3. The coplanar waveguide is as described with reference to FIG. 2A. However, the number of coplanar waveguides formed on the PCB 3 is not particularly limited and may be any number. As shown in FIG. 11D, a plurality of through holes 12 are provided in the PCB 3. These through holes 12 penetrate the dielectric 8 and electrically connect the surface GND 9 and the back surface GND 11. The through hole 12 is manufactured, for example, by forming a hole penetrating the dielectric 8, the surface GND 9, and the back surface GND 11 and then plating the inside of the hole with a metal.

[0047] In FIG. 9, the back surface GND11 of the PCB3 is in contact with the pedestal 2. Therefore, the metal pedestal 2, the back surface GND11 of the PCB3, the through hole 12 of the PCB3, and the front surface GND9 of the PCB3 are electrically connected. In addition, a through hole 4 is provided near the center of the PCB3. This through hole 4 may have the same shape as, for example, the chip 7 of the superconducting quantum circuit mounted on the sample holder 1, that is, a rectangular or square shape. Further, in order for the chip 7 to enter the inside of the through hole 4, the area of the through hole 4 is larger than the area of the chip 7.

[0048] In addition, the PCB3 used for the sample holder 1 of the first embodiment has a conductor that conducts the front surface GND9 and the back surface GND11 on the end face of the through hole 4. In FIG. 11E, this conductor is the conductor 14. More specifically, the feature of the PCB3 used for the sample holder 1 of the first embodiment is that, as shown in FIG. 11E, in the through hole 4 of the PCB3, by forming the conductor 14 on the end face of the through hole 4, the front surface GND9 and the back surface GND11 of the PCB3 are electrically connected. That is, the conductor 14 is not formed on the end face of the PCB3 near the core wire 10 of the PCB3. Therefore, the conductor 14 is provided on a portion of the end face of the through hole 4 other than the end face of the PCB3 near the core wire 10. This prevents the core wire 10 of the PCB3 from being electrically contacted with each GND of the PCB3. The conductor 14 formed on the end face of the through hole 4 is, for example, a metal. More specifically, the conductor 14 is Cu, Cu plated with Au, or the like. Further, as the conductor 14, a material that becomes a superconductor in an extremely low temperature environment of about 10 [mK] (millikelvin) for operating the superconducting quantum circuit, for example, Pb (lead), may be used.

[0049] Fig. 12 shows the simulation result of S11 for the system in which chip 7 is mounted on sample holder 1 of the first embodiment shown in Fig. 9 with bonding wire 13. Here, S11 is the reflection to Port1 when a high-frequency signal is input from Port1 as shown in Fig. 11A, similar to the above description. Fig. 12 is an explanatory diagram showing the simulation result of S11 when chip 7 is mounted on sample holder 1 of the first embodiment with bonding wire 13. In the simulation in Fig. 12, a = 5 [mm], b = 5 [mm], d = 3 [mm], and s = 1 [mm].

[0050] As shown in Fig. 12, the lowest resonance frequency of the chip mode is 36.6 [GHz]. Therefore, as shown in Fig. 12, the lowest resonance frequency of the chip mode can be made higher than the simulation result shown in Fig. 8 obtained by simulating using sample holder 101 shown in Figs. 7A to 7C. It is considered that the resonance frequency of the chip mode could be made higher by using sample holder 1 of the first embodiment for the following reasons. In the example of sample holder 101 shown in Figs. 7A to 7C, the electric field of the standing wave generated when resonance of the chip mode occurs does not stay within the silicon substrate of chip 107, but spreads into the dielectric 108 through the end face of the via hole 104 of PCB 103. On the other hand, in the case of sample holder 1 of the first embodiment, by forming conductor 14 on the end face of via hole 4 of PCB 3 and electrically connecting the front surface GND9 and the back surface GND11 of PCB 3, it is possible to suppress the spread of the electric field of the standing wave generated when resonance of the chip mode occurs into the dielectric 8 of PCB 3. For this reason, according to the first embodiment, it is considered that the size of the cavity resonator can be substantially reduced.

[0051] In the first embodiment, for example, the chip 7 mounted on the sample holder 1 has a rectangular shape. Let the length of the short side of the chip 7 be v, and the length of the long side of the chip 7 be w. In such a case, in the cavity 5 shown in FIGS. 10A to 10C, it is preferably the case that a < b, and preferably a is greater than or equal to v, and b is greater than or equal to w. If not, the contact area between the back surface of the chip 7 and the pedestal 2 increases, and the resonance frequency of the chip mode decreases.

[0052] Also, in this case, the shape of the through-hole 4 of the PCB 3 of the first embodiment is not particularly limited, but it is more preferably rectangular. As shown in FIGS. 11A and 11B, when the length of the short side of the through-hole 4 of the PCB 3 is x1 and the length of the long side of the through-hole 4 is y1, the chip 7 must enter inside the through-hole 4. For this reason, it is necessary that v < x1 and w < y1. Furthermore, the shorter x1 and y1 are, the smaller the substantial dimensions of the cavity resonator can be made, and thus the resonance frequency of the chip mode can be increased. Thus, x1 is preferably 1.2v or less, and more preferably 1.1v or less. For the same reason, b is preferably 1.2w or less, and more preferably 1.1w or less.

[0053] On the other hand, when the chip 7 has a square shape and the length of one side of the chip 7 is v, in the cavity 5 shown in FIGS. 10A to 10C, it is preferably the case that a = b, and preferably a is greater than or equal to v. Also, in this case, the through-hole 4 of the PCB 3 according to the first embodiment is preferably square. When the length of one side of the through-hole 4 of the PCB 3 is x1, since the chip 7 must enter inside the through-hole 4, it is necessary that v < x1. Furthermore, since the resonance frequency of the chip mode can be increased as x1 is shorter, x1 is preferably 1.2v or less, and more preferably 1.1v or less.

[0054] Also, according to the simulation, as the height d of the cavity 5 increases, the resonance frequency of the chip mode increases. However, when d is increased to a certain extent, further increasing d hardly changes the resonance frequency of the chip mode. Therefore, in the first embodiment, when the thickness of the chip 7 mounted on the sample holder 1 is t, the height d of the cavity 5 shown in FIGS. 10A to 10C is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0055] Also, in the first embodiment, the smaller the bottom area of the four corner posts 6 shown in FIGS. 10A to 10C, the smaller the contact area between the back surface of the chip 7 and the pedestal 2, so that the resonance frequency of the chip mode can be increased. Therefore, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, s is preferably 0.5v or less. Further, s is preferably 0.3v or less, and more preferably 0.2v or less. On the other hand, when the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, s is preferably 0.5v or less. Further, s is preferably 0.3v or less, and more preferably 0.2v or less.

[0056] [Modification Example of the First Embodiment] In the first embodiment, an example in which the PCB 3 has two metal layers has been described. The metal layer of the PCB 3 is not limited to two layers and may be three or more layers. In the modification example of the first embodiment, the case where the metal layer of the PCB 3 has three or more layers will be described.

[0057] FIG. 13A is a top view showing the structure of the PCB 3 according to a modified example of the first embodiment. FIG. 13B is a cross-sectional view taken along a plane parallel to the xy plane so that the core wires formed in the region sandwiched between the surface GND 9 and the back surface GND 11 of the PCB 3 according to the modified example of the first embodiment can be seen. Note that the cross-sectional view shown in FIG. 13B is a cross-sectional view taken in the vicinity of a plane (a plane parallel to the xy plane including the cutting line P-PP shown in FIG. 13C) where the PCB 3 is cut. FIG. 13C is an enlarged view of the vicinity of the core wire 10 of a cross-section obtained by cutting the PCB 3 according to the modified example of the first embodiment along a plane parallel to the xz plane including the cutting line D-DD shown in FIG. 13A. FIG. 13D is a bottom view showing the structure of the PCB 3 according to the modified example of the first embodiment. FIG. 13E is a perspective view of the PCB 3 according to the modified example of the first embodiment. FIG. 13F is an enlarged view of the vicinity of the through hole 4 of the PCB 3 according to the modified example of the first embodiment. The sample holder 1 of the modified example of the first embodiment has a configuration in which the PCB 3 is placed on the metal pedestal 2 as shown in FIG. 9. The pedestal 2 forms a cavity 5 having the same shape as that shown in FIGS. 10A to 10C. As described above, in the sample holder 1 of the first embodiment, the PCB 3 shown in FIGS. 11A to 11E is used. The PCB 3 shown in FIGS. 11A to 11E has two metal layers. Specifically, the PCB 3 shown in FIGS. 11A to 11E has a total of two metal layers, namely, a metal layer on which the surface GND 9 and the core wire 10 are formed and a metal layer on which the back surface GND 11 is formed. On the other hand, in the modified example of the first embodiment, a PCB 3 having three or more metal layers is used.

[0058] As shown in FIG. 13C, the PCB 3 has a structure in which, for example, the surface GND 9 is formed on one surface of the plate-shaped dielectric 8 extending parallel to the xy plane. Further, the PCB 3 has a structure in which the back surface GND 11 is formed on the other surface of the dielectric 8. Furthermore, the PCB 3 has a structure in which the core wire 10 is formed inside the dielectric 8, that is, in the region sandwiched between the surface GND 9 and the back surface GND 11. A circuit having such a structure is generally called a stripline.

[0059] As shown in FIG. 13A, on the upper surface of the PCB 3, a surface GND 9, input / output pads 15, and bonding pads 16 are formed. The input / output pads 15 are pads for connecting the core wires 10 of the PCB 3 to an external measuring instrument or the like and are used for signal input and output. The bonding pads 16 are pads for connecting the core wires 10 of the PCB 3 and the pads of the chip 7 with bonding wires 13 or the like. The input / output pads 15 and bonding pads 16 formed on the upper surface of the PCB 3 are electrically connected to the core wires 10 formed in the region sandwiched between the surface GND 9 and the back surface GND 11. In the top view of FIG. 13A, the core wires 10 are not visible because they are hidden by the surface GND 9. On the other hand, FIG. 13B shows a cross-sectional view taken along a plane parallel to the xy plane near the core wires 10. From FIG. 13A to FIG. 13F, four strip lines are formed on the PCB 3. However, the number of strip lines formed on the PCB 3 is not particularly limited and may be any number. As shown in FIGS. 13B, 13C, and 13E, a plurality of through holes 12 are provided in the PCB 3. These through holes 12 penetrate the dielectric 8 and electrically connect the surface GND 9 and the back surface GND 11. In addition, a through hole 4 is provided near the center of the PCB 3. As shown in FIG. 13F, at the end face of the through hole 4 in the through hole 4 of the PCB 3, a conductor 14 is formed to electrically connect the surface GND 9 and the back surface GND 11 of the PCB 3.

[0060] Even for a PCB 3 having three or more metal layers, as shown in FIG. 13F, by forming a conductor 14 on the end face of the through hole 4, the sample holder 1 on which the PCB 3 is placed on the same pedestal 2 as in FIGS. 10A to 10C has the same effect as in the first embodiment.

[0061] In the first embodiment and its modification, the shape of the column 6 is a triangular prism with a right-angled isosceles triangle as the bottom surface. However, the shape of the column 6 does not have to be a triangular prism. The shape of the column 6 may be, for example, a column with a polygonal bottom surface such as a quadrangular prism, or the bottom surface of the column does not have to be a polygon. Regardless of the shape of the column, the effects described in the first embodiment and its modification are achieved.

[0062] (Second Embodiment) The second embodiment will be described in detail with reference to the drawings. Hereinafter, the description of the content overlapping with the above description will be omitted as long as the description of the second embodiment is not made unclear.

[0063] The sample holder 1 of the second embodiment has a configuration in which the PCB 3 is placed on the pedestal 2 as shown in FIG. 9 described in the first embodiment. The pedestal 2 is formed with a cavity 5 having the same shape as the cavity 5 shown in FIGS. 10A to 10C.

[0064] FIG. 14 is an enlarged view of the vicinity of the through hole 4 of the PCB 3 used in the sample holder 1 of the second embodiment. The difference between the PCB 3 used in the first embodiment and the PCB 3 used in the second embodiment is as follows. In the PCB 3 described in the first embodiment, as shown in FIG. 11E, the conductor 14 is formed on the end face of the through hole 4 of the PCB 3, but the conductor 14 is not formed on the end face of the PCB 3 near the core wire 10 of the PCB 3. This prevents the core wire 10 of the PCB 3 from being electrically contacted with the GND of the PCB 3. On the other hand, in the PCB 3 of FIG. 14 used in the second embodiment, the core wire 10 of the PCB 3 is made slightly shorter than that in the first embodiment so that the core wire 10 of the PCB 3 does not contact the end face of the through hole 4. That is, the core wire 10 of the PCB 3 is formed on the surface of the dielectric with a length that does not contact the end face of the through hole 4. And the PCB 3 forms the conductor 14 on the entire end face of the through hole 4 of the PCB 3. This electrically connects the surface GND 9 and the back surface GND 11 of the PCB 3. By adopting such a structure, it is possible to form the conductor 14 on the entire end face of the through hole 4 of the PCB 3 while preventing the core wire 10 of the PCB 3 from being electrically contacted with the GND of the PCB 3.

[0065] Here, the effects of the second embodiment will be described. In the first embodiment, there is an effect of suppressing the spread of the electric field of the standing wave generated when the resonance in the chip mode occurs into the interior of the dielectric 8 of the PCB 3. However, since the conductor 14 was not formed on the end face of the PCB 3 near the core wire 10 of the PCB 3, a part of the electric field leaks into the interior of the dielectric 8 of the PCB 3 through the portion where the conductor 14 is not formed on the end face of the PCB 3, that is, the portion where the dielectric 8 on the end face of the through hole 4 of the PCB 3 is exposed. On the other hand, in the second embodiment, since the conductor 14 is formed on the entire end face of the through hole 4 of the PCB 3, the spread of the electric field of the standing wave generated when the resonance in the chip mode occurs into the interior of the dielectric 8 of the PCB 3 can be further suppressed compared to the first embodiment, and the resonance frequency in the chip mode can be made even higher.

[0066] FIG. 15 is an explanatory diagram showing the simulation result of S11 when the chip 7 is mounted on the sample holder 1 of the second embodiment with the bonding wire 13. As shown in FIG. 15, the lowest resonance frequency in the chip mode can be increased to 36.8 [GHz], which is higher than that of the first embodiment. Thus, the sample holder 1 of the second embodiment has the effect that the resonance frequency in the chip mode can be made higher than that of the sample holder 1 of the first embodiment.

[0067] [Modification of the Second Embodiment] The sample holder 1 of the modification of the second embodiment has a configuration in which the PCB 3 is placed on the metal pedestal 2 as shown in FIG. 9. The pedestal 2 is formed with a cavity 5 having the same shape as the example shown in FIGS. 10A to 10C. And in the modification of the second embodiment, a PCB 3 having three or more metal layers is used. As an example of the PCB 3 having three or more metal layers, a configuration example of the PCB 3 having three metal layers is shown in FIG. 16.

[0068] FIG. 16 is an enlarged view of the vicinity of the through-hole 4 of the PCB 3 used in the sample holder 1 of the modification of the second embodiment. The difference between the PCB 3 (FIG. 13) described in the modification of the first embodiment and the PCB 3 of FIG. 16 described in the modification of the second embodiment is as follows. In the PCB 3 described in the modification of the first embodiment, as shown in FIG. 13F, a conductor 14 is formed on the end face of the through-hole 4 of the PCB 3, but no conductor 14 is formed on the end face of the PCB 3 near the bonding pad 16 of the PCB 3. This prevents the bonding pad 16 and the GND of the PCB 3 from being electrically contacted. On the other hand, in the PCB 3 of FIG. 16 used in the modification of the second embodiment, by separating the tip of the bonding pad 16 slightly from the through-hole, the bonding pad 16 is prevented from contacting the end face of the through-hole 4, and a conductor 14 is formed on the entire end face of the through-hole 4 of the PCB 3 to electrically connect the surface GND 9 and the back GND 11 of the PCB 3. By adopting such a structure, it is possible to prevent the bonding pad 16 and the GND of the PCB 3 from being electrically contacted while forming the conductor 14 on the entire end face of the through-hole 4 of the PCB 3.

[0069] In the modification of the first embodiment, there is an effect of suppressing the spread of the electric field of the standing wave generated when the resonance in the chip mode occurs into the inside of the dielectric 8 of the PCB 3. However, since no conductor 14 is formed on the end face of the PCB 3 near the bonding pad 16 of the PCB 3, it is conceivable that a part of the electric field leaks into the inside of the dielectric 8 of the PCB 3 through the portion where the conductor 14 is not formed on the end face of the PCB 3, that is, the portion where the dielectric 8 of the end face of the through-hole 4 of the PCB 3 is exposed. On the other hand, in the modification of the second embodiment, since the conductor 14 is formed on the entire end face of the through-hole 4 of the PCB 3, it is expected that the spread of the electric field of the standing wave generated when the resonance in the chip mode occurs into the inside of the dielectric 8 of the PCB 3 can be further suppressed compared to the modification of the first embodiment, and the resonance frequency in the chip mode can be further increased.

[0070] As described above, even for the PCB3 having three or more metal layers, by forming the conductor 14 on the entire end face of the through hole 4 as shown in FIG. 16, the sample holder 1 with such a PCB3 placed on the pedestal 2 similar to FIGS. 10A to 10C exhibits the same effects as the second embodiment.

[0071] In the second embodiment and its modified examples, as described in the first embodiment, the shape of the column 6 is a triangular prism with a right-angled isosceles triangle as the bottom surface. However, the shape of the column 6 does not have to be a triangular prism. The shape of the column 6 may be, for example, a prism such as a quadrangular prism where the bottom surface of the column is a polygon, or the bottom surface of the column 6 does not have to be a polygon. Regardless of the shape of the column 6, the effects described in the second embodiment and its modified examples are achieved.

[0072] (Third Embodiment) The third embodiment will be described in detail with reference to the drawings. Hereinafter, the description of the content overlapping with the above description will be omitted as long as the description of the third embodiment is not made unclear. In the third embodiment, similar to the first embodiment, the sample holder 1 includes the pedestal 2 and the PCB3 in contact with the pedestal 2. And in the third embodiment, similar to the first embodiment 1, 2, the PCB3 has the through hole 4, and at least a part of the lower side of the through hole 4 in the pedestal 2 has the cavity 5, and there is a support structure in the cavity 5 that supports the surface of the chip 7 and is electrically connected to the pedestal 2. Here, in the third embodiment, at least a part of the portion that supports the chip 7 in the support structure is characterized by not being parallel to the back surface of the chip 7.

[0073] FIG. 17A is a perspective view of the sample holder 1 according to the third embodiment. FIG. 17B is a top view of the sample holder 1 according to the third embodiment. FIG. 17C is an end view of the sample holder 1 according to the third embodiment cut along a plane parallel to the xz plane including the cutting line E-EE shown in FIG. 17B. Also, in FIG. 17C, the chip 7 is mounted on the sample holder 1.

[0074] The sample holder 1 according to the third embodiment includes a pedestal 2 and a PCB 3. That is, the sample holder 1 of the third embodiment has a configuration in which the PCB 3 is placed on the metal pedestal 2 as shown in FIG. 9. In the third embodiment, the PCB 3 having the structure shown in FIG. 11, which is the same as that of the first and second embodiments, is used. And in the third embodiment, a cavity 5 having a structure as shown in FIGS. 17A to 17C is formed in the pedestal 2. The PCB 3 has through holes 4. There is a cavity 5 in at least a part of the lower side of the through hole 4 in the pedestal 2. Similar to the first and second embodiments, the shape of the cavity 5 is not particularly limited. For example, the bottom surface of the cavity 5 may be a flat surface or a non-flat surface. The side surface of the cavity 5 may be a flat surface or a non-flat surface. For example, there may be depressions or the like on the side surface or the bottom surface of the cavity 5. In FIGS. 17A to 17C, the sample holder 1 has a cavity 5 in a portion of the pedestal 2 that corresponds directly below the through hole 4 of the PCB 3. In other words, in FIGS. 17A to 17C, the sample holder 1 has a cavity 5 in a portion of the pedestal 2 that corresponds directly below the chip 7 when the chip 7 is mounted on the sample holder 1 with the bonding wire 13. In FIGS. 17A to 17C, the cavity 5 has a shape of a quadrangular prism with a height of d and having a bottom surface that is a quadrilateral with side lengths a and b.

[0075] The cavity 5 has a support structure that conducts to the pedestal 2 and supports the surface of the chip 7. Here, the surface of the chip 7 is the back surface of the chip 7 opposite to the circuit surface of the chip 7. As described above, as a feature of the third embodiment, at least a part of the portion that supports the chip 7 in the support structure is not parallel to the back surface of the chip 7. In the third embodiment, similar to the first embodiment, the support structure is not particularly limited. Here, the support structure will be described by taking the pillar 6 as an example. An example in which the pillars 6 are arranged at the four corners of the cavity 5 will be used for the description. The lower bottom surface of the pillars 6 at the four corners has a right-angled isosceles triangle shape, the length of the equal two sides of this bottom surface is s, and the height of the pillar 6 is d. The conductive pillars 6 at the four corners are in electrical contact with the pedestal 2. The four conductive pillars 6 shown in FIGS. 17A to 17C may be separate from the pedestal 2. Alternatively, the pillar 6 may be made of the same material as the pedestal 2, that is, the pedestal 2 and the four pillars 6 may be integrated.

[0076] As described above, the difference from the structure of the cavity 5 in the first embodiment shown in FIGS. 10A to 10C is that in the third embodiment, at least a part of the upper surface of the pillars 6 at the four corners, that is, the surface facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1, is not parallel to the back surface of the chip 7. In other words, at least a part of the upper surface of the pillars 6 at the four corners is not parallel to the upper surface of the pedestal 2. As shown in FIG. 17C, the pillar 6 used for the sample holder 1 in the third embodiment has a structure connecting the upper part 61 and the lower part 62. The shapes of the upper part 61 and the lower part 62 are not particularly limited. The lower part 62 has a triangular prism shape, the bottom surface of the lower part 62 has a right-angled isosceles triangle shape, the length of the equal two sides of this bottom surface is s, and the height of the lower part 62 is d1. The upper part 61 has a triangular pyramid shape, the bottom surface of the upper part 61 has a right-angled isosceles triangle shape, and the height of the upper part 61 is d2. Here, d1 + d2 = d. Also, for example, the bottom surface of the upper part 61 and the bottom surface of the lower part 62 have the same shape and dimensions. In this structure, when the chip 7 is mounted on the sample holder 1, at least a part of each of the pillars 6 at the four corners contacts the back surface of the chip 7. With this structure, the contact area between the back surface of the chip 7 and the conductive pillar 6 can be reduced compared to the first embodiment.

[0077] Fig. 18 shows the simulation result of S11 when the chip 7 is mounted on the sample holder 1 of the third embodiment with the bonding wire 13. Fig. 18 is an explanatory diagram showing the simulation result of S11 according to the third embodiment. In the simulation in Fig. 18, a = 5 [mm], b = 5 [mm], d = 3 [mm], d1 = 2 [mm], d2 = 1 [mm], and s = 1 [mm]. As shown in Fig. 18, the lowest resonance frequency of the chip mode can be increased to 37.5 [GHz], which is higher than that of the first embodiment.

[0078] Thus, the sample holder 1 of the third embodiment has the effect of being able to increase the resonance frequency of the chip mode compared to the sample holder 1 of the first embodiment. In the case of the aforementioned first embodiment, when the resonance of the chip mode occurs, the electric field of the standing wave generated mainly spreads in the silicon substrate and in the cavity 5 (vacuum) provided in the pedestal 2. However, in the portion directly above the columns 6 at the four corners, the space sandwiched between the GND plane 73 on the surface of the chip 7 and the column 6 is only silicon, and the electric field cannot spread into the vacuum. Therefore, the effective dielectric constant is high in the portion directly above the columns 6 at the four corners. On the other hand, in the case of the third embodiment, since at least a part of the upper surface of the columns 6 at the four corners is made non-parallel to the back surface of the chip 7, in the portion directly above the columns 6 at the four corners, the space sandwiched between the GND plane 73 on the surface of the chip 7 and the column 6 is silicon and vacuum. Therefore, the electric field can spread into the vacuum in this portion. For this reason, in the third embodiment, it is considered that the effective dielectric constant in the portion directly above the columns 6 at the four corners is lower than that of the first embodiment, so that the resonance frequency of the chip mode can be made higher.

[0079] As another example of the third embodiment, FIGS. 19A to 19C show the case where the thickness s of the columns 6 at the four corners is made larger than that in FIGS. 17A to 17C. FIG. 19A is a perspective view of the sample holder 1 according to another example of the third embodiment. FIG. 19B is a top view of the sample holder 1 according to another example of the third embodiment. FIG. 19C is an end view of the sample holder according to another example of the third embodiment, cut along a plane parallel to the xz plane including the cutting line F-FF shown in FIG. 19B. In FIG. 19C, the chip 7 is mounted on the sample holder 1 according to another example of the third embodiment.

[0080] FIG. 20 shows the simulation result of S11 when the chip 7 is mounted on the sample holder 1 using the pedestal 2 with the cavity 5 formed in FIGS. 19A to 19C by the bonding wire 13.

[0081] FIG. 20 is an explanatory diagram showing the simulation result of S11 according to another example of the third embodiment. In the simulation, a = 5 [mm], b = 5 [mm], d = 3 [mm], d1 = 0.5 [mm], d2 = 2.5 [mm], and s = 2.5 [mm]. As shown in FIG. 20, the lowest resonance frequency of the chip mode can be made even higher, up to 38.1 [GHz]. Thus, in the third embodiment, by changing the thickness s of the columns 6 at the four corners, the height d1 of the lower part 62 of the column 6, the height d2 of the upper part 61 of the column 6, the height d of the cavity 5, the thickness t of the chip 7, etc., the resonance frequency can be made even higher.

[0082] [Modification of the Third Embodiment] In the modification of the third embodiment, a part of the upper surface of the upper part 61 of the column 6 at the four corners of the cavity 5, that is, a part of the surface facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1, is not parallel to the back surface of the chip 7, but a part is parallel to the back surface of the chip 7.

[0083] FIG. 21A is a perspective view of the sample holder 1 according to a modified example of the third embodiment. FIG. 21B is a top view of the sample holder 1 according to a modified example of the third embodiment. FIG. 21C is an end view of the sample holder 1 according to a modified example of the third embodiment, cut along a plane parallel to the xz plane including the cutting line G-GG shown in FIG. 21B. In FIG. 21C, the chip 7 is mounted on the sample holder 1 according to a modified example of the third embodiment. In FIGS. 21A, 21B, and 21C, the upper surface of the upper portion 61 of the column 6 at the four corners of the cavity 5, that is, a part of the surface of the pedestal 2 forming the cavity 5 that faces the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1, is not parallel to the back surface of the chip 7, but a part is parallel to the back surface of the chip 7. In other words, at least a part of the upper surface of the upper portion 61 of the column 6 at the four corners is not parallel to the upper surface of the pedestal 2, but a part is parallel to the upper surface of the pedestal 2. The lower portion 62 of the column 6 has a triangular prism shape as in the cases of FIGS. 17A, 17B, 17C, 19A, 19B, and 19C. The bottom surface of the lower portion 62 is a right isosceles triangle, and the length of the equal sides is s1.

[0084] On the other hand, the upper portion 61 of the column 6 has a frustum of a triangular pyramid shape. The lower bottom surface of the upper portion 61 is a right isosceles triangle, and the length of the equal sides is s1. However, the upper bottom surface of the upper portion 61 is a right isosceles triangle, and the length of the equal sides is s2. Here, s1 > s2. The height of the lower portion 62 of the column 6 is d1, and the height of the upper portion 61 is d2. In this structure, when the chip 7 is mounted on the sample holder 1, at least a part of each of the columns 6 at the four corners contacts the back surface of the chip 7. With this structure, the contact area between the back surface of the chip 7 and the conductive column 6 can be reduced compared to the first embodiment. However, the contact area between the back surface of the chip 7 and the conductive column 6 is larger than in the cases of FIGS. 17A to 17C and FIGS. 19A to 19C.

[0085] FIG. 22 is an explanatory diagram showing the simulation result of S11 when the chip 7 is mounted on the sample holder 1 using the pedestal 2 having the cavity 5 shown in FIGS. 21A to 21C with the bonding wire 13. In the simulation in FIG. 22, a = 5 [mm], b = 5 [mm], d = 3 [mm], d1 = 2 [mm], d2 = 1 [mm], s1 = 1 [mm], and s2 = 0.5 [mm]. As shown in FIG. 22, the lowest resonance frequency of the chip mode is 37.5 [GHz]. This is almost equal to the resonance frequency in the simulation results in the case of FIGS. 17A to 17C described in the third embodiment. Thus, in the third embodiment, even if a part of the upper surface of the upper part 61 of the columns 6 at the four corners is parallel to the back surface of the chip 7, the effect that the resonance frequency of the chip mode can be made higher is obtained.

[0086] In the third embodiment and its modification, for example, the chip 7 mounted on the sample holder 1 has a rectangular shape, and let the length of the short side of the chip 7 be v and the length of the long side of the chip 7 be w. In such a case, in the cavity 5 shown in FIGS. 17A to 17C, the cavity 5 shown in FIGS. 19A to 19C, and the cavity 5 shown in FIGS. 21A to 21C, it is preferable that a < b, and it is preferable that a is equal to or greater than v and b is equal to or greater than w. If it is not like this, the contact area between the back surface of the chip 7 and the pedestal 2 will increase, and there is a risk that the resonance frequency of the chip mode will decrease. Also, in this case, the through hole 4 of the PCB 3 used in the third embodiment and its modification is preferably rectangular. When the length of the short side of the through hole 4 of the PCB 3 is x1 and the length of the long side of the through hole 4 is y1, since the chip 7 must enter inside the through hole 4, it is necessary that v < x1 and w < y1. And since the resonance frequency of the chip mode can be made higher the shorter x1 and y1 are, it is preferable that x1 is equal to or less than 1.2v, and more preferably equal to or less than 1.1v. For the same reason, it is preferable that b is equal to or less than 1.2w, and more preferably equal to or less than 1.1w.

[0087] On one hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a = b in the cavities 5 of FIGS. 17A to 17C, FIGS. 19A to 19C, and FIGS. 21A to 21C, and it is preferable that a is equal to or greater than v. Also, in this case, the through-hole 4 of the PCB 3 used in the third embodiment and its modified example is preferably square. When the length of one side of the through-hole 4 of the PCB 3 is x1, since the chip 7 must enter inside the through-hole 4, it is necessary that v < x1. And since the resonance frequency of the chip mode can be increased as x1 becomes shorter, it is preferable that x1 is 1.2v or less, and more preferably 1.1v or less.

[0088] Also, in the third embodiment and its modified example, when the thickness of the chip 7 mounted on the sample holder 1 is t, the height d of the cavity 5 of FIGS. 17A to 17C, FIGS. 19A to 19C, and FIGS. 21A to 21C is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0089] Also, in the third embodiment, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, it is preferable that s is 0.1v or more and 0.5v or less. Also, when the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, it is preferable that s is 0.1v or more and 0.5v or less. Similarly, in the modified example of the third embodiment, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, it is preferable that s1 is 0.1v or more and 0.5v or less. Also, when the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, it is preferable that s1 is 0.1v or more and 0.5v or less. Note that in the modified example of the third embodiment, s2 only needs to satisfy s2 < s1.

[0090] Also, in the third embodiment and its modified examples, if d2 is greater than 0, it has the effect of increasing the chip mode. Therefore, d2 is preferably greater than 0 and less than or equal to d. When d2 = d, d1 = 0, and in that case, the pillar 6 is composed only of the upper part 61.

[0091] In addition, in the third embodiment and its modified examples, the PCB3 (Figs. 11A to 11E) of the first embodiment was used. The same effect can be obtained by using the sample holder 1 with the PCB3 (Figs. 13A to 13F) of the modified example of the first embodiment, the PCB3 (Fig. 14) of the second embodiment, or the PCB3 (Fig. 16) of the modified example of the second embodiment placed on the pedestal 2 having the cavity 5 formed as shown in Figs. 17A to 17C, Figs. 19A to 19C, and Figs. 21A to 21C.

[0092] In the third embodiment and its modified examples, the shape of the lower part 62 of the pillar 6 is a triangular prism with a right isosceles triangle as the bottom surface, and the shape of the upper part 61 is a triangular pyramid. However, the shapes of the lower part 62 and the upper part 61 of the pillar 6 are not particularly limited. If at least a part of the upper surface of the upper part 61, that is, the surface of the upper part 61 facing the back surface of the chip 7, is not parallel to the back surface of the chip 7 or the upper surface of the pedestal 2, the effects described in the third embodiment and its modified examples can be achieved.

[0093] (Fourth Embodiment) The fourth embodiment will be described in detail with reference to the drawings. Hereinafter, the description of the content overlapping with the above description will be omitted as long as the description of the fourth embodiment is not made unclear.

[0094] The sample holder 1 of the fourth embodiment has a configuration in which a PCB 3 is placed on a metal pedestal 2 as shown in FIG. 9. In the fourth embodiment, similar to the first embodiment, the PCB 3 shown in FIGS. 11A to 11E is used. Further, in the fourth embodiment, the sample holder 1 has a cavity 5 in a portion of the pedestal 2 that corresponds directly below the through hole 4 of the PCB 3. In other words, the sample holder 1 has a cavity 5 in a portion of the pedestal 2 that corresponds directly below the chip 7 when the chip 7 is mounted on the sample holder 1. And in the fourth embodiment, the cavity 5 has a shape combining a column and a truncated pyramid, and the smaller bottom surface of the truncated pyramid and the upper bottom surface of the column have the same shape. For example, the larger bottom surface of the truncated pyramid is on the side of the through hole 4. As an example of the truncated pyramid of the cavity 5, a truncated square pyramid will be described as an example. As an example of the column of the cavity 5, the column will be described by taking a square column as an example.

[0095] The sample holder 1 according to the fourth embodiment is shown in FIGS. 23A to 23C. FIG. 23A is a perspective view of the sample holder 1 according to the fourth embodiment. FIG. 23B is a top view of the sample holder 1 according to the fourth embodiment. FIG. 23C is an end view of the sample holder 1 according to the fourth embodiment cut along a plane parallel to the xz plane including the cutting line H-HH shown in FIG. 23B. In FIG. 23C, a chip 7 is mounted on the sample holder 1 according to the fourth embodiment with bonding wires 13.

[0096] As shown in FIGS. 23B and 23C, the cavity 5 formed in the pedestal 2 in the fourth embodiment has a structure in which a square column portion 51, which is a square column, and a truncated square pyramid portion 52, which is a truncated square pyramid, are connected. In FIGS. 23B and 23C, the bottom surface of the square column portion 51 and the smaller bottom surface of the truncated square pyramid portion 52 are connected. For this reason, the bottom surface of the square column portion 51 and the smaller bottom surface of the truncated square pyramid portion 52 have the same shape and the same area.

[0097] In FIGS. 23A to 23C, the square column portion 51 has a shape of a square prism with a square bottom surface having side lengths a1 and b1 and a height d1. In FIGS. 23A to 23C, the truncated square pyramid portion 52 is a truncated square pyramid.

[0098] Here, the lengths of the sides of the chip 7 and the prism portion 51 will be described when the chip 7 mounted on the sample holder 1 has a rectangular shape, for example. When the length of the short side of the chip 7 is v and the length of the long side of the chip 7 is w, it is preferable that a1 < b1 in the prism portion 51, and it is preferable that a1 is smaller than v and b1 is smaller than w.

[0099] On the other hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a1 = b1 in the prism portion 51, and it is preferable that a1 is smaller than v.

[0100] In FIGS. 23A to 23C, the frustum pyramid portion 52 has a shape of a quadrilateral with the smaller bottom area of the two bottom surfaces having side lengths a1 and b1. In FIGS. 23A to 23C, the frustum pyramid portion 52 has a shape of a quadrilateral with the larger bottom area having side lengths a2 and b2.

[0101] Here, for example, when the chip 7 mounted on the sample holder 1 has a rectangular shape, let the length of the short side of the chip 7 be v and the length of the long side of the chip 7 be w. In such a case, it is preferable that a2 < b2 in the frustum pyramid portion 52, and it is preferable that a2 is equal to or greater than v and equal to or less than 1.5v, and b2 is equal to or greater than w and equal to or less than 1.5w.

[0102] On the other hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a2 = b2 in the frustum pyramid portion 52, and it is preferable that a2 is equal to or greater than v and equal to or less than 1.5v. Also, the height of the frustum pyramid portion 52 is d2. The cavity 5 formed in the pedestal 2 of the sample holder 1 of the present embodiment has a structure in which the frustum pyramid portion 52 is connected on the prism portion 51, and the upper bottom surface of the prism portion 51 and the lower bottom surface of the frustum pyramid portion 52 are the same surface. Here, the lower bottom surface of the frustum pyramid portion 52 is the smaller bottom surface of the two bottom surfaces of the frustum pyramid portion 52.

[0103] The feature of the sample holder 1 of the fourth embodiment is that by providing the frustum of a pyramid portion 52 above the cavity 5, when the chip 7 is mounted on the sample holder 1, at least a part of the surface of the pedestal 2 facing the back surface of the chip 7 is not parallel to the back surface of the chip 7. In FIGS. 23A to 23C, this part is the side surface of the frustum of a pyramid portion 52. As shown in FIG. 23C, let the angle formed by the side surface of the frustum of a pyramid portion 52, that is, the part of the surface facing the back surface of the chip 7 that is not parallel to the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1, and the back surface of the chip 7 be θ. In other words, let the angle formed by the side surface of the frustum of a pyramid portion 52 and the upper surface of the pedestal 2 be θ. θ is in the range such that a part of the side surface of the frustum of a pyramid portion 52 that is not parallel to the back surface of the chip 7 can be formed. For example, θ is less than 90 degrees. In the structure of the sample holder 1 of the fourth embodiment, when the chip 7 is mounted on the sample holder 1, at least a part of the pedestal 2 contacts the back surface of the chip 7. With this structure, the contact area between the back surface of the chip 7 and the pedestal 2 can be reduced compared to the first embodiment.

[0104] FIG. 24 is an explanatory diagram showing the simulation result of S11 when the chip 7 is mounted on the sample holder 1 according to the fourth embodiment with the bonding wire 13. In the simulation in FIG. 24, assume a1 = 4 [mm], b1 = 4 [mm], d1 = 2.5 [mm], a2 = 5 [mm], b2 = 5 [mm], and d2 = 0.5 [mm]. In this case, θ is 45 degrees. As shown in FIG. 24, the lowest resonance frequency of the chip mode can be increased to 38.6 [GHz], which is higher than that of the first embodiment.

[0105] As described above, the sample holder 1 of the fourth embodiment has the effect of being able to increase the resonance frequency of the chip mode compared to the sample holder 1 of the first embodiment. The reason why the resonance frequency of the chip mode could be increased in the fourth embodiment compared to the first embodiment will be explained. In the case of the first embodiment, the standing wave electric field generated when the resonance of the chip mode occurs mainly spreads in the silicon substrate and in the cavity 5 (vacuum) provided in the pedestal 2. However, in the case of the first embodiment, in the portion directly above the columns 6 at the four corners, in other words, in the four corner portions of the chip 7, the space sandwiched between the GND plane 73 on the surface of the chip 7 and the columns 6 is only silicon, and the electric field cannot spread into the vacuum. Therefore, in the case of the first embodiment, the effective dielectric constant is high in the four corner portions of the chip 7. On the other hand, in the case of the fourth embodiment, by providing the frustum of a pyramid portion 52 in the cavity 5, even in the four corner portions of the chip 7, the space sandwiched between the GND plane 73 on the surface of the chip 7 and the pedestal 2 becomes silicon and vacuum, so that the electric field can spread into the vacuum in this portion. Therefore, in the fourth embodiment, it is considered that the effective dielectric constant in the four corner portions of the chip 7 is lower than that in the first embodiment, so that the resonance frequency of the chip mode can be made higher.

[0106] [Modification Example of the Fourth Embodiment] As a modification of the fourth embodiment, the sample holder 1 in the case where the prismatic portion 51 of the cavity 5 is eliminated and only the frustum portion 52 is provided is shown in FIGS. 25A to 25C. FIG. 25A is a perspective view of the sample holder 1 according to the modification of the fourth embodiment. FIG. 25B is a top view of the sample holder 1 according to the modification of the fourth embodiment. FIG. 25C is an end view of the sample holder 1 according to the modification of the fourth embodiment, cut along a plane parallel to the xz plane including the cutting line I-II shown in FIG. 25B. In FIG. 25C, the chip 7 according to the modification of the fourth embodiment is mounted with the bonding wire 13. As shown in FIGS. 25A to 25C, the cavity 5 has no prismatic portion 51 and has a frustum portion 52. In FIGS. 25A to 25C, the frustum portion 52 is a square frustum. Also, θ is in a range such that the side surface of the frustum portion 52 is not parallel to the back surface of the chip 7. For example, when the frustum portion 52 is a square frustum, θ is less than 90 degrees.

[0107] FIG. 26 is an explanatory diagram showing the simulation result of S11 when the chip 7 is mounted with the bonding wire 13 on the sample holder 1 using the pedestal 2 in which the cavity 5 shown in FIGS. 25A to 25C is formed. In the simulation in FIG. 26, a1 = 2 [mm], b1 = 2 [mm], a2 = 5 [mm], b2 = 5 [mm], d1 = 0 [mm], and d2 = 5 [mm]. In this case, θ is about 73.3 degrees. As shown in FIG. 26, the lowest resonance frequency of the chip mode can be made higher than 39.0 [GHz]. Thus, in the fourth embodiment, the resonance frequency can be made even higher by changing the dimensions a1, b1, d1, a2, b2, d2 of the prismatic portion 51 and the frustum portion 52 of the cavity 5, the thickness t of the chip 7, and the like.

[0108] In the fourth embodiment and its modification, when the thickness of the chip 7 mounted on the sample holder 1 is t, the height d1 + d2 of the cavity 5 in FIGS. 23A to 23C and FIGS. 25A to 25C is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0109] Also, in the fourth embodiment and its modified examples, if d2 is greater than 0, it has the effect of increasing the chip mode. Therefore, it is preferable that d2 is greater than 0. On the other hand, since d1 may be 0, it is preferable that d2 is 0 or more. When d1 = 0, the cavity 5 is composed of only the frustum portion 52.

[0110] In addition, in the fourth embodiment and its modified examples, the PCB 3 (Figs. 11A to 11E) of the first embodiment was used. The same effect can be obtained by using the sample holder 1 on which the PCB 3 (Figs. 13A to 13F) of the modified example of the first embodiment, the PCB 3 (Fig. 14) of the second embodiment, or the PCB 3 (Fig. 16) of the modified example of the second embodiment is placed on the pedestal 2 in which the cavity 5 of Figs. 23A to 23C and Figs. 25A to 25C is formed.

[0111] In the fourth embodiment and its modified examples, the cavity 5 has a structure in which the prism portion 51 and the frustum portion 52 are connected, or a structure composed of only the frustum portion 52. However, the frustum portion 52 does not have to have the shape of a frustum. For example, the side surface of the frustum portion 52 may be a curved surface instead of a flat surface. That is, if at least a part of the surface of the pedestal 2 that forms the cavity 5 and faces the back surface of the chip 7 is not parallel to the back surface of the chip 7 or the upper surface of the pedestal 2, the effects described in the fourth embodiment and its modified examples are achieved. Also, instead of the frustum shape of the frustum portion 52, a pyramid shape may be used. Therefore, the cavity 5 may have a structure in which the prism portion 51 and the pyramid are connected, or a structure composed of only the pyramid.

[0112] (Fifth Embodiment) The fifth embodiment will be described in detail with reference to the drawings. Hereinafter, the description of the content overlapping with the above description will be omitted as long as the description of the fifth embodiment is not made unclear.

[0113] The sample holder 1 of the fifth embodiment has a configuration in which a PCB 3 is placed on a metal pedestal 2 as shown in FIG. 9. In the fifth embodiment, the PCB 3 having the structure shown in FIGS. 11A to 11E, which is the same as that of the first embodiment, is used. And in the fifth embodiment, the sample holder 1 has a cavity 5 at a portion of the pedestal 2 that corresponds directly below the through-hole 4 of the PCB 3, in other words, at a portion that corresponds directly below the chip 7 when the chip 7 is mounted on the sample holder 1. The cavity 5 has a shape that combines a prism and a frustum of a pyramid, similar to the fourth embodiment, and is a shape in which the smaller bottom surface of the frustum of the pyramid and the upper bottom surface of the prism are connected. Further, in the fifth embodiment, unlike the fourth embodiment, the frustum of the pyramid may be deformed. As a result, in the fifth embodiment, when the chip 7 is mounted on the sample holder 1, at least a part of the surface of the pedestal 2 that forms the cavity 5 and faces the back surface of the chip 7 is not parallel to the back surface of the chip 7.

[0114] FIG. 27A is a perspective view of the sample holder 1 of the fifth embodiment. FIG. 27B is a top view of the sample holder 1 of the fifth embodiment. FIG. 27C is a cross-sectional view of the sample holder of the fifth embodiment cut along a plane parallel to the xz plane including the cutting line J-JJ shown in FIG. 27B. In FIG. 27C, the chip 7 is mounted on the sample holder 1 according to the fifth embodiment with bonding wires 13. As shown in FIGS. 27A to 27C, the cavity 5 formed in the pedestal 2 in the fifth embodiment has a structure connecting a prism portion 51 and a frustum of a pyramid deformed portion 53.

[0115] The prism portion 51 has a bottom surface in the shape of a quadrilateral with side lengths a1 and b1 for each side, and has the shape of a quadrangular prism with a height of d1.

[0116] Here, for example, the chip 7 mounted on the sample holder 1 has a rectangular shape, and let the length of the short side of the chip 7 be v and the length of the long side of the chip 7 be w. In such a case, it is preferable that a1 < b1 in the prism portion 51, and it is preferable that a1 is smaller than v and b1 is smaller than w.

[0117] On one hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a1 = b1 in the prism portion 51, and it is preferable that a1 is smaller than v.

[0118] The frustum pyramid-shaped deformed portion 53 has a shape of a quadrilateral with the lengths of each side being a1 and b1 for the smaller-bottom surface among the two bottom surfaces, and a shape of an octagon with the four corners of the quadrilateral with the lengths of each side being a2 and b2 for the larger-bottom surface being cut diagonally.

[0119] Here, for example, when the chip 7 mounted on the sample holder 1 has a rectangular shape, let the length of the short side of the chip 7 be v and the length of the long side of the chip 7 be w. In such a case, it is preferable that a2 < b2 in the frustum pyramid-shaped deformed portion 53, and it is preferable that a2 is equal to or greater than v and equal to or less than 1.5v, and b2 is equal to or greater than w and equal to or less than 1.5w.

[0120] On one hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a2 = b2 in the frustum pyramid-shaped deformed portion 53, and it is preferable that a2 is equal to or greater than v and equal to or less than 1.5v.

[0121] Also, the height of the frustum pyramid-shaped deformed portion 53 is d2. The cavity 5 formed in the pedestal 2 of the sample holder 1 of the present embodiment has a structure in which the frustum pyramid-shaped deformed portion 53 is connected on the prism portion 51, and the upper bottom surface of the prism portion 51 and the lower bottom surface of the frustum pyramid-shaped deformed portion 53 are the same plane. Here, the lower bottom surface of the frustum pyramid-shaped deformed portion 53 is the smaller-bottom surface among the two bottom surfaces of the frustum pyramid-shaped deformed portion 53. To accurately describe the shape of the cavity 5 in FIGS. 27A to 27C of the fifth embodiment, FIGS. 28A to 28C and FIGS. 29A to 29C are used for explanation.

[0122] FIG. 28A is a perspective view showing a first example of the shape of the cavity 5 of the sample holder 1 according to the fifth embodiment. FIG. 28B is a top view showing the first example of the shape of the cavity 5 of the sample holder 1 according to the fifth embodiment. FIG. 28C is an end view of the cavity 5 of the sample holder 1 according to the fifth embodiment, in which the vicinity of the cavity 5 of the sample holder 1 is cut along a plane parallel to the xz plane including the cutting line K-KK shown in FIG. 28B. In FIG. 28C, the chip 7 is mounted on the sample holder 1 according to the fifth embodiment with the bonding wire 13.

[0123] FIG. 29A is a perspective view showing a second example of the shape of the cavity 5 of the sample holder 1 according to the fifth embodiment. FIG. 29B is a top view showing the second example of the shape of the cavity 5 of the sample holder 1 according to the fifth embodiment. FIG. 29C is a cross-sectional view of the cavity of the sample holder according to the fifth embodiment, in which the sample holder 1 is cut along a plane parallel to the xz plane including the cutting line L-LL shown in FIG. 29B. In the cross-sectional view shown in FIG. 29C, although the column 6 is not present on the cut surface, a pattern is provided on the column 6 for the purpose of clearly showing the column 6. In FIG. 29C, the chip 7 is mounted on the sample holder 1 according to the fifth embodiment with the bonding wire 13.

[0124] The cavity 5 shown in FIGS. 28A to 28C has the same structure as the cavity 5 shown in FIGS. 23A to 23C of the fourth embodiment. That is, the cavity 5 has a configuration in which the prismatic portion 51 and the frustum of a pyramid portion 52 are connected. In the fifth embodiment, four conductor columns 6 shown in FIGS. 29A to 29C are further added to the four corners of the cavity 5 shown in FIGS. 28A to 28C, which is the same as that of the fourth embodiment. Thereby, the cavity 5 having the structure shown in FIGS. 27A to 27C can be formed in the pedestal 2. As shown in FIGS. 29A to 29C, in the present embodiment, the conductor columns 6 at the four corners are triangular prisms, the bottom surface of the triangular prism has a shape of a right isosceles triangle, the length of the equal two sides of this bottom surface is s, and the height of the triangular prism is d1 + d2. The conductor columns 6 at the four corners are in electrical contact with the pedestal 2. The four conductor columns 6 shown in FIGS. 29A to 29C may be separate from the pedestal 2, or may be made of the same material as the pedestal 2, that is, the pedestal 2 and the four columns 6 may be integrated.

[0125] The feature of the sample holder 1 of the fifth embodiment is that by providing a frustum-shaped deformed portion 53 above the cavity 5, at least a part of the surface facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1 is not parallel to the back surface of the chip 7. As shown in Fig. 27C, let the angle formed by the side surface of the frustum-shaped deformed portion 53, that is, the portion of the surface facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1 that is not parallel to the back surface of the chip 7, and the back surface of the chip 7 be θ. In other words, the angle formed by the side surface of the frustum-shaped deformed portion 53 and the upper surface of the pedestal 2 is θ. θ is in the range such that the side surface of the frustum-shaped deformed portion 53 is not parallel to the back surface of the chip 7. For example, when the frustum-shaped deformed portion 53 is created based on the frustum-shaped portion 52 which is a square frustum, θ is less than 90 degrees. In the structure of the sample holder 1 of the fifth embodiment, when the chip 7 is mounted on the sample holder 1, at least a part of the pedestal 2 contacts the back surface of the chip 7.

[0126] Fig. 30 shows the simulation results of S11 when the chip 7 is mounted on the sample holder 1 using the pedestal 2 with the cavity 5 formed therein from Figs. 27A to 27C by the bonding wire 13. Fig. 30 is an explanatory diagram showing the simulation results of S11 of the system in which the chip 7 is mounted on the sample holder 1 of the fifth embodiment by the bonding wire 13. In the simulation in Fig. 30, a1 = 3 [mm], b1 = 3 [mm], a2 = 5 [mm], b2 = 5 [mm], d1 = 1 [mm], d2 = 2 [mm], and s = 1 [mm] were used. In this case, θ is approximately 63.4 degrees.

[0127] As shown in Fig. 30, the lowest resonance frequency of the chip mode can be increased to 37.4 [GHz], which is higher than that of the first embodiment.

[0128] As described above, the sample holder 1 of the fifth embodiment has the effect of being able to increase the resonance frequency of the chip mode compared to the sample holder 1 of the first embodiment. In the sample holder 1 shown in FIGS. 27A to 27C of the fifth embodiment, the upper surfaces of the columns 6 at the four corners are in contact with the back surface of the chip 7. And in the simulation shown in FIG. 30, s = 1 [mm], but in that case, the contact area between the upper surface of the column 6 at the four corners and the back surface of the chip 7 in the sample holder 1 of this embodiment is the same as that analyzed in the simulation of FIG. 12 in the first embodiment. In the simulation of FIG. 12, for the first embodiment with s = 1 [mm], the resonance frequency of the chip mode is 36.6 [GHz], and in FIG. 30 for the fifth embodiment, the resonance frequency of the chip mode is 37.4 [GHz]. Therefore, the fifth embodiment has a higher resonance frequency of the chip mode than the first embodiment. It is considered that the reason why the fifth embodiment can increase the resonance frequency of the chip mode compared to the first embodiment is as follows. In the case of the fifth embodiment, it is considered that the resonance frequency of the cavity 5 itself becomes higher than that of the first embodiment because the dimensions of the cavity 5 are smaller than the dimensions (a and b) of the cavity 5 in the first embodiment. Specifically, in the case of the fifth embodiment, the dimensions of the cavity 5 directly below the chip 7 become smaller as going downward, and at the bottom of the cavity 5, the dimensions (a1 and b1) of the cavity 5 are smaller than those (a and b) of the first embodiment. By adopting such a structure, it is considered that the resonance frequency of the cavity 5 itself is higher in the fifth embodiment than in the first embodiment. As a result, even if the contact area between the back surface of the chip 7 and the column 6 is the same, it is considered that the fifth embodiment can achieve the effect of increasing the resonance frequency of the chip mode compared to the first embodiment.

[0129] [Modification Example of the Fifth Embodiment] As a modification of the fifth embodiment, FIGS. 31A to 31C show a sample holder in the case where the prismatic portion 51 of the cavity 5 is eliminated and only the frustum pyramid-shaped modified portion 53 remains. FIG. 31A is a perspective view of the sample holder 1 of the modification of the fifth embodiment. FIG. 31B is a top view of the sample holder 1 of the modification of the fifth embodiment. FIG. 31C is a cross-sectional view of the sample holder of the modification of the fifth embodiment cut along a plane parallel to the xz plane including the cutting line M-MM shown in FIG. 31B. In FIG. 31C, the chip 7 is mounted on the sample holder 1 according to the fifth embodiment with the bonding wire 13. Further, in order to explain in more detail the shape of the cavity 5 shown in FIGS. 31A, 31B, and 31C of the modification of the fifth embodiment, FIGS. 32A to 32C and FIGS. 33A to 33C are used for explanation.

[0130] FIG. 32A is a perspective view showing Shape Example 1 of the cavity 5 of the sample holder 1 of the modification of the fifth embodiment. FIG. 32B is a top view showing Shape Example 1 of the cavity 5 of the sample holder 1 of the modification of the fifth embodiment. FIG. 32C is an end view of Shape Example 1 of the cavity 5 of the sample holder 1 of the modification of the fifth embodiment, in which the vicinity of the cavity 5 of the sample holder 1 is cut along a plane parallel to the xz plane including the cutting line N-NN shown in FIG. 32B. In FIG. 32C, the chip 7 is mounted on the sample holder 1 according to the modification of the fifth embodiment with the bonding wire 13.

[0131] FIG. 33A is a perspective view showing Shape Example 2 of the cavity 5 of the sample holder 1 of the modification of the fifth embodiment. FIG. 33B is a top view showing Shape Example 2 of the cavity 5 of the sample holder 1 of the modification of the fifth embodiment. FIG. 33C is a cross-sectional view of the sample holder of the modification of the fifth embodiment in Shape Example 2 of the cavity, in which the sample holder is cut along a plane parallel to the xz plane including the cutting line O-OO shown in FIG. 33B. In FIG. 33C, the chip 7 is mounted on the sample holder 1 according to the modification of the fifth embodiment with the bonding wire 13.

[0132] The cavity 5 shown in FIGS. 32A to 32C has the same structure as the cavity 5 in FIGS. 25A to 25C of the modification of the fourth embodiment. That is, the cavity 5 shown in FIGS. 32A to 32C is composed of a frustum of a pyramid portion 52. In the modification of the fifth embodiment, in the same manner as in the modification of the fourth embodiment, four conductor columns 6 shown in FIGS. 33A to 33C are further added to the four corners of the cavity 5 shown in FIGS. 32A to 32C. Thereby, the cavity 5 shown in FIGS. 31A to 31C can be formed in the pedestal 2. θ is a range in which a portion not parallel to the back surface of the chip 7 can be formed on the side surface of the cavity 5 (frustum of a pyramid portion 52) shown in FIGS. 32A to 32C. For example, when the cavity 5 shown in FIGS. 32A to 32C is a frustum of a square pyramid, θ is less than 90 degrees.

[0133] FIG. 34 shows the simulation result of S11 when the chip 7 is mounted on the sample holder 1 using the pedestal 2 in which the cavity 5 shown in FIGS. 31A to 31C is formed, with the bonding wire 13. FIG. 34 is an explanatory diagram showing the simulation result of S11 of the system in which the chip 7 is mounted on the sample holder 1 of the modification of the fifth embodiment with the bonding wire 13. In the simulation in FIG. 34, a1 = 2 [mm], b1 = 2 [mm], a2 = 5 [mm], b2 = 5 [mm], d2 = 5 [mm], and s = 1 [mm]. In this case, θ is about 73.3 degrees. As shown in FIG. 34, the lowest resonance frequency of the chip mode can be increased to 37.5 [GHz], which is higher than that of the first embodiment. Thus, in the fifth embodiment, the resonance frequency can be further increased by changing the dimensions a1, b1, d1, a2, b2, d2 of the prism portion 51 and the frustum of a pyramid deformation portion 53 of the cavity 5, the thickness t of the chip 7, and the like.

[0134] In the fifth embodiment and its modification, let the thickness of the chip 7 mounted on the sample holder 1 be t. In such a case, the sum (d1 + d2) of the height d1 of the prism portion 51 and the height d2 of the frustum of a pyramid deformation portion 53 of the cavity 5 in FIGS. 27A to 27C and FIGS. 31A to 31C is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0135] Also, in the fifth embodiment and its modified examples, if d2 is greater than 0, it has the effect of increasing the chip mode. Therefore, it is preferable that d2 is greater than 0. On the other hand, since d1 may be 0, it is preferable that d2 is 0 or more. When d1 = 0, the cavity 5 is composed only of the frustum pyramid-shaped portion 53.

[0136] Also, in the fifth embodiment and its modified examples, as shown in FIGS. 29A to 29C and FIGS. 33A to 33C, the smaller the bottom area of the columns 6 at the four corners, the smaller the contact area between the back surface of the chip 7 and the pedestal 2, so that the resonance frequency of the chip mode can be increased. Therefore, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, s needs to be 0.5v or less, preferably 0.3v or less, and more preferably 0.2v or less. On the other hand, when the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, s needs to be 0.5v or less, preferably 0.3v or less, and more preferably 0.2v or less.

[0137] In the fifth embodiment and its modified examples, the PCB 3 (FIGS. 11A to 11E) of the first embodiment is used. The same effect can be obtained by using a sample holder 1 in which the PCB 3 (FIGS. 13A to 13F) of the modified example of the first embodiment, the PCB 3 (FIG. 14) of the second embodiment, or the PCB 3 (FIG. 16) of the modified example of the second embodiment is placed on the pedestal 2 having the cavity 5 formed as shown in FIGS. 27A to 27C and FIGS. 31A to 31C.

[0138] In the fifth embodiment and its modified examples, the cavity 5 has a structure in which a prism portion and a frustum pyramid-shaped portion are connected, or a structure composed only of the frustum pyramid-shaped portion, but the shape of the cavity 5 may be another shape. For example, the side surface of the frustum pyramid-shaped portion may be a curved surface instead of a flat surface. That is, if at least a part of the surface of the pedestal 2 forming the cavity 5 that faces the back surface of the chip 7 is not parallel to the back surface of the chip 7 or the upper surface of the pedestal 2, the effects described in the fifth embodiment and its modified examples can be achieved.

[0139] [Other Embodiments] In the first to fifth embodiments and their modifications, as a method of mounting the chip 7 of the superconducting quantum circuit, a configuration in which the chip 7 is directly placed on the metal pedestal 2 has been described. However, the mounting method is not limited to this. For example, even in the case of a mounting form in which a resin material such as varnish is applied on the metal pedestal 2 and then the chip 7 is placed on the resin material such as varnish, the effects of each embodiment, that is, the effect of being able to make the resonance frequency of the chip mode higher, can be obtained.

[0140] Also, in the first to fifth embodiments and their modifications, as the configuration of the sample holder 1, a configuration in which the PCB 3 is directly placed on the metal pedestal 2 has been described. The sample holder 1 having a configuration in which a metal sheet such as In (indium) is placed on the metal pedestal 2 and the PCB 3 is placed on the metal sheet such as In can also obtain the effects of each embodiment. By sandwiching a soft metal sheet such as In between the pedestal 2 and the PCB 3, it is possible to make it difficult to generate a gap between the back surface GND11 of the PCB 3 and the pedestal 2. As a result, the high-frequency characteristics of the sample holder 1 may be improved. Specifically, if there is a gap between the PCB 3 and the pedestal 2, the gap may form a new cavity resonator and resonance may occur when a signal of a specific frequency is input to the chip 7. Therefore, it is preferable to prevent a gap from occurring between the back surface GND11 of the PCB 3 and the pedestal 2.

[0141] In the first to fifth embodiments and their modifications, the configuration of the sample holder 1 was described as placing the PCB 3 on the metal pedestal 2. Further, a metal lid may be placed on the PCB 3. Even when the lid is placed, the effects of each embodiment can be obtained. In such a sample holder 1, the metal lid is in electrical contact with the surface GND 9 of the PCB 3. However, the lid is prevented from contacting the core wires 10 or chips 7 of the PCB 3. This is to prevent the circuits and wirings of the core wires 10 and chips 7 of the PCB 3 from contacting the GND. For the same reason as above, it is preferable that no gap is formed between the lid and the surface GND 9 of the PCB 3, so a sheet such as In may be sandwiched between the lid and the surface GND 9 of the PCB 3.

[0142] Also, in the first to fifth embodiments and their modifications, as the shape of the sample holder 1, the case where the pedestal 2 is a rectangular parallelepiped or a cube was shown. However, even if the shape of the pedestal 2 is another shape such as a cylinder, the effects of each embodiment can be obtained. Similarly, even if the shape of the PCB 3 is a shape other than a rectangle or a square, such as a circle, the effects of each embodiment can be obtained.

[0143] (Sixth Embodiment) In the sixth embodiment, the basic configuration of the content described in the first to fifth embodiments will be described. Here, the sixth embodiment will be described with reference to FIGS. 9 and 11E used in the first embodiment.

[0144] As shown in FIG. 9, the sample holder 1 includes a pedestal 2 and a PCB 3 in contact with the pedestal 2. And as shown in FIG. 11E, the PCB 3 includes a dielectric 8, a surface GND 9 formed on the surface of the dielectric 8, a back surface GND 11 formed on the back surface of the dielectric 8, a through hole 4 penetrating from the surface GND 9 to the back surface GND 11 for storing the chip 7, and a conductor (conductor) 14 for conducting the surface GND 9 and the back surface GND 11 on the end surface of the through hole 4.

[0145] As shown in FIG. 9, there is a cavity 5 in at least a part of the pedestal 2 below the through hole 4. The shape of the cavity 5 is not particularly limited. For example, the bottom surface of the cavity 5 may be a flat surface or other than a flat surface. The side surface of the cavity 5 may be a flat surface or other than a flat surface. For example, there may be a depression or the like on the side surface or the bottom surface of the cavity 5.

[0146] Next, the cavity 5 has a support structure that conducts to the pedestal 2 and supports the surface of the chip 7. The shape of the support structure is not particularly limited. The support structure may be a pillar or the like. The support structure may be integral with the pedestal. Therefore, the support structure may be formed according to the shape of the cavity 5.

[0147] In the sixth embodiment, by forming the cavity 5 in the pedestal 2 and providing a conductor (conductor) 14 that conducts the surface GND 9 and the back surface GND 11 on the end face of the through hole 4 of the PCB 3, the resonance frequency in the chip mode can be made higher.

[0148] This concludes the description of the sample holder 1 according to each embodiment. Further, the superconducting quantum computer according to each embodiment includes the sample holder 1 according to each embodiment and a chip on which a superconducting quantum circuit is formed and stored in the sample holder 1.

[0149] Although the present disclosure has been described with reference to each embodiment above, the present disclosure is not limited to the above embodiments. The configurations and details of each disclosure may include embodiments to which various changes understandable by those skilled in the art within the scope of the present disclosure are applied. The present disclosure may include embodiments in which the matters described in this specification are appropriately combined or replaced as necessary. For example, the matters described using a specific embodiment can also be applied to other embodiments within a range where no contradiction occurs.

[0150] Some or all of the above embodiments can also be described as follows. However, some or all of the above embodiments are not limited to the following.

[0151] (Appendix 1) A pedestal, a PCB in contact with the pedestal, and are provided, the PCB has a dielectric, a surface ground formed on the surface of the dielectric, a back ground formed on the back surface of the dielectric, a through hole penetrating from the surface ground to the back ground in which a chip is stored, and a conductor for connecting the surface ground and the back ground to the end face of the through hole, at least a part of the lower side of the through hole in the pedestal has a cavity, the cavity has a support structure that supports the surface of the chip and is electrically connected to the pedestal, a sample holder.

[0152] (Appendix 2) At least a part of the portion of the support structure that supports the chip is parallel to the surface of the chip, The sample holder according to Appendix 1.

[0153] (Appendix 3) The support structure is a pillar, The sample holder according to Appendix 1 or 2.

[0154] (Appendix 4) The support structure is a plurality of pillars provided in the cavity, The sample holder according to Appendix 3.

[0155] (Appendix 5) The plurality of pillars are provided at the four corners of the cavity, The sample holder according to Appendix 4.

[0156] (Appendix 6) When each of the plurality of pillars is a triangular prism, the length of the equal side of the isosceles triangle surface of the triangular prism is shorter than half the length of the short side of the surface of the chip, The sample holder according to Appendix 5.

[0157] (Appendix 7) The PCB has a coplanar waveguide core wire on the surface of the dielectric. The sample holder according to any one of Appendices 1 to 6.

[0158] (Appendix 8) The conductor is provided on a portion of the end face of the through hole other than the end face of the PCB near the core wire. The sample holder according to Appendix 7.

[0159] (Appendix 9) The core wire has a length such that it does not contact the end face of the through hole. The conductor is formed on the entire end face of the through hole. The sample holder according to Appendix 7.

[0160] (Appendix 10) The PCB further has a core wire in a region of the dielectric sandwiched between the surface ground and the back ground. On the surface of the dielectric, in addition to the surface ground, there is a pad for electrically connecting the chip and the core wire, and the pad is electrically connected to the core wire. The sample holder according to any one of Appendices 1 to 6.

[0161] (Appendix 11) The support structure is made of metal or a mixture containing metal. The sample holder according to any one of Appendices 1 to 10.

[0162] (Appendix 12) The pedestal is made of metal. The sample holder according to any one of Appendices 1 to 11.

[0163] (Appendix 13) The height of the cavity is greater than the thickness of the chip. The sample holder according to any one of Appendices 1 to 12.

[0164] (Appendix 14) The height of the cavity is at least twice the thickness of the chip. The sample holder according to Supplementary Note 13.

[0165] (Supplementary Note 15) A sample holder, A chip on which a superconducting quantum circuit is formed, stored in the sample holder, comprising: The sample holder has a pedestal, a PCB in contact with the pedestal, and comprises: The PCB has a dielectric, a surface ground formed on the surface of the dielectric, a back ground formed on the back surface of the dielectric, a through hole penetrating from the surface ground to the back ground for storing the chip, and a conductor for connecting the surface ground and the back ground on the end face of the through hole. There is a cavity in at least a part of the lower side of the through hole in the pedestal, and there is a support structure in the cavity that supports the surface of the chip and is conductive to the pedestal. A superconducting quantum computer.

Description of Reference Numerals

[0166] 1 Sample holder 2 Pedestal 3 PCB 4 Through hole 5 Cavity 6 Column 7 Chip 8 Dielectric 9 Surface GND 10 Core wire 11 Back ground 12 Through hole 13 Bonding wire 14 Conductor 15 Input / output pad 16 Bonding pad 51 Prismatic portion 52 Frustum of pyramid portion 53 Deformed frustum of pyramid portion 61 Upper part 62 Lower part 71 First coplanar waveguide 72 Second coplanar waveguide 73 GND plane 74 First core wire 75 Second core wire 76 First pad 77 Second pad 101 Sample holder 102 Pedestal 103 PCB 104 Through hole 105 Cavity 106 Column 107 Chip 108 Dielectric 109 Surface GND 110 Core wire 110a First core wire 110b Second core wire 111 Backside GND 112 Through hole 113 Bonding wire

Claims

1. A pedestal, and a PCB (Printed Circuit Board) in contact with the pedestal, wherein the PCB has a dielectric, a surface ground formed on the surface of the dielectric, a back surface ground formed on the back surface of the dielectric, a through hole penetrating from the surface ground to the back surface ground for storing a chip, and a conductor for connecting the surface ground and the back surface ground at an end face of the through hole, wherein at least a part of the pedestal below the through hole has a cavity, wherein the cavity has a support structure that is in conduction with the pedestal and supports a surface of the chip, wherein at least a part of a portion of the support structure that supports the chip is not parallel to the surface of the chip, a sample holder.

2. The support structure is a column of a conductor, The sample holder according to claim 1.

3. The column has a shape combining a frustum of a cone and a prism, wherein a bottom surface with a smaller area of the frustum of the cone is on the side of the through hole, wherein a bottom surface with a larger area of the frustum of the cone and an upper bottom surface of the prism have the same shape and are connected, The sample holder according to claim 2.

4. The column is a plurality of columns provided in the cavity, The sample holder according to claim 2 or 3.

5. The plurality of columns are provided at four corners of the cavity, The sample holder according to claim 4.

6. The cavity has a shape of a frustum of a cone, wherein a bottom surface with a larger area of the frustum of the cone is on the side of the through hole, The sample holder according to claim 1.

7. The cavity has a shape combining the frustum of the cone and the prism, wherein a bottom surface with a smaller area of the frustum of the cone and an upper bottom surface of the prism have the same shape and are connected, The sample holder according to claim 6.

8. The prism is a quadrangular prism, The frustum of the cone is a frustum of a square pyramid, The sample holder according to claim 7.

9. The cavity is further provided with a prism of a conductor, wherein an upper bottom surface of the prism of the conductor is parallel to an upper surface of the pedestal, The sample holder according to any one of claims 6 to 8.

10. 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The PCB has a dielectric, a surface ground formed on the surface of the dielectric, a back surface ground formed on the back surface of the dielectric, a through hole penetrating from the surface ground to the back surface ground for storing the chip, and a conductor for connecting the surface ground and the back surface ground to the end face of the through hole. At least a part of the pedestal below the through hole has a cavity. The cavity has a support structure that supports the surface of the chip and is electrically connected to the pedestal. At least a part of the portion of the support structure that supports the chip is not parallel to the surface of the chip. Superconducting quantum computer.

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