Memory controller

Abstract

To suppress a decrease in access efficiency in a memory controller.SOLUTION: A memory controller 100 has: an access request holding section 110; an access request selection section 130; a command generation section 120; a refresh interval counter 140; and refresh counters 150, 151, 152. The access request selection section executes: calculation of total processing time for each multiple ranks; selection of multiple access requests to an access object rank as an access request group; and determination of processing order in the selected access request group. The command generation section executes: issuance of a first refresh command to a refresh object rank; and issuance of a second refresh command to an access object rank when a counter value corresponding to the access object rank becomes a second threshold or larger that is larger than a first threshold.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a memory controller.

Background Art

[0002] There exists a memory system including a DRAM (Dynamic Random Access Memory) having a plurality of ranks as a semiconductor memory. Such a semiconductor memory device needs to be refreshed periodically to hold data. The memory controller described in Patent Document 1 predicts the timing at which an access request is issued for each rank, and refreshes all of the plurality of banks included in each rank according to the predicted time until the request is issued, or refreshes some of the plurality of banks.

[0003] Also, the memory controller described in Patent Document 2 executes a refresh at an interval shorter than a predetermined interval for a rank without an access request among a plurality of ranks, and even for a rank with an access request, if the value of a counter provided corresponding to the rank is equal to or greater than a threshold value, interrupts the access to the rank and refreshes all of the plurality of banks included in the rank.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the memory controller described in Patent Document 1, when a method of refreshing some of a plurality of banks is frequently used, the number of issued refresh commands increases, and there is a problem that the command bus of the DRAM becomes congested and the access efficiency decreases.

[0006] Further, in the memory controller described in Patent Document 2, when there is an access request only to a specific rank over a long period of time, the access to the rank must be interrupted at any timing and a refresh must be executed. During that time, no access is executed to any rank, so similarly, there is a problem that the access efficiency decreases.

Means for Solving the Problems

[0007] The present disclosure can be realized in the following forms.

[0008] According to one embodiment of the present disclosure, in response to an access request from an arithmetic unit (210, 220, 230) to a semiconductor memory device (300) including a plurality of ranks (R0, R1, R2) each having a plurality of banks, a memory controller (100) that issues a command to the semiconductor memory device is provided. This memory controller includes an access request holding unit (110) that holds a plurality of the access requests and holds, for each of the plurality of access requests, an access target address, an access type, and a data length; an access request selection unit (130) that calculates an assumed processing time of the access request from the data length and determines a processing order of the access request according to the assumed processing time, the access target address, and the access type held in the access request holding unit; a command generation unit (120) that converts each into an access command which is a command for instructing an access of the access type indicated by the access request held in the access request holding unit and issues the access command to the semiconductor memory device according to the processing order; a refresh interval counter (140) that issues a notification for each refresh interval of the semiconductor memory device; and refresh counters (150, 151, 152) that hold a counter value held for each of the plurality of ranks, the counter value being incremented each time the notification is issued and decremented each time a refresh is executed. The access request selection unit calculates, for each of the plurality of ranks, a total processing time which is a sum of the assumed processing times of the plurality of access requests, selects, as an access request group, the plurality of access requests for an access target rank which is a rank in which the total processing time is greater than a refresh processing time which is a time required for a refresh, and determines a processing order in the selected access request group. The command generation unit issues the access command to the access target rank and, for a refresh target rank which is a rank other than the access target rank and in which the counter value corresponding to the rank is greater than a predetermined first threshold value,Issuing a first refresh command, which is a command for instructing to refresh all of the plurality of banks included in the refresh target rank, and when the counter value corresponding to the access target rank becomes equal to or greater than a second threshold value that is greater than the first threshold value, issuing a second refresh command, which is a command for instructing to refresh a part of the plurality of banks included in the access target rank, to the access target rank, and executing the above.

[0009] According to the memory controller of this embodiment, when the counter value corresponding to the access target rank becomes equal to or greater than the second threshold value, the issuance of the access command to the access target rank is interrupted, and a second refresh command, which is a command for instructing to refresh a part of the plurality of banks included in the access target rank, is issued to the access target rank. Therefore, access can be continued to the banks among the plurality of banks included in the access target rank that are not the target of the second refresh command, and a decrease in access efficiency can be suppressed. Further, since the second refresh command is issued only to the access target rank for which the corresponding counter value has become equal to or greater than the second threshold value, congestion of the command bus included in the semiconductor memory device can be suppressed, and a decrease in access efficiency can be suppressed.

Brief Description of Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0011] A. Embodiment: A-1. System Configuration: As shown in FIG. 1, the memory controller 100 is connected to the arithmetic units 210 to 230 via a bus 400. The arithmetic units 210 to 230 correspond to, for example, a CPU or a GPU (Graphics Processing Unit). Note that the memory controller 100 may be connected to one arithmetic unit instead of a plurality of arithmetic units. Further, the memory controller 100 is connected to the semiconductor memory device 300 via a bus 500. The semiconductor memory device 300 of the present embodiment is a DRAM including a plurality of ranks R0 to R2. Note that the number of ranks included in the semiconductor memory device 300 may be two or four or more. The semiconductor memory device 300 is configured to be able to read and write data for any storage unit designated by a command issued by the memory controller 100, and each of the ranks R0 to R2 includes a plurality of banks. The memory controller 100 issues a command to the semiconductor memory device 300 in response to an access request issued from the arithmetic units 210 to 230, and causes the semiconductor memory device 300 to execute data reading and writing. In the present embodiment, the commands issued by the memory controller 100 include a read command for instructing the semiconductor memory device 300 to read data, a write command for instructing data writing, and a refresh command for instructing refresh.

[0012] The memory controller 100 includes an access request holding unit 110, a command generation unit 120, an access request selection unit 130, a refresh interval counter 140, and refresh counters 150 to 152. The access request holding unit 110 holds access requests issued from the arithmetic units 210 to 230 and information regarding the access requests (hereinafter also referred to as "access request information"). The access request information includes the access target address of the held access request, the access type, and the data length. The "access target address" means the logical address of the access target data. The "access type" indicates whether the access request is a read access request indicating data readout from the semiconductor memory device 300 or a write access request indicating data writing to the semiconductor memory device 300 in this embodiment. The "data length" indicates the length of the data for which the read access request or the write access request requests reading and writing. When an access command described later is issued, the access request holding unit 110 deletes the access request on the assumption that the processing of the access request corresponding to the issued access command has been completed.

[0013] The command generation unit 120 converts the access target address of the access request held in the access request holding unit 110 into a physical address indicating the data storage area on the semiconductor memory device 300 in which the access target data is stored. In this embodiment, the command generation unit 120 determines the bits specifying the rank among the physical addresses by referring to the lower bits of the logical address. The "lower bits" mean a bit string that includes the least significant bit and in which a sufficient number of bits for specifying the rank are consecutive among the bit string indicating the logical address. In this way, by determining the bits specifying the rank among the physical addresses by referring to the lower bits of the logical address, it becomes easier to disperse the access destination, and it is possible to suppress the access requests from being concentrated on a specific rank.

[0014] In addition, the command generation unit 120 generates an access command including the converted physical address. The "access command" means a read command for instructing the reading of data indicated by a read access request and a write command for instructing the writing of data indicated by a write access request. The command generation unit 120 issues an access command to the semiconductor memory device 300 in accordance with the issue order of the command determined by the access request selection unit 130, which will be described later.

[0015] In addition, when causing the semiconductor memory device 300 to execute a refresh, the command generation unit 120 issues a refresh command to the semiconductor memory device 300. In the present embodiment, the command generation unit 120 issues an All Bank Refresh (hereinafter also referred to as "ABR") command and a Per Bank Refresh (hereinafter also referred to as "PBR") command as the refresh command. The ABR command means a command for instructing the execution of a process (hereinafter also referred to as "ABR process") of performing a refresh for all of the plurality of banks included in each rank for ranks R0 to R2, and corresponds to the "first refresh command" in the present disclosure. The PBR command means a command for instructing the execution of a process (hereinafter also referred to as "PBR process") of performing a refresh by designating a part of the plurality of banks included in each rank for ranks R0 to R2, and corresponds to the "second refresh command" in the present disclosure.

[0016] The access request selection unit 130 executes an access request selection process, which will be described later, and determines the processing order of the access requests held by the access request holding unit 110. The processing order of the access requests means, in other words, the issue order of the access commands.

[0017] The refresh interval counter 140 issues a notification to the refresh counters 150 to 152 every refresh interval. The "refresh interval" means the time obtained by dividing the longest time allowed for performing a refresh on all rows, which is defined by the standard of the semiconductor memory device 300, by the number of rows constituting a bank.

[0018] The refresh counters 150 to 152 respectively correspond to the ranks R0 to R2 provided in the semiconductor memory device 300, execute the count process described later, and hold the counter values Cnt0 to Cnt2 respectively. The counter values Cnt0 to Cnt2 are represented by positive or negative integers.

[0019] A-2. Access Request Selection Process: The access request selection process shown in FIGS. 2 and 3 will be described. The access request selection unit 130 executes the access request selection process every time a refresh is executed in any one of the ranks during the operation of the memory controller 100. As a result, every time a refresh is executed in any one of the ranks, the issue order of commands is updated. Note that the access request selection unit 130 may execute the access request selection process at a predetermined interval.

[0020] In step S110 shown in FIG. 2, the access request selection unit 130 determines whether there is an access request held by the access request holding unit 110. If it is determined that there is no access request held by the access request holding unit 110 (step S110: No), the access request selection unit 130 waits until an access request is held by the access request holding unit 110.

[0021] If it is determined that there is an access request held by the access request holding unit 110 (step S110: Yes), in step S120, the access request selection unit 130 acquires the access request information held by the access request holding unit 110.

[0022] In step S130, the access request selection unit 130 calculates the assumed processing time for each access request. The "assumed processing time" means the time assumed to be required for processing the access request, which is calculated based on the data length among the acquired access request information.

[0023] In step S140, the access request selection unit 130 calculates the total processing time for each access request group candidate. The "access request group candidate" means a plurality of access requests that specify the same rank, and for each bank, a plurality of access requests that specify the same row address. Also, the "total processing time" means the sum of the assumed processing times of each access request forming the access request group candidate.

[0024] In step S150, the access request selection unit 130 determines an access request group for each rank. The "access request group" means the access request group candidate with the maximum total processing time among a plurality of access request group candidates.

[0025] In step S160 shown in FIG. 3, the access request selection unit 130 determines whether there is a rank corresponding to the access target rank among the ranks targeted by the access request group. The "access target rank" means a rank for which the total processing time of the access request group to that rank is longer than the time required for refresh (hereinafter also referred to as "refresh processing time").

[0026] When it is determined that there is an access target rank (step S160: Yes), in step S170, the access request selection unit 130 determines the order of issuing access commands so that the access request group to the access target rank is processed next, and ends the access request selection process. Note that the access request selection unit 130 determines the processing order of the access requests included in the access request group so as to improve access efficiency, such as processing command requests of the same access type continuously. Also, when there are multiple ranks corresponding to the access target rank, the access request selection unit 130 determines the order of issuing access commands so as to preferentially process the access request group including the access request with a higher priority preset by the arithmetic units 210 to 230. Note that the priority may be set so that the priority increases as the elapsed time since the access request was issued becomes longer.

[0027] When it is determined that there is no access target rank (step S160: No), in step S162, the access request selection unit 130 determines whether there is a combination of a plurality of ranks corresponding to the access target rank group. The "access target rank group" means a combination of a plurality of ranks whose total processing time of the access request group to each rank is longer than the refresh processing time.

[0028] When it is determined that there is an access target rank group (step S162: Yes), in step S172, the access request selection unit 130 determines the order of issuing access commands so that the access request group to the access target rank group is processed next, and ends the access request selection process. When there are multiple combinations of a plurality of ranks corresponding to the access target rank group, similar to the case where there are multiple ranks corresponding to the access target rank described above, the order of issuing access commands is determined so as to preferentially process the access request group including the access request with a higher priority set.

[0029] When it is determined that there is no access target rank group (step S162: No), in step S174, the access request selection unit 130 determines the issuance order of access commands so that the access request group including the access requests with the set high priority is processed next, and ends the access request selection process.

[0030] A-3. Counting Process: The counting process shown in FIG. 4 will be described. Since the counting processes executed in the refresh counters 150 to 152 are the same, the counting process in the refresh counter 150 provided corresponding to the rank R0 will be described as an example. When the refresh counter 150 receives a notification issued from the refresh interval counter 140 (step S210: Yes), in step S220, 1 is added to the counter value Cnt0.

[0031] On the other hand, when a refresh is executed in the rank R0 (step S212: Yes), the refresh counter 150 subtracts 1 from the counter value Cnt0 in step S222. Here, "executing a refresh" means that either the ABR process is executed once in the rank R0 or the PBR process is executed as many times as the number of banks that the rank R0 has in the rank R0. In this way, the refresh counter 150 executes the addition process executed every time a notification is issued from the refresh interval counter 140 and the subtraction process executed every time a refresh in the corresponding rank R0 in parallel, and continuously executes during the operation of the memory controller 100.

[0032] A-4. Memory Access Process: The memory controller 100 executes the memory access process shown in FIG. 5 in response to access requests issued from the arithmetic units 210 to 230, and issues a refresh command and an access command. The memory access process is executed in parallel with the above-described access request selection process and counting process.

[0033] As shown in FIG. 5, the memory controller 100 executes the refresh processes (steps S300, S400, S500) in each of ranks R0 to R2 and the access command issuance process (step S600) in parallel with each other. The memory controller 100 continuously executes each refresh process and the access command issuance process during the operation of the memory controller 100.

[0034] The refresh process shown in FIG. 6 will be described. Since the refresh processes executed in ranks R0 to R2 are the same, FIG. 6 illustrates the refresh process in rank R0 as an example. In step S302, the command generation unit 120 determines whether there is an access plan to or an ongoing access to rank R0. In other words, the command generation unit 120 determines whether rank R0 is a rank included in the access target rank or the access target rank group. Here, "access" means a state in which the issuance of an access command is continuously performed.

[0035] When it is determined that there is no access plan to or ongoing access to rank R0 (step S302: No), in step S304, the command generation unit 120 determines whether the counter value Cnt0 of the refresh counter 150 is equal to or greater than the threshold value ThA. The threshold value ThA is the maximum number defined by the standard of the semiconductor memory device 300, and is set according to the maximum number of times that the semiconductor memory device 300 can execute a refresh prior to the refresh interval. The semiconductor memory device 300 of the present embodiment can execute a refresh up to 8 times in advance, and the threshold value ThA is set to -8. Note that the threshold value ThA corresponds to the "first threshold value" in the present disclosure.

[0036] When it is determined that the counter value Cnt0 is less than the threshold ThA (step S304: No), the command generation unit 120 executes step S302 again. When it is determined that the counter value Cnt0 is greater than or equal to the threshold ThA (step S304: Yes), in step S306, the command generation unit 120 issues an ABR command and executes the ABR process for rank R0. When executing the process of step S306, if other ranks are also in a state where the ABR process can be executed, in this embodiment, the command generation unit 120 executes the ABR process in order from the rank with the larger counter value of the refresh counter corresponding to each rank. Note that a rank that is neither a rank included in the access target rank group nor an access target rank and has a counter value greater than the threshold ThA corresponds to the "refresh target rank" in the present disclosure.

[0037] When it is determined that access is scheduled or in progress to rank R0 (step S302: Yes), in step S308, the command generation unit 120 determines whether the counter value Cnt0 is greater than or equal to the threshold ThB. When it is determined that the counter value Cnt0 is less than the threshold ThB (step S308: No), step S302 described above is executed again. An arbitrary value of 0 or more is set for the threshold ThB. The threshold ThB is greater than the above-described threshold ThA and less than the threshold ThC described later. The threshold ThB corresponds to the "third threshold" in the present disclosure.

[0038] When it is determined that the counter value Cnt0 is greater than or equal to the threshold ThB (step S308: Yes), in step S310, the command generation unit 120 determines whether there is an accessible rank. The "accessible rank" means a rank other than rank R0 that is the access target rank, for which the refresh has already been completed, and for which there is an access request. In this embodiment, the command generation unit 120 determines whether there is an accessible rank by using the access request information held in the access request holding unit 110.

[0039] When it is determined that there is an accessible rank (step S310: Yes), in step S312, the command generation unit 120 interrupts the access to rank R0, in other words, interrupts the issuance of the access command to rank R0. Also, in step S314, the command generation unit 120 updates the command issuance order so that the access request to the accessible rank is processed next, and executes step S306 described above.

[0040] On the other hand, when it is determined that there is no accessible rank (step S310: No), in step S316, the command generation unit 120 determines whether the counter value Cnt0 is greater than or equal to the threshold value ThC. An arbitrary value greater than the threshold value ThB is set for the threshold value ThC. The threshold value ThC corresponds to the "second threshold value" in the present disclosure. When it is determined that the counter value Cnt0 is less than the threshold value ThC (step S316: No), step S310 is executed again.

[0041] When the counter value Cnt0 is greater than or equal to the threshold value ThB and less than the threshold value ThC, although the necessity of refreshing rank R0 is increasing, it can be said that there is little necessity to execute the refresh of rank R0 until the access to rank R0 is interrupted in a situation where there is no other accessible rank. Therefore, in the present embodiment, when the counter value Cnt0 is greater than or equal to the threshold value ThB and less than the threshold value ThC and there is no accessible rank, the access to rank R0 is continued until an accessible rank appears, and the refresh of rank R0 is not executed. Thereby, it is possible to suppress a situation where access is not executed to any rank, and to suppress a decrease in access efficiency.

[0042] When it is determined that the counter value Cnt0 is equal to or greater than the threshold value ThC (step S316: Yes), in step S318, the command generation unit 120 issues a PBR command and executes PBR processing. More specifically, the command generation unit 120 issues a PBR command that designates one of the plurality of banks included in rank R0 in a predetermined order. In the present embodiment, when accessing the bank targeted by the PBR command when issuing the PBR command, the command generation unit 120 temporarily interrupts the access as described later and executes the PBR processing for the bank. After the completion of the PBR processing for the bank, the command generation unit 120 may resume the access to the bank.

[0043] In step S320, the command generation unit 120 determines whether or not PBR processing has been executed in all the banks included in rank R0. In the present embodiment, the command generation unit 120 adds a count each time it issues a PBR command in a predetermined order, and when the count reaches a value preset according to the number of banks included in rank R0, it is determined that PBR processing has been executed in all the banks.

[0044] When it is determined that PBR processing has not been executed in all the banks (step S320: No), step S318 described above is executed again. That is, the command generation unit 120 sequentially issues PBR commands that designate each of the plurality of banks included in rank R0. When it is determined that PBR processing has been executed in all the banks (step S320: Yes), step S302 described above is executed again.

[0045] As described above, in this embodiment, when the counter value Cnt0 becomes greater than the threshold ThC, the access to rank R0 is interrupted regardless of the presence or absence of an accessible rank, and the PBR process for rank R0 is executed. Therefore, when the counter value Cnt0 becomes greater than the threshold ThC, that is, when there is a possibility that the maximum time allowed as the refresh interval has elapsed, the access to rank R0 can be interrupted to forcibly execute the refresh. Even for the rank being accessed, the refresh can be surely executed, and a decrease in the data retention stability of the semiconductor memory device 300 can be suppressed. Further, since the PBR process is sequentially executed for each bank, unlike the case of executing the ABR process for all banks, the access to the bank for which the PBR process has not been executed can be continued, and a decrease in the access efficiency can be suppressed.

[0046] The access command issuance process shown in FIG. 7 will be described. In step S610, the command generation unit 120 acquires the issuance order of the access commands determined by the above-described access request selection process.

[0047] In step S620, the command generation unit 120 determines whether or not the above-described PBR process is being executed in the bank to be accessed. If it is determined that the PBR process is being executed (step S620: Yes), the command generation unit 120 waits for the issuance of the access command for the bank. If it is determined that the PBR process is not being executed (step S620: No), in step S630, the command generation unit 120 issues an access command to the bank. Thereafter, the command generation unit 120 executes step S610 again. As described above, in this embodiment, the command generation unit 120 sequentially issues access commands in accordance with the issuance order of the access commands.

[0048] According to the memory controller 100 of the embodiment described above, when the counter value corresponding to the access target rank becomes equal to or greater than the threshold value ThC, the issuance of the access command to the access target rank is interrupted, a PBR command is issued to the access target rank, and the PBR process is executed. Therefore, among the plurality of banks included in the access target rank, access can be continued to the banks that are not the targets of the PBR process, and a decrease in access efficiency can be suppressed. Further, since the PBR command is issued only to the access target rank for which the corresponding counter value Cnt0 has become equal to or greater than the threshold value ThC, congestion of the command bus included in the semiconductor memory device 300 can be suppressed, and a decrease in access efficiency can be suppressed.

[0049] Further, when the counter value of the access target rank becomes equal to or greater than the threshold value ThB and there is an accessible rank in addition to the said rank, the memory controller 100 interrupts the issuance of the access command to the rank being accessed, issues a refresh command, and issues an access command to the accessible rank. Therefore, as for the entire memory system, refreshing can be executed without stopping the issuance of access commands, and a decrease in access efficiency can be suppressed.

[0050] Further, the memory controller 100 selects, as an access request group, a plurality of access requests that specify the same row address for each bank. Therefore, the number of changes in the row address can be suppressed, and a decrease in access efficiency can be further suppressed.

[0051] Further, when there are a plurality of ranks to be refreshed, the memory controller 100 issues ABR commands in order from the rank with the largest counter value. Therefore, the ABR process can be preferentially executed in order from the rank with a higher necessity for refreshing, and a decrease in the stability of data retention in the semiconductor memory device 300 can be suppressed.

[0052] Further, when there are a plurality of access target ranks, the memory controller 100 processes them in order from the rank including the access request with a higher set priority. Therefore, access requests can be processed efficiently.

[0053] Also, when there is no access target rank, the memory controller 100 issues an access command to the access target rank group, and while issuing an access command to the access target rank group, it issues an ABR command to another rank and executes ABR processing. Therefore, even when issuing an access command to the access target rank group, it is possible to suppress a decrease in access efficiency in the same manner as when issuing an access command to the access target rank.

[0054] Also, when converting from a logical address to a physical address, the memory controller 100 determines the rank address among the physical addresses by referring to the lower bits of the logical address, making it easier to disperse the access destination and suppressing the concentration of access requests to a specific rank.

[0055] B. Other Embodiments: (B1) In the above embodiment, when there are a plurality of ranks to be refreshed, the command generation unit 120 issues ABR commands in order from the rank with the largest counter value, but the present disclosure is not limited to this. The command generation unit 120 may issue ABR commands in an arbitrary order regardless of the counter value.

[0056] (B2) In the above embodiment, the access request selection unit 130 selects, as an access request group, a plurality of access requests that specify the same row address for each bank, but the present disclosure is not limited to this. The access request selection unit 130 may select, as an access request group, a plurality of access requests that specify different row addresses for each bank. When selecting access requests in this way, for example, when there are sufficient access requests to other banks, it is preferable to process the access requests in an order that can suppress a decrease in access efficiency, such as executing the processing of access requests to other banks during the processing of two access requests with different specified row addresses.

[0057] (B3) In the above embodiment, when there are multiple access target ranks or a group of access target ranks, the access request selection unit 130 determines the order of issuing access commands so as to preferentially process an access request group including an access request with a higher set priority. However, the present disclosure is not limited to this. The access request selection unit 130 may process the access request group in any order regardless of the priority.

[0058] (B4) In the above embodiment, when converting the access target address from a logical address to a physical address, the command generation unit 120 determines the bit specifying the rank address among the physical addresses by referring to the lower bits of the logical address. However, the present disclosure is not limited to this. The command generation unit 120 may determine the bit specifying the rank address among the physical addresses by referring to the upper bits of the logical address.

[0059] (B5) In the above embodiment, when issuing a PBR command, if access to the bank targeted by the PBR command is scheduled, the command generation unit 120 temporarily interrupts the access and executes the PBR process for the bank. However, the present disclosure is not limited to this. When issuing a PBR command, if access to the bank targeted by the PBR command is scheduled, the command generation unit 120 may postpone the PBR process for the bank and first execute the PBR process for other banks where no access is scheduled. According to such a form, when the target bank is being accessed during the execution of the PBR process, the PBR process for other banks is first executed, so the frequency of access interruption due to the PBR process can be suppressed, and a decrease in access efficiency can be further suppressed.

[0060] More specifically, for example, the command generation unit 120 may use, as a PBR process completion flag, a bit string having a number of digits corresponding to the number of a plurality of banks provided in each rank, where each digit corresponds to each of the plurality of banks, to manage the execution status of the PBR process for each bank in each rank. The command generation unit 120 sequentially refers to the digits from the left side of the bit string. When the referred digit is 0 and the bank corresponding to the digit is not being accessed, the command generation unit 120 executes the PBR process for the bank and changes the digit corresponding to the bank to 1. When the referred digit is 0 and the bank corresponding to the digit is being accessed, the command generation unit 120 refers to other digits. If there are other digits that are 0, the command generation unit 120 executes the PBR process for the other banks corresponding to the other digits. When there are no other digits that are 0, in other words, when the bank being accessed is the last bank for which the PBR process has not been completed, the command generation unit 120 interrupts the access to the bank and executes the PBR process for the bank. When all the digits of the bit string become 1, the command generation unit 120 determines that the PBR processes for all the banks have been completed.

[0061] (B6) In the above embodiment, the command generation unit 120 executes steps S308 to S314 in the refresh process shown in FIG. 6, but the present disclosure is not limited thereto. The command generation unit 120 may not execute steps S308 to S314 in the refresh process. That is, when it is planned to access or accessing the rank R0, the determination in step S316 may be executed. Even in such a form, when it is planned to access or accessing the rank R0 and the counter value Cnt0 is equal to or greater than the threshold value ThC, the PBR process for each bank of the rank R0 can be executed, and the same effect as the above embodiment can be obtained. In such a form, when the counter value Cnt0 is less than the threshold value ThC (step S316: No), step S302 may be executed again.

[0062] The present disclosure is not limited to the above-described embodiments, and can be implemented in various configurations without departing from the spirit thereof. For example, the technical features in each embodiment corresponding to the technical features in the forms described in the summary of the invention can be appropriately replaced or combined in order to solve some or all of the above-described problems, or to achieve some or all of the above-described effects. Further, if the technical feature is not described as essential in this specification, it can be appropriately deleted.

[0063] The memory controller 100 and its method described in the present disclosure may be implemented by a dedicated computer provided by configuring a processor and a memory programmed to execute one or more functions embodied by a computer program. Alternatively, the memory controller 100 and its method described in the present disclosure may be implemented by a dedicated computer provided by configuring a processor with one or more dedicated hardware logic circuits. Or, the memory controller 100 and its method described in the present disclosure may be implemented by one or more dedicated computers configured by a combination of a processor and a memory programmed to execute one or more functions and a processor configured by one or more hardware logic circuits. Further, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions to be executed by a computer.

Description of Reference Numerals

[0064] R0, R1, R2... ranks, 100... memory controller, 110... access request holding unit, 120... command generation unit, 130... access request selection unit, 140... refresh interval counter, 150, 151, 152... refresh counters, 210... arithmetic unit, 300... semiconductor memory device

Claims

1. A memory controller (100) that issues a command to a semiconductor memory device (300) including a plurality of ranks (R0, R1, R2), each having a plurality of banks, in response to an access request from a computing device (210, 220, 230), an access request holding unit (110) that holds a plurality of the access requests and holds, for each of the plurality of access requests, an access target address, an access type, and a data length; an access request selection unit (130) that calculates an assumed processing time of the access request from the data length and determines a processing order of the access request according to the assumed processing time, the access target address, and the access type held in the access request holding unit; a command generation unit (120) that converts each into an access command that is a command instructing an access of the access type indicated by the access request held in the access request holding unit and issues the access command to the semiconductor memory device according to the processing order; a refresh interval counter (140) that issues a notification for each refresh interval of the semiconductor memory device; a refresh counter (150, 151, 152) that holds a counter value held for each of the plurality of ranks, the counter value being incremented each time the notification is issued and decremented each time a refresh is executed; comprising: The access request selection unit: calculates, for each of the plurality of ranks, a total processing time that is a sum of the assumed processing times of the plurality of access requests; selects, as an access request group, the plurality of access requests for an access target rank that is a rank in which the total processing time is greater than a refresh processing time that is a time required for a refresh; determines a processing order in the selected access request group; and executes; The command generation unit: issues the access command to the access target rank; issues a first refresh command, which is a command instructing to refresh all of the plurality of banks of the refresh target rank, to a refresh target rank that is a rank other than the access target rank and in which a counter value corresponding to the rank is greater than a predetermined first threshold value; When the counter value corresponding to the access target rank becomes equal to or greater than a second threshold value that is greater than the first threshold value, issue a second refresh command that is a command for instructing to refresh some of the plurality of banks included in the access target rank with respect to the access target rank. Execute Memory controller.

2. The memory controller according to claim 1, When the counter value corresponding to the access target rank becomes equal to or greater than a third threshold value that is greater than the first threshold value and less than the second threshold value, and there is an access request for a rank other than the access target rank and there is an accessible rank that is a rank for which a refresh has already been completed, The command generation unit Interrupt the issuance of the access command for the access target rank, Issue the first refresh command for the access target rank, Issue the access command for the accessible rank, Execute Memory controller.

3. The memory controller according to claim 1 or claim 2, In the access request group, the access requests that specify each of the banks specify a common row address. Memory controller.

4. The memory controller according to claim 1 or claim 2, When there are a plurality of ranks to be refreshed, the command generation unit issues the first refresh command in order from the rank with the larger corresponding counter value. Memory controller.

5. The memory controller according to claim 1 or claim 2, When there are a plurality of access target ranks, the command generation unit issues the access commands in order from the rank including the access request with the higher set priority. Memory controller.

6. The memory controller according to claim 5, The priority is preset by the arithmetic unit. Memory controller.

7. The memory controller according to claim 5, The access request selection unit sets the priority so that the priority increases as the elapsed time from the issuance of the access request increases. Memory controller.

8. The memory controller according to claim 1 or claim 2, When the semiconductor memory device includes three or more ranks and there is no rank corresponding to the access target rank, the command generation unit issues the access command to an access target rank group that is a combination of a plurality of ranks whose total processing time of each rank is greater than the refresh processing time, and issues the first refresh command to ranks other than the access target rank group and having a counter value greater than the first threshold value. Memory controller.

9. The memory controller according to claim 1 or claim 2, wherein, when converting a logical address to a physical address, the command generation unit determines a rank address by referring to lower bits of the logical address. Memory controller.

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