Storage apparatus and control method for storage apparatus

Abstract

To assure reliability and availability of data while retaining performance of a storage apparatus.SOLUTION: A storage apparatus comprises: a first control device having a first memory; a second control device having a second memory; and a memory module having a third memory. The first memory and the second memory store drive control information including correspondence between a logical address and a physical address, cache data in data I / O processing, and cache control information including correspondence between a logical address of the cache data and a cache address of the cache data. The third memory stores the drive control information, dirty data of the cache data in the first memory, dirty data of the cache data in the second memory, and the cache control information. Even in a case where the control device or the memory module is blocked or the like, the dirty data is set to be redundantly stored in each of different apparatuses.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a storage device and a control method for a storage device.

Background Art

[0002] In recent years, against the backdrop of the expansion of cloud utilization accompanying the progress of IT technology and the promotion of DX (Digital Transformation), storage devices operating in DC (Data Center), IDC (Internet Data Center), etc. are required to have even higher reliability and availability than before, and various technologies for enhancing reliability and availability have been proposed.

[0003] For example, Patent Document 1 describes a data access system configured to solve problems such as excessive consumption of the CPU performance of a control system functioning as an information providing side among two control systems and a decrease in the reliability of the entire system. The data access system includes two memory sharing devices and two control devices connected to the memory sharing devices. The two memory sharing devices constitute a memory sharing resource pool in the data access system. Each control device corresponds to each memory sharing device, and when one of at least two control devices reads data in the memory sharing resource pool, the control device reads the required data in the memory sharing resource pool by using the memory sharing device corresponding to the control device. Each memory sharing device belongs to the same memory sharing resource pool and has a plurality of memory units. The memory units receive unified addressing throughout the memory sharing resource pool. Each memory sharing device processes a memory access request received from the control device and reads data from the memory unit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] A storage device generally has a redundant configuration of a control device that receives data I / O requests sent from a host device and performs data input / output to a storage drive such as an SSD (Solid State Drive) for the purpose of ensuring reliability and availability. In addition, the storage device improves performance by placing some data such as frequently accessed data in a high-speed memory such as DRAM (Dynamic Random Access Memory), and improves availability by placing the same data in the memories provided in each control device for redundancy.

[0006] However, in a storage device having such a redundant configuration, there is a problem that redundancy is impaired and availability is reduced when one of the control devices shifts to a power-saving mode or shuts down. In addition, when one of the control devices shuts down, the operation is usually switched to directly writing data to the storage drive, which reduces the performance of the storage device.

[0007] Patent Document 1 describes that a memory unit receives unified addressing in the entire memory shared resource pool. However, a mechanism for ensuring data reliability and availability while maintaining the performance of the storage device when one of the control devices shifts to a power-saving mode or shuts down is not disclosed.

[0008] An object of the present invention is to provide a storage device and a control method for a storage device that can maintain the performance of the storage device while ensuring data reliability and availability. MEANS FOR SOLVING THE PROBLEMS

[0009] One aspect of the present invention for achieving the above object is a storage device that is communicably connected to other devices and performs data I / O processing on a storage device in response to a data I / O request received from the other devices, comprising: two control devices communicably connected; and three memories that can be directly or indirectly accessed by each of the two control devices. The first memory stores drive control information, which is information for managing the correspondence between a logical address, which is information indicating the location of data handled by the other device in the data I / O processing, and a physical address, which is information indicating the location of the data in the storage device; first cache data in the data I / O processing; the logical address of the first cache data; and first cache control information, which is information for managing the correspondence between the logical address of the first cache data and a cache address, which is information indicating the location of the first cache data in the first memory. The second memory stores drive control information; second cache data in the data I / O processing; the logical address of the second cache data; and second cache control information, which is information for managing the correspondence between the logical address of the second cache data and a cache address, which is information indicating the location of the second cache data in the first memory. The third memory stores drive control information; first dirty data, which is dirty data of the first cache data; second dirty data, which is dirty data of the second cache data; the logical address of the first dirty data or the second dirty data; and third cache control information, which is information for managing the correspondence between the logical address of the first dirty data or the second dirty data and a cache address, which is information indicating the location of the first dirty data or the second dirty data in the third memory. The data I / O processing is performed while redundantly storing the first dirty data and the second dirty data in a plurality of the memories. When stopping the function of any one of the memories, the first dirty data and the second dirty data are transferred between the memories so that the first dirty data and the second dirty data are redundantly stored in each of a plurality of the memories other than the memory whose function is stopped. After stopping the function of the memory,While redundantly storing the first dirty data and the second dirty data in each of the plurality of memories, perform the data I / O process.

[0010] Problems, configurations, and effects other than those described above will be clarified by the description of the embodiments for carrying out the following invention.

Advantages of the Invention

[0011] According to the present invention, it is possible to ensure the reliability and availability of data while maintaining the performance of the storage device.

Brief Description of the Drawings

[0012]

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Figure 10A

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Modes for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the following embodiments are merely examples for explaining the present invention, and for the sake of clarity of explanation, appropriate omissions and simplifications have been made. The present invention can be implemented in various other forms. Unless otherwise particularly limited, each component may be singular or plural.

[0014] In the following description, when there are a plurality of components having common functions, in order to distinguish each component, different subscripts may be attached to the same reference numeral for explanation. Also, when it is not necessary to particularly distinguish these plurality of components, the subscripts may be omitted for explanation.

[0015] Also, when explaining each component separately, expressions such as "identification information", "identifier", and "ID" are used, but these can be mutually replaced.

[0016] Also, hereinafter, as examples of various information, explanations may be given using expressions such as "information" and "data", but various information may be represented by other data structures ("table", "list", etc.).

[0017] In the following, there may be an explanation of the processing performed by various devices functioning as information processing devices (computers, computers) when executing a program. The above information processing device executes a program by a processor (for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit)), and performs the processing defined by the program while using a storage resource (for example, a memory) and an interface. Therefore, the subject of the processing performed by executing the program may be the processor. Similarly, the subject of the processing performed by executing the program may be a control device (controller), a device, a system, a computer, or a node having a processor.

[0018] The subject of the processing performed by executing the program only needs to function as at least an arithmetic unit, and may include, for example, a dedicated circuit that performs specific processing such as an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a CPLD (Complex Programmable Logic Device).

[0019] Also, in the following description, input / output may be denoted as "I / O" (Input / Output), and an interface may be denoted as "I / F" (InterFace).

[0020] Also, in the following description, the character "S" attached before a symbol means a processing step.

[0021] FIG. 1 shows an example of a storage system 1 having a redundant configuration. The illustrated storage system 1 includes a host device 2 (also referred to as a "higher-level device", a "server device", an "external device", etc.), a communication system 5, and a storage device 10.

[0022] The host device 2 is communicatively connected to the storage device 10 via a communication system 5. The communication system 5 is, for example, a storage area network (SAN), a local area network (LAN), a wide area network (WAN), the Internet, etc.

[0023] The host device 2 is an information processing device (computer) that uses the memory area provided by the storage device 10 via the communication system 5 as a data storage location, and is, for example, a personal computer, office computer, mainframe, smartphone, tablet, etc.

[0024] The storage device 10 has two control devices 100 (control device 100A, control device 100B) and a storage device 17. The two control devices 100 (control device 100A, control device 100B) and the storage device 17 are communicatively connected via, for example, a high-speed serial communication I / F (SATA (Serial ATA) or the like), a LAN, a SAN, or the like.

[0025] When accessing the above storage area, the host device 2 sends an I / O request (a data write request requesting writing of data to the storage device 17, or a data read request requesting reading of data from the storage device 17) to the storage device 10.

[0026] Which of the two control devices 100 (control device 100A, control device 100B) receives a data I / O request sent from the host device 2 and sent to the storage device 10 via the communication system 5 is determined, for example, by the configuration or settings of the host device 2 or the communication system 5.

[0027] The two control devices 100 (control device 100A, control device 100B) are provided in the housing (case, rack, etc.) of the storage device 10, for example, as independent boards (circuit boards) that can be attached and detached.

[0028] The control device 100A and the control device 100B still have the same basic configuration, and the elements with the same name in each have the same function. Therefore, in order to avoid duplicate explanations, hereinafter, when explaining the common configuration, in principle, only the control device 100A will be explained.

[0029] The control device 100A includes a processor 110A, a memory 120A, a communication I / F 130A, and a drive I / F 140A. These are communicably connected to each other via an internal bus capable of high-speed communication (for example, a PCIe (Peripheral Component Interconnect-Express) bus, etc.). Further, the processor 110A is communicably connected to the processor 110B of the control device 100B via the internal bus 30 (such as a PCIe bus).

[0030] The processor 110A is configured using an arithmetic core, a cache memory, DMA (Direct Memory Access), etc. The processor 110A performs processing related to data transfer performed among the communication I / F 130A, the memory 120A, and the drive I / F 140A in response to an I / O request sent from the communication I / F 130A. For example, the processor 110A transfers data (data read from the storage device 17 (hereinafter referred to as "read data") and data written to the storage device 17 (hereinafter referred to as "write data")) between the communication I / F 130A and the drive I / F 140A via the memory 120A. Further, the processor 110A performs data staging (reading data from the storage device 17 to the memory 120A) to the memory 120A and destaging (writing data from the memory 120A to the storage device 17) of the data stored in the memory 120A.

[0031] The communication I / F 130A communicates with the host device 2 via the communication system 5. The communication I / F 130A receives the data I / O requests sent from the host device 2, and transfers the received I / O requests and the data (e.g., write data) sent together with the I / O requests to the processor 110A. Also, the communication I / F 130A receives the data (e.g., read data read from the storage device 17) sent from the processor 110A, and transmits the received data to the host device 2.

[0032] In addition, the communication I / F 130A mutually converts the communication protocol used on the communication system 5 side and the communication protocol used on the control device 100A side in the communication between the storage device 10 and the host device 2 via the communication system 5. The communication I / F 130A is also referred to as an "HBA (Host Bus Adaptor)". Examples of the communication protocol used on the communication system 5 side include Fibre Channel, Ethernet (registered trademark), iSCSI (Internet Small Computer System Interface), etc.

[0033] The memory 120A is configured using a storage element capable of high-speed access compared to semiconductor storage devices such as DRAM (Dynamic Random Access Memory) (SSD (Solid State Drive)) and hard disk drives (HDD (Hard Disk Drive)). The memory 120A stores, for example, programs and data used to implement the functions of the storage device 10. Also, the memory 120A functions as a cache that enables a faster response than accessing the storage device 17 by temporarily storing the data of the storage device 17. Hereinafter, the temporary data written to the memory 120A is referred to as "cache data".

[0034] The drive I / F 140A performs processing related to data transfer with the storage device 17 when reading data from the storage device 17 to the memory 120A or writing data from the memory 120A to the storage device 17.

[0035] The storage device 17 has one or more storage drives 171 which are recording media providing a physical storage area. The storage drive 171 is, for example, a semiconductor storage device (SSD) or a hard disk drive (HDD). The storage device 17 may be housed in the same housing as the storage device 10, or may be housed in a housing separate from the housing in which the storage device 10 is housed. The storage device 10 provides the host device 2 with the above storage area as a logical storage area organized using RAID (Redundant Array of Inexpensive Disks) technology or the like.

[0036] In addition to the above configuration, the storage device 10 may include, for example, an information processing device (computer) (hereinafter referred to as a "management device") that monitors, controls, sets, etc. each component of the storage device 10. The management device includes a processor, a storage device (memory, SSD, etc.), a recording medium reading device (a device that reads data from a non-temporary storage medium), a communication device, and input / output devices (keyboard, mouse, touch panel, display, speaker, etc.). The management device is communicably connected to each of the above components via communication means such as a LAN or an internal bus (PCIe, etc.). Also, the management device may be connected to the storage device 10 via, for example, a service processor (SVP: SerVice Processor) provided in the storage device 10. The management device transfers (writes, uploads, etc.) programs and data acquired via the communication device and the recording medium reading device to the components of the storage device 10.

[0037] The memory 120A of the control device 100A stores each piece of information (data) of the OS / app 121A, drive control information 122A, cache control information 123A, and cache data 124A.

[0038] The cache data 124A is distinguished into clean data and dirty data. The clean data is the data among the cache data 124A for which the writing to the storage device 17 has been completed and the consistency with the corresponding data stored in the storage device 17 is guaranteed. On the other hand, the dirty data is the data among the cache data 124A for which the writing to the storage device 17 has not been completed or the data for which the consistency with the corresponding data stored in the storage device 17 is not guaranteed (data whose content is not synchronized). For example, the data that has been stored as cache data 124A in the memory 120A due to a data write request (including the case where the content of existing data is changed (updated)) but for which the writing to the storage device 17 has not been completed (the update has not been completed) becomes dirty data. In the same figure, the dirty data is shown as "dirty data 125A".

[0039] The OS / app 121A is a program for realizing an operating system (hereinafter also referred to as "OS") and various applications (hereinafter also referred to as "apps"), a program for realizing a device driver, and the like.

[0040] The OS / app 121A realizes, for example, a function of shutting down (stopping the data I / O processing function) the control device 100 that has detected a failure or a sign of a failure among the control devices 100 (control device 100A, control device 100B). Note that the control device 100 in the shutdown state does not receive a data I / O request from the host device 2.

[0041] Also, the OS / app 121A realizes, for example, a function of detecting a failure or a sign of a failure of the memory module 200.

[0042] Also, the OS / app 121A realizes a function (hereinafter referred to as "power-saving function") of shifting one of the control devices 100 (control device 100A and control device 100B) from the normal operating state (hereinafter referred to as "normal mode") to an operating state with lower power consumption (hereinafter referred to as "power-saving mode") than in the normal mode during a period when the load on the storage device 10 is low, such as a period when the number of received data I / O requests from the host device 2 is small. The control device 100 operating in the power-saving mode stops the data I / O processing function as in the case of congestion.

[0043] The drive control information 122A is information used when the processor 110A accesses the storage area provided by the storage device 17. The drive control information 122A includes information (hereinafter referred to as "logical address") indicating the location of write data and read data specified in the data I / O request of the host device 2, and information (hereinafter referred to as "physical address") specifying the storage area of the storage device where these data are stored, in association with each other. The above logical address is, for example, a directory name (folder name), a file name, or a URL (Uniform Resource Locator).

[0044] The cache control information 123A is information used when the processor 110A accesses the cache data 124A stored in the memory 120A. The cache control information 123A includes information associating the above-mentioned logical address with information (hereinafter referred to as "cache address") specifying the storage area of the memory 120A, which is the storage destination of the cache data.

[0045] As shown in the figure, the memory 120B of the control device 100B stores each information (data) of the OS / app 121B, the drive control information 122B, the cache control information 123B, and the cache data 124B. The cache data 124B includes clean data and dirty data (the "dirty data 125B" in the figure), similar to the cache data 124A.

[0046] Each piece of information stored in the memory 120A of the control device 100A and each piece of information stored in the memory 120B of the control device 100B, which has the same name as each piece of information stored in the memory 120A of the control device 100A, basically have the same meaning and properties.

[0047] The processor 110A manages information (for example, a flag) indicating whether each piece of cache data 124A stored in the memory 120A is clean data or dirty data 125A, for example, in the memory 120A as information attached to the cache data 124A.

[0048] Furthermore, the processor 110B manages information (for example, a flag) indicating whether each piece of cache data 124B stored in the memory 120B is clean data or dirty data 125B, for example, in the memory 120B as information attached to the cache data 124B.

[0049] <Basic operation of the control device> Next, a description will be given of the basic operation of the control device 100. Note that, although the operation of the control device 100A will be described below, the operation of the control device 100B is basically the same as that of the control device 100A.

[0050] 2A is a diagram illustrating the main process (hereinafter referred to as "data read process S200") that the control device 100A performs when it receives a data read request from the host device 2. The data read process S200 will be described below with reference to this diagram.

[0051] The control device 100A monitors in real time whether a data read request has been received from the host device 2 (S211: NO). When the control device 100A receives a data read request from the host device 2 (S211: YES), it refers to the cache control information 123A to check whether the data specified in the data read request is stored in the memory 120A (as cache data 124A) (S212).

[0052] When the above data is stored as cache data 124A in the memory 120A (S212: YES), the control device 100A transmits the data as read data to the host device 2 (S213). Thereafter, the process returns to S211.

[0053] On the other hand, when the above data is not stored in the memory 120A (S212: NO), the control device 100A reads the above data from the storage device 17 and stores (stages) it as cache data 124A in the memory 120A (S221), and transmits the data as read data to the host device 2 (S222). Thereafter, the process returns to S211.

[0054] In this way, when the data specified in the data read request exists in the memory 120A as the cache data 124A, the control device 100A reads the data from the memory 120A and transmits it to the host device 2, so that the read data can be provided to the host device 2 at high speed.

[0055] FIG. 2B is a diagram for explaining the main process (hereinafter referred to as "data write process S250") performed by the control device 100A when a data write request is received from the host device 2. Hereinafter, the data write process S250 will be described with reference to the figure.

[0056] The control device 100A monitors in real time the reception of a data write request from the host device 2 (S251: NO). When the control device 100A receives a data write request from the host device 2 (S251: YES), it stores the write data received together with the data write request as cache data 124A in the memory 120A (S252). Note that the write data stored in the memory 120A becomes dirty data 125A.

[0057] Subsequently, the control device 100A communicates with the control device 100B via the internal bus 30 and transfers the above-written data received from the host device 2 to the control device 100B (S253). The control device 100B receives the above-written data from the control device 100A and stores the received written data as cache data 124B (dirty data 125B) in the memory 120B (S254).

[0058] Subsequently, the control device 100A transmits a notification (hereinafter referred to as "write completion notification") to the host device 2 indicating that the processing of the data write request has been completed (S255).

[0059] FIG. 2C is a flowchart for explaining the main processing (hereinafter referred to as "data write processing S270 to the storage device") performed when the control device 100A writes (destages) the dirty data 125A stored in the memory 120A to the storage device 17. Hereinafter, the data write processing S270 to the storage device will be described with reference to the same figure.

[0060] The control device 100A monitors in real time whether the timing for writing the dirty data 125A stored in the memory 120A to the storage device 17 has arrived (S271: NO). Note that the above timing arrives, for example, when a predetermined time has elapsed since the write data was written to the memory 120A.

[0061] When the above timing arrives (S271: YES), the control device 100A stores the dirty data 125A stored in the memory 120A in the storage device 17 (S272). Thereafter, the dirty data 125A is deleted or changed to clean data (S273).

[0062] Subsequently, the control device 100A notifies the control device 100B via the internal bus 30 that the dirty data 125A has been deleted or changed to clean data (S274). When receiving the above notification, the control device 100B deletes the dirty data 125B corresponding to the dirty data 125A from the memory or changes it to clean data (S275).

[0063] As described above, according to the illustrated storage device 10, even when one of the two control devices 100 (control device 100A, control device 100B) is blocked (function stopped), the other control device 100 can continue to provide services to the host device 2.

[0064] However, when one of the control devices 100 is blocked, the redundancy of the dirty data 125A or the dirty data 125B is impaired, and the availability is reduced. Therefore, when one of the control devices 100 is blocked, for example, the operation is switched to directly writing data to the storage drive 171 with lower performance than the memory 120, which results in a decrease in the performance of the storage device 10.

[0065] In addition, when the storage device 10 shifts one of the control devices (control device 100A and control device 100B) from the normal mode to the power-saving mode by the power-saving function, there are the following problems. (1) When one of the control devices 100 operating in the normal mode receives a new data I / O request, it is necessary to return the other control device 100 operating in the power-saving mode to the normal mode and store (duplicate) the dirty data in the other control device 100, and the effect of the power-saving function is diminished. (2) When trying to enhance the effect of the power-saving function without returning the other control device 100 to the normal mode, in order to ensure the redundancy of the dirty data, it is necessary to write (destage) the dirty data to the storage device 17 by one of the control devices 100 operating in the normal mode, which results in a decrease in the performance of the storage device 10.

[0066] Therefore, in the present invention, the storage device 10 is configured as follows to solve the above problem.

[0067] [First embodiment] Figure 3 shows the configuration of a storage system 1 shown as a first embodiment. The storage system 1 shown in this figure differs in configuration from the storage system 1 illustrated in Figure 1 in that the storage device 10 further comprises a memory module 200. Of the configuration provided in the storage device 10, the storage device 17 is the same as in Figure 1, so it is omitted in the figures referenced below. Also, in the figures referenced in the following explanation, "dirty data" is written as "dirty."

[0068] The memory module 200 is, for example, provided in a detachable state as a substrate (circuit board) independent of the two control devices 100 (control device 100A, control device 100B) in the housing of the storage device 10. Power is supplied to the memory module 200 independently of the two control devices 100 (control device 100A, control device 100B). Therefore, even if the power supply to the control device 100 is lost, data loss can be prevented.

[0069] As shown in the figure, the memory module 200 includes two ports 205 (port 205a and port 205b), a memory controller 210, and a memory 220. The memory controller 210 and the memory 220 are communicatively connected via a bus (PCIe, etc.) not shown.

[0070] The memory controller 210 writes and reads data to and from the memory 220 in response to instructions sent from the processor 110A of the control device 100A. The memory controller 210 also writes and reads data to and from the memory 220 in response to instructions sent from the processor 110B of the control device 100B.

[0071] Memory 220 has a volatile memory element that enables high-speed access, such as DRAM. Further, the memory 220 may include a non-volatile memory element (NVRAM) that backs up the data of the volatile memory element in order to prevent data loss when power supply is lost.

[0072] As shown in the figure, the memory 220 stores drive control information 122C, cache control information 123C, and cache data 124C.

[0073] Among these, the drive control information 122C is information referred to when the processor 110A or the processor 110B accesses the storage area provided by the storage device 17, and includes information associating a logical address with a physical address. The drive control information 122C maintains the content consistency between the drive control information 122A and the drive control information 122B when the memory module 200 communicates with the control device 100A or the control device 100B via the port 205.

[0074] The cache control information 123C is information used when the processor 110A or the processor 110B accesses the cache data 124C stored in the memory 220. The cache control information 123C includes information associating a logical address with a cache address of the memory 220, which is the storage destination of the cache data. The cache control information 123C is updated to the latest state by the memory controller 210 as the cache data 124C is updated.

[0075] The cache data 124C includes dirty data 125A' that has the same content as the dirty data 125A stored in the memory 120A, and dirty data 125B' that has the same content as the dirty data 125B stored in the memory 120B. In the figure, the dirty data 125A and the dirty data 125A' are shown with the same thick line frame, and the dirty data 125B and the dirty data 125B' are shown with the same broken line frame.

[0076] The memory module 200 communicates with the processor 110A of the control device 100A via the I / O bus 105A and the port 205a. The memory module 200 also communicates with the processor 110B of the control device 100B via the I / O bus 105B and the port 205b. These communications are performed using functions such as PCIe and CXL (Compute Express Link).

[0077] Port 205a and port 205b cannot both be used at the same time, and memory module 200 communicates with control device 100A or control device 100B using either selected port 205. For example, when port 205a is selected, only control device 100A can directly access (read and write data to) memory 220 of memory module 200. Also, for example, when port 205b is selected, only control device 100B can directly access memory 220 of memory module 200.

[0078] However, even when port 205a is selected, the control device 100B can indirectly access the memory 220 via the internal bus 30, the control device 100A, the I / O bus 105A, and the port 205a using functions such as NTB (Non Transparent Bridge) and CXL. Similarly, even when port 205b is selected, the control device 100A can indirectly access the memory 220 via the internal bus 30, the control device 100B, the I / O bus 105B, and the port 205b using functions such as NTB and CXL.

[0079] The selection (switching) of the port 205 is performed by transmitting a selection instruction (switching instruction) of the port 205 to the memory module 200 from, for example, the control device 100A or 100B or a management device (not shown).

[0080] The I / O bus 105A has the function of maintaining coherency between a cache memory (not shown) inside the processor 110A and cache data 124C in memory 220 of the memory module 200. When the processor 110A accesses the memory module 200 via the I / O bus 105A, the cache data 124C in the memory module 200 is stored in the cache memory of the processor 110A. When the processor 110A accesses the same data again, high-speed operation is achieved by accessing the data stored in the cache memory inside the processor 110A. The same applies to the I / O bus 105B.

[0081] For example, when port 205a is selected and memory 220 of memory module 200 is occupied by processor 110A, data accessed by processor 110B in memory module 200 via processor 110A may be cached in the internal cache memory of processor 110B. In this case, processor 110A cannot know that the data in the internal cache memory of processor 110B has been updated, so when processor 110B writes data to memory 120B, the data is also written to memory 220 in a write-through manner using the NTB or CXL function, for example. The above also applies when port 205b is selected and memory 220 of memory module 200 is occupied by processor 110B, and processor 110A accesses memory module 200 via processor 110B.

[0082] <Data reading process> Next, the operation of the storage device 10 shown in FIG. 3 when the storage device 10 receives a data read request from the host device 2 (another device) will be described.

[0083] FIG. 4 is a diagram for explaining the main processing (hereinafter referred to as "data readout processing S400") performed by the control device 100A of the storage device 10 shown in FIG. 3 when receiving a data readout request from the host device 2. Hereinafter, the data readout processing S400 will be described with reference to the same figure.

[0084] As shown in the figure, the control device 100A monitors in real time the reception of a data readout request from the host device 2 (S411: NO). When the control device 100A receives a data readout request from the host device 2 (S411: YES), it checks whether the data specified in the data readout request is stored in the memory 120A (as cache data 124A) by referring to the cache control information 123A (S412).

[0085] When the above data is stored in the memory 120A (S412: YES), the control device 100A reads out the cache data 124A stored in the memory 120A as readout data and transmits it to the host device 2 (S413). Then, the process returns to S411.

[0086] On the other hand, when the above data is not stored in the memory 120A (S412: NO), the control device 100A reads out the above data from the storage device 17 and stores (stages) it in the memory 120A as cache data 124A (S421), and transmits the data to the host device 2 as readout data (S422). Then, the process returns to S411.

[0087] Note that when the control device 100B of the storage device 10 shown in FIG. 3 receives a data readout request from the host device 2, the same processing as above is performed.

[0088] <Data writing process> Next, the operation of the storage device 10 when the control device 100A of the storage device 10 receives a data write request from the host device 2 will be described. Hereinafter, it is assumed that the memory 220 of the memory module 200 is occupied by the processor 110A (the port 205a is selected).

[0089] FIG. 5A is a diagram for explaining the main process (hereinafter referred to as "data write process S500") performed by the control device 100A of the storage device 10 when the control device 100A of the storage device 10 receives a data write request from the host device 2. Hereinafter, the data write process S500 will be described with reference to the same figure.

[0090] As shown in the figure, the control device 100A monitors in real time the reception of a data write request from the host device 2 (S511: NO). When the control device 100A receives a data write request from the host device 2 (S511: YES), it stores the write data received together with the data write request in the memory 120A as cache data 124A. Further, the control device 100A updates the cache control information 123A to the latest state (S512). Note that the above write data stored in the memory 120A becomes dirty data 125A.

[0091] Subsequently, the control device 100A directly accesses the above write data received from the host device 2 via the I / O bus 105A, accesses the memory 220 of the memory module 200, and stores it as cache data 124C. Further, the control device 100A updates the cache control information 123C to the latest state (S513). Note that the above write data stored in the memory 220 becomes dirty data 125A'.

[0092] Subsequently, the control device 100A sends a notification (hereinafter referred to as "write completion notification") to the host device 2 indicating that the processing of the data write request has been completed (S514). Thereafter, the process returns to S511.

[0093] As described above, the dirty data of the control device 100A is duplicated (duplicated as dirty data 125A and dirty data 125A') between the control device 100A and the memory module 200.

[0094] FIG. 5B is a diagram for explaining the main processing (hereinafter referred to as "data writing process S550") performed by the control device 100A when the memory 220 of the memory module 200 is occupied by the processor 110A (port 205a is selected) and the control device 100B of the storage device 10 receives a data write request from the host device 2. Hereinafter, the data writing process S500 will be described with reference to the same figure.

[0095] As shown in the figure, the control device 100B monitors in real time the reception of a data write request from the host device 2 (S551: NO). When the control device 100B receives a data write request from the host device 2 (S551: YES), it stores the write data received together with the data write request in the memory 120B as cache data 124B. Further, the control device 100B updates the cache control information 123B (S552). Note that the above write data stored in the memory 120B becomes dirty data 125B.

[0096] Subsequently, the control device 100B stores the above write data in the memory 220 of the memory module 200. Since the memory 220 of the memory module 200 is occupied by the processor 110A, the control device 100B cannot directly access the memory 220 of the memory module 200. Therefore, the control device 100B indirectly accesses the memory 220 of the memory module 200 via the internal bus 30, the processor 110A of the control device A, the I / O bus 105A, and the port 205a using functions such as NTB and CXL, and stores the above write data in the memory 220 as cache data 124C. Further, the control device 100B updates the cache control information 123C to the latest state (S553). Note that the above write data stored in the memory 220 becomes dirty data 125B'.

[0097] Subsequently, the control device 100B transmits a notification to the host device 2 indicating that the processing of the data write request has been completed (hereinafter referred to as the "write completion notification") (S554). Thereafter, the process returns to S551.

[0098] As described above, the dirty data of the control device 100B is duplicated (duplicated as dirty data 125B and dirty data 125B') between the control device 100B and the memory module 200.

[0099] <Writing Dirty Data to the Storage Device> FIG. 5C is a flowchart for explaining the process (hereinafter referred to as the "data write process to the storage device S570") performed when the control device 100A writes (destages) the dirty data 125A stored in the memory 120A and the dirty data 125A' stored in the memory 220 of the memory module 200 to the storage device 17. Hereinafter, it is assumed that the memory 220 of the memory module 200 is occupied by the processor 110A (port 205a is selected). Hereinafter, the data write process to the storage device S570 will be described with reference to the same figure.

[0100] As shown in the figure, the control device 100A monitors in real time whether the timing for writing the dirty data 125A stored in the memory 120A to the storage device 17 has arrived (S571: NO). Note that the above timing arrives when, for example, a predetermined time has elapsed since the write data was written to the memory 120A.

[0101] When the above timing arrives (S571: YES), the control device 100A stores (destages) the dirty data 125A stored in the memory 120A in the storage device 17 (S572)

[0102] Subsequently, the control device 100A deletes the dirty data 125A from the memory 120A or changes the dirty data 125A to clean data (S573).

[0103] Subsequently, the control device 100A accesses the memory module 200 via the I / O bus 105A, the I / O bus 105A, and the port 205a, and deletes the dirty data 125A' stored in the memory 220 or changes it to clean data (S574). After that, the process returns to S571.

[0104] In addition, when the control device 100B writes (destages) the dirty data 125B stored in the memory 120B and the dirty data 125B' stored in the memory 220 of the memory module 200 to the storage device 17, the same processing as above is performed. However, since the memory 220 of the memory module 200 is occupied by the processor 110A (the port 205a is selected), the control device 100B indirectly issues an instruction to the memory module 200 via the control device 100A by using the NTB or CXL function, thereby deleting the dirty data 125B' stored in the memory 220 of the memory module 200 or changing it to clean data.

[0105] <Operation when one of the control devices shifts to the power-saving mode or shuts down> Subsequently, the operation of the storage device 10 having the above configuration when one of the control devices 100 shifts to the power-saving mode or shuts down will be described.

[0106] FIG. 6 is a diagram for explaining the operation of the storage device 10 when the memory 220 of the memory module 200 is occupied by the processor 110A (the port 205a is selected) and the control device 100B shifts to the power-saving mode or shuts down.

[0107] As shown in the figure, when the control device 100B is shifted to the power saving mode or blocked, the control device 100A (processor 110A) directly accesses the memory 220 of the memory module 200 via the I / O bus 105A and the port 205a to read the dirty data 125B' stored in the memory 220, and stores the read dirty data 125B' in the memory 120A. The control device 100A also updates the cache control information 123A to the latest state.

[0108] Next, the storage apparatus 10 switches the control apparatus 100B to a power saving mode or blocks it.

[0109] Thereafter, the storage device 10 starts processing the data I / O request sent from the host device 2 using the control device 100A and the memory module 200.

[0110] As a result, even after the control device 100B transitions to a power saving mode or is blocked, the dirty data of the control device 100B is duplicated in the control device 100A and the memory module 200, ensuring redundancy of the dirty data. Furthermore, there is no need to switch to an operation in which data is written directly to the storage drive 171, and the performance of the storage device 10 can be maintained.

[0111] In the above, dirty data 125B' in memory 220 of memory module 200 is transferred to memory 120A of control device 100A, but it is also possible to transfer dirty data 125B in memory 120B of control device 100B to memory 120A of control device A via internal bus 30 using functions such as NTB or CXL.

[0112] The same operation as above also occurs when the control device 100A is switched to a power saving mode or blocked while the memory 220 of the memory module 200 is occupied by the processor 110B (port 205b is selected).

[0113] FIG. 7 is a diagram for explaining the operation of the storage device 10 when the control device 100A is closed while the memory 220 of the memory module 200 is occupied by the processor 110A of the control device 100A (port 205a is selected).

[0114] When the processor 110A of the control device 100A detects a failure or a sign of failure in the control device 100A, first, the updated data stored in its internal cache memory (not shown) is directly accessed and written to the memory 220 of the memory module 200 via the I / O bus 105A and the port 205a.

[0115] Subsequently, the processor 110A of the control device 100A reads the dirty data 125A' stored in the memory 220 of the memory module 200 via the I / O bus 105A and the port 205a, and stores the read dirty data 125A' in the memory 120B via the internal bus 30 and the processor 110B of the control device 100B using functions such as NTB or CXL. Also, the control device 100B updates the cache control information 123B to the latest state.

[0116] Subsequently, the storage device 10 closes the control device 100A.

[0117] Subsequently, the control device 100B transmits a port switching instruction (an instruction to switch from port 205a to port 205b) to the memory module 200 via the I / O bus 105A.

[0118] When the memory module 200 receives the above instruction, it switches the port 205 (switches from port 205a to port 205b) according to the received instruction, and transmits a port switching completion notification to the control device 100B (processor 110B).

[0119] Upon receiving the completion notification, the control device 100B maps the address space of the memory 220 in the memory module 400 to its own address space (so that the storage area of the memory 220 can be specified by the address in the address space managed by itself). The firmware of the control device 100B determines whether the memory module 200 is directly connected via the I / O port 205B and the port 205b, or indirectly connected via the control device 100A using functions such as NTB or CXL, and then maps the address space of the memory module 200, and notifies the OS (Operating System) of the control device 100B of the start address of the mapped address space. The OS notifies the app (application operating on the OS) of the notified start address. The app manages the offsets (relative addresses) used in the drive control information 122B and the cache control information 123B, and accesses the drive control information 122C and the cache control information 123C of the memory module 200 using the start address (base address) notified from the OS and the offset.

[0120] Thereafter, the storage device 10 starts processing the data I / O requests sent from the host device 2 by the control device 100B and the memory module 200.

[0121] According to the above, when the control device 100A is blocked while the memory 220 of the memory module 200 is occupied by the control device 100A (the port 205a is selected), the dirty data of the control device 100A is duplicated in the control device 100B and the memory module 200, and the redundancy of the dirty data can be ensured. Also, it is not necessary to switch to an operation of directly writing data to the storage drive 171 to ensure the redundancy of the dirty data, and a decrease in the performance of the storage device 10 can be prevented.

[0122] Incidentally, in the above description, the processor 110A of the control device 100A reads the dirty data 125A' and stores it in the memory 120B via the processor 110B of the control device 100B. However, after the control device 100A is shut down, the control device 100B may read the dirty data 125A' and store it in the memory 120B.

[0123] In addition, when the control device 100B is shut down while the memory 220 of the memory module 200 is occupied by the processor 110B (the port 205b is selected), the operation is basically the same as described above.

[0124] FIG. 8 is a diagram for explaining the operation of the storage device 10 (control device 100A, control device 100B) when a failure or a sign of a failure of the memory module 200 is detected.

[0125] When a failure or a sign of a failure of the memory module 200 is detected in the storage device 10, first, the processor 110A of the control device 100A reads the dirty data 125A stored in the memory 120A, and transmits the read dirty data 125A to the processor 110B of the control device 100B via the internal bus 30. The processor 110B of the control device 100B receives the above-mentioned dirty data 125A sent from the control device 100A, and stores the received dirty data 125A as dirty data 125A' in the memory 120B. At this time, the control device 100B updates the cache control information 123B to the latest state.

[0126] On the one hand, the processor 110B of the control device 100B reads out the dirty data 125B stored in the memory 120B, and transmits the read dirty data 125B to the processor 110A of the control device 100A via the internal bus 30. The processor 110A of the control device 100A receives the above-mentioned dirty data 125B sent from the control device 100B, and stores the received dirty data 125B in the memory 120B as dirty data 125B'. At this time, the control device 100A updates the cache control information 123A to the latest state.

[0127] After that, the storage device 10 processes the data I / O requests sent from the host device 2 while redundantly storing the dirty data 125 (dirty data 125A, dirty data 125B) by the control device A and the control device 100B.

[0128] For example, when the control device 100A receives a data write request from the host device 2, the control device 100A stores the write target data of the received data write request in the memory 120A as dirty data 125A, and updates the cache control information 123A to the latest state. Also, the control device 100A transmits the above-mentioned dirty data 125A to the control device 100B via the internal bus 30. When the control device 100B receives the dirty data 125A, the control device 100B stores the received write data in the memory 120B as dirty data 125A', and updates the cache control information 123B to the latest state.

[0129] For example, when the control device 100B receives a data write request from the host device 2, it stores the write target data of the received data write request in the memory 120B as dirty data 125B, and updates the cache control information 123B to the latest state. Further, the control device 100B transmits the dirty data 125B to the control device 100A via the internal bus 30. When the control device 100A receives the dirty data 125B, it stores the received write data in the memory 120A as dirty data 125B', and updates the cache control information 123A to the latest state.

[0130] Note that the dirty data 125A and dirty data 125B' stored in the memory 120A, and the dirty data 125B and dirty data 125A' stored in the memory 120B are destaged at a predetermined timing after being written to the storage device 17, and are deleted from the memory 120A or the memory 120B or changed to clean data.

[0131] According to the above, the dirty data 125A of the control device 100A is duplicated in the control device 100A and the control device 100B, and the redundancy of the dirty data 125A of the control device 100A can be ensured. Also, the dirty data 125B of the control device 100B is duplicated in the control device 100A and the control device 100B, and the redundancy of the dirty data 125B of the control device 100B can be ensured. Further, there is no need to switch to an operation of directly writing data to the storage drive 171, and the performance of the storage device 10 can be maintained.

[0132] [Second Embodiment] FIG. 9 shows the configuration of the storage system 1 shown as the second embodiment. The storage system 1 shown in the figure is different in configuration from the storage system 1 shown in FIG. 3 in that the storage device 10 further includes two memory modules 200C and 200D.

[0133] As shown in the figure, the cache data 124C of the memory module 200C includes dirty data 125A' that has the same content as the dirty data 125A stored in the memory 120A of the control device 100A. Also, the cache data 124D of the memory 220D of the memory module 200D includes dirty data 125B' that has the same content as the dirty data 125B stored in the memory 120B of the control device 100B.

[0134] In this example, in a state where any of the control devices 100 (control device 100A, control device 100B) of the storage device 10 is functioning (a state where a data I / O request can be received from the host device 2 and corresponding data I / O processing can be performed. Hereinafter, referred to as the "normal state"), port 205a is selected for the memory module 200C, and port 205b is selected for the memory module 200D. For this reason, the control device 100A can directly access the memory 220C of the memory module 200C via port 205a, and the control device 100B can also directly access the memory 220D of the memory module 200D via port 205b.

[0135] Here, as shown in FIG. 10A, when the control device 100B is shifted to the power-saving mode or shut down, the dirty data 125B is stored as dirty data 125B' in the memory 120A of the control device 100A, so that the redundancy of the dirty data 125B is ensured even after the control device 100B is shifted to the power-saving mode or shut down. In this case, the control device 100A may obtain the dirty data 125B from the control device 100B via the internal bus 30, or may obtain it from the memory 220D of the memory module 200D via the control device 100B by the function of NTB or CXL. Note that when the control device 100A is shifted to the power-saving mode or shut down, the redundancy of the dirty data 125B can be ensured in the same mechanism as above.

[0136] Also, as shown in FIG. 10B, when closing the memory module 200D, the dirty data 125B in the memory 120B is stored as dirty data 125B' in the memory 120A of the control device 100A, so that the redundancy of the dirty data 125B is ensured even after the memory module 200D is closed. In this case, the control device 100A may acquire the dirty data 125B from the control device 100B via the internal bus 30, or may acquire it from the memory 220D of the memory module 200D via the control device 100B by the function of NTB or CXL. Note that when closing the memory module 200C, the redundancy of the dirty data 125B can be ensured in the same manner as above.

[0137] According to the storage device 10 of the second embodiment, in the normal state, the control device 100A can access the dirty data 125A' in the memory 220C of the memory module 200C at high speed, and the control device 100B can access the dirty data 125B' in the memory 220D of the memory module 200D at high speed. Therefore, the performance of the storage device 10 can be improved. Also, even when the control device 100 shifts to the power-saving mode or is closed, or when the memory module 200 is closed, the redundancy of the dirty data 125 (dirty data 125A, dirty data 125B) is maintained, and the reliability and availability of the data can be ensured.

[0138] [Third Embodiment] FIG. 11 shows the configuration of the storage system 1 shown as the third embodiment. The storage system 1 shown in the figure is different in configuration from the storage system 1 shown in FIG. 3 in the following points. (1) The storage device 10 includes three memory modules 200A, 200B, and 200C. (2) The drive control information 122A, cache control information 123A, and cache data 124A, which were stored in the memory 120A of the control device 100A in FIG. 3, are stored in the memory 220A of the memory module 200A. (3) In FIG. 3, the memory 220B of the memory module 200B stores the drive control information 122B, the cache control information 123B, and the cache data 124B that were stored in the memory 120B of the control device 100B. (4) The memory 220C of the memory module 200C stores the dirty data 125A' that has the same content as the dirty data 125A of the memory 220A and the dirty data 125B' that has the same content as the dirty data 125B of the memory 220B.

[0139] In the storage device 10 illustrated, when any one of the memory modules 200 is blocked, the dirty data 125 (dirty data 125A, dirty data 125B) is stored in each of the other two memory modules 200 so that the redundancy of the dirty data 125 is maintained in the other two memory modules 200. In this case, the transfer (sharing) of the dirty data 125 between the memory modules may be performed by the control device 100 (control device 100A, control device 100B) directly accessing the memory 220 via the I / O bus 105 (I / O bus 105A, I / O bus 105B), or by indirectly accessing the memory 220 via another control device 100 using the functions of NTB or CXL.

[0140] According to the storage system 1 of the third embodiment, similar to the case of the storage system 1 of the first embodiment, it is possible to ensure the reliability and availability of data while maintaining the performance of the storage device 10. Further, since the drive control information 122, the cache control information 123, and the cache data 124 are not stored in the memory 120A of the control device 100A or the memory 120B of the control device 100B, the capacity of the memory 120 of the control device 100 can be reduced. Also, by not placing these pieces of information in the memory 120 of the control device 100, the load on the control device 100 is reduced, and the possibility of a failure occurring in the control device 100 can be reduced.

[0141] As described above, the embodiments of the present invention have been explained. However, the present invention is not limited to the above embodiments, and includes various modifications, and is not necessarily limited to those having all the configurations described.

[0142] For example, the present invention can also be applied to a storage system of a type different from the storage system 1 shown in the first to third embodiments as long as it is a storage system configured using a storage device in which a control device is made redundant and a memory module can be mounted. As an example of a different type of storage system, there is a storage system including a plurality of control devices (channel adapters) that function as communication adapters and a plurality of drive adapters that function as drive control devices, and these are connected by a switch such as a high-speed crossbar switch to configure a storage device (for example, an enterprise type storage device).

Explanation of Signs

[0143] 1 Storage system, 2 Host device, 5 Communication system, 10 Storage device, 100 Control device, 110 Processor, 120 Memory, 122 Drive control information, 123 Cache control information, 124 Cache data, 125 Dirty data, 130 Communication I / F, 140 Drive I / F, 17 Storage device, 171 Storage drive, 200 Memory module, 205 Port, 210 Memory controller, 220 Memory

Claims

1. A storage device that is communicably connected to other devices and performs data I / O processing on a storage device in response to a data I / O request received from the other devices, comprising two control devices that are communicably connected, and three memories that can be directly or indirectly accessed by each of the two control devices, wherein: The first memory stores drive control information, which is information for managing the correspondence between a logical address, which is information indicating the location of data handled by the other device in the data I / O processing, and a physical address, which is information indicating the location of the data in the storage device, first cache data in the data I / O processing, and first cache control information, which is information for managing the correspondence between the logical address of the first cache data and a cache address, which is information indicating the location of the first cache data in the first memory; The second memory stores the drive control information, second cache data in the data I / O processing, and second cache control information, which is information for managing the correspondence between the logical address of the second cache data and a cache address, which is information indicating the location of the second cache data in the first memory; The third memory stores the drive control information, first dirty data, which is the dirty data of the first cache data, second dirty data, which is the dirty data of the second cache data, and third cache control information, which is information for managing the correspondence between the logical address of the first dirty data or the second dirty data and a cache address, which is information indicating the location of the first dirty data or the second dirty data in the third memory; The data I / O processing is performed while the first dirty data and the second dirty data are redundantly stored in a plurality of the memories, and when stopping the function of any of the memories, the first dirty data and the second dirty data are transferred between the memories so that the first dirty data and the second dirty data are redundantly stored in each of the plurality of memories other than the memory whose function is stopped. ​ ​ ​ ​ ​ ​ ​ After stopping the function of the memory, perform the data I / O process while redundantly storing the first dirty data and the second dirty data in each of the plurality of memories. Storage device.

2. The storage device according to claim 1, wherein the first cache data is data stored in the storage device in the data I / O process of the first control device, the second cache data is data stored in the storage device in the data I / O process of the second control device, the first control device is set to a state in which it can directly access the third memory, the second control device is set to a state in which it can indirectly access the third memory via the first control device, when stopping the function of the second memory, the first control device directly accesses the third memory to obtain the second dirty data, and stores the obtained second dirty data in the first memory as the first cache data, after stopping the function of the second memory, perform the data I / O process while redundantly storing the first dirty data and the second dirty data in the first memory and the third memory respectively. Storage device.

3. The storage device according to claim 1, wherein the first cache data is data stored in the storage device in the data I / O process of the first control device, the second cache data is data stored in the storage device in the data I / O process of the second control device, the first control device is set to a state in which it can directly access the third memory, the second control device is set to a state in which it can indirectly access the third memory via the first control device, when stopping the function of the first memory, the second control device indirectly accesses the third memory via the first control device to obtain the first dirty data, and stores the obtained first dirty data in the second memory as the second cache data, reset to a state in which it can directly access the third memory. After stopping the function of the first memory, the data I / O process is performed while redundantly storing the first dirty data and the second dirty data in the second memory and the third memory, respectively. Storage device.

4. The storage device according to claim 1, wherein the first cache data is data to be stored in the storage device in the data I / O process of the first control device, the second cache data is data to be stored in the storage device in the data I / O process of the second control device, when stopping the function of the third memory, the first control device communicates with the second control device to acquire the second dirty data of the second memory, and stores the acquired second dirty data in the first memory as the first cache data, the second control device communicates with the first control device to acquire the first dirty data of the first memory, and stores the acquired first dirty data in the second memory as the second cache data, After stopping the function of the third memory, the data I / O process is performed while redundantly storing the first dirty data and the second dirty data in the first memory and the second memory, respectively. Storage device.

5. The storage device according to claim 1, comprising a plurality of memory modules that provide the memory, storing the first dirty data in the third memory provided by the first memory module, storing the second dirty data in the third memory provided by the second memory module. Storage device.

6. The storage device according to claim 1, comprising a plurality of memory modules that provide the memory, storing the first dirty data in the first memory provided by the first memory module, storing the second dirty data in the second memory provided by the second memory module, storing the first dirty data and the second dirty data in the third memory provided by the third memory module. Storage device.

7. The storage device according to any one of claims 1 to 4, The stop of the function of the memory is caused by the operation state of the control circuit shifting to the power-saving mode, or by the control circuit or the memory being blocked. Storage device.

8. A storage device according to any one of claims 1 to 4, wherein the control device includes a processor, the memory, a communication interface for communicating with other control devices, and a drive interface for communicating with the storage device. Storage device.

9. A storage device according to any one of claims 1 to 4, wherein the indirect access from the control device to the memory is performed using the functions of NTB (Non Transparent Bridge) or CXL (Compute Express Link). Storage device.

10. Connected communicably to other devices, performing data I / O processing on the storage device in response to a data I / O request received from the other devices, two control devices connected communicably, and three memories that can be directly or indirectly accessed by each of the two control devices. Comprising The first memory stores drive control information, which is information managing the correspondence between a logical address, which is information indicating the location of data handled by the other device in the data I / O processing, and a physical address, which is information indicating the location of the data in the storage device, first cache data in the data I / O processing, and first cache control information, which is information managing the correspondence between the logical address of the first cache data and a cache address, which is information indicating the location of the first cache data in the first memory. Storing The second memory stores the drive control information, second cache data in the data I / O processing, and second cache control information, which is information managing the correspondence between the logical address of the second cache data and a cache address, which is information indicating the location of the second cache data in the first memory. Storing The third memory stores the drive control information, first dirty data, which is the dirty data of the first cache data, and second dirty data, which is the dirty data of the second cache data. Third cache control information for managing the correspondence between the logical address of the first dirty data or the second dirty data and the cache address which is information indicating the location of the first dirty data or the second dirty data in the third memory, storing, a storage device, performing the data I / O process while redundantly storing the first dirty data and the second dirty data in a plurality of the memories, when stopping the function of any one of the memories, transferring the first dirty data and the second dirty data between the memories so that the first dirty data and the second dirty data are redundantly stored in each of the plurality of memories other than the memory whose function is stopped, and after stopping the function of the memory, performing the data I / O process while redundantly storing the first dirty data and the second dirty data in each of the plurality of memories, A control method for a storage device that executes.

11. A control method for a storage device according to claim 10, wherein the first cache data is data stored in the storage device in the data I / O process of the first control device, the second cache data is data stored in the storage device in the data I / O process of the second control device, the first control device is set to a state in which it can directly access the third memory, the second control device is set to a state in which it can indirectly access the third memory via the first control device, the storage device, when stopping the function of the second memory, the first control device directly accesses the third memory to obtain the second dirty data, and stores the obtained second dirty data in the first memory as the first cache data, and after stopping the function of the second memory, performing the data I / O process while redundantly storing the first dirty data and the second dirty data in each of the first memory and the third memory, A control method for a storage device that further executes.

12. A control method for a storage device according to claim 10, The first cache data is data stored in the storage device in the data I / O processing of the first control device, The second cache data is data stored in the storage device in the data I / O processing of the second control device, The first control device is set to a state in which it can directly access the third memory, The second control device is set to a state in which it can indirectly access the third memory via the first control device, The storage device, When stopping the function of the first memory, The second control device indirectly accesses the third memory via the first control device to obtain the first dirty data, and stores the obtained first dirty data in the second memory as the second cache data, Resetting to a state in which it can directly access the third memory, and, After stopping the function of the first memory, performing the data I / O processing while redundantly storing the first dirty data and the second dirty data in the second memory and the third memory respectively, A control method for a storage device that further executes.

13. A control method for a storage device according to claim 10, The first cache data is data stored in the storage device in the data I / O processing of the first control device, The second cache data is data stored in the storage device in the data I / O processing of the second control device, The storage device, When stopping the function of the third memory, The first control device obtains the second dirty data in the second memory by communicating with the second control device, and stores the obtained second dirty data in the first memory as the first cache data, The second control device obtains the first dirty data in the first memory by communicating with the first control device, and stores the obtained first dirty data in the second memory as the second cache data, and, After stopping the function of the third memory, while redundantly storing the first dirty data and the second dirty data in the first memory and the second memory respectively, performing the data I / O process step, A control method for a storage device that further executes.

14. A control method for a storage device according to any one of claims 10 to 13, wherein the storage device comprises a plurality of memory modules that provide the memory, storing the first dirty data in the third memory provided by the first memory module, and storing the second dirty data in the third memory provided by the second memory module, A control method for a storage device that further executes.

15. A control method for a storage device according to any one of claims 10 to 13, wherein the storage device comprises a plurality of memory modules that provide the memory, storing the first dirty data in the first memory provided by the first memory module, storing the second dirty data in the second memory provided by the second memory module, and storing the first dirty data and the second dirty data in the third memory provided by the third memory module, A control method for a storage device that further executes.

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