Semiconductor device and method of manufacturing semiconductor device
The described semiconductor device achieves enhanced integration and reliability through three-dimensional memory cell stacking with a gate structure of alternately stacked films and metal channel films, improving operating speed and stability.
Patent Information
- Application Number
- JP2024160136
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-01-16
- Filing Date
- 2024-09-17
- Publication Date
- 2025-07-29
AI Technical Summary
The integration degree of semiconductor devices has reached its limit in two-dimensional structures, and there is a need for improved reliability and stability in three-dimensional memory cell stacking.
A semiconductor device with a gate structure composed of alternately stacked conductive and insulating films, incorporating a metal channel film and a ferroelectric film surrounding a semiconductor channel film, along with drain and source selection transistors, enables three-dimensional memory cell stacking.
This configuration enhances integration, improves operating speed, and provides a stable structure with increased reliability by utilizing high carrier mobility metal channel films and ferroelectric memory cells.
Smart Images
Figure 2025110864000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an electronic device, and more particularly to a semiconductor device and a method of manufacturing the semiconductor device.
Background Art
[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, since the improvement in the integration degree of a semiconductor device that forms a memory cell in a single layer on a substrate has reached its limit, a three-dimensional semiconductor device that stacks memory cells on a substrate has been proposed. In addition, various structures and manufacturing methods have been developed to improve the operation reliability of such a semiconductor device.
Summary of the Invention
Problems to be Solved by the Invention
[0003] Embodiments of the present invention provide a semiconductor device and a method of manufacturing the semiconductor device having a stable structure and improved characteristics.
Means for Solving the Problems
[0004] A semiconductor device according to an embodiment of the present invention may include a gate structure including alternately stacked conductive films and insulating films, a metal channel film extending through the gate structure, a first semiconductor channel film extending through the gate structure and connected to the metal channel film, and a ferroelectric film surrounding the metal channel film and the first semiconductor channel film.
[0005] A semiconductor device according to an embodiment of the present invention may include a bit line, a memory string including a ferroelectric memory cell including a metal channel film and a drain selection transistor including a first semiconductor channel film, a word line connected to the ferroelectric memory cell, and a drain selection line connected to the drain selection transistor and controlling the connection between the memory string and the bit line.
[0006] A method of manufacturing a semiconductor device according to an embodiment of the present invention may include forming a stack including a first material film and a second material film stacked alternately, forming a first opening in the stack, forming a ferroelectric film in the first opening, forming a metal channel film in the ferroelectric film, partially etching the metal channel film to form a second opening, and forming a first semiconductor channel film in the second opening.
[0007] A method of manufacturing a semiconductor device according to an embodiment of the present invention may include forming a source line, forming a source selection line on the source line, forming a stack including a first material film and a second material film stacked alternately on the source selection line, forming an opening extending into the source line through the stack and the source selection line, forming a second semiconductor channel film penetrating the source selection line and connected to the source line in the opening, forming a metal channel film extending through the stack and connected to the second semiconductor channel film in the opening, and forming a first semiconductor channel film extending through the stack and connected to the metal channel film in the opening.
Advantages of the Invention
[0008] By stacking memory cells three-dimensionally, the integration degree of the semiconductor device can be improved. In addition, a semiconductor device having a stable structure and improved reliability can be provided.
Brief Description of the Drawings
[0009]
Figure 1
Figure 2A
Figure 2B
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Figure 3C
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Figure 8A
Figure 8B
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Figure 8F
BEST MODE FOR CARRYING OUT THE INVENTION
[0010] Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the attached drawings.
[0011] FIG. 1 is a circuit diagram showing a cell array of a semiconductor device according to an embodiment of the present invention.
[0012] Referring to FIG. 1, the semiconductor device may include bit lines BL1 to BLk, a memory string MS, word lines WL1 to WLn, and a drain selection line DSL. Each of the memory strings MS may include at least one drain selection transistor DST and a plurality of ferroelectric memory cells MC1 to MCn. Here, the ferroelectric memory cells MC1 to MCn may be FTJ elements (Ferroelectric Tunnel Junction Elements). The word lines WL1 to WLn may be connected to the gate electrodes of the ferroelectric memory cells MC1 to MCn. The drain selection line DSL may be connected to the gate electrode of the drain selection transistor DST. Here, k and n may be integers of 1 or more.
[0013] The drain selection transistor DST can control the connection between the memory string MS and the bit line BL. The drain selection transistor DST may include a semiconductor channel film. As an example, the semiconductor channel film may include polysilicon.
[0014] The ferroelectric memory cells MC1 to MCn can store data according to the polarization state of the ferroelectric film. The ferroelectric memory cells MC1 to MCn may include a channel film having a higher carrier mobility than the semiconductor channel film of the drain selection transistor DST. The ferroelectric memory cells MC1 to MCn may include a metal channel film. As an example, the metal channel film may include metals such as titanium and tungsten.
[0015] According to the configuration as described above, by increasing the number of ferroelectric memory cells MC1 to MCn included in the memory string MS, the memory integration degree of the semiconductor device can be increased. Since the ferroelectric memory cells MC1 to MCn include a metal channel film with a high carrier mobility, the operating speed can be improved. Also, by using the drain select transistor DST as a switch, it is possible to operate while distinguishing between a selected memory string and a non-selected memory string.
[0016] On the other hand, the cell array according to an embodiment of the present invention can be utilized for the operation of analog computing in memory. Referring to Equation 1, by mapping the voltages applied to the word lines WL1 to WLn to an input vector and mapping the conductance of the ferroelectric memory cell MC to a weight vector, a multiply-accumulate (MAC) operation is performed, whereby an output vector output via the bit line BL can be calculated. Therefore, it is possible to perform the analog operations required for AI operations inside the memory by utilizing the cell array.
[0017]
Number
[0018] Referring to FIG. 2A, during the erasing operation, a turn-on voltage can be applied to the drain selection lines DSL1 and DSL2, and a ground voltage can be applied to the bit lines BL1 and BL2. Here, the turn-on voltage may be about 2V. As a result, the memory strings MS1 to MS4 can be connected to the bit lines BL1 and BL2, and the channel potential of the memory strings MS1 to MS4 can have a ground level. An erase voltage Vers can be applied to the word lines WL1 to WLn. Here, the erase voltage Vers may be a negative voltage. As a result, the ferroelectric films of the ferroelectric memory cells MC1 to MCn can have a first polarization state. Therefore, an erasing operation can be performed on all the memory strings MS1 to MS4 belonging to the memory block.
[0019] Referring to FIG. 2B, during the programming operation, a turn-on voltage can be applied to the selected first drain selection line DSL1, and a first bit line voltage can be applied to the selected first bit line BL1. Here, the first bit line voltage may be a ground voltage. As a result, the channel potential of the selected first memory string MS1 can have a ground level.
[0020] A program voltage Vpgm can be applied to the selected word line WL2, and a pass voltage Vpass can be applied to the non-selected word lines WL1, WL3 to WLn. Here, the program voltage Vpgm may be a positive voltage, and the pass voltage Vpass may be Vpgm / 2. As a result, the ferroelectric film of the second memory cell MC2 selected by the program voltage Vpgm can have a second polarization state. Therefore, a programming operation can be performed on the selected second memory cell MC2.
[0021] On the one hand, among the non-selected memory strings MS2 to MS4, the second memory string MS2 can share the selected first memory string MS1 and the first drain selection line DSL1, and does not necessarily need to share the first bit line BL1. Therefore, a second bit line voltage higher than the first bit line voltage can be applied to the non-selected second bit line BL2. Here, the second bit line voltage may be the operating voltage Vcc. As a result, the drain selection transistor DST may be turned off, and the channel of the second memory string MS2 may be floated. The floated channel may be boosted compared to the program voltage Vpgm and the pass voltage Vpass, and the program operation of the non-selected second memory string MS2 can be inhibited.
[0022] Among the non-selected memory strings MS2 to MS4, the third memory string MS3 does not necessarily need to share the selected first memory string MS1 and the first drain selection line DSL1, and can share the first bit line BL1. Therefore, a ground voltage can be applied to the non-selected second drain selection line DSL2, and the program operation of the non-selected third memory string MS3 can be inhibited.
[0023] Among the non-selected memory strings MS2 to MS4, the fourth memory string MS4 does not necessarily need to share the selected first memory string MS1 and the first drain selection line DSL1, and does not necessarily need to share the first bit line BL1. A ground voltage can be applied to the non-selected second drain selection line DSL2, and a second bit line voltage higher than the first bit line voltage can be applied to the non-selected second bit line BL2. As an example, the second bit line voltage may be Vpgm / 2. As a result, the program operation of the non-selected fourth memory string MS4 can be inhibited.
[0024] Figures 3A to 3C are diagrams for explaining the structure and operation of a semiconductor device according to an embodiment of the present invention. Figures 3B and 3C are enlarged views of the A region in Figure 3A. Hereinafter, descriptions overlapping with those described above can be omitted.
[0025] Referring to Figure 3A, the semiconductor device can include a gate structure GST, a metal channel film 35, a first semiconductor channel film 36, and a ferroelectric film 34. The semiconductor device can further include at least one of an interface film 33 and an insulating core 37.
[0026] The gate structure GST can include a conductive film 31 and an insulating film 32 laminated alternately. As an example, the conductive film 31 may be a word line or a drain select line. As an example, at least one of the uppermost conductive films 31 among the conductive films 31 may be a drain select line, and the remaining conductive films 31 may be word lines. The conductive film 31 can include a conductive material such as polysilicon, tungsten (W), molybdenum (Mo). As an example, the conductive film 31 can include a barrier film 31A and a metal film 31B within the barrier film 31A. The barrier film 31A can include a metal nitride such as titanium nitride (TiN), and the metal film 31B can include tungsten (W).
[0027] The metal channel film 35 can extend through the gate structure GST. The metal channel film 35 can include a first metal film 35A, a barrier film 35B, and a second metal film 35C. The barrier film 35B can surround the second metal film 35C, and the first metal film 35A can surround the barrier film 35B. As an example, the first metal film 35A can include titanium (Ti), the barrier film 35B can include a metal nitride such as titanium nitride (TiN), and the second metal film 35C can include tungsten (W).
[0028] The first semiconductor channel film 36 can extend through the gate structure GST and can be connected to the metal channel film 35. The first semiconductor channel film 36 can include a polysilicon film 36A and a metal silicide film 36B. The metal silicide film 36B may be located between the polysilicon film 36A and the metal channel film 35. FIG. 3A shows an example in which the metal silicide film 36B is formed at the interface between the first metal film 35A and the first semiconductor channel film 36. However, it is also possible to form a metal silicide film at the interface between the barrier film 35B and the first semiconductor channel film 36, or at the interface between the second metal film 35C and the first semiconductor channel film 36. During the silicidation reaction, the reactivities of the first metal film 35A, the barrier film 35B, and the second metal film 35C may be different, and a relatively thick metal silicide film 36B may be formed at the interface between the first metal film 35A and the first semiconductor channel film 36. The metal silicide film 36B can form an ohmic contact between the first semiconductor channel film 36 and the metal channel film 35.
[0029] An insulating core 37 may be located within the first semiconductor channel film 36. The first semiconductor channel film 36 can surround the sidewalls of the insulating core 37 and can extend between the insulating core 37 and the metal channel film 35. As an example, the insulating core 37 can include an insulating material such as an oxide or a nitride.
[0030] The ferroelectric film 34 can surround the first semiconductor channel film 36 and the metal channel film 35. The ferroelectric film 34 can include hafnium oxide (HfO), hafnium zirconium oxide (HfZrO), etc.
[0031] The interface film 33 can surround the ferroelectric film 34. The interface film 33 can include a dielectric material such as tantalum oxide (Ta2O5). When a high-pressure heat treatment process is performed after forming the tantalum oxide film, the oxygen bonds in the tantalum oxide film are broken, and positively ionized oxygen vacancies (Vo ++ ) can be generated. The oxygen vacancies (Vo ++) applies an imprinting field to the ferroelectric film 34, enabling the ferroelectric memory cell to have self-rectifying characteristics.
[0032] According to the structure as described above, the ferroelectric memory cell MC may be located in the intersecting region of the metal channel film 35 and the conductive film 31. The ferroelectric memory cells MC can be stacked along the metal channel film 35. The drain select transistor DST may be located in the intersecting region of the first semiconductor channel film 36 and the conductive film 31. The ferroelectric memory cells MC and at least one drain select transistor DST stacked along the interconnected metal channel film 35 and the first semiconductor channel film 36 can constitute one memory string.
[0033] Referring to FIG. 3B, during the erase operation, an erase voltage Vers can be applied to the word line WL, and the ferroelectric film 34 may be polarized to the first polarization state by the erase voltage Vers. Therefore, the erase operation can be performed on the ferroelectric memory cells MC included in the memory block at once.
[0034] Referring to FIG. 3C, during the program operation, a program voltage Vpgm can be applied to the selected word line sel_WL, and a pass voltage Vpass can be applied to the unselected word line unsel_WL. Thereby, the ferroelectric film 34 of the selected ferroelectric memory cell MC may be switched to the second polarization state, and the ferroelectric film 34 of the unselected ferroelectric memory cell MC can hold the first polarization state. Therefore, the program operation can be performed only on the selected ferroelectric memory cell MC.
[0035] FIGS. 4A to 4C are diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. Hereinafter, descriptions overlapping with those described above can be omitted.
[0036] Referring to FIG. 4A, a stack ST can be formed on a substrate 40. The stack ST can include a first material film 41 and a second material film 42 that are alternately stacked. The first material film 41 may be for forming gate lines such as word lines and drain selection lines. As an example, at least one topmost first material film 41 may be for forming a drain selection line, and the remaining first material films 41 may be for forming word lines. The first material film 41 can include a sacrificial material such as a nitride or a conductive material such as polysilicon or metal. The second material film 42 may be for insulating the stacked gate lines from each other. The second material film 42 can include an insulating material such as an oxide, a nitride, or an air gap.
[0037] Next, a first opening OP1 can be formed in the stack ST. The first opening OP1 can extend through the stack ST and can have a depth that exposes the substrate 40. Next, an interface film 43 can be formed in the first opening OP1. The interface film 43 may be formed along the inner surface of the first opening OP1. The interface film 43 may be formed on the inner wall and the bottom surface of the first opening OP1. The interface film 43 can include a dielectric material such as tantalum oxide (Ta2O5).
[0038] Next, a ferroelectric film 44 can be formed in the first opening OP1. The ferroelectric film 44 may be formed along the profile of the interface film 43. The ferroelectric film 44 may be formed on the inner wall and the bottom surface of the first opening OP1.
[0039] Next, a metal channel film 45 can be formed in the first opening OP1. The metal channel film 45 may be formed of a single film or a multilayer film. The metal channel film 45 can include a first metal film 45A, a barrier film 45B, and a second metal film 45C. As an example, the first metal film 45A can be formed along the profile of the ferroelectric film 44, the barrier film 45B can be formed along the profile of the first metal film 45A, and the second metal film 45C can be formed within the barrier film 45B. The barrier film 45B can surround the sidewalls and the bottom surface of the second metal film 45C, and the first metal film 45A can surround the sidewalls and the bottom surface of the barrier film 45B. The ferroelectric film 44 can surround the sidewalls and the bottom surface of the metal channel film 45.
[0040] Referring to FIG. 4B, the metal channel film 45 can be partially etched to form a second opening OP2. As an example, the metal channel film 45 can be etched using a wet etching process. The portion of the metal channel film 45 corresponding to the drain selection line can be removed.
[0041] Referring to FIG. 4C, the first semiconductor channel film 46 can be formed within the second opening OP2. The first semiconductor channel film 46 can be formed along the inner surface of the second opening OP2. The first semiconductor channel film 46 may be formed along the profiles of the ferroelectric film 44 and the metal channel film 45. As an example, after depositing a polysilicon film to form the first semiconductor channel film 46, a heat treatment process can be performed. By the heat treatment process, the silicon of the first semiconductor channel film 46 and the metal of the metal channel film 45 can react, and a metal silicide film 46A may be formed by a silicidation reaction. The metal silicide film 46A may be formed at a portion of the first semiconductor channel film 46 that abuts the metal channel film 45. Thereby, the first semiconductor channel film 46 is partially silicided, and an ohmic contact can be formed between the metal channel film 45 and the first semiconductor channel film 46. As an example, the first semiconductor channel film 46 and the first metal film 45A may react to form titanium silicide. A first semiconductor channel film 46 may be formed including a polysilicon film 46B and a metal silicide film 46A located between the polysilicon film 46B and the metal channel film 45.
[0042] Next, an insulating core 47 can be formed within the first semiconductor channel film 46. The second opening OP2 may be filled with the insulating core 47. The insulating core 47 can include insulating materials such as PSZ (polysilazane), oxides, nitrides.
[0043] Next, the first material film 41 can be replaced with a third material film 49. As an example, after removing the first material film 41 to form the third opening OP3, the third material film 49 can be formed within the third opening OP3. The third material film 49 may be a gate line and can include a conductive material such as metal. After forming a barrier film 49A within the third opening OP3, a metal film 49B can be formed within the barrier film 49A. The barrier film 49A can include titanium nitride (TiN), and the metal film 49B can include tungsten (W).
[0044] Thereby, a gate structure GST including alternately stacked second material films 42 and third material films 49 may be formed. A ferroelectric memory cell may be formed in a region where the third material film 49 and the metal channel film 45 intersect, and a drain select transistor may be formed in a region where the first semiconductor channel film 46 and the third material film 49 intersect.
[0045] On the other hand, when the first material film 41 contains a conductive material, the step of replacing the first material film 41 with the third material film 49 can be omitted. In this case, the first material film 41 can be used as a gate line, and the stack ST can be used as a gate structure GST.
[0046] According to the manufacturing method as described above, a ferroelectric memory cell including a metal channel film 45 and a drain select transistor including a first semiconductor channel film 46 can be formed.
[0047] FIG. 5 is a circuit diagram showing a cell array of a semiconductor device according to an embodiment of the present invention. Hereinafter, descriptions overlapping with those described above can be omitted.
[0048] Referring to FIG. 5, the semiconductor device can include bit lines BL1 to BLk, a memory string MS, word lines WL1 to WLn, a drain select line DSL, and a source select line SSL. The semiconductor device can further include a source line SL, and the memory string MS can be connected between the bit line BL and the source line SL.
[0049] Each of the memory strings MS can include at least one drain selection transistor DST, a plurality of ferroelectric memory cells MC1 to MCn, and at least one source selection transistor SST. The ferroelectric memory cells MC1 to MCn may be FTJ elements (Ferroelectric Tunnel Junction Elements). Word lines WL1 to WLn can be connected to the gate electrodes of the ferroelectric memory cells MC1 to MCn. A drain selection line DSL can be connected to the gate electrode of the drain selection transistor DST. A source selection line SSL can be connected to the gate electrode of the source selection transistor SST. Here, k and n may be integers of 1 or more.
[0050] The drain selection transistor DST can control the connection between the memory string MS and the bit line BL. The drain selection transistor DST can include a first semiconductor channel film. As an example, the first semiconductor channel film can include polysilicon.
[0051] The source selection transistor SST can control the connection between the memory string MS and the source line SL. The source selection transistor SST can include a second semiconductor channel film. As an example, the second semiconductor channel film can include polysilicon.
[0052] The ferroelectric memory cells MC1 to MCn can store data according to the polarization state of the ferroelectric film. The ferroelectric memory cells MC1 to MCn can include a channel film having a higher carrier mobility than the first semiconductor channel film and / or the second semiconductor channel film. The ferroelectric memory cells MC1 to MCn can include a metal channel film. As an example, the metal channel film can include metals such as titanium and tungsten.
[0053] According to the configuration as described above, by increasing the number of ferroelectric memory cells MC1 to MCn included in the memory string MS, the memory integration degree of the semiconductor device can be increased. Since the ferroelectric memory cells MC1 to MCn include a metal channel film with a high carrier mobility, the operating speed can be improved. By using the drain selection transistor DST as a switch, it is possible to operate while distinguishing between the selected memory string and the non-selected memory string. Also, by using the source selection transistor SST as a switch, the connection between the memory string MS and the source line SL can be controlled.
[0054] FIGS. 6A and 6B are diagrams for explaining an operation method of a semiconductor device according to an embodiment of the present invention. Hereinafter, descriptions overlapping with the previously described content can be omitted.
[0055] Referring to FIG. 6A, during the erase operation, a turn-on voltage can be applied to the drain selection lines DSL1 and DSL2, and a ground voltage can be applied to the bit lines BL1 and BL2. A turn-on voltage can be applied to the source selection line SSL, and a ground voltage can be applied to the source line SL. As a result, the memory strings MS1 to MS4 can be connected to the bit lines BL1 and BL2 and the source line SL at the ground level, and the channel potential of the memory strings MS1 to MS4 can have the ground level. An erase voltage Vers can be applied to the word lines WL1 to WLn. As a result, the ferroelectric films of the ferroelectric memory cells MC1 to MCn can have the first polarization state. Therefore, an erase operation can be performed on all the memory strings MS1 to MS4 belonging to the memory block.
[0056] Referring to FIG. 6B, a ground voltage can be applied to the source selection line SSL, and a source voltage having a level higher than the ground level can be applied to the source line SL. Here, the source voltage may be about 2V. Thereby, the source selection transistor SST can be turned off. A turn-on voltage can be applied to the selected first drain selection line DSL1, and a first bit line voltage can be applied to the selected first bit line BL1. Here, the first bit line voltage may be the ground voltage. Thereby, the channel potential of the selected first memory string MS1 can have the ground level.
[0057] A program voltage Vpgm can be applied to the selected word line WL2, and a pass voltage Vpass can be applied to the non-selected word lines WL1, WL3 to WLn. Here, the pass voltage Vpass may be Vpgm / 2. Thereby, the ferroelectric film of the selected second memory cell MC2 can have a second polarization state. Therefore, a program operation can be performed on the selected second memory cell MC2.
[0058] On the other hand, among the non-selected memory strings MS2 to MS4, the second memory string MS2 can share the selected first memory string MS1 and the first drain selection line DSL1, and does not necessarily have to share the first bit line BL1. Therefore, a second bit line voltage higher than the first bit line voltage can be applied to the non-selected second bit line BL2. Here, the second bit line voltage may be the operating voltage Vcc. Thereby, the drain selection transistor DST may be turned off, and the channel of the second memory string MS2 may be floated. The floated channel may be boosted compared to the program voltage Vpgm and the pass voltage Vpass, and the program operation of the non-selected second memory string MS2 can be inhibited.
[0059] Among the non-selected memory strings MS2 to MS4, the third memory string MS3 does not have to share the selected first memory string MS1 and the first drain selection line DSL1, and can share the first bit line BL1. Therefore, a ground voltage can be applied to the non-selected second drain selection line DSL2, and the program operation of the non-selected third memory string MS3 can be inhibited.
[0060] Among the non-selected memory strings MS2 to MS4, the fourth memory string MS4 does not have to share the selected first memory string MS1 and the first drain selection line DSL1, and does not have to share the first bit line BL1. A ground voltage can be applied to the non-selected second drain selection line DSL2, and a second bit line voltage higher than the first bit line voltage can be applied to the non-selected second bit line BL2. As an example, the second bit line voltage may be Vpgm / 2. Thereby, the program operation of the non-selected fourth memory string MS4 can be inhibited.
[0061] FIG. 7 is a diagram for explaining the structure of a semiconductor device according to an embodiment of the present invention. Hereinafter, descriptions overlapping with those described above can be omitted.
[0062] Referring to FIG. 7, the semiconductor device can include a gate structure GST, a metal channel film 75, a first semiconductor channel film 76, and a ferroelectric film 74. The semiconductor device can further include at least one of a substrate 60, an insulating film 61, a source line 62, a buffer film 63, a source selection line 64, a second semiconductor channel film 66, a second insulating core 67, an interface film 73, and a first insulating core 77.
[0063] The gate structure GST can include a conductive film 71 and an insulating film 72 laminated alternately. As an example, the conductive film 71 may be a word line or a drain selection line. The conductive film 71 can include a barrier film 71A and a metal film 71B inside the barrier film 71A.
[0064] A source line 62 may be positioned between the substrate 60 and the gate structure GST. The source line 62 can include a conductive material such as polysilicon. A source selection line 64 may be positioned between the source line 62 and the gate structure GST. The source selection line 64 can include a conductive material such as polysilicon. A buffer film 63 may be positioned between the source line 62 and the source selection line 64. The buffer film 63 may be for insulating the source line 62 and the source selection line 64 from each other and can include an insulating material such as an oxide. An insulating film 61 may be positioned between the substrate 60 and the source line 62. The insulating film 61 may be for insulating the substrate 60 and the source line 62 from each other and can include an insulating material such as an oxide.
[0065] The metal channel film 75 can extend through the gate structure GST. The metal channel film 75 can include a first metal film 75A, a barrier film 75B, and a second metal film 75C. The barrier film 75B can surround the second metal film 75C, and the first metal film 75A can surround the barrier film 75B. As an example, the first metal film 75A can include titanium (Ti), the barrier film 75B can include a metal nitride such as titanium nitride (TiN), and the second metal film 75C can include tungsten (W).
[0066] The first semiconductor channel film 76 can extend through the gate structure GST and can be connectable to the metal channel film 75. The first semiconductor channel film 76 can include a polysilicon film 76A and a metal silicide film 76B. The metal silicide film 76B may be positioned between the polysilicon film 76A and the metal channel film 75. A first insulating core 77 may be positioned within the first semiconductor channel film 76.
[0067] The second semiconductor channel film 66 can extend through the source selection line 64 and can be connected to the metal channel film 75 and the source line 62. The second semiconductor channel film 66 can penetrate the source selection line 64 and the buffer film 63 and can extend into the source line 62. A second insulating core 67 may be located within the second semiconductor channel film 66.
[0068] The second semiconductor channel film 66 can include a first semiconductor pattern 66A and a second semiconductor pattern 66B. The second semiconductor pattern 66B can connect the source line 62 and the metal channel film 75. The first semiconductor pattern 66A can partially surround the sidewall of the second semiconductor pattern 66B. The first semiconductor pattern 66A may be located between the second semiconductor pattern 66B and the ferroelectric film 74.
[0069] The second semiconductor channel film 66 can include polysilicon. The second semiconductor channel film 66 can include a metal silicide film 66C located at a portion in contact with the metal channel film 75. Thereby, an ohmic contact can be formed between the second semiconductor channel film 66 and the metal channel film 75.
[0070] The ferroelectric film 74 can surround the first semiconductor channel film 76, the metal channel film 75, and the second semiconductor channel film 66. The ferroelectric film 74 can surround the first semiconductor pattern 66A and can expose the second semiconductor pattern 66B. The interface film 73 can surround the ferroelectric film 74 and can expose the second semiconductor pattern 66B.
[0071] According to the structure as described above, ferroelectric memory cells MC may be located in the intersecting region of the metal channel film 75 and the conductive film 71. Drain selection transistors DST may be located in the intersecting region of the first semiconductor channel film 76 and the conductive film 71. Source selection transistors SST may be located in the intersecting region of the second semiconductor channel film 66 and the source selection line 64. At least one source selection transistor SST, stacked ferroelectric memory cells MC, and at least one drain selection transistor DST stacked along the interconnected second semiconductor channel film 66, metal channel film 75, and first semiconductor channel film 76 can constitute one memory string.
[0072] Figures 8A to 8F are diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. Hereinafter, descriptions overlapping with those described above can be omitted.
[0073] Referring to Figure 8A, an insulating film 81, a source line 82, a buffer film 83, and a source selection line 84 can be formed on a substrate 80. The source line 82 can include polysilicon, the buffer film 83 can include an oxide, and the source selection line 84 can include polysilicon.
[0074] Next, a stack ST can be formed on the source selection line 84. The stack ST can include a first material film 91 and a second material film 92 stacked alternately. The first material film 91 may be for forming gate lines such as word lines and drain selection lines. The first material film 91 can include a sacrificial material such as nitride or a conductive material such as polysilicon or metal. The second material film 92 may be for insulating the stacked gate lines from each other. The second material film 92 can include an insulating material such as oxide, nitride, or void.
[0075] Next, a first opening OP1 can be formed in the stack ST. The first opening OP1 can extend into the source selection line 84 through the stack ST. The first opening OP1 can have a depth that exposes the buffer film 83.
[0076] Next, an interface film 93 can be formed in the first opening OP1. The interface film 93 may be formed along the inner surface of the first opening OP1. The interface film 93 may be formed on the inner wall and bottom surface of the first opening OP1. The interface film 93 can contain a dielectric material such as tantalum oxide (Ta2O5).
[0077] Next, a ferroelectric film 94 can be formed in the first opening OP1. The ferroelectric film 94 may be formed along the profile of the interface film 93. The ferroelectric film 94 may be formed on the inner wall and bottom surface of the first opening OP1.
[0078] Next, a first semiconductor pattern 96A can be formed in the first opening OP1. The first semiconductor pattern 96A may be formed along the profile of the ferroelectric film 94. The first semiconductor pattern 96A may be formed on the inner wall and bottom surface of the first opening OP1.
[0079] Referring to FIG. 8B, a second opening OP2 can be formed. The first semiconductor pattern 96A, the ferroelectric film 94, and the interface film 93 can be etched to expose the buffer film 83, and the buffer film 83 can be etched to form the second opening OP2. The second opening OP2 can expose the source line 82 and can extend into the source line 82. Thereby, an opening can be formed that penetrates the stack ST, the source selection line 84, and the buffer film 83 and exposes the source line 82.
[0080] Next, the second semiconductor pattern 96B can be formed in the first opening OP1 and the second opening OP2. The second semiconductor pattern 96B may be formed along the profile of the first semiconductor pattern 96A and may be formed on the inner wall and bottom surface of the second opening OP2. The second semiconductor pattern 96B can be connected to the source line 82.
[0081] Referring to FIG. 8C, a second insulating core 97 can be formed in the second semiconductor pattern 96B. An insulating film can be formed in the first opening OP1 and the second opening OP2, and the insulating film can be partially etched to form the second insulating core 97. The second insulating core 97 can fill the second opening OP2 and can fill the lower part of the first opening OP1. The upper surface of the second insulating core 97 may be positioned corresponding to the upper surface of the source selection line 84.
[0082] Referring to FIG. 8D, the second semiconductor pattern 96B and the first semiconductor pattern 96A exposed by the second insulating core 97 can be etched. The portion corresponding to the stack ST in the first semiconductor pattern 96A and the second semiconductor pattern 96B can be removed. Thereby, the second semiconductor channel film 96 including the first semiconductor pattern 96A and the second semiconductor pattern 96B can be formed. The second semiconductor channel film 96 can extend into the source line 82 via the source selection line 84 and can be connected to the source line 82.
[0083] Next, the metal channel film 95 can be formed. First, the first metal film 95A can be formed along the profiles of the ferroelectric film 94, the second semiconductor channel film 96, and the second insulating core 97 exposed through the first opening OP1. Next, a barrier film 95B can be formed in the first metal film 95A, and a second metal film 95C can be formed in the barrier film 95B. The first metal film 95A can be in contact with the second semiconductor channel film 96. The portion of the second semiconductor channel film 96 that abuts against the first metal film 95A can be silicided to form a metal silicide film 96C.
[0084] Referring to FIG. 8E, the metal channel film 95 can be partially etched to form the third opening OP3. A portion of the metal channel film 95 corresponding to the drain selection line can be removed, and the ferroelectric film 94 can be exposed.
[0085] Referring to FIG. 8F, the first semiconductor channel film 106 can be formed in the third opening OP3. The first semiconductor channel film 106 can at least partially fill the third opening OP3. The first semiconductor channel film 106 may be formed along the profiles of the ferroelectric film 94 and the metal channel film 95. A portion of the first semiconductor channel film 106 that contacts the metal channel film 95 can be silicided to form a metal silicide film. Next, the first insulating core 107 can be formed in the first semiconductor channel film 106. The third opening OP3 may be filled by the first insulating core 107.
[0086] Next, the first material film 91 can be replaced with the third material film 99. As an example, after removing the first material film 91 to form the fourth opening OP4, the third material film 99 can be formed in the fourth opening OP4. After forming the barrier film 99A in the fourth opening OP4, the metal film 99B can be formed in the barrier film 99A. The barrier film 99A can include titanium nitride (TiN), and the metal film 99B can include tungsten (W).
[0087] Thereby, a gate structure GST including the second material film 92 and the third material film 99 laminated alternately may be formed. A source selection transistor may be formed in the region where the source selection line 84 intersects with the second semiconductor channel film 96, a ferroelectric memory cell may be formed in the region where the third material film 99 intersects with the metal channel film 95, and a drain selection transistor may be formed in the region where the first semiconductor channel film 106 intersects with the third material film 99.
[0088] On the one hand, when the first material film 91 contains a conductive material, the step of replacing the first material film 91 with the third material film 99 can be omitted. In this case, the first material film 91 can be used as a gate line, and the laminate ST can be used as a gate structure GST. Also, it is possible to omit at least one of the insulating film 81, the source line 82, the buffer film 83, and the source selection line 84.
[0089] According to the manufacturing method as described above, a source selection transistor including the second semiconductor channel film 96, a ferroelectric memory cell including the metal channel film 95, and a drain selection transistor including the first semiconductor channel film 106 can be formed.
[0090] As described above, the embodiments according to the technical idea of the present invention have been described with reference to the attached drawings, but this is merely for explaining the embodiments according to the concept of the present invention, and the present invention is not limited to the above embodiments. Within the scope not departing from the technical idea of the present invention, various forms of substitution, modification, change, and combination of the embodiments are possible by those having ordinary knowledge in the technical field to which the present invention pertains, and these also belong to the scope of the present invention.
Explanation of Reference Numerals
[0091] 31: Conductive film, 31A: Barrier film 31B: Metal film, 32: Insulating film 33: Interface film, 34: Ferroelectric film 35: Metal channel film, 35A: First metal film 35B: Barrier film, 35C: Second metal film 36: First semiconductor channel film, 36A: Polysilicon film 36B: Metal silicide film, 37: Insulating core 40: Substrate, 41: First material film 42: Second material film, 43: Interface film 44: Ferroelectric film, 45: Metal channel film 45A: First metal film, 45B: Barrier film 45C: Second metal film, 46: First semiconductor channel film 46A: Metal silicide film, 46B: Polysilicon film 47: Insulating core, 49: Third substance film 49A: Barrier film, 49B: Metal film 60: Substrate, 61: Insulating film 62: Source line, 63: Buffer film 64: Source selection line, 66: Second semiconductor channel film 66A: First semiconductor pattern, 66B: Second semiconductor pattern 66C: Metal silicide film, 67: Second insulating core 71: Conductive film, 71A: Barrier film 71B: Metal film, 72: Insulating film 73: Interface film, 74: Ferroelectric film 76: First semiconductor channel film, 76A: Polysilicon film 76B: Metal silicide film, 77: First insulating core 80: Substrate, 81: Insulating film 82: Source line, 83: Buffer film 84: Source selection line, 91: First substance film 92: Second substance film, 93: Interface film 94: Ferroelectric film, 95: Metal channel film 95A: First metal film, 95B: Barrier film 95C: Second metal film, 96: Second semiconductor channel film 96A: First semiconductor pattern, 96B: Second semiconductor pattern 96C: Metal silicide film, 97: Second insulating core 99: Third substance film, 99A: Barrier film 99B: Metal film, 106: First semiconductor channel film 107: First insulating core
Claims
1. A gate structure including a conductive film and an insulating film laminated alternately, a metal channel film extending through the gate structure, a first semiconductor channel film extending through the gate structure and connected to the metal channel film, and a ferroelectric film surrounding the metal channel film and the first semiconductor channel film A semiconductor device including the above.
2. A drain select transistor is located in a region where the first semiconductor channel film intersects with the conductive film, A ferroelectric memory cell is located in a region where the metal channel film intersects with the conductive film, The semiconductor device according to Claim 1.
3. The first semiconductor channel film includes a polysilicon film, and a metal silicide film located between the polysilicon film and the metal channel film, The semiconductor device according to Claim 1.
4. A source line, a source select line located between the source line and the gate structure, and a second semiconductor channel film extending through the source select line and connected to the metal channel film and the source line The semiconductor device according to Claim 1, further including the above.
5. A drain select transistor is located in a region where the first semiconductor channel film intersects with the conductive film, A source select transistor is located in a region where the second semiconductor channel film intersects with the source select line, A ferroelectric memory cell is located in a region where the metal channel film intersects with the conductive film, The semiconductor device according to Claim 4.
6. The conductive film includes a metal, and the source select line includes polysilicon, The semiconductor device according to Claim 4.
7. An interface film surrounding the ferroelectric film The semiconductor device according to Claim 1, further including the above.
8. The interface film contains tantalum oxide (Ta ２ O ５ ). The semiconductor device according to Claim 7.
9. An insulating core located within the first semiconductor channel film The semiconductor device according to Claim 1, further including the above.
10. The first semiconductor channel film surrounds the sidewall of the insulating core and extends between the metal channel film and the insulating core, The semiconductor device according to Claim 9.
11. A bit line, a memory string including a ferroelectric memory cell including a metal channel film and a drain select transistor including a first semiconductor channel film, a word line connected to the ferroelectric memory cell, and a drain select line connected to the drain select transistor and controlling the connection between the memory string and the bit line A semiconductor device including
12. During an erase operation, applying a negative erase voltage to the word line The semiconductor device according to claim 11.
13. During the erase operation, applying a turn-on voltage to the drain selection line and applying a ground voltage to the bit line The semiconductor device according to claim 12.
14. During a program operation, applying a program voltage to a selected word line among the word lines and applying a pass voltage to a non-selected word line The semiconductor device according to claim 11.
15. During the program operation, applying a first bit line voltage to a selected bit line among the bit lines and applying a second bit line voltage at a level higher than the first bit line voltage to a non-selected bit line The semiconductor device according to claim 14.
16. The first bit line voltage is a ground voltage The semiconductor device according to claim 15.
17. During the program operation Applying a turn-on voltage to a selected drain selection line among the drain selection lines and applying a ground voltage to a non-selected drain selection line The semiconductor device according to claim 15.
18. A source line and A source selection line for controlling the connection between the source line and the memory string Further including Each of the memory strings includes a source selection transistor including a second semiconductor channel film The semiconductor device according to claim 11.
19. During an erase operation, applying a turn-on voltage to the source selection line and applying a ground voltage to the source line The semiconductor device according to claim 18.
20. During a program operation, applying a ground voltage to the source selection line The semiconductor device according to claim 18.
21. Forming a stack including alternately stacked first and second material films Forming a first opening in the stack Forming a ferroelectric film in the first opening Forming a metal channel film in the ferroelectric film Partially etching the metal channel film to form a second opening Forming a first semiconductor channel film in the second opening A method of manufacturing a semiconductor device including
22. The step of forming the metal channel film Forming a first metal film in the ferroelectric film Forming a barrier film in the first metal film forming a second metal film within the barrier film; The method of manufacturing a semiconductor device according to claim 21.
23. Before forming the ferroelectric film, forming an interface film within the first opening The method of manufacturing a semiconductor device according to claim 21, further comprising.
24. The interface film contains tantalum oxide (Ta ２ O ５ ). The method of manufacturing a semiconductor device according to claim 23.
25. forming a metal silicide film between the first semiconductor channel film and the metal channel film The method of manufacturing a semiconductor device according to claim 21, further comprising.
26. replacing the first material film with a third material film The method of manufacturing a semiconductor device according to claim 21, further comprising.
27. forming a source line; forming a source selection line on the source line; forming a stack including a first material film and a second material film laminated alternately on the source selection line; forming an opening extending into the source line through the stack and the source selection line; forming a second semiconductor channel film within the opening, penetrating the source selection line and connected to the source line; forming a metal channel film within the opening, extending through the stack and connected to the second semiconductor channel film; forming a first semiconductor channel film within the opening, extending through the stack and connected to the metal channel film A method of manufacturing a semiconductor device including.
28. The step of forming the opening includes forming a first opening extending into the source selection line through the stack; forming a ferroelectric film within the first opening; forming a first semiconductor pattern within the ferroelectric film; etching the ferroelectric film and the first semiconductor pattern to form a second opening exposing the source line, including. The method of manufacturing a semiconductor device according to claim 27.
29. The step of forming the second semiconductor channel film includes forming a second semiconductor pattern within the first opening and the second opening; removing portions corresponding to the stack among the first semiconductor pattern and the second semiconductor pattern, including. The method of manufacturing a semiconductor device according to claim 28.
30. Before forming the ferroelectric film, forming an interface film within the first opening The method of manufacturing a semiconductor device according to claim 28, further comprising
31. The interface film contains tantalum oxide (Ta ２ O ５ ). The method of manufacturing a semiconductor device according to claim 30.
32. The step of forming the metal channel film includes a step of forming a first metal film in the opening, a step of forming a barrier film in the first metal film, and a step of forming a second metal film in the barrier film, and includes The method of manufacturing a semiconductor device according to claim 27.
33. A step of forming a metal silicide film between the first semiconductor channel film and the metal channel film The method of manufacturing a semiconductor device according to claim 27, further comprising
34. A step of forming a metal silicide film between the second semiconductor channel film and the metal channel film The method of manufacturing a semiconductor device according to claim 27, further comprising
35. A step of replacing the first material film with a third material film The method of manufacturing a semiconductor device according to claim 27, further comprising