Semiconductor device, electronic apparatus, and vehicle

Abstract

To appropriately drive a capacitive load without impairing an abnormality protection function.SOLUTION: A semiconductor device 1 comprises, for example, an output switch 9, and an overheat protection circuit 36 that forcibly turns off the output switch 9 when a monitoring target temperature ΔTemp exceeds an overheat protection threshold Ttsd, and cancels the forcible turn-off of the output switch 9 when the monitoring target temperature ΔTemp falls below an overheat cancellation threshold TtsdL. The overheat protection threshold Ttsd is increased as the end-to-end voltage Vds of the output switch 9 becomes lower.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, an electronic device, and a vehicle.

Background Art

[0002] The applicant of the present application has proposed a number of new technologies so far regarding semiconductor devices called IPD [intelligent power device] and SPS [smart power switch] (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] However, there has been room for consideration regarding the driving method of capacitive loads (compatibility with abnormal protection functions) in conventional semiconductor devices.

[0005] For example, the semiconductor device according to the present disclosure includes an output switch and a thermal protection circuit configured to forcibly turn off the output switch when the monitored temperature exceeds a thermal protection threshold value and release the forced turn-off of the output switch when the monitored temperature falls below a thermal release threshold value, and the thermal protection threshold value is raised as the voltage across the output switch becomes lower.

Brief Description of the Drawings

[0006]

Figure 1

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Figure 17

[0007] [Detailed Description] <Electronic Device> Figure 1 is a diagram showing a configuration example of an electronic device including a semiconductor device. The electronic device A in this configuration example includes a semiconductor device 1, a DC power supply 2, and a load 3.

[0008] The semiconductor device 1 is a high-side switch IC (a type of IPD) that conducts / blocks between the DC power supply 2 and the load 3, and is formed by integrating a power MISFET [metal insulator semiconductor field effect transistor] 9 and a controller 10.

[0009] Also, the semiconductor device 1 includes a plurality of external electrodes as means for establishing an electrical connection with the outside of the device. Speaking with reference to this figure, the semiconductor device 1 includes a drain electrode 11 (corresponding to the power supply electrode VBB), a source electrode 12 (corresponding to the output electrode OUT), an input electrode 13 (corresponding to the input electrode IN), and a reference voltage electrode 14 (corresponding to the ground electrode GND).

[0010] The power MISFET 9 is an example of an insulated-gate power transistor (= output switch) and functions as a high-side switch element that conducts / blocks between the drain electrode 11 and the source electrode 12.

[0011] The controller 10 includes a plurality of types of functional circuits that realize various functions. For example, the plurality of types of functional circuits include a circuit that generates a gate drive signal VG for driving and controlling the power MISFET 9 based on an electrical signal from the outside.

[0012] The drain electrode 11 transmits the power supply voltage VB to the drain of the power MISFET 9 and the various circuits of the controller 10. The source electrode 12 is connected to the source of the power MISFET 9 and transmits the output voltage VOUT and the output current IOUT to the load 3. Note that an inductance component L (and a resistance component) generally accompanies the signal line (for example, a wire harness) laid between the source electrode 12 and the load 3. The input electrode 13 transmits an input voltage (input signal) for driving the controller 10. The reference voltage electrode 14 transmits a reference voltage (for example, a ground voltage) to the controller 10. Note that a resistance component R generally accompanies between the reference voltage electrode 14 and the ground terminal.

[0013] <Semiconductor Device (First Embodiment)> FIG. 2 is a diagram showing a first embodiment of the semiconductor device 1 (= the electrical structure of the semiconductor device 1 shown in FIG. 1). Hereinafter, the case where the semiconductor device 1 is mounted on a vehicle will be described as an example. Note that the semiconductor device 1 can be applied as a high-side switch for energization control of a light source such as a valve lamp or an LED [light emitting diode] lamp, or other types of electronic control devices when mounted on a vehicle.

[0014] The semiconductor device 1 includes a drain electrode 11, a source electrode 12, an input electrode 13, a reference voltage electrode 14, an enable electrode 15, a sense electrode 16, a gate control wiring 17, a power MISFET 9, and a controller 10.

[0015] The drain electrode 11 (= power supply electrode VBB) is connected to the DC power supply 2. The drain electrode 11 supplies the power supply voltage VB to the power MISFET 9 and the controller 10. The power supply voltage VB may be 10V or more and 20V or less. On the other hand, the source electrode 12 (= output electrode OUT) is connected to the load 3.

[0016] The input electrode 13 (= input electrode IN) may be connected to an MCU [micro controller unit], a DC / DC converter, an LDO [low drop out] regulator, etc. The input electrode 13 supplies the input voltage to the controller 10. The input voltage may be 1V or more and 10V or less. The reference voltage electrode 14 is connected to the reference voltage wiring (ground terminal). The reference voltage electrode 14 supplies the reference voltage to the power MISFET 9 and the controller 10.

[0017] The enable electrode 15 may be connected to the MCU. An electrical signal for enabling or disabling some or all of the functions of the controller 10 is input to the enable electrode 15. The sense electrode 16 transmits an electrical signal for detecting an abnormality of the controller 10 to the outside of the device. Note that the sense electrode 16 may be pulled up or pulled down by a resistor.

[0018] The gate of the power MISFET 9 is connected to the controller 10 (specifically, the gate control circuit 25 described later) via the gate control wiring 17. The drain of the power MISFET 9 is connected to the drain electrode 11. The source of the power MISFET 9 is connected to the controller 10 (specifically, the current detection circuit 27 described later) and the source electrode 12.

[0019] The controller 10 includes a sensor MISFET 21, an input circuit 22, a current / voltage control circuit 23, a protection circuit 24, a gate control circuit 25, an active clamp circuit 26, a current detection circuit 27, a power reverse connection protection circuit 28, and an abnormality detection circuit 29.

[0020] The gate of the sensor MISFET 21 is connected to the gate control circuit 25. The drain of the sensor MISFET 21 is connected to the drain electrode 11. The source of the sensor MISFET 21 is connected to the current detection circuit 27.

[0021] The input circuit 22 is connected to the input electrode 13 and the current / voltage control circuit 23. The input circuit 22 may include a Schmitt trigger circuit. The input circuit 22 shapes the waveform of the electrical signal applied to the input electrode 13. The signal generated by the input circuit 22 is input to the current / voltage control circuit 23.

[0022] The current / voltage control circuit 23 is connected to the protection circuit 24, the gate control circuit 25, the power reverse connection protection circuit 28, and the abnormality detection circuit 29. The current / voltage control circuit 23 may include a logic circuit.

[0023] The current / voltage control circuit 23 generates various voltages according to the electrical signal from the input circuit 22 and the electrical signal from the protection circuit 24. In this form, the current / voltage control circuit 23 includes a drive voltage generation circuit 30, a first constant voltage generation circuit 31, a second constant voltage generation circuit 32, and a reference voltage / reference current generation circuit 33.

[0024] The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25. The drive voltage may be set to a value obtained by subtracting a predetermined value from the power supply voltage VB. The drive voltage generation circuit 30 may generate a drive voltage of 5 V or more and 15 V or less obtained by subtracting 5 V from the power supply voltage VB. The drive voltage is input to the gate control circuit 25.

[0025] The first constant voltage generation circuit 31 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generation circuit 31 may include a Zener diode or a regulator circuit (here, a Zener diode). The first constant voltage may be 1 V or more and 5 V or less. The first constant voltage is input to the protection circuit 24 (more specifically, a load open detection circuit 35 or the like described later).

[0026] The second constant voltage generation circuit 32 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generation circuit 32 may include a Zener diode or a regulator circuit (here, a regulator circuit). The second constant voltage may be 1 V or more and 5 V or less. The second constant voltage is input to the protection circuit 24 (more specifically, the overheat protection circuit 36 and the low voltage malfunction suppression circuit 37 described later).

[0027] The reference voltage / reference current generation circuit 33 generates a reference voltage and a reference current for various circuits. The reference voltage may be 1 V or more and 5 V or less. The reference current may be 1 mA or more and 1 A or less. The reference voltage and the reference current are input to various circuits. When the various circuits include a comparator, the reference voltage and the reference current may be input to the comparator.

[0028] The protection circuit 24 is connected to the current / voltage control circuit 23, the gate control circuit 25, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The protection circuit 24 includes an overcurrent protection circuit 34, a load open detection circuit 35, an overheat protection circuit 36, and a low voltage malfunction suppression circuit 37.

[0029] The overcurrent protection circuit 34 protects the power MISFET 9 from overcurrent. The overcurrent protection circuit 34 is connected to the gate control circuit 25 and the source of the sensor MISFET 21. The overcurrent protection circuit 34 may include a current monitoring circuit. The signal generated by the overcurrent protection circuit 34 is input to the gate control circuit 25 (more specifically, the drive signal output circuit 40 described later).

[0030] The load open detection circuit 35 detects the short state and open state of the power MISFET 9. The load open detection circuit 35 is connected to the current / voltage control circuit 23 and the source of the power MISFET 9. The signal generated by the load open detection circuit 35 is input to the current / voltage control circuit 23.

[0031] The overheat protection circuit 36 monitors the temperature of the power MISFET 9 and protects the power MISFET 9 from excessive temperature rise. The overheat protection circuit 36 is connected to the current / voltage control circuit 23. The overheat protection circuit 36 may include a temperature sensing device such as a temperature sensing diode or a thermistor. The signal generated by the overheat protection circuit 36 is input to the current / voltage control circuit 23.

[0032] The low voltage malfunction suppression circuit 37 suppresses the malfunction of the power MISFET 9 when the power supply voltage VB is less than a predetermined value. The low voltage malfunction suppression circuit 37 is connected to the current / voltage control circuit 23. The signal generated by the low voltage malfunction suppression circuit 37 is input to the current / voltage control circuit 23.

[0033] The gate control circuit 25 controls the on state and off state of the power MISFET 9, and the on state and off state of the sensor MISFET 21, respectively. The gate control circuit 25 is connected to the current / voltage control circuit 23, the protection circuit 24, the gate of the power MISFET 9, and the gate of the sensor MISFET 21.

[0034] The gate control circuit 25 outputs a gate drive signal VG to the gate control wiring 17 in accordance with the electrical signals from the current / voltage control circuit 23 and the protection circuit 24. The gate drive signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17, respectively. Specifically speaking, the gate control circuit 25 turns on / off the power MISFET 9 by controlling the gate drive signal VG in accordance with the electrical signal (input signal) applied to the input electrode 13.

[0035] More specifically, the gate control circuit 25 includes an oscillation circuit 38, a charge pump circuit 39, and a drive signal output circuit 40. The oscillation circuit 38 oscillates in accordance with the electrical signal from the current / voltage control circuit 23 and generates a predetermined electrical signal. The electrical signal generated by the oscillation circuit 38 is input to the charge pump circuit 39. The charge pump circuit 39 generates a boosted voltage VCP based on the electrical signal from the oscillation circuit 38. The boosted voltage VCP generated by the charge pump circuit 39 is input to the drive signal output circuit 40.

[0036] The drive signal output circuit 40 operates in response to the boosted voltage VCP output from the charge pump circuit 39 and generates a gate drive signal VG in accordance with the electrical signal from the protection circuit 24 (more specifically, the overcurrent protection circuit 34). The gate drive signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. The sensor MISFET 21 and the power MISFET 9 are controlled simultaneously by the gate control circuit 25.

[0037] The active clamp circuit 26 protects the power MISFET 9 from the back electromotive force. The active clamp circuit 26 is connected to the drain electrode 11, the gate of the power MISFET 9, and the gate of the sensor MISFET 21. The active clamp circuit 26 may include a plurality of diodes.

[0038] The active clamp circuit 26 may include a plurality of diodes connected in forward bias to each other. The active clamp circuit 26 may include a plurality of diodes connected in reverse bias to each other. The active clamp circuit 26 may include a plurality of diodes connected in forward bias to each other and a plurality of diodes connected in reverse bias to each other.

[0039] The plurality of diodes may include pn junction diodes, or Zener diodes, or pn junction diodes and Zener diodes. The active clamp circuit 26 may include a plurality of Zener diodes connected in bias to each other. The active clamp circuit 26 may include a Zener diode and a pn junction diode connected in reverse bias to each other.

[0040] The current detection circuit 27 detects the current flowing through the power MISFET 9 and the sensor MISFET 21. The current detection circuit 27 is connected to the protection circuit 24, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The current detection circuit 27 generates a current detection signal according to the electrical signal (= output current IOUT) generated by the power MISFET 9 and the electrical signal (= sense current ISNS showing the same behavior as the output current IOUT) generated by the sensor MISFET 21. The current detection signal is input to the abnormality detection circuit 29.

[0041] The power reverse connection protection circuit 28 protects the current-voltage control circuit 23, the power MISFET 9, etc. from the reverse voltage when the DC power supply 2 is reversely connected. The power reverse connection protection circuit 28 is connected to the reference voltage electrode 14 and the current-voltage control circuit 23.

[0042] The abnormality detection circuit 29 monitors the voltage of the protection circuit 24. The abnormality detection circuit 29 is connected to the current-voltage control circuit 23, the protection circuit 24, and the current detection circuit 27. When an abnormality (such as voltage fluctuation) occurs in any of the overcurrent protection circuit 34, the load open detection circuit 35, the overheat protection circuit 36, and the low-voltage malfunction suppression circuit 37, the abnormality detection circuit 29 generates an abnormality detection signal corresponding to the voltage of the protection circuit 24 and outputs it externally.

[0043] More specifically, the abnormality detection circuit 29 includes a first multiplexer circuit 41 and a second multiplexer circuit 42. The first multiplexer circuit 41 includes two input parts, one output part, and one selection control input part. The protection circuit 24 and the current detection circuit 27 are respectively connected to the input parts of the first multiplexer circuit 41. The second multiplexer circuit 42 is connected to the output part of the first multiplexer circuit 41. The current-voltage control circuit 23 is connected to the selection control input part of the first multiplexer circuit 41.

[0044] The first multiplexer circuit 41 generates an abnormality detection signal according to the electrical signal from the current-voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 27. The abnormality detection signal generated by the first multiplexer circuit 41 is input to the second multiplexer circuit 42.

[0045] The second multiplexer circuit 42 includes two input parts and one output part. The output part of the second multiplexer circuit 42 and the enable electrode 15 are respectively connected to the input parts of the second multiplexer circuit 42. The sense electrode 16 is connected to the output part of the second multiplexer circuit 42.

[0046] When an MCU is connected to the enable electrode 15 and a resistor for pull-up or pull-down is connected to the sense electrode 16, an on signal is input from the MCU to the enable electrode 15, and an abnormality detection signal is extracted from the sense electrode 16. The abnormality detection signal is converted into an electrical signal by the resistor connected to the sense electrode 16. The state abnormality of the semiconductor device 1 is detected based on this electrical signal.

[0047] <Problems of Mechanical Fuses> FIG. 3 is a diagram showing an example of an electronic device equipped with a mechanical fuse. The electronic device B in this configuration example includes a control unit B10, a battery B20, a load B30, and a fuse box B40.

[0048] The control unit B10 drives the load B30 by receiving the supply of the power supply voltage VB from the battery B20 via the fuse box B40. Specifically in this figure, the control unit B10 includes a DC / DC converter B11, a microcomputer B12, an upper switch B13, a power supply electrode B14, an output electrode B15, and a reference voltage electrode B16. The control unit B10 may be, for example, an ECU [electronic control unit].

[0049] The DC / DC converter B11 generates a desired internal power supply voltage from the power supply voltage VB and outputs it to each part (such as the microcomputer B12) of the control unit B10.

[0050] The microcomputer B12 performs on / off control of the upper switch B13 by receiving the supply of the internal power supply voltage from the DC / DC converter B11.

[0051] The upper switch B13 is connected between the power supply electrode B14 and the output electrode B15, and is controlled to be on / off according to an instruction from the microcomputer B12.

[0052] The power supply electrode B14 receives the supply of the power supply voltage VB from the battery B20 via the fuse box B40. The output electrode B15 is connected to the load B30 via, for example, the wire W3. The reference voltage electrode B16 is connected to, for example, the ground terminal.

[0053] The fuse box B40 includes n fuses B41(1) to B41(n), an input electrode B42, and output electrodes B43(1) to B43(n).

[0054] The fuse B41(i) (where i = 1, 2, …, n) is connected between the input electrode B42 and the output electrode B43(i). The fuse B41(i) is a so-called mechanical fuse, and when a current exceeding its rating flows through itself, it is blown by Joule heat to protect the circuit.

[0055] The input electrode B42 is connected to the positive electrode terminal of the battery B20 (= the applied terminal of the power supply voltage VB) via, for example, the wire W1. The output electrode B43(1) is connected to the power supply electrode B14 of the control unit B10 via, for example, the wire W2.

[0056] There are two problems in the electronic device B using the fuse box B40. The first is that the reaction time of the fuse B41(i) (= the time required until it blows) is unknown and the accuracy is poor. Therefore, damage to the control unit B10 to be protected often becomes a problem. The second is that replacement work for the blown fuse B41(i) is required. In many cases, a complete system replacement (= replacement of the fuse box B40) is required.

[0057] In order to solve the above problems, for example, it is conceivable to use an electronic fuse (so-called e-fuse) by IPD instead of the mechanical fuse. However, the control unit B10 often has a unique input capacitor in subsystems such as the DC / DC converter B11. Therefore, the control unit B10 functions as a capacitive load having a large capacitance value (generally in the mF range) when viewed from the electronic fuse.

[0058] Therefore, in a typical IPD with an electronic fuse, the output switch must be large so that the overheat protection function does not activate even if a large inrush current flows when the control unit B10 starts up, which increases the cost of the IPD.

[0059] Incidentally, if a precharge circuit using discrete components is provided, it is possible to avoid increasing the size of the IPD output switch, but this would require an increase in the number of components and a larger PCB (printed circuit board), which could increase the cost of the entire electronic device.

[0060] A novel semiconductor device that can solve the above problems will be proposed below.

[0061] <Semiconductor Device (Second Embodiment)> 4 is a diagram showing a second embodiment of the semiconductor device 1 (i.e., a configuration example of the semiconductor device 1 replacing a mechanical fuse). In the electronic device B of this configuration example, the fuse box B40 is replaced with the semiconductor device 1, based on the above-mentioned FIG.

[0062] The control unit B10, which is externally attached to the source electrode 12 (=output electrode OUT) of the semiconductor device 1, functions as a capacitive load with a large capacitance value when viewed from the semiconductor device 1. Therefore, the control unit B10 is depicted equivalently as a parallel circuit of a capacitor C1 and a resistor R1. Also shown in this figure is a resistor R2 for pulling down the sense electrode 16 to the ground terminal.

[0063] The semiconductor device 1 has a configuration basically similar to that of the first embodiment (FIG. 2) described above, and further includes a CMODE enable electrode 51, an input circuit 52, and a mode control circuit 53. Therefore, the components already described are given the same reference numerals as in FIG. 2 to avoid redundant explanations, and the following description will focus on new components and components related to them.

[0064] The power MISFET 9 is an output switch that connects / disconnects the drain electrode 11 and the source electrode 12 in response to a gate drive signal VG.

[0065] The overcurrent protection circuit 34 detects the output current IOUT flowing through the power MISFET 9 and controls the gate drive signal VG so as to provide overcurrent protection.

[0066] The overheat protection circuit 36 detects the temperature to be monitored and controls the gate drive signal VG to provide overheat protection.

[0067] The temperature to be monitored may be a first temperature Temp1 detected in a power element forming region including the power MISFET 9. The first temperature Temp1 may be, for example, a pn junction temperature Tj1 of the power element forming region.

[0068] The monitored temperature may be a temperature difference ΔTemp (=Temp1-Temp2) between a first temperature Temp1 and a second temperature Temp2 detected in an area other than the power element forming area. The second temperature Temp2 may be, for example, a pn junction temperature Tj2 in the analog circuit forming area or the logic circuit forming area, or a case temperature Tc or an ambient temperature Ta of the semiconductor device 1.

[0069] The CMODE enable electrode 51 is an external electrode for switching the mode control circuit 53 between enabled and disabled.

[0070] The input circuit 52 shapes the waveform of the electrical signal applied to the CMODE enable electrode 51 and outputs it to the mode control circuit 53 .

[0071] The mode control circuit 53 generates a mode control signal S1 for switching between the normal mode and the capacitive load drive mode for each of the overcurrent protection circuit 34 and the overheat protection circuit 36. The mode control signal S1 is output to each of the overcurrent protection circuit 34 and the overheat protection circuit 36.

[0072] Note that the mode control circuit 53 becomes effective, for example, when the electrical signal applied to the CMODE enable electrode 51 is at a high level, and is in a state where the logic level of the mode control signal S1 can be switched. For example, the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the normal mode when the mode control signal S1 is at a high level, and are set to the capacitive load drive mode when the mode control signal S1 is at a low level.

[0073] In the capacitive load drive mode, the overcurrent protection circuit 34 performs a current limiting operation to limit the output current IOUT to be equal to or less than the overcurrent protection threshold Iocp. In particular, in the capacitive load drive mode, the overcurrent protection threshold Iocp is set to a second overcurrent protection threshold Iocp2 (for example, Iocp2 = Iocp1 × 0.7) that is lower than the first overcurrent protection threshold Iocp1 set in the normal mode.

[0074] Also, the overheat protection circuit 36 repeats the forced turn-off and restart of the power MISFET 9 each time the monitored temperature (for example, the previous temperature difference ΔTemp) rises to the overheat protection threshold Ttsd. In particular, in the capacitive load drive mode, the overheat protection threshold Ttsd is set to a second overheat protection threshold Ttsd2 (for example, Ttsd2 = 30°C) that is lower than the first overheat protection threshold Ttsd1 (for example, Ttsd1 = 90°C) set in the normal mode.

[0075] On the other hand, the mode control circuit 53 becomes ineffective, for example, when the electrical signal applied to the CMODE enable electrode 51 is at a low level. In this case, the mode control signal S1 is fixed at a high level. Therefore, the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the normal mode.

[0076] As described above, in the electronic device B of this configuration example, the prior fuse box B40 is replaced by the semiconductor device 1. That is, when the output current IOUT becomes excessive (for example, several tens to 100 A), the power MISFET 9 is forced to turn off, so that the output current IOUT is limited or cut off quickly and accurately. Therefore, both the semiconductor device 1 and the control unit B10 can be safely protected. Also, different from the configuration using a mechanical fuse, even when a failure occurs, the replacement work of the blown fuse B41(i) is not required.

[0077] Furthermore, the semiconductor device 1 has a capacitive load driving mode as its operation mode. Therefore, the capacitive load (the control unit B10 in this figure) can be appropriately driven without increasing the size of the power MISFET 9 or requiring additional external components.

[0078] Hereinafter, while paying attention to the abnormal protection operation of the semiconductor device 1, the difference between the normal mode and the capacitive load driving mode of the semiconductor device 1 will be described. From this description, the advantages of using the capacitive load driving mode will become clear.

[0079] <Abnormal protection operation> FIG. 5 is a diagram showing a first example of the abnormal protection operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this figure, the applied voltage of the input electrode IN (= input voltage), the output current IOUT, and the output voltage VOUT are depicted in order from the top.

[0080] Note that in this figure, the behavior when a resistive load (or inductive load) is driven by the semiconductor device 1 of the second embodiment (FIG. 4) is shown. In this case, when the electrical signal applied to the input electrode IN rises to a high level, the output voltage VOUT rises to the power supply voltage VB. Also, the output current IOUT reaches the target value (nominal value) without exceeding the overcurrent protection threshold Iocp.

[0081] The above-described behavior is independent of whether the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the normal mode or the capacitive load drive mode. In other words, when a resistive load or an inductive load is driven by the semiconductor device 1 of the second embodiment (FIG. 4), even if the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the capacitive load drive mode, there is no particular influence on the operation of the semiconductor device 1.

[0082] On the other hand, when a capacitive load is driven by the semiconductor device 1 of the second embodiment (FIG. 4), the behavior of the semiconductor device 1 differs depending on whether the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the normal mode or the capacitive load drive mode.

[0083] FIG. 6 is a diagram showing a second example of the abnormal protection operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this figure, the applied voltage (= input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted in order from the top.

[0084] Note that in this figure, the behavior when a capacitive load (for example, the control unit B10) is driven by the semiconductor device 1 of the second embodiment (FIG. 4) is shown. Also, in this figure, it is assumed that the electrical signal applied to the CMODE enable electrode 51 is at a low level and the mode control signal S1 is fixed at a high level. That is, in this figure, the behavior when the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the normal mode is shown.

[0085] In this case, when the electrical signal applied to the input electrode IN is raised to a high level, a large inrush current flows through the capacitive load, so the output current IOUT increases steeply. At this time, the overcurrent protection circuit 34 performs a current limiting operation so that the output current IOUT becomes equal to or less than the overcurrent protection threshold Iocp (= Iocp1).

[0086] Also, when the capacitance value of the capacitive load is large and the device size of the power MISFET 9 is small, the heat generation of the power MISFET 9 increases. As a result, the overheat protection circuit 36 repeats the forced turn-off and restart of the power MISFET 9 each time the monitored temperature (e.g., the previous temperature difference ΔTemp) rises to the overheat protection threshold Ttsd (= Ttsd1).

[0087] Note that a certain cooling time Tcd is required from when the power MISFET 9 is forced to turn off until it is restarted due to the overheat protection operation. During that time, the output current IOUT continues to be not supplied to the capacitive load. Therefore, as shown in this figure, there is a possibility of hindering the startup of the output voltage VOUT.

[0088] If the device size of the power MISFET 9 is increased, the overheat protection operation is less likely to be activated, so the output voltage VOUT can be correctly started up. However, as described above, increasing the size of the power MISFET 9 leads to an increase in the cost of the semiconductor device 1.

[0089] FIG. 7 is a diagram showing a third example of the abnormal protection operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this figure, the applied voltage (= input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted in order from the top.

[0090] Note that in this figure, as in the previous FIG. 6, the behavior when the capacitive load (e.g., the control unit B10) is driven by the semiconductor device 1 of the second embodiment (FIG. 4) is shown. Also, the fact that the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the normal mode is the same as before. However, the overcurrent protection operation in the normal mode is different from before.

[0091] Referring to this figure, the overcurrent protection circuit 34 performs an off-latch operation so as to continuously keep the power MISFET 9 turned off when the output current IOUT increases to the overcurrent protection threshold Iocp (= Iocp1).

[0092] Such an off-latch operation is extremely effective when aiming to meet strict safety standards such as the AEC-Q100-012 standard. However, in view of driving capacitive loads, it has to be said that it is unsuitable. This is because, with the forced off-latch of the power MISFET9, the supply of the output current IOUT to the capacitive load is completely cut off, so that the output voltage VOUT does not rise at all.

[0093] Therefore, when the overcurrent protection circuit 34 performs an off-latch operation, increasing the size of the power MISFET9 makes no sense at all, and an external precharge circuit becomes essential.

[0094] FIG. 8 is a diagram showing a fourth example of the abnormal protection operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this figure, the applied voltage of the input electrode IN (= input voltage), the output current IOUT, and the output voltage VOUT are depicted in order from the top.

[0095] Note that in this figure, as in FIGS. 6 and 7 described above, the behavior when the capacitive load (for example, the control unit B10) is driven by the semiconductor device 1 of the second embodiment (FIG. 4) is shown. However, it is different from the above in that the overcurrent protection circuit 34 and the overheat protection circuit 36 are set in the capacitive load drive mode instead of the normal mode.

[0096] Specifically in this figure, in the capacitive load drive mode, the overcurrent protection circuit 34 performs a current limiting operation to limit the output current IOUT to be equal to or lower than the overcurrent protection threshold Iocp (= Iocp2 < Iocp1). Also, each time the monitored temperature (for example, the above-mentioned temperature difference ΔTemp) rises to the overheat protection threshold Ttsd (= Ttsd2 < Ttsd1), the overheat protection circuit 36 repeatedly performs forced turn-off and restart of the power MISFET9.

[0097] In this way, in the capacitive load drive mode, both the overcurrent protection threshold Iocp and the overheat protection threshold Ttsd (at least the overheat protection threshold Ttsd) are set to be lower than those in the normal mode, and the forced turn-off and restart of the power MISFET9 are repeatedly performed.

[0098] Therefore, the cooling time Tcd required for restarting the power MISFET 9 after it has been forcibly turned off by the overheat protection operation is shortened, making it possible to charge the capacitive load and raise the output voltage VOUT without increasing the size of the power MISFET 9 or requiring an external precharge circuit.

[0099] In this way, in the capacitive load drive mode, it is possible to appropriately drive a capacitive load that is difficult to drive in the normal mode.

[0100] In the capacitive load driving mode, as described above, the overcurrent protection threshold Iocp and the overheat protection threshold Ttsd are lowered compared to those in the normal mode, so that the semiconductor device 1 and the capacitive load connected thereto (e.g., the control unit B10) are maintained within a safe operation area (SOA) while the capacitive load is being charged.

[0101] In addition, in the capacitive load driving mode, at least one of the second overcurrent protection threshold Iocp2 and the second overheat protection threshold Ttsd2 may be gradually increased to the first overcurrent protection threshold Iocp1 and the first overheat protection threshold Ttsd1 in response to an increase in the output voltage VOUT or over time.

[0102] In addition, the mode control circuit 53 may switch the overcurrent protection circuit 34 and the overheat protection circuit 36 from the capacitive load drive mode to the normal mode when a predetermined recovery condition (described in detail later) is satisfied (see "CMODE EXIT" in this figure).

[0103] For example, the overcurrent protection operation after returning to the normal mode may be a current limiting operation that limits the output current IOUT to an overcurrent protection threshold Iocp (=Iocp1) or less, similar to the capacitive load driving mode.

[0104] Furthermore, for example, the overcurrent protection operation after returning to the normal mode may be a hiccup operation in which the power MISFET 9 is forcibly turned off and restarted repeatedly every time the output current IOUT increases up to the overcurrent protection threshold Iocp (=Iocp1). Such a hiccup operation can suppress heat generation in the power MISFET 9 more effectively than the current limiting operation described above.

[0105] Furthermore, for example, the overcurrent protection operation after returning to the normal mode may be an off-latch operation that forcibly keeps the power MISFET 9 off when the output current IOUT increases to the overcurrent protection threshold Iocp (=Iocp1). Such an off-latch operation further enhances safety when an overcurrent occurs compared to the above-mentioned current limiting operation and hiccup operation.

[0106] In this way, the semiconductor device 1 of this configuration example can switch between the normal mode and the capacitive load drive mode as needed, and is therefore compatible with process technologies that require stricter overcurrent protection operation, for example, when the on-resistance of the power MISFET 9 is relatively high.

[0107] To summarize the operation and architecture of the capacitive load driving mode described above, the most important attributes are:

[0108] (1) In the capacitive load drive mode, the overheat detection / restart operation (= the state in which the power MISFET 9 is forcibly turned off by overheat detection and restarted by overheat release) is forced as the overheat protection operation. This causes the capacitive load to be repeatedly charged until the output voltage VOUT rises sufficiently.

[0109] (2) In capacitive load drive mode, current limiting is enforced as an overcurrent protection operation, which prevents the output current IOUT from being latched off before the capacitive load is fully charged.

[0110] (3) In the capacitive load driving mode, the overcurrent protection threshold value Iocp is lowered (Iocp1 → Iocp2). As a result, the peak of the inrush current flowing through the capacitive load during charging is reduced. For example, the second overcurrent protection threshold value Iocp2 set in the capacitive load driving mode may be 70% of the first overcurrent protection threshold value Iocp1 set in the normal mode (i.e., Iocp2 = Iocp1 × 0.7). However, the above ratio is not limited to the above at all.

[0111] (4) In the capacitive load driving mode, the thermal protection threshold value Ttsd is lowered (Ttsd1 → Ttsd2). This has two effects. The first is the effect that the semiconductor device 1 is maintained in the safe operating region while the capacitive load is not fully charged, that is, while the capacitive load functions as a virtual short circuit. The second is the effect that since the semiconductor device 1 is quickly cooled to the overheat release temperature (safe temperature), the restart timing of the power MISFET 9 is advanced, and the capacitive load can continue to be charged. That is, since the charge pump effect is obtained, the output voltage VOUT can be surely raised.

[0112] (5) When the output voltage VOUT becomes higher than the predetermined threshold voltage Vth, it automatically returns from the capacitive load driving mode to the normal mode. That is, the above threshold voltage Vth corresponds to the end threshold of the capacitive load driving mode. Regarding the overcurrent protection operation after returning to the normal mode, as described above, any of the current limiting operation, hiccup operation, or off latch operation may be used.

[0113] (6) It may automatically return to the normal mode when a predetermined time (for example, 50 ms) has elapsed since the capacitive load driving mode was set. Thereby, even when an output short circuit or other failure occurs, the semiconductor device 1 can be maintained in the safe operating region.

[0114] (7) The semiconductor device 1 includes a CMODE enable electrode 51 for switching the validity of the mode control circuit 53 (and thus the capacitive load driving mode). Thereby, the user can arbitrarily determine whether to use the capacitive load driving mode. Furthermore, the validity of the mode control circuit 53 can be easily switched without applying a special gimmick (such as high-frequency PWM [pulse width modulation] driving or multi-level input) to the input electrode IN.

[0115] <Startup operation> FIG. 9 is a diagram showing a first example of the startup operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this figure, the output current IOUT, the output voltage VOUT, and the mode control signal S1 are depicted in order from the top.

[0116] Note that in this figure, the behavior when a pure resistive load (for example, R1 = 2Ω, C1 = 0F) is driven by the semiconductor device 1 of the second embodiment (FIG. 4) is shown. Also, the on-resistance of the power MISFET 9 is assumed to be 4 mΩ.

[0117] As shown in this figure, the mode control circuit 53 lowers the mode control signal S1 to a low level when the power MISFET 9 turns on. Therefore, the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the above-described capacitive load driving mode. Note that the capacitive load driving mode has no effect on the driving operation (for example, slew rate) of the resistive load.

[0118] Also, the mode control circuit 53 raises the mode control signal S1 to a high level when a predetermined return condition is satisfied. Thereby, the overcurrent protection circuit 34 and the overheat protection circuit 36 are switched from the capacitive load driving mode to the normal mode.

[0119] Referring to this figure, as the above return condition, it is detected that the output voltage VOUT has become higher than a predetermined threshold voltage Vth. For example, the threshold voltage Vth may be set to a voltage value (Vth = VB - Vx) that is lower than the power supply voltage VB (e.g., 14V) by the bias voltage Vx (e.g., 2V). According to such a setting, when the output voltage VOUT has sufficiently risen, the capacitive load driving mode is automatically terminated.

[0120] Also, as the above return condition, it may be detected that a predetermined time (e.g., 50 ms) has elapsed since the mode control signal S1 was lowered to the low level.

[0121] FIG. 10 is a diagram showing a second example of the startup operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this figure, as in the previous FIG. 9, the output current IOUT, the output voltage VOUT, and the mode control signal S1 are respectively depicted in order from the top.

[0122] Note that in this figure, the behavior when the capacitive load (e.g., R1 = 2Ω, C1 = 1mF) is driven by the semiconductor device 1 of the second embodiment (FIG. 4) is shown. Also, the on-resistance of the power MISFET 9 is 4mΩ.

[0123] As shown in this figure, at the on-transition of the power MISFET 9, the mode control signal S1 is lowered to the low level, and the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the capacitive load driving mode. As a result, the output voltage VOUT rises to the threshold voltage Vth within the required startup time t1 (e.g., less than 2 ms). The return conditions (output voltage monitoring or timer monitoring) from the capacitive load driving mode to the normal mode are the same as before.

[0124] FIG. 11 is a diagram showing a third example of the startup operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this figure, as in the previous FIGS. 9 and 10, the output current IOUT, the output voltage VOUT, and the mode control signal S1 are respectively depicted in order from the top.

[0125] 10. Note that this figure shows the behavior when the semiconductor device 1 of the second embodiment (FIG. 4) drives a capacitive load (for example, R1=2Ω, C1=4 mF) larger than that in FIG. 10. Also, the on-resistance of the power MISFET 9 is set to 4 mΩ.

[0126] As shown in the figure, when the power MISFET 9 is turned on, the mode control signal S1 is pulled low, and the overcurrent protection circuit 34 and the overheat protection circuit 36 are set to the capacitive load drive mode. As a result, the output voltage VOUT rises to the threshold voltage Vth within the required start-up time t2 (for example, less than 7.5 ms). The conditions for returning from the capacitive load drive mode to the normal mode (output voltage monitoring or timer monitoring) are the same as those described above.

[0127] <Considerations regarding large capacity driving> However, the important point for driving a large capacity by the semiconductor device 1 is not just the capacitance value of the capacitive load. The first point is shortening the driving time. In other words, the shorter the time required for the semiconductor device 1 to charge the capacitive load, the better. The second point concerns the resistor connected to the capacitive load. For example, in the aforementioned FIG. 4, it is desirable for the semiconductor device 1 to be able to drive the capacitor C1 even if the resistance value of the resistor R1 is small.

[0128] To satisfy these two points, it is effective to increase the overcurrent protection threshold Iocp (=Iocp2) and the overheat protection threshold Ttsd (=Ttsd2) set in the capacitive load drive mode (CMODE). However, simply increasing the overcurrent protection threshold Iocp and the overheat protection threshold Ttsd will impair the safety performance of the semiconductor device 1. As a result, there is a risk that the semiconductor device 1 will no longer pass the short circuit test compliant with AECQ100-012.

[0129] In view of the above considerations, a third embodiment will be proposed below, which can achieve both the safety performance of the semiconductor device 1 and the driving capability of the capacitive load.

[0130] <Semiconductor Device (Third Embodiment)> FIG. 12 is a diagram showing a third embodiment of the semiconductor device 1. In the semiconductor device 1 of the present embodiment, the overheat protection circuit 36 includes current sources CS1, CS2, and CS4, diodes D1 and D2, a comparator CMP, and an offset resistor Ros.

[0131] The anode of the diode D1 is connected to the applied end of the power supply voltage VB. The cathode of the diode D1 is connected to the applied end of the node voltage V1. The diode D1 is formed in the power element formation region including the power MISFET 9. The forward voltage drop Vf1 of the diode D1 has a negative temperature characteristic with respect to the first temperature Temp1 of the power element formation region. That is, the forward voltage drop Vf1 decreases as the first temperature Temp1 increases. Conversely, the node voltage V1 (= VB - Vf1) increases as the first temperature Temp1 increases. Thus, the diode D1 functions as a first temperature detection element.

[0132] The anode of the diode D2 is connected to the applied end of the power supply voltage VB. The cathode of the diode D2 is connected to the applied end of the node voltage V2. The diode D2 is formed outside the above-mentioned power element formation region. The forward voltage drop Vf2 of the diode D2 has a negative temperature characteristic with respect to the second temperature Temp2 outside the power element formation region. That is, the forward voltage drop Vf2 decreases as the second temperature Temp2 increases. Conversely, the node voltage V2 (= VB - Vf2) increases as the second temperature Temp2 increases. Thus, the diode D2 functions as a second temperature detection element.

[0133] The current source CS1 is connected between the applied end of the node voltage V1 and the applied end of the internal power supply voltage VBBM5. The current source CS1 generates a fixed current I1. The internal power supply voltage VBBM5 may be a floating voltage that is 5V lower than the power supply voltage VB.

[0134] The current source CS2 is connected between the applied end of the node voltage V2 and the applied end of the internal power supply voltage VBBM5. The current source CS2 generates a fixed current I2.

[0135] The offset resistor Ros and the current source CS4 are connected, for example, between the comparator CMP and the applied end of the internal power supply voltage VBBM5. The current source CS4 generates an added current I3 + I4 of a fixed current I3 and a variable current I4. The variable current I4 is increased or decreased according to the drain-source voltage Vds of the power MISFET9. Details of the current source CS4 will be described later.

[0136] In the overheat protection circuit 36 of this configuration example, the voltage across both ends of the offset resistor Ros corresponds to an offset voltage Vos (= (I3 + I4) × Ros) for determining the overheat protection threshold Ttsd. Note that the overheat protection threshold Ttsd is calculated by Vos / k. However, k is the temperature dependence coefficient (absolute value) of the forward voltage drops Vf1 and Vf2.

[0137] The comparator CMP compares the node voltage V1 input to the inverting input terminal (-) with the node voltage V2 input to the non-inverting input terminal (+) to generate an internal signal S15. More specifically, the comparator CMP compares the offset node voltage V1’ (= V1 - Vos) with the node voltage V2 to generate an internal signal S15. The internal signal S15 becomes high level when V1’ < V2. On the other hand, the internal signal S15 becomes low level when V1’ > V2.

[0138] First, consider the case where the detection voltage (V1 - V2) corresponding to the temperature difference ΔTemp is lower than the offset voltage Vos. In this case, the offset node voltage V1’ becomes lower than the node voltage V2. As a result, the internal signal S15 becomes high level.

[0139] Next, consider the case where the detection voltage (V1 - V2) corresponding to the temperature difference ΔTemp is higher than the offset voltage Vos. In this case, the offset node voltage V1’ becomes higher than the node voltage V2. As a result, the internal signal S15 becomes low level.

[0140] Note that the internal signal S15 can be understood as an overheat protection signal for forcibly turning off the power MISFET9. For example, when the internal signal S15 is at a low level, the power MISFET9 may be forcibly turned off. On the other hand, when the internal signal S15 is at a high level, the forced turn-off of the power MISFET9 may be released.

[0141] Incidentally, in the equilibrium state of the overheat protection circuit 36, that is, in a state where the detected voltage (V1 - V2) corresponding to the temperature difference ΔTemp is equal to the offset voltage Vos, Vos = (I3 + I4) × Ros holds. Here, the added current I3 + I4 changes according to the variable current I4. Therefore, the offset voltage Vos changes according to the variable current I4. In other words, the overheat protection threshold Ttsd changes according to the variable current I4 (details will be described later).

[0142] FIG. 13 is a diagram showing a configuration example of the current source CS4 (particularly, the part for generating the variable current I4). The current source CS4 of this configuration example includes a current source CS6, an inverter INV4, transistors N5 to N9 (N-channel type field effect transistors in this figure), transistors P7 to P18 (P-channel type field effect transistors in this figure), and a resistor R17.

[0143] The current source CS6 is connected between the applied end of the power supply voltage VB and the drain of the transistor N5. The current source CS6 generates a fixed current I10.

[0144] The gates of the transistors N5 to N7 are all connected to the drain of the transistor N5. The sources of the transistors N5 to N7 are all connected to the applied end of the internal power supply voltage VBBM5. The transistors N5 to N7 connected in this way function as a current mirror that outputs the fixed current I10 input to the drain of the transistor N5 as the fixed current I11 and the fixed current I12 from the drains of the transistors N6 and N7, respectively, by mirroring.

[0145] The drain of the transistor P7 is connected to a first terminal of a resistor R17, a second terminal of the resistor R17 is connected to an application terminal of the output voltage VOUT, and a gate of the transistor P7 is connected to an application terminal of the internal signal S16.

[0146] The transistor P7 is in an off state when the internal signal S16 is at a high level, and in an on state when the internal signal S16 is at a low level. The internal signal S16 is at a low level when the semiconductor device 1 is in an active state (= a state in which the gate drive signal VG can be generated), and is at a high level when the semiconductor device 1 is in an inactive state. In other words, the transistor P7 is in an on state when the semiconductor device 1 is in an active state, and in an off state when the semiconductor device 1 is in an inactive state.

[0147] When the transistor P7 is in the on state, a variable current I13 (≈Vds / R17) according to the drain-source voltage Vds (=VB-VOUT) of the power MISFET 9 flows through a path from the application terminal of the power supply voltage VB via the transistor P8, the transistor P7, and the resistor R17 to the application terminal of the output voltage VOUT.

[0148] The sources of the transistors P8 and P9 are both connected to the terminal to which the power supply voltage VB is applied. The gates of the transistors P8 and P9 are both connected to the drain of the transistor P8. The drain of the transistor P9 is connected to the drain of the transistor N6. The transistors P8 and P9 connected in this manner function as a current mirror that mirrors the variable current I13 input to the drain of the transistor P8 and outputs it as a variable current I14 (≈Vds / R17) from the drain of the transistor P9.

[0149] The sources of transistors P10 to P14 are all connected to the applied end of the power supply voltage VB. The gates of transistors P10 to P14 are all connected to the drain of transistor P10. The drain of transistor P10 is connected to the drain of transistor N7. Transistors P10 to P14 connected in this way function as a current mirror that outputs fixed currents I15 and fixed currents I16 to I18 from the drains of transistors P11 to P14 respectively by mirroring the fixed current I12 input to the drain of transistor P10.

[0150] The source of transistor P15 is connected to the drain of transistor P11. The source of transistor P16 is connected to the drain of transistor P12. The source of transistor P17 is connected to the drain of transistor P13. The gates of transistors P15 to P17 are all connected to the drain of transistor P15. The drain of transistor P15 is connected to the drain of transistor P9 and the drain of transistor N6. Transistors P15 to P17 connected in this way function as a current mirror that outputs variable currents I20 and I21 (for example, both I19 / 2) from the drains of transistors P16 and P17 respectively by mirroring the variable current I19 (=I11 - I14) input to the drain of transistor P15.

[0151] The upper limit value of the variable current I19 is the fixed current I15. The upper limit value of the variable current I20 is the fixed current I16. The upper limit value of the variable current I21 is the fixed current I17.

[0152] Inverter INV4 generates internal signal S17 by inverting the logic level of internal signal S10 (= mode control signal S1). Therefore, internal signal S17 becomes low level when internal signal S10 is high level, and becomes high level when internal signal S10 is low level. That is, internal signal S17 becomes low level when semiconductor device 1 is in the normal mode (NORMAL), and becomes high level when semiconductor device 1 is in the capacitive load drive mode (CMODE).

[0153] The source of transistor P18 is connected to the drain of transistor P16. The drains of transistors P14, P17, and P18 are each connected to the drain of transistor N8. The gate of transistor P18 is connected to the applied end of internal signal S17.

[0154] Transistor P18 turns off when internal signal S17 is high level, and turns on when internal signal S17 is low level. That is, transistor P18 turns on when semiconductor device 1 is in the normal mode (NORMAL), and turns off when semiconductor device 1 is in the capacitive load drive mode (CMODE).

[0155] The sources of transistors N8 and N9 are each connected to the applied end of internal power supply voltage VBBM5. The gates of transistors N8 and N9 are each connected to the drain of transistor N8. Transistors N8 and N9 thus connected function as a current mirror that outputs variable current I23 (= I22) from the drain of transistor N9 by mirroring variable current I22 (= I18(+I20)+I21) input to the drain of transistor N8. Note that variable current I23 corresponds to variable current I4 in FIG. 12.

[0156] As described above, when the semiconductor device 1 is in the normal mode, the transistor P18 is turned on. Therefore, the variable current I4 becomes the current value (I18 + I19 / 2 + I19 / 2) obtained by adding the fixed current I18 and the variable currents I20 and I21. On the other hand, when the semiconductor device 1 is in the capacitive load driving mode (CMODE), the transistor P18 is turned off. Therefore, the variable current I4 becomes the current value (I18 + I19 / 2) obtained by adding the fixed current I18 and the variable current I21.

[0157] The variable current I19 is limited to a current value of i1 or less by the transistor P11. On the other hand, the transistor N6 can conduct current up to a current value of i2 (>i1). Therefore, when 0 ≦ I14 < i3 (where i3 = i2 - i1), that is, when 0 ≦ I13 < i4 (where i4 ∝ i3), the variable current I19 is maintained at the current value i1 even if the variable current I14 fluctuates. Note that the current value i4 corresponds to the current value when Vds = Vds1. Therefore, when 0 ≦ Vds < Vds1, the thermal protection threshold Ttsd does not depend on the drain-source voltage Vds.

[0158] Also, when i3 ≦ I14 < i2, that is, when i4 ≦ I13 < i5 (where i5 ∝ i2), the variable current I19 also fluctuates in response to the fluctuation of the variable current I14. Note that the current value i5 corresponds to the current value when Vds = Vds2 (>Vds1). Therefore, when Vds1 ≦ Vds < Vds2, the thermal protection threshold Ttsd depends on the drain-source voltage Vds.

[0159] When I14 ≧ i2, that is, when I13 ≧ i5, the variable current I19 stops flowing. Therefore, when Vds ≧ Vds2, the thermal protection threshold Ttsd does not depend on the drain-source voltage Vds again.

[0160] In summary, the set value Vds1 at which the Vds dependency of the overheat protection threshold Ttsd starts to take effect is determined by transistors N5, N6, and N7 and transistors P10 and P11. On the other hand, the set value Vds2 at which the Vds dependency of the overheat protection threshold Ttsd stops taking effect is determined by transistors N5 and N6.

[0161] 14 is a diagram showing the behavior of the change in the overheat protection threshold Ttsd. The vertical axis represents the temperature difference ΔTemp, which is the temperature to be monitored. The horizontal axis of this diagram represents the drain-source voltage Vds of the power MISFET 9.

[0162] For example, let's look at the overheat protection threshold Ttsd(@CMODE) in capacitive load drive mode (CMODE). When the drain-source voltage Vds falls below the set value Vds1, the overheat protection threshold Ttsd(@CMODE) becomes the set value Ttsd1. On the other hand, when the drain-source voltage Vds exceeds the set value Vds2, the overheat protection threshold Ttsd(@CMODE) becomes the set value Ttsd2. Furthermore, when the drain-source voltage Vds fluctuates between the set values Vds1 and Vds2, the overheat protection threshold Ttsd(@CMODE) increases or decreases between the set values Ttsd1 and Ttsd2.

[0163] In this way, the thermal protection threshold Ttsd(@CMODE) increases as the drain-source voltage Vds decreases. Note that the thermal protection threshold Ttsd(@NORMAL) for the normal mode (NORMAL) may be set to a higher temperature range than the thermal protection threshold Ttsd(@CMODE) for the capacitive load drive mode (CMODE).

[0164] The overheat protection circuit 36 forcibly turns off the power MISFET 9 when the temperature difference ΔTemp, which is the temperature to be monitored, exceeds the overheat protection threshold Ttsd (S15=L). On the other hand, the overheat protection circuit 36 cancels the forced turning off of the power MISFET 9 when the temperature difference ΔTemp falls below the overheat release threshold TtsdL (S15=H).

[0165] FIG. 15 is a diagram showing a first example (when not grounded) of the startup operation in the third embodiment. In this figure, the output voltage VOUT and the output current IOUT are depicted in order from the top. Note that "grounding" refers to an abnormal state in which the source electrode 12 (= output electrode OUT) of the semiconductor device 1 is short-circuited to the ground terminal or a low potential terminal equivalent thereto.

[0166] As shown in this figure, when the source electrode 12 (= output electrode OUT) of the semiconductor device 1 is not grounded, as the output voltage VOUT rises, the drain-source voltage Vds of the power MISFET 9 decreases. Therefore, the overheat protection threshold Ttsd is raised. As a result, the time t from when the overcurrent protection of the output current IOUT is applied until the overheat protection of the temperature difference ΔTemp is applied extends. Therefore, the driving ability of the capacitive load can be enhanced while keeping the overcurrent protection threshold Iocp low.

[0167] FIG. 16 is a diagram showing a second example (when grounded) of the startup operation in the third embodiment. In this figure, as in the previous FIG. 15, the output voltage VOUT and the output current IOUT are depicted in order from the top.

[0168] For example, in a short test compliant with AECQ100-012, the source electrode 12 (= output electrode OUT) of the semiconductor device 1 is set in a grounded state. At this time, the output voltage VOUT is maintained at approximately 0V. Therefore, the drain-source voltage Vds of the power MISFET 9 does not decrease. As a result, the overheat protection threshold Ttsd becomes the lower limit value. Therefore, the safety performance of the semiconductor device 1 is enhanced.

[0169] As described above, in the semiconductor device 1 of this embodiment, it is possible to achieve both the safety performance of the semiconductor device 1 and the driving ability of the capacitive load.

[0170] <Example of application to a low-side switch IC> In the above embodiment, a high-side switch IC that replaces a mechanical fuse is exemplified, but the target for implementing the capacitive load driving mode is not limited to this. For example, the capacitive load driving mode can be widely implemented in other IPDs as well.

[0171] For example, the foregoing power MISFET 9 may be provided as a low-side switch element that conducts / blocks between an output electrode to which one end of the load is connected and a reference voltage electrode to which a reference voltage (e.g., ground voltage) is applied.

[0172] In that case, the mode control circuit 53 may set the operation mode to the capacitive load driving mode when the output voltage VOUT applied to the output electrode is higher than a predetermined threshold voltage Vth', and set the operation mode to the normal mode when the output voltage VOUT is lower than the threshold voltage Vth'.

[0173] Note that the threshold voltage Vth' may be a voltage (=GND + Vy) generated with reference to a reference voltage (e.g., ground voltage). That is, the threshold voltage Vth' may be different from the foregoing threshold voltage Vth (=VB - Vx) generated with reference to the power supply voltage VB.

[0174] <Application to Vehicles> FIG. 17 is an external view showing a configuration example of a vehicle. The vehicle X in this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0175] The vehicle X includes, in addition to engine vehicles, electric vehicles (xEVs) such as battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles / plug-in hybrid vehicles (PHEVs / PHVs), or fuel cell electric vehicles / fuel cell vehicles (FCEVs / FCVs).

[0176] Note that the semiconductor device 1 described above can be incorporated into any of the electronic devices mounted on the vehicle X.

[0177] <Supplementary Note> According to the present disclosure, it is possible to appropriately drive a capacitive load without impairing the abnormal protection function. Hereinafter, the present disclosure will be supplemented.

[0178] [Supplementary Note 1] An output switch (9), A thermal protection circuit (36) configured to forcibly turn off the output switch (9) when the monitored temperature (ΔTemp) exceeds the thermal protection threshold value (Ttsd) and to cancel the forced turn-off of the output switch (9) when the monitored temperature (ΔTemp) falls below the thermal release threshold value (TtsdL), Comprising, The semiconductor device (1) in which the thermal protection threshold value (Ttsd) is raised as the voltage (Vds) between both ends of the output switch (9) is lower.

[0179] [Supplementary Note 2] The monitored temperature (ΔTemp) is the temperature difference (ΔTemp) between a first temperature (Temp1) detected in a power element region including the output switch (9) and a second temperature (Temp2) detected outside the power element region, of the semiconductor device (1) according to Supplementary Note 1.

[0180] [Supplementary Note 3] The thermal protection circuit (36) forcibly turns off the output switch (9) when a detection voltage (V1 - V2) corresponding to the temperature difference (ΔTemp) is higher than an offset voltage (Vos), and cancels the forced turn-off of the output switch (9) when the detection voltage (V1 - V2) is lower than the offset voltage (Vos), of the semiconductor device (1) according to Supplementary Note 2.

[0181] [Supplementary Note 4] The overheat protection circuit (36) of the semiconductor device (1) according to appended note 3 includes a current source (CS4) configured to generate a variable current (I4) that increases or decreases according to the voltage (Vds) across both ends of the output switch (9), and an offset resistor (Ros) configured to generate the offset voltage (Vos) according to the variable current (I4).

[0182] [Appended note 5] An overcurrent protection circuit (34) configured to limit the output current (IOUT) flowing through the output switch (9) to be equal to or less than the overcurrent protection threshold (Iocp). A mode control circuit (53) configured to switch between setting each of the overcurrent protection circuit (34) and the overheat protection circuit (36) to the normal mode (NORMAL) or the capacitive load driving mode (CMODE). The semiconductor device (1) further includes: In the capacitive load driving mode (CMODE), the overcurrent protection threshold (Iocp) and the overheat protection threshold (Ttsd) are lowered compared to the normal mode (NORMAL). The semiconductor device (1) according to any one of appended notes 1 to 4.

[0183] [Appended note 6] The mode control circuit (53) sets each of the overcurrent protection circuit (34) and the overheat protection circuit (36) to the capacitive load driving mode (CMODE) at the time of the on-transition of the output switch (9), and switches each of the overcurrent protection circuit (34) and the overheat protection circuit (36) from the capacitive load driving mode (CMODE) to the normal mode (NORMAL) when the return condition is satisfied. The semiconductor device (1) according to appended note 5.

[0184] [Appended note 7] In the normal mode, the overcurrent protection circuit (34) of the semiconductor device (1) according to Appendix 5 or 6 performs one of the following operations: a current limiting operation that limits the output current (IOUT) to be equal to or less than the overcurrent protection threshold (Ttsd); a hiccup operation that repeatedly forces the output switch (9) to turn off and restart each time the output current (IOUT) increases to the overcurrent protection threshold (Ttsd); or an off latch operation that continuously forces the output switch (9) to turn off when the output current (IOUT) increases to the overcurrent protection threshold (Ttsd).

[0185] [Appendix 8] The output switch (9) of the semiconductor device (1) according to any one of Appendices 1 to 7 is a high-side switch configured to conduct / block between the power supply electrode (VBB) and the output electrode (OUT), or a low-side switch configured to conduct / block between the output electrode (OUT) and the reference voltage electrode (GND).

[0186] [Appendix 9] An electronic device (B) comprising the semiconductor device (1) according to any one of Appendices 1 to 8, a load (B10) connected to the semiconductor device, and

[0187] [Appendix 10] A vehicle (X) comprising the electronic device (B) according to Appendix 9.

[0188] <Others> Note that various technical features disclosed in this specification can be variously modified without departing from the gist of the technical creation in addition to the above embodiments. That is, the above embodiments should be considered as illustrative in all respects and not restrictive. Also, the technical scope of the present disclosure is defined by the scope of the claims, and it should be understood that all modifications belonging to the meaning and scope equivalent to the scope of the claims are included.

Description of Reference Numerals

[0189] 1 Semiconductor device (high-side switch IC) 2 DC power supply 3 Load 9 Power MISFET (output switch) 10 Controller 11 Drain electrode (power supply electrode) 12 Source electrode (output electrode) 13 Input electrode 14 Reference voltage electrode 15 Enable electrode 16 Sense electrode 17 Gate control wiring 21 Sensor MISFET 22 Input circuit 23 Current / voltage control circuit 24 Protection circuit 25 Gate control circuit 26 Active clamp circuit 27 Current detection circuit 28 Power reverse connection protection circuit 29 Abnormality detection circuit 30 Drive voltage generation circuit 31 First constant voltage generation circuit 32 Second constant voltage generation circuit 33 Reference voltage / reference current generation circuit 34 Overcurrent protection circuit 35 Load open detection circuit 36 Overheat protection circuit 37 Low voltage malfunction suppression circuit 38 Oscillation circuit 39 Charge pump circuit 40 Drive signal output circuit 41 First multiplexer circuit 42 Second multiplexer circuit 51 CMODE enable electrode 52 Input circuit 53 Mode control circuit A Electronic device B Electronic device B10 Control unit (ECU) B11 DC / DC converter B12 Microcomputer Upper switch of B13 Power electrode of B14 Output electrode of B15 Reference voltage electrode of B16 Battery of B20 Load of B30 Fuse box of B40 Fuses of B41(1)~B41(n) Input electrode of B42 Output electrodes of B43(1)~B43(n) Capacitor of C1 Comparator of CMP Current sources of CS1, CS2, CS4, CS6 Diodes of D1, D2 Inverter of INV4 Inductance component of L Transistors (N-channel field-effect transistors) of N5~N9 Node of Nd Transistors (P-channel field-effect transistors) of P7~P18 Resistance component of R Resistors of R1, R2, R17 Offset resistor of Ros Wires of W1~W3 Vehicle of X

Claims

1. An output switch, a thermal protection circuit configured to forcibly turn off the output switch when the temperature to be monitored exceeds a thermal protection threshold value and to release the forced turn-off of the output switch when the temperature to be monitored falls below a thermal release threshold value, and a semiconductor device in which the thermal protection threshold value is raised as the voltage across the output switch becomes lower.

2. The semiconductor device according to claim 1, wherein the temperature to be monitored is a temperature difference between a first temperature detected in a power element region including the output switch and a second temperature detected outside the power element region.

3. The semiconductor device according to claim 2, wherein the thermal protection circuit forcibly turns off the output switch when a detection voltage corresponding to the temperature difference is higher than an offset voltage and releases the forced turn-off of the output switch when the detection voltage is lower than the offset voltage.

4. The semiconductor device according to claim 3, wherein the thermal protection circuit includes a current source configured to generate a variable current that increases or decreases according to the voltage across the output switch, and an offset resistor configured to generate the offset voltage according to the variable current.

5. an overcurrent protection circuit configured to limit an output current flowing through the output switch to be equal to or less than an overcurrent protection threshold value, and a mode control circuit configured to switch between setting each of the overcurrent protection circuit and the thermal protection circuit to a normal mode or a capacitive load driving mode, and in the capacitive load driving mode, the overcurrent protection threshold value and the thermal protection threshold value are lowered as compared with the normal mode. The semiconductor device according to claim 1.

6. The semiconductor device according to claim 5, wherein the mode control circuit sets each of the overcurrent protection circuit and the thermal protection circuit to the capacitive load driving mode at the time of an on-transition of the output switch, and switches each of the overcurrent protection circuit and the thermal protection circuit from the capacitive load driving mode to the normal mode when a return condition is satisfied.

7. In the normal mode, the overcurrent protection circuit performs any one of a current limiting operation of limiting the output current to be equal to or less than the overcurrent protection threshold value, a hiccup operation of repeatedly forcing the output switch off and restarting each time the output current increases up to the overcurrent protection threshold value, or an off latch operation of continuously forcing the output switch off when the output current increases up to the overcurrent protection threshold value. The semiconductor device according to claim 5.

8. The output switch is a high-side switch configured to conduct / interrupt between a power supply electrode and an output electrode, or a low-side switch configured to conduct / interrupt between an output electrode and a reference voltage electrode. The semiconductor device according to claim 1.

9. A semiconductor device according to any one of claims 1 to 8, A load connected to the semiconductor device, An electronic device comprising:

10. A vehicle comprising the electronic device according to claim 9.

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