Display device

Abstract

To provide a semiconductor device having a thin film transistor using an oxide semiconductor layer, in which a low power consumption semiconductor device is provided, and to provide a highly reliable semiconductor device in the semiconductor device having a thin film transistor using the oxide semiconductor layer.SOLUTION: In the semiconductor device, a gate electrode layer (gate wiring layer) and a wiring layer that electrically connects to a source electrode layer or a drain electrode layer intersect with each other via an insulating layer covering the oxide semiconductor layer of the thin film transistor and a gate insulating layer present in between. It is possible to reduce the parasitic capacitance formed by the laminated structure of the gate electrode layer, the gate insulating layer, and the source electrode layer or the drain electrode layer, and it is possible to realize low power consumption of the semiconductor device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology of constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as C and electro-optical devices, especially in switching of image display devices. Metal oxides exist in a wide variety of forms and are used for a variety of purposes. Indium oxide is a well-known material that is needed for applications such as liquid crystal displays. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using metal oxides with excellent semiconductor properties as the channel formation region are already known. (See Patent Documents 1 and 2).

[0005] Electrical devices using thin film transistors include mobile phones and laptop personal computers. For such portable electronic devices, The problem of power consumption, which affects continuous operation time, is significant. It is important for all parties to curb the increase in power consumption that accompanies larger sizes. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0007] In a semiconductor device having a thin film transistor using an oxide semiconductor layer, One of the objects is to provide a conductor device.

[0008] In a semiconductor device having a thin film transistor using an oxide semiconductor layer, One of the objects is to provide a conductor device. [Means for solving the problem]

[0009] In a semiconductor device, a gate electrode layer (gate wiring layer) and a source electrode layer or a drain electrode layer The wiring layer electrically connected to the insulating layer and the oxide semiconductor layer of the thin film transistor The gate electrode layer of the thin film transistor and the source electrode layer are interposed between the gate insulating layer and the source electrode. The gate electrode layer, the gate electrode layer, and the drain electrode layer are formed on the oxide semiconductor layer except that they partially overlap each other. The semiconductor device does not have a laminated structure of a gate insulating layer and a source electrode layer or a drain electrode layer.

[0010] Therefore, a stacked structure of a gate electrode layer, a gate insulating layer, and a source electrode layer or a drain electrode layer This reduces the parasitic capacitance formed by the Cut.

[0011] One embodiment of the configuration of the invention disclosed in this specification includes a gate electrode layer and a gate insulating film formed on the gate electrode layer. an oxide semiconductor layer on the gate insulating layer; and a source electrode layer and a drain electrode layer on the oxide semiconductor layer. and an oxide insulating layer in contact with the oxide semiconductor layer on the source electrode layer and the drain electrode layer. a wiring layer electrically connected to the source electrode layer or the drain electrode layer on the oxide insulating layer; an opening reaching the source electrode layer or the drain electrode layer is provided in the oxide insulating layer; The line layer is in contact with the source electrode layer or the drain electrode layer at the opening, and is connected to the gate electrode layer and the wiring layer. is a semiconductor device in which a gate insulating layer and an oxide semiconductor layer are interposed therebetween.

[0012] The source electrode layer and the drain electrode layer are preferably thin, with a thickness of 0.1 nm to 50 nm. The source electrode layer and the drain electrode layer are made of a thin conductive film. Therefore, the parasitic capacitance with the gate electrode layer can be reduced.

[0013] The source electrode layer and the drain electrode layer are made of a material containing a metal with high oxygen affinity. The metal having a high oxygen affinity is preferably titanium, aluminum, or manganese. , magnesium, zirconium, beryllium, or thorium. In this embodiment, the source electrode layer and the drain electrode layer are preferably made of a material having a thickness of 100 nm or less. A titanium film is used as the substrate.

[0014] When an oxide semiconductor layer is brought into contact with a metal layer having a high oxygen affinity and heat treatment is performed, the oxide semiconductor Oxygen atoms move from the silicon layer to the metal layer, increasing the carrier density near the interface. Thereby, a low-resistance region is formed near the interface, and the contact resistance between the oxide semiconductor layer and the source electrode layer and the drain electrode layer can be reduced.

[0015] Further, a heat-resistant conductive material may be used for the source electrode layer and the drain electrode layer. When a heat-resistant conductive material is used, alteration and deterioration of the source electrode layer and the drain electrode layer can be prevented even when a heat treatment is performed after forming the source electrode layer and the drain electrode layer.

[0016] Examples of the heat-resistant conductive material include an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing the above-described element as a component, an alloy film combining the above-described elements, or a nitride containing the above-described element as a component. Further, a conductive film having improved heat resistance by combining the above-described heat-resistant conductive material with a low-resistance conductive material such as aluminum (Al) or copper (Cu) may be used.

[0017] Further, the source electrode layer and the drain electrode layer may include a metal oxide layer. For example, a structure having a titanium oxide film between the oxide semiconductor layer and the titanium film, or a structure having a titanium oxide film (for example, a film thickness of 1 nm or more and 20 nm or less) between a titanium film (for example, a film thickness of 0.1 nm or more and 5 nm or less) and an oxide insulating layer may be used.

[0018] When the source electrode layer and the drain electrode layer have a thin film thickness that allows light to pass through, the source electrode layer and the drain electrode layer have light transmittance.

[0019] The wiring layer uses a conductive film having a lower resistance than the source electrode layer and the drain electrode layer. Specifically, Aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, A metal material such as scandium or an alloy material mainly composed of these can be used to form it in a single layer or in a laminated manner. In this embodiment, a laminated structure of an aluminum film for the first wiring layer and a titanium film for the second wiring layer is used as the wiring layer.

[0020] Another form of the configuration of the invention disclosed in this specification is to form a gate electrode layer, form a gate insulating layer on the gate electrode layer, form an oxide semiconductor layer on the gate insulating layer, dehydrate or dehydrogenate the oxide semiconductor layer, and then, without exposing it to the atmosphere, prevent re-mixing of water and hydrogen into the oxide semiconductor layer, form a source electrode layer and a drain electrode layer on the oxide semiconductor layer, form an oxide insulating layer in contact with a part of the oxide semiconductor layer on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, form an opening reaching the source electrode layer or the drain electrode layer in the oxide insulating layer, form a wiring layer in contact with the source electrode layer or the drain electrode layer in the opening and partially overlapping with the gate electrode layer through the gate insulating layer and the oxide insulating layer, and the wiring layer is thinner in film thickness and lower in resistance than the source electrode layer and the drain electrode layer, which is a method for manufacturing a semiconductor device.

[0021] Each of the above configurations solves at least one of the above problems.

[0022] Note that as the oxide semiconductor layer, it is a thin film represented by InMO3(ZnO) m (m>0), and a thin film transistor using the thin film as the oxide semiconductor layer is manufactured. Here, M represents one metal element or a plurality of metal elements selected from , Ga, Fe, Ni, Mn, and Co. For example, in addition to the case where M is Ga, there are cases such as Ga and Ni or Ga and Fe, G ​ The above metal elements other than a may be included. Also, in the above oxide semiconductor, in addition to the metal elements included as M , as impurity elements, there are those containing Fe, Ni and other transition metal elements, or oxides of the transition metals. In this specification, among the oxide semiconductor layers having a structure represented by InMO3(Zn O) m (m>0), an oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also referred to as an In-Ga-Z n-O-based non-single crystal film.

[0023] In addition to the above, as metal oxides applicable to the oxide semiconductor layer, In-Sn-O-based, I n-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga -Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al- Zn-O-based, In-O-based, Sn-O-based, Zn-O-based metal oxides can be applied. Also, silicon oxide may be included in the oxide semiconductor layer made of the above metal oxide.

[0024] Also, dehydration or dehydrogenation is a heat treatment at 400 °C or higher and 750 °C or lower, preferably 425 °C or higher and lower than the strain point of the substrate, in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.), which reduces impurities such as the contained moisture in the oxide semiconductor layer. Also, subsequent re-impregnation of water (H2O) can be prevented.

[0025] The heat treatment of dehydration or dehydrogenation is preferably carried out in a nitrogen atmosphere where H2O is 20 ppm or less. Also, it may be carried out in ultra-dry air where H2O is 20 ppm or less.

[0026] The heat treatment for dehydration or dehydrogenation can use heating methods such as those using an electric furnace, the GRTA (Gas Rapid Thermal Anneal) method that uses heated gas, or the LRTA (Lamp Rapid Thermal Anneal) method that uses lamp light, and other rapid heating methods. That is, it can use rapid heating methods such as those using an electric furnace, the GRTA (Gas Rapid Thermal Anneal) method that uses heated gas,

[0027] The oxide semiconductor layer that has undergone dehydration or dehydrogenation is such that when measured by TDS up to 450 °C for the oxide semiconductor layer after dehydration or dehydrogenation, two peaks of water are not detected, and at least one peak that appears around 300 °C is not detected. Therefore, for a thin film transistor using the oxide semiconductor layer that has undergone dehydration or dehydrogenation, when measured by TDS up to 45 0 °C, at least one peak of water that appears around 300 °C is not detected. And from the heating temperature T at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, it is slowly cooled without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, so that water or hydrogen is not mixed into the oxide semiconductor layer again. It is important that after performing dehydration or dehydrogenation to lower the resistance of the oxide semiconductor layer, that is, to make it N-type (N

[0028] etc.), and then increasing the resistance to make it I-type, when a thin film transistor is fabricated using the oxide semiconductor layer, the threshold voltage value of the thin film transistor can be made a plus, and a so-called normally-off switching element can be realized. It is desirable for a display device that a channel is formed at a positive threshold voltage as close as possible to 0 V for the gate voltage of the thin film transistor. Note that if the threshold voltage value of the thin film transistor is negative, a current flows between the source electrode and the drain electrode even when the gate voltage is 0 V, a so-called normally off state. - N + etc.), and then increasing the resistance to make it I-type, when a thin film transistor is fabricated using the oxide semiconductor layer, the threshold voltage value of the thin film transistor can be made a plus, and a so-called normally-off switching element can be realized. When a thin film transistor is formed with a channel formed at a positive threshold voltage as close as possible to 0 V for the gate voltage of the thin film transistor, it is desirable for a display device. Note that if the threshold voltage value of the thin film transistor is negative, a current flows between the source electrode and the drain electrode even when the gate voltage is 0 V, a so-called normally off state. This is desirable for a display device. Note that if the threshold voltage value of the thin film transistor is negative, a current flows between the source electrode and the drain electrode even when the gate voltage is 0 V, a so-called normally on state. It is likely to become a lion. In an active matrix type display device, the electrical characteristics of the thin film transistors that make up the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of thin film transistors, the threshold voltage (Vth) is important. Even if the field effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, when the driving voltage is low, the switching function as a TFT cannot be achieved, and there is a risk of becoming a load. In the case of an n-channel type thin film transistor, it is desirable that a channel is formed only when a positive voltage is applied to the gate voltage and a drain current flows out. A transistor in which a channel is not formed unless the driving voltage is increased, or a transistor in which a channel is formed and a drain current flows even in a negative voltage state, is not suitable as a thin film transistor used in a circuit.

[0029] Also, the gas atmosphere for lowering the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere when the temperature is raised to the heating temperature T. For example, in the same furnace where dehydration or dehydrogenation has been performed, without exposing it to the atmosphere, the inside of the furnace is filled with high-purity oxygen gas or N2O gas, or ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower) and cooled.

[0030] After reducing the contained moisture in the film by a heat treatment for dehydration or dehydrogenation, the electrical characteristics of the thin film transistor are improved while slowly cooling (or cooling) in an atmosphere free of moisture (dew point is -40°C or lower, preferably -60°C or lower), and the oxide semiconductor film obtained is used for mass production. Realize a thin film transistor having both properties and high performance.

[0031] In this specification, heat treatment in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium) is called heat treatment for dehydration or dehydrogenation. In this specification, this heat treatment is not only called dehydrogenation when desorbing as H2, but also includes desorbing H , OH, etc., and is conveniently called dehydration or dehydrogenation.

[0032] When heat treatment is performed in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), the oxide semiconductor layer becomes oxygen-deficient by heat treatment and its resistance decreases, i.e., it becomes N-type ( N - type conversion, etc.).

[0033] Also, a high-resistance drain region (also called HRD (High Resistance Drain) region) that is oxygen-deficient and overlaps with the drain electrode layer is formed. Also, a source electrode layer and a high-resistance source region (also called HRS (High Resistanc e Source) region) that is oxygen-deficient and overlaps with it are formed.

[0034] Specifically, the carrier concentration of the high-resistance drain region is in the range of 1×10 18 / cm 3 or more, and is higher than at least the carrier concentration (less than 1×10 18 / cm 3 3 of the channel formation region). Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature.

[0035] And at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is brought into an oxygen-excess state By doing so, further increase the resistance, that is, make it into the I-type to form a channel formation region. Note that the treatment of bringing the dehydrated or dehydrogenated oxide semiconductor layer into an oxygen-excess state includes sputtering (also referred to as sputtering method) of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer, or heat treatment after forming the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or treatment of cooling in an oxygen atmosphere after heating in an inert gas atmosphere, treatment of cooling with ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower), etc. film formation, or heat treatment after forming the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or treatment of cooling in an oxygen atmosphere after heating in an inert gas atmosphere, treatment of cooling with ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower), etc. film formation, or heat treatment after forming the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or treatment of cooling in an oxygen atmosphere after heating in an inert gas atmosphere, treatment of cooling with ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower), etc. .

[0036] Also, in order to make at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer into the channel formation region, by selectively bringing it into an oxygen-excess state, it is also possible to increase the resistance, that is, make it into the I-type. A source electrode layer or a drain electrode layer made of a metal electrode such as Ti is formed in contact with the dehydrated or dehydrogenated oxide semiconductor layer, and an exposed region that does not overlap with the source electrode layer or the drain electrode layer is selectively brought into an oxygen-excess state to form the channel formation region. Also, in order to make at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer into the channel formation region, by selectively bringing it into an oxygen-excess state, it is also possible to increase the resistance, that is, make it into the I-type. A source electrode layer or a drain electrode layer made of a metal electrode such as Ti is formed in contact with the dehydrated or dehydrogenated oxide semiconductor layer, and an exposed region that does not overlap with the source electrode layer or the drain electrode layer is selectively brought into an oxygen-excess state to form the channel formation region. When selectively bringing it into an oxygen-excess state, a high-resistance source region overlapping with the source electrode layer and a high-resistance drain region overlapping with the drain electrode layer are formed, and the region between the high-resistance source region and the high-resistance drain region becomes the channel formation region. That is, the channel length of the channel formation region becomes self-aligned with the source electrode layer and the drain electrode layer. When selectively bringing it into an oxygen-excess state, a high-resistance source region overlapping with the source electrode layer and a high-resistance drain region overlapping with the drain electrode layer are formed, and the region between the high-resistance source region and the high-resistance drain region becomes the channel formation region. That is, the channel length of the channel formation region becomes self-aligned with the source electrode layer and the drain electrode layer. When selectively bringing it into an oxygen-excess state, a high-resistance source region overlapping with the source electrode layer and a high-resistance drain region overlapping with the drain electrode layer are formed, and the region between the high-resistance source region and the high-resistance drain region becomes the channel formation region. That is, the channel length of the channel formation region becomes self-aligned with the source electrode layer and the drain electrode layer. Accordingly, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0037] Accordingly, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0038] ​In the oxide semiconductor layer overlapping with the drain electrode layer, a high-resistance drain region is formed. By doing so, it is possible to improve the reliability when forming a drive circuit. Specifically, by forming a high-resistance drain region, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region and the channel formation region. Therefore, when operating by connecting to a wiring for supplying a high power supply potential VDD to the drain electrode layer, even when a high electric field is applied between the gate electrode layer and the drain electrode layer, the high-resistance drain region serves as a buffer and a local high electric field is not applied, and a configuration can be obtained in which the breakdown voltage of the thin film transistor is improved.

[0039] Also, in the oxide semiconductor layer overlapping with the drain electrode layer and the source electrode layer, by forming a high-resistance drain region and a high-resistance source region, it is possible to reduce the leakage current in the channel formation region when forming a drive circuit. Specifically, by forming a high-resistance drain region, the leakage current of the transistor flowing between the drain electrode layer and the source electrode layer follows the order of the drain electrode layer, the high-resistance drain region on the drain electrode layer side, the channel formation region, the high-resistance source region on the source electrode layer side, and the source electrode layer. At this time, in the channel formation region, the leakage current flowing into the channel region from the high-resistance drain region on the drain electrode layer side can be concentrated near the interface between the gate insulating layer, which becomes high resistance when the transistor is off, and the channel formation region, and the leakage current in the back channel portion (a part of the surface of the channel formation region away from the gate electrode layer) can be reduced.

[0040] ​​​​​​In addition, the high-resistance source region overlapping the source electrode layer and the high-resistance drain region overlapping the drain electrode layer overlap with a part of the gate electrode layer via the gate insulating layer, although it depends on the width of the gate electrode layer, and can more effectively relax the electric field strength

[0041] near the end of the drain electrode layer. In addition, an oxide conductive layer may be formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The oxide conductive layer preferably contains zinc oxide as a component and preferably does not contain indium oxide. For example, zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be used. The oxide conductive layer also functions as a low-resistance drain region (also called an LRN (Low Resistance N-type conductivity) region or an LRD (Low Resistance Drain) region). Specifically, the carrier concentration of the low-resistance drain region is larger than that of the high-resistance drain region (HRD region), for example, 1×10 20 / cm 3 or more and 1×10 21 / cm 3 or less is preferably within the range. By providing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the contact resistance can be reduced, and the high-speed operation of the transistor can be realized, so that the frequency characteristics of the peripheral circuit (driving circuit) can be improved.

[0042] The metal layer for forming the oxide conductive layer, the source electrode layer, and the drain electrode layer allows for continuous film formation.

[0043] In addition, the aforementioned first wiring and second wiring are made of an oxide that functions as an LRN or LRD It may be a laminated wiring composed of the same material as the physical conductive layer and a metal material. Metal and oxide By forming a laminate of conductive layers, the covering property against steps such as overstepping and openings of the lower layer wiring can be improved and the wiring resistance can be reduced. In addition, since an effect of preventing local increase in resistance and disconnection of the wiring due to migration or the like can also be expected, a highly reliable semiconductor device can be provided .

[0044] Also, when connecting the first wiring and the second wiring described above, by sandwiching an oxide conductive layer in between and connecting continuously, it can be expected to prevent an increase in contact resistance (contact resistance) due to the formation of an insulating oxide on the metal surface of the connection part (contact part), and a highly reliable semiconductor device can be provided .

[0045] In addition, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the thin film transistors in the pixel portion on the same substrate with respect to the gate line or the source line. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer .

[0046] Note that the ordinal numbers attached as the first and the second are used for convenience and do not indicate the process order or the lamination order. Also, they do not indicate specific names for identifying the invention in this specification .

[0047] In addition, a thin film transistor using an oxide semiconductor layer can be used for an electronic device or an optical device . For example, a thin film transistor using an oxide semiconductor layer can be used for a switching element of a liquid crystal display device, a switching element of a light emitting device, a switching element of an electronic paper, or the like . ​​​It can be used.

[0048] Moreover, not limited to the display device, an insulated gate semiconductor device for high-power control, particularly a semiconductor device called a power MOS device can also be manufactured. Examples of the power MOS device include MOSFET and IGBT.

Advantages of the Invention

[0049] In a semiconductor device having a thin film transistor using an oxide semiconductor layer, the parasitic capacitance can be reduced, and a semiconductor device with low power consumption can be provided.

[0050] In a semiconductor device having a thin film transistor using an oxide semiconductor layer, a highly reliable semiconductor device can be provided.

Brief Description of the Drawings

[0051]

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Mode for Carrying Out the Invention

[0052] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0053] (Embodiment 1) One form of a semiconductor device and a method of manufacturing the semiconductor device will be described with reference to FIGS. 1, 2, and 6.

[0054] FIG. 1 shows an example of the planar and cross - sectional structures of the semiconductor device. The thin - film transistors shown in FIGS. 1(A2) and (B) Transistor 410 is a type of bottom gate structure called a channel etch type, and has an inverted staggered It is also called a thin film transistor.

[0055] FIG. 1(A1) shows the gate wiring layer (formed in the same process as the gate electrode layer) and the source wiring layer ( (A2) is a plan view of the intersection with the channel etch type FIG. 1B is a plan view of the thin film transistor 410, and is taken along the line C1-C1 in FIGS. C2 and a cross-sectional view taken along line D1-D2.

[0056] The thin film transistor 410 is a channel-etched thin film transistor having an insulating surface. On a substrate 400, a gate electrode layer 411, a gate insulating layer 402, and at least a channel forming layer are formed. An oxide layer having a region 413, a high-resistivity source region 414a, and a high-resistivity drain region 414b. The semiconductor layer 412, the source electrode layer 415a, and the drain electrode layer 415b. The oxide insulating layer 407 covering the thin film transistor 410 and in contact with the channel formation region 413 A protective insulating layer 408 is provided thereon.

[0057] The oxide insulating layer 407 and the protective insulating layer 408 are covered with a source electrode layer 415a and a drain electrode layer 415b. An opening (contact hole) is formed in the opening, which reaches the wiring layers 417a and 417b. On the other hand, at the intersections, gate wiring layers 17b, 418a, and 418b are formed. 421 and source wiring layers 422 and 423 are formed by the gate insulating layer 402, the oxide insulating layer 407, and The layers are stacked with a protective insulating layer 408 interposed therebetween.

[0058] In this way, the gate electrode layer (gate wiring layer) and the source electrode layer or the drain electrode layer are electrically connected. The wiring layer connected thereto has a structure in which it intersects with an insulating layer covering the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. The gate electrode layer, source electrode layer, and drain electrode layer of the thin film transistor do not have a stacked structure of a gate electrode layer, a gate insulating layer, and a source electrode layer or a drain electrode layer, except that they partially overlap on the oxide semiconductor layer. Therefore, the parasitic capacitance formed by the stacked structure of the gate electrode layer, the gate insulating layer, and the source electrode layer or the drain electrode layer can be reduced, and low power consumption of the semiconductor device can be achieved. In addition, although the thin film transistor 410 has been described using a thin film transistor having a single gate structure, a thin film transistor having a multi-gate structure having a plurality of channel formation regions can also be formed as needed. Hereinafter, the process of manufacturing the thin film transistor 410 on the substrate will be described with reference to FIGS. 2(A) to (F).

[0059] First, after forming a conductive film on a substrate 400 having an insulating surface, a gate electrode layer 411 and a gate wiring layer 421 are formed by a first photolithography process. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance enough to withstand subsequent heat treatment.

[0060]

[0061]

[0062]

[0063] ​​​​​​​​​​​​A glass substrate such as silicate glass or aluminoborosilicate glass can be used.

[0064] Also, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is preferable to use one having a strain point of 730 ° C or higher. In addition, for the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. By containing more barium oxide (BaO) than boric acid, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0065] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can be used.

[0066] An insulating film serving as an underlayer film may be provided between the substrate 400, the gate electrode layer 411, and the gate wiring layer 421. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 400, and can be formed by a single-layer or laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0067] Also, the materials of the gate electrode layer 411 and the gate wiring layer 421 can be formed by using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material mainly composed of these, either singly or in a laminated manner.

[0068] Next, a gate insulating layer 402 is formed on the gate electrode layer 411 and the gate wiring layer 421. ​​​​​​​

[0069] The gate insulating layer 402 is formed by depositing a silicon oxide layer using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer in a single layer or For example, SiH4, oxygen, and nitrogen are used as the deposition gas. A silicon oxynitride layer may be formed by plasma CVD. The thickness is 100 nm to 500 nm. In the case of a laminate, for example, the thickness is 50 nm to 2 a first gate insulating layer having a thickness of 500 nm or less and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer; The second gate insulating layer is laminated to a thickness of 1 m or less.

[0070] In this embodiment, the gate insulating layer 402 is formed by plasma CVD to a thickness of 200 nm or more. A bottom silicon nitride layer is formed.

[0071] Next, an oxide semiconductor film 44 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 402. After the oxide semiconductor film 440 is formed, heat treatment for dehydration or dehydrogenation is performed. In order to make the oxide semiconductor film amorphous even after the etching treatment, the thickness of the oxide semiconductor film is set to be as thin as 50 nm or less. It is preferable that the thickness of the oxide semiconductor film is thinned, so that the heat treatment after the formation of the oxide semiconductor layer can be easily performed. When the film is processed, crystallization can be suppressed.

[0072] Before the oxide semiconductor film 440 was formed by a sputtering method, argon gas was introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 402 to generate plasma. It is preferable to remove the dust particles that are sputtered. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is a method of modifying the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. Any of them may be used.

[0073] The oxide semiconductor film 440 is an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn-O based , In-Al-Zn-O based, Sn-Ga-Zn-O based, Al-Ga-Zn-O based, Sn- Al-Zn-O based, In-Zn-O based, Sn-Zn-O based, Al-Zn-O based, In-O Based oxide semiconductor films are used.

[0074] In this embodiment, an In-Ga-Zn-O based oxide semiconductor target is used as the oxide semiconductor film 440, and film formation is performed by a sputtering method. The cross-sectional view at this stage corresponds to FIG. 2(A). Also, the oxide semiconductor film 440 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. When using the sputtering method, film formation is performed using a target containing 2 wt% or more and 10 wt% or less of SiO2, and SiOx (X>0) that inhibits crystallization is included in the oxide semiconductor film 440 to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. It is preferable. Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO = 1:1:1 [mol ratio], In:Ga:Zn = 1:1:0.5 [atom ratio ) is used, the distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, the direct current (D C) power supply is 0.5 kW, and argon and oxygen (argon:oxygen = 30 sccm:20 sccm ) are used.

[0075] [[ID=X]] 3:ZnO = 1:1:1 [mol ratio], In:Ga:Zn = 1:1:0.5 [atom ratio ) is used, the distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, the direct current (D C) power supply is 0.5 kW, and argon and oxygen (argon:oxygen = 30 sccm:20 sccm , film formation is carried out in an atmosphere with an oxygen flow ratio of 40%). When using a pulsed direct current (DC) power supply, , dust can be reduced, and it is preferable because the film thickness distribution becomes uniform. In-Ga-Zn-O-based non-single The film thickness of the crystalline film shall be 5 nm or more and 200 nm or less. In this embodiment, the oxide semiconductor film As, an In-Ga-Zn-O-based oxide semiconductor target is used and a non-single crystal film of In-Ga-Zn-O with a film thickness of 20 nm is formed by sputtering. Also, In, Ga, and As an oxide semiconductor target containing Zn, a target having a composition ratio of In:Ga:Zn = 1:1:1 [atom ratio], or a target having a composition ratio of In:Ga:Zn = 1:1:2 [atom ratio] can also be used.

[0076] The sputtering method includes the RF sputtering method using a high-frequency power supply for the sputtering power supply and the D C sputtering method, and there is also a pulsed DC sputtering method in which a bias is applied pulsedly. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

[0077] There is also a multi-source sputtering apparatus capable of installing a plurality of targets made of different materials. The multi-source sputtering apparatus can laminate and deposit different material films in the same chamber, or can simultaneously discharge a plurality of types of materials in the same chamber to form a film.

[0078] Also, there are sputtering apparatuses using the magnetron sputtering method equipped with a magnet mechanism inside the chamber, and ECR sputtering apparatuses using plasma generated using microwaves without using glow discharge.

[0079] In addition, as a film-forming method using a sputtering method, during film formation, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted to form a compound thin film thereof and a bias sputtering method in which a voltage is also applied to a substrate during film formation are also available.

[0080] Next, the oxide semiconductor film 440 is processed into island-shaped oxide semiconductor layers by a second photolithography process. Further, a resist mask for forming the island-shaped oxide semiconductor layer may be formed by an ink jet method. When the resist mask is formed by the ink jet method, since a photomask is not used, the manufacturing cost can be reduced.

[0081] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 400°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without contacting the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 441 is obtained ( see Fig. 2(B)). ).

[0082] Regarding an example of the mechanism of water desorption in the oxide semiconductor film, the following reaction pathway was analyzed (in the oxide semiconductor film, reactions not only as water but also as OH or H). An In-Ga-Zn-O-based amorphous film was used as the oxide semiconductor film.

[0083] In addition, the optimal molecular structure in the ground state of the calculation model was calculated using the density functional theory (DFT). The total energy of the DFT is the potential energy, the electrostatic energy between electrons, and the electric It is expressed as the sum of the exchange-correlation energy that includes all of the kinetic energy of the child and the complex electron-electron interactions. In DFT, since the exchange-correlation interaction is approximated by a functional (a function of a function) of the one-electron potential expressed by the electron density, the calculation is fast and highly accurate. Here, using the hybrid functional B3LYP, the weights of the parameters related to the exchange and correlation energies were specified. Also, as the basis functions, for indium atoms, gallium atoms, and zinc atoms, Lan L2DZ (a basis function obtained by adding a split valence basis system to the effective core potential of the Ne shell) was used, and for the other atoms, 6-311 (a basis function of a triple split valence basis system that uses three contracted functions for each valence orbital) was applied. With the above basis functions, for example, for a hydrogen atom, the 1s to 3s orbitals are considered, and for an oxygen atom, the 1s to 4s, 2p to 4p orbitals are considered. Furthermore, for improving the calculation accuracy, as a polarization basis system, a p function was added to the hydrogen atom and a d function was added to the oxygen atom.

[0084] Note that Gaussian03 was used as the quantum chemistry calculation program. The calculation was performed using a high performance computer (manufactured by SGI, Altix4700).

[0085] It is considered that -OH groups contained in the oxide semiconductor film react with each other by heat treatment for dehydration or dehydrogenation to generate H2O. Therefore, the water generation / desorption mechanism as shown in Fig. 26 was analyzed. In Fig. 26, since Zn is divalent, in the case of M = Zn, one M-O bond in Fig. 26 was removed.

[0086] In Fig. 26, M represents a metal atom, and the three types of In, Ga, and Zn apply. Initial state 1 In the initial state 1, -OH forms a coordination bond so as to crosslink M1 and M2. In the transition state 2, the H of -O H migrates to another -OH. In the intermediate 3, the generated H2O molecule forms a coordination bond with the metal atom In the final state 4, the H2O molecule desorbs and moves away to infinity.

[0087] (M1-M2) has all combinations of 1. In-In, 2. Ga-Ga, 3. Zn-Zn, 4. In-Ga, 5. In-Zn, 6. Ga-Zn, so calculations were performed for all combinations In this calculation, a cluster calculation using a calculation model in which M' was replaced with H was performed for the sake of simplifying the calculation.

[0088] In the calculation, an energy diagram corresponding to the reaction path in Fig. 26 was obtained. Representing from all six combinations of ( M1-M2), the calculation results for the case of 1. In-In are shown in Fig. 27 .

[0089] From Fig. 27, it was found that the activation energy for water generation is 1.16 eV. When the generated water molecule desorbs, it becomes unstable by about 1.58 eV.

[0090] Conversely, when Fig. 27 is regarded as a reaction from right to left, it can be regarded as a reaction in which water enters the oxide semiconductor film Then, the water coordinated to the metal hydrolyzes to form two OH groups The activation energy of the reaction is 0.47 eV.

[0091] Similarly, the reaction paths were also analyzed for other combinations of (M1-M2). For cases 1 to 6 , the activation energy (Ea [eV]) of the water generation reaction is shown in Table 1.

[0092] ​

Table 1

[0093] From Table 1, it can be seen that in the case of 1.In-In and 4.In-Ga, the water generation reaction is likely to occur. . In contrast, in the case of 3.Zn-Zn, the water generation reaction is less likely to occur. From this, it is speculated that the water generation reaction mediated by Zn atoms tends to be less likely to occur.

[0094] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be provided with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, RTA (Rapid Thermal An neal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. As the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the object to be treated by heat treatment are used.

[0095] For example, as the first heat treatment, the substrate may be moved and placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then GRTA may be performed by moving the substrate out of the inert gas heated to a high temperature. When GRTA is used, high-temperature heat treatment can be performed in a short time.

[0096] In the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Or, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Or, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film. In addition, the first heat treatment of the oxide semiconductor layer can also be performed on the oxide semiconductor film 440 before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating apparatus and a photolithography process is performed. The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer is performed after forming the oxide semiconductor layer and laminating the source electrode and drain electrode on the oxide semiconductor layer, and then the source electrode and drain electrode

[0097] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film. In addition, the first heat treatment of the oxide semiconductor layer can also be performed on the oxide semiconductor film 440 before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating apparatus and a photolithography process is performed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film. In addition, the first heat treatment of the oxide semiconductor layer can also be performed on the oxide semiconductor film 440 before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating apparatus and a photolithography process is performed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film.

[0098] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film.

[0099] The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer is performed after forming the oxide semiconductor layer and laminating the source electrode and drain electrode on the oxide semiconductor layer, and then the source electrode and drain electrode Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or polycrystalline film may be formed. For example, the crystallization rate may be 90% or more, or a microcrystalline oxide semiconductor film of 80% or more may be formed. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor film containing no crystal component may be formed. Also, an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor may be formed. Also, when high-temperature heat treatment is performed using RTA (GRTA, LRTA), needle-like crystals in the longitudinal direction (film thickness direction) may be generated on the surface side of the oxide semiconductor film. ​After forming the protective insulating film thereon, it may be performed by any of them.

[0100] Also, when forming a contact hole in the gate insulating layer 402, the process may be performed before or after performing a dehydration or dehydrogenation treatment on the oxide semiconductor film 440.

[0101] The oxide semiconductor layer is preferably an oxide semiconductor containing In, and more preferably an oxide semiconductor containing In, and Ga. Dehydration or dehydrogenation is effective for making the oxide semiconductor layer of type I (intrinsic).

[0102] Note that the etching of the oxide semiconductor film here is not limited to wet etching, and dry etching may be used.

[0103] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CC l4), etc.) is preferable.

[0104] Also, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF 6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. can be used.

[0105] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. It can be etched into a desired processed shape As such, the etching conditions (the amount of electric power applied to the coil-shaped electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are adjusted as appropriate. The amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are adjusted as appropriate.

[0106] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2), etc. can be used. Further, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used. Ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2), etc. can be used. Further, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0107] In addition, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing the materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced. The waste liquid of the etching solution containing the removed material is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing the materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced.

[0108] The etching conditions (etching solution, etching time, temperature, etc.) are adjusted as appropriate according to the material so that etching can be performed into a desired processed shape. The etching conditions (etching solution, etching time, temperature, etc.) are adjusted as appropriate according to the material so that etching can be performed into a desired processed shape.

[0109] Next, after forming a metal conductive film on the gate insulating layer 402 and the oxide semiconductor layer 441, a resist mask is formed by a third photolithography process, and selective etching is performed to form the source electrode layer 415a and the drain electrode layer 415b, and then the resist mask is removed (see Fig. 2(C)). Next, after forming a metal conductive film on the gate insulating layer 402 and the oxide semiconductor layer 441, a resist mask is formed by a third photolithography process, and selective etching is performed. After forming the source electrode layer 415a and the drain electrode layer 415b by performing selective etching, the resist mask is removed. (See Fig. 2(C).) After forming the source electrode layer 415a and the drain electrode layer 415b by performing selective etching, the resist mask is removed. (See Fig. 2(C).)

[0110] Note that when etching the metal conductive film, the oxide semiconductor layer 441 is not removed, and the respective materials and etching conditions are adjusted as appropriate. Note that when etching the metal conductive film, the oxide semiconductor layer 441 is not removed, and the respective materials and etching conditions are adjusted as appropriate.

[0111] In this embodiment, a Ti film is used as the metal conductive film, and an In- Ga-Zn-O based oxide is used for the oxide semiconductor layer 441, and aqueous ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the etchant.

[0112] The source electrode layer and the drain electrode layer preferably use a thin film with a film thickness of 0.1 nm or more and 50 nm or less, and a film thinner than the wiring layer is used. Since the source electrode layer and the drain electrode layer are thin conductive films, the parasitic capacitance with the gate electrode layer can be reduced.

[0113] It is preferable to use a material containing a metal with high oxygen affinity for the source electrode layer and the drain electrode layer. Also, the metal with high oxygen affinity is preferably a material selected from any one or more of titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as the source electrode layer and the drain electrode layer. When the oxide semiconductor layer and the metal layer with high oxygen affinity are brought into contact and heat-treated, oxygen atoms move from the oxide semiconductor layer to the metal layer, and the carrier density increases in the vicinity of the interface. Therefore, a low-resistance region is formed in the vicinity of the interface,

[0114] and the contact resistance between the oxide semiconductor layer and the source electrode layer and the drain electrode layer can be reduced. Furthermore, a heat-resistant conductive material may be used for the source electrode layer and the drain electrode layer. When a heat-resistant conductive material is used, even if heat treatment is performed after forming the source electrode layer and the drain electrode layer, alteration and deterioration of the source electrode layer and the drain electrode layer can be prevented.

[0115]

[0116] ​​​As the heat-resistant conductive material, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc) are selected from the elements, or an alloy containing the above-mentioned elements, or an alloy formed by combining the above-mentioned elements, a film, or a nitride containing the above-mentioned elements as a component can be used. Also, a conductive film with improved heat resistance can be used by combining the above heat-resistant conductive material

[0117] with a low-resistance conductive material such as aluminum (Al) or copper (Cu). In addition, the source electrode layer and the drain electrode layer may include a metal oxide layer. For example, a structure having a titanium oxide film between an oxide semiconductor layer and a titanium film, or a structure having a titanium oxide film (for example, with a film thickness of 1 nm or more and 20 nm or less) between a titanium film (for example, with a film thickness of 0.1 nm or more and 5 nm or less) and an oxide insulating layer may be used.

[0118] When the source electrode layer and the drain electrode layer have a thin film thickness that allows light to pass through, the source

[0119] electrode layer and the drain electrode layer have light transmittance. Note that in the third photolithography process, only a part of the oxide semiconductor layer 441 may be etched, resulting in an oxide semiconductor layer having a groove portion (concave portion). Also, a resist mask for forming the source electrode layer 415a and the drain electrode layer 415b may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0120] In addition, in order to reduce the number of photomasks and the number of processes used in the photolithography process, a transmissive The resist mask formed by a multi-tone mask, which is an exposure mask where incident light has multiple intensities, may be used for an etching process. The resist mask formed using the multi-tone mask has a shape with multiple film thicknesses, and the shape can be further deformed by performing etching. Therefore, it can be used for multiple etching processes for processing into different patterns. Thus, with a single multi-tone mask, a resist mask corresponding to at least two or more different patterns can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography processes can also be reduced, enabling the simplification of the process.

[0121] Next, plasma treatment using a gas such as N2O, N2, or Ar is performed. This plasma treatment removes adsorbed water and the like adhering to the surface of the exposed oxide semiconductor layer. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0122] After the plasma treatment, without being exposed to the atmosphere, an oxide insulating layer 407 serving as a protective insulating film in contact with a part of the oxide semiconductor layer is formed.

[0123] The oxide insulating layer 407 has a film thickness of at least 1 nm and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer 407. If the oxide insulating layer 407 contains hydrogen, the hydrogen may penetrate into the oxide semiconductor layer, or oxygen in the oxide semiconductor layer may be extracted by hydrogen, resulting in a decrease in the back channel resistance (N-type conversion) of the oxide semiconductor layer and the formation of a parasitic channel. Therefore, it is important not to use hydrogen in the film formation method so that the oxide insulating layer 407 becomes a film that contains as little hydrogen as possible. There is.

[0124] In this embodiment, a silicon oxide film with a thickness of 200 nm is used as the oxide insulating layer 407, and it is formed by sputtering using the ring method. The substrate temperature during film formation may be from room temperature to 300 °C, and in this embodiment, it is set to 100 °C. The film formation of the silicon oxide film by sputtering can be carried out in an inert gas (typically argon) atmosphere, an oxygen atmosphere, or an inert gas (typically argon) and an oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, a silicon oxide film can be formed by sputtering in an oxygen and nitrogen atmosphere. The oxide insulating layer 407 formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH and blocks the intrusion of these from the outside. An inorganic insulating - film is used, and typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or aluminum oxynitride etc. is used.

[0125] Next, a second heat treatment (preferably 2 00 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is carried out in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250 °C for 1 hour is carried out in a nitrogen atmosphere. When the second heat treatment is carried out, a part (channel formation region) of the oxide semiconductor layer is heated in a state of being in contact with the oxide insulating layer 407.

[0126] By going through the above steps, after performing a heat treatment for dehydration or dehydrogenation on the formed oxide semiconductor film to reduce the resistance, a part of the oxide semiconductor film is selectively made oxygen-excessive Set it to this state. As a result, the channel formation region 413 overlapping with the gate electrode layer 411 becomes of the I-type, and a high-resistance source region 414a overlapping with the source electrode layer 415a and a high-resistance drain region 414b overlapping with the drain electrode layer 415b are self-alignedly formed. In the above process, the thin film transistor 410 is formed. and a high-resistance source region 414a overlapping with the source electrode layer 415a and a high-resistance drain region 414b overlapping with the drain electrode layer 41 5b are self-alignedly formed. In the above process, the thin film transistor 410 is formed.

[0127] Furthermore, heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or longer and 30 hours or shorter. In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeating the temperature increase from room temperature to a heating temperature of 100°C or higher and 200°C and the temperature decrease from the heating temperature to room temperature a plurality of times. Also, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. When the heat treatment is performed under reduced pressure, the heating time can be shortened. By this heat treatment, hydrogen is taken into the oxide insulating layer from the oxide semiconductor layer, and a normally-off thin film transistor can be obtained. Therefore, the reliability of the semiconductor device can be improved. Furthermore, by forming the high-resistance drain region 414b (and the high-resistance source region 414a) in the oxide semiconductor layer overlapping with the drain electrode layer 415b (and the source electrode layer 415a), the reliability of the thin film transistor can be improved. Specifically, by forming the high-resistance drain region 414b, a structure can be formed such that the conductivity can be changed stepwise from the drain electrode layer 415b to the high-resistance drain region 414b and the channel formation region. Therefore, a wiring for supplying a high power supply potential VDD to the drain electrode layer 415b is connected

[0128] Note that in the oxide semiconductor layer overlapping with the drain electrode layer 415b (and the source electrode layer 415a), by forming the high-resistance drain region 414b (and the high-resistance source region 414a), the reliability of the thin film transistor can be improved. Specifically, by forming the high-resistance drain region 414b, a structure can be formed such that the conductivity can be changed stepwise from the drain electrode layer 415b to the high-resistance drain region 414b and the channel formation region. Therefore, a wiring for supplying a high power supply potential VDD to the drain electrode layer 415b is connected to the drain electrode layer 415b, and a structure can be formed such that the conductivity can be changed stepwise from the drain electrode layer 415b to the high-resistance drain region 414b and the channel formation region. to the drain electrode layer 415b, and a structure can be formed such that the conductivity can be changed stepwise from the drain electrode layer 415b to the high-resistance drain region 414b and the channel formation region. When the transistor is operated continuously, a high electric field is generated between the gate electrode layer 411 and the drain electrode layer 415b. Even if a high electric field is applied, the high-resistance drain region acts as a buffer, preventing the application of a local high electric field. This allows for a configuration that improves the breakdown voltage of the transistor.

[0129] The high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is preferably formed of an oxide semiconductor. When the oxide layer is thin, 15 nm or less, it is formed throughout the entire thickness direction. When the thickness of the conductor layer is thicker, between 30 nm and 50 nm, a part of the oxide semiconductor layer, The resistance of the region in contact with the source electrode layer or the drain electrode layer and its vicinity is reduced, forming a high-resistance source region. Alternatively, a high-resistance drain region is formed, and the region of the oxide semiconductor layer close to the gate insulating film is It can also be type I.

[0130] A protective insulating layer may be further formed on the oxide insulating layer 407. For example, RF sputtering The RF sputtering method is excellent for mass production, so it is easy to maintain. This is a preferred method for forming a protective insulating layer. The protective insulating layer is formed by absorbing moisture, hydrogen ions, and OH - etc. It does not contain impurities such as nitrogen, and uses an inorganic insulating film that blocks these from entering from the outside. A silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film. (See Figure 2(D)).

[0131] Next, a resist mask is formed by a fourth photolithography process and selectively etched. The oxide insulating layer 407 and the protective insulating layer 408 are partially removed by etching, and the source electrode layer 4 15a. Form openings 442a and 442b that reach the drain electrode layer 415b (see Fig. 2(E ).).

[0132] Form a conductive layer stack in openings 442a and 442b by sputtering or vacuum evaporation so as to be in contact with the source electrode layer 415a and the drain electrode layer 415b, and form a resist mask in the fifth photolithography process. Selectively etch the conductive layer stack to form wiring layers 4 17a, 417b, 418a, 418b. At the intersections, form source wiring layers 422 and 423 (see Fig. 2(F)).

[0133] For wiring layers 417a, 417b, 418a, and 418b, use a conductive film with lower resistance than the source and drain electrode layers. Specifically, metal materials such as aluminum, copper, chromium, tantalum, molyb denum, tungsten, titanium, neodymium, scandium, etc., or alloy materials with these as the main components can be used to form them either singly or in a stack. In this embodiment , a stacked structure is used as the wiring layer. Wiring layers 417a and 417b, which are the first wiring layers, are made of aluminum films, and wiring layers 418a and 418b, which are the second wiring layers, are made of titanium films.

[0134] A planarization insulating layer for planarization may be provided on the protective insulating layer 408. An example of providing the planarization insulating layer is shown in Fig. 6(A). Fig. 6(A) shows that a planarization insulating layer 409 is formed on the protective insulating layer 408, and wiring layers 417a, 417b, 418a, and 418b are formed in openings provided in the oxide insulating layer 407, protective insulating layer 408, and planarization insulating layer 409. On the other hand, source wiring layers 422 and 423 are formed on the planarization insulating layer 409. Planarization insulating layer 409 When provided, the distance between the gate wiring layer 421 and the source wiring layers 422 and 423 becomes even longer, so that parasitic capacitance can be further reduced.

[0135] As the planarization insulating layer 409, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide , epoxy, etc. can be used. In addition to the above organic materials , a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BP SG (borophosphosilicate glass), etc. can be used. Note that the planarization insulating layer 409 may be formed by laminating a plurality of insulating films formed of these materials.

[0136] Note that the siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. As substituents, the siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group. Further, the organic group may have a fluoro group.

[0137] The method for forming the planarization insulating layer 409 is not particularly limited, and depending on the material, a sputtering method , a spin coating method, a dipping method, a spray coating method, a droplet ejection method (inkjet method, screen printing, offset printing, etc.), a roll coating method, a curtain coating method, a knife coating method , etc. can be used.

[0138] Further, as shown in FIG. 6(B), without providing a protective insulating layer, a wiring layer and a source wiring layer may be formed on the oxide insulating layer 407. In FIG. 6(B), a source wiring layer 422 is provided on the oxide insulating layer 407, and wiring layers 417a and 417b are provided in openings formed in the oxide insulating layer 407. Thus, the wiring layer may also have a single-layer structure.​​​​

[0139] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, a semiconductor device with reduced parasitic capacitance and low power consumption can be provided.

[0140] Also, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, a semiconductor device with high reliability can be provided.

[0141] (Embodiment 2) In this embodiment, as an example of a semiconductor device having a thin film transistor with a structure different from that of Embodiment 1, it will be described below.

[0142] FIG. 3 shows an example of the planar and cross-sectional structures of a semiconductor device. The thin film transistor 450 shown in FIGS. 3(A2) and (B) is one of the bottom gate structures called channel protection type (also called channel stop type), and is also called an inverted staggered type thin film transistor.

[0143] FIG. 3(A1) is a plan view of the intersection of a gate wiring layer (formed in the same process as the gate electrode layer) and a source wiring layer ( formed in the same process as the wiring layer). FIG. 3(A2) is a plan view of the channel protection type thin film transistor 450. FIG. 3(B) is a cross-sectional view taken along lines C3-C 4 and D3-D4 of FIGS. 3(A1) and (A2).

[0144] The thin film transistor 450 is a channel protection type thin film transistor, and includes a gate electrode layer 451, a gate insulating layer 402, at least a channel formation region 453, a high resistance source region 454a, and a high resistance drain region 454b on a substrate 400 having an insulating surface, an oxide semiconductor layer 452, a source electrode layer 455a, and a drain electrode layer 455b. Also, the thin ​​​​​The oxide insulating layer 456 covers the thin film transistor 450, contacts the channel formation region 413, and functions as a channel protection layer. Further, a protective insulating layer 408 is provided thereon. An opening (contact hole) reaching the source electrode layer 455a and the drain electrode layer 455b is formed in the protective insulating layer 408, and wiring layers 457a, 457b, 458a, and 458b are formed in the opening. On the other hand, at the intersection, the gate wiring layer 421 and the source wiring layers 422 and 423 are laminated with the gate insulating layer 402, the oxide insulating layer 459, and the protective insulating layer 408 interposed therebetween.

[0145] (contact hole) is formed, and wiring layers 457a, 457b, 458a, 45 8b are formed. On the other hand, at the intersection, the gate wiring layer 421 and the source wiring layer 4 22, 423 are laminated with the gate insulating layer 402, the oxide insulating layer 459, and the protective insulating layer 408 interposed therebetween.

[0146] The oxide insulating layer 459 is not necessarily provided at the intersection, but providing the oxide insulating layer 459 can further separate the gate wiring layer 421 from the source wiring layers 422 and 423, so that the parasitic capacitance can be further reduced.

[0147] The oxide insulating layer 456 and the oxide insulating layer 459 can be formed by etching the oxide insulating layer, and the material and the manufacturing method may be the same as those of the oxide insulating layer 407 shown in the first embodiment. In this embodiment, the oxide insulating layer is formed by a sputtering method and processed into the oxide insulating layer 456 and the oxide insulating layer 459 using a photolithography process.

[0148] In this way, the gate electrode layer (gate wiring layer) and the wiring layer electrically connected to the source electrode layer or the drain electrode layer have a structure in which they cross with the protective insulating layer and the gate insulating layer covering the thin film transistor interposed therebetween. The gate electrode layer, the source electrode layer, and the drain of the thin film transistor ​​​​​​​​​The electrode layer does not have a stacked structure such as a gate electrode layer, a gate insulating layer, and a source electrode layer or a drain electrode layer, except for partially overlapping on the oxide semiconductor layer.

[0149] Therefore, the parasitic capacitance formed by the stacked structure of the gate electrode layer, the gate insulating layer, and the source electrode layer or the drain electrode layer can be reduced, and low power consumption of the semiconductor device can be realized.

[0150] Also, although the thin film transistor 450 has been described using a thin film transistor with a single gate structure, a thin film transistor with a multi-gate structure having a plurality of channel formation regions can also be formed as needed.

[0151] Hereinafter, a process of manufacturing the thin film transistor 450 on a substrate will be described with reference to FIGS. 4(A) to (F).

[0152] First, after forming a conductive film on a substrate 400 having an insulating surface, a gate electrode layer 451 and a gate wiring layer 421 are formed by a first photolithography process. Note that a resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0153] Also, the materials of the gate electrode layer 451 and the gate wiring layer 421 can be formed as a single layer or in a stacked manner using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material mainly composed of these.

[0154] Next, a gate insulating layer 402 is formed on the gate electrode layer 451 and the gate wiring layer 421. ​​​​​​

[0155] In this embodiment, a silicon nitride layer with a thickness of less than 200 nm is formed as the gate insulating layer 402 by plasma CVD method. Next, an oxide semiconductor film with a thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 402, and is processed into an island-shaped oxide semiconductor layer by the second photolithography process. In this embodiment, an In-Ga-Zn-O-based oxide semiconductor target is used as the oxide semiconductor film, and is formed by sputtering method.

[0156] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or more and 750°C or less, preferably 400°C or more and less than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without being exposed to the atmosphere, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 441 is obtained (see Fig. 4(A)). Next, plasma treatment using a gas such as N2O, N2, or Ar is performed. By this plasma treatment, adsorbed water or the like attached to the surface of the exposed oxide semiconductor layer is removed. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon. Next, after forming an oxide insulating layer on the gate insulating layer 402 and the oxide semiconductor layer 441, a resist mask is formed by the third photolithography process, and selective etching is performed to form the oxide insulating layer 456 and the oxide insulating layer 459, and then the resist mask is removed.

[0157]

[0158]

[0159] ​​​​​​​​​​​​​ Do it.

[0160] In this embodiment, silicon oxide films with a film thickness of 200 nm are formed as the oxide insulating layer 456 and the oxide insulating layer 459 by sputtering. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. The film formation of the silicon oxide film by sputtering can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a rare gas ( typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used to form a silicon oxide film by sputtering in an atmosphere of oxygen and nitrogen. The oxide insulating layer 456 formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or aluminum oxynitride is used. ions, etc., and - prevents these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or aluminum oxynitride is used. film, or aluminum oxynitride is used.

[0161] Next, a second heat treatment (preferably 2 00 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) may be performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer (channel formation region) is heated in a state of being in contact with the oxide insulating layer 456 is heated. is heated.

[0162] In this embodiment, an oxide semiconductor with an oxide insulating layer 456 provided and a part of it exposed The layer 441 is heat-treated in a nitrogen or inert gas atmosphere or under reduced pressure. The exposed region of the oxide semiconductor layer 441 not covered by the oxide insulating layer 4 56 can be made to have a lower resistance when heat-treated in a nitrogen or inert gas atmosphere or under reduced pressure. For example, heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere.

[0163] Due to the heat treatment in a nitrogen atmosphere for the oxide semiconductor layer 441 provided with the oxide insulating layer 4 56, the exposed region of the oxide semiconductor layer 441 becomes a lower resistance, and the oxide semiconductor layer 452 having regions with different resistances (indicated by the hatched region and the blank region in FIG. 4(B )) is obtained.

[0164] Next, after forming a metal conductive film on the gate insulating layer 402, the oxide semiconductor layer 452, and the oxide insulating layer 456, a resist mask is formed by a fourth photolithography process, selectively etched to form the source electrode layer 455a and the drain electrode layer 455b, and then the resist mask is removed (see FIG. 4(C)).

[0165] The source electrode layer 455a and the drain electrode layer 455b preferably have a thin film with a thickness of 0.1 nm or more and 50 nm or less, and a film thinner than the wiring layer is used. Since the source electrode layer and the drain electrode layer have a thin conductive film, the parasitic capacitance with the gate electrode layer can be reduced.

[0166] It is preferable to use a material containing a metal with a high oxygen affinity for the source electrode layer 455a and the drain electrode layer 455b. Further, the metal with a high oxygen affinity is any one of titanium, aluminum nium, manganese, magnesium, zirconium, beryllium, and thorium. or a material selected from a plurality of materials. In this embodiment, a titanium film is used as the source electrode layer 45 5a and the drain electrode layer 455b.

[0167] When the oxide semiconductor layer is brought into contact with a metal layer having a high oxygen affinity and heat-treated, oxygen atoms move from the oxide semiconductor layer to the metal layer, and the carrier density increases in the vicinity of the interface. Therefore, a low-resistance region is formed in the vicinity of the interface, and the contact resistance between the oxide semiconductor layer and the source electrode layer and the drain electrode layer can be reduced.

[0168] Alternatively, a heat-resistant conductive material may be used for the source electrode layer 455a and the drain electrode layer 455b. When a heat-resistant conductive material is used, even if heat treatment is performed after forming the source electrode layer 455a and the drain electrode layer 455b, alteration and deterioration of the source electrode layer 455a and the drain electrode layer 455b can be prevented.

[0169] Examples of the heat-resistant conductive material include an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), an alloy containing the above-described element as a component, an alloy formed by combining the above-described elements, a nitride containing the above-described element as a component, etc. can be used. Further, a conductive film in which the above heat-resistant conductive material is combined with a low-resistance conductive material such as aluminum (Al) or copper (Cu) to improve heat resistance may be used.

[0170] Alternatively, the source electrode layer 455a and the drain electrode layer 455b may contain a metal oxide layer. For example, a structure having a titanium oxide film between the oxide semiconductor layer and the titanium film, or a titanium film ( For example, it may have a structure in which a titanium oxide film (for example, a film having a thickness of 1 nm or more and 20 nm or less) is provided between a film having a thickness of 0.1 nm or more and 5 nm or less) and an oxide insulating layer. It may have a thickness of 1 nm or more and 20 nm or less.

[0171] Further, when the source electrode layer 455a and the drain electrode layer 455b have a thin film thickness that allows light to pass through, the source electrode layer 455a and the drain electrode layer 455b have translucency.

[0172] By going through the above steps, after performing heat treatment for dehydration or dehydrogenation on the oxide semiconductor film after film formation to reduce the resistance, a part of the oxide semiconductor film is selectively made into an oxygen-excessive state. As a result, the channel formation region 453 overlapping with the gate electrode layer 451 becomes of type I, and a high-resistance source region 454a overlapping with the source electrode layer 455a and a high-resistance drain region 454b overlapping with the drain electrode layer 45 5b are self-alignedly formed. The thin film transistor 450 is formed by the above steps. In the above steps, the thin film transistor 450 is formed.

[0173] Furthermore, heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeatedly raising the temperature from room temperature to a heating temperature of 100°C or higher and 200°C and then lowering the temperature from the heating temperature to room temperature a plurality of times. Also, this heat treatment may be performed under reduced pressure before forming the oxide insulating film. When performing heat treatment under reduced pressure, the heating time can be shortened. By this heat treatment, hydrogen is taken into the oxide insulating layer from the oxide semiconductor layer, and a normally-off thin film transistor can be obtained. As a result, the reliability of the semiconductor device can be improved. Therefore, the reliability of the semiconductor device can be improved.

[0174] Note that the oxide semiconductor layer overlapping with the drain electrode layer 455b (and the source electrode layer 455a) forming a high-resistance drain region 454b (and a high-resistance source region 454a) in This improves the reliability of the thin film transistor. By forming the drain electrode layer 455b, the high-resistance drain region 4 54b, a structure that can change the conductivity stepwise toward the channel forming region. Therefore, the drain electrode layer 415b is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated continuously, a high electric field is generated between the gate electrode layer 451 and the drain electrode layer 455b. Even if a high electric field is applied, the high-resistance drain region acts as a buffer, preventing the application of a local high electric field. This allows for a configuration that improves the breakdown voltage of the transistor.

[0175] The source electrode layer 455a, the drain electrode layer 455b, the oxide insulating layer 456, and the oxide insulating layer 4 A protective insulating layer 408 is formed on the insulating film 59. For example, a silicon nitride film is formed by RF sputtering. The RF sputtering method is suitable for mass production, and is therefore used as a method for forming the protective insulating layer 408. The protective insulating layer 408 is preferably formed by absorbing moisture, hydrogen ions, and OH ions. - Impurities such as It does not contain silicon nitride, and uses an inorganic insulating film that blocks these substances from entering from the outside. An aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film (see FIG. 4D).

[0176] The source electrode layer 455a, the drain electrode layer 455b, the oxide insulating layer 456, and the oxide insulating layer 457 are An oxide insulating layer is further formed on the edge layer 459, and a protective insulating layer 408 is stacked on the oxide insulating layer. It may be a layer, or a planarization insulating layer 409 as shown in FIG. 6(A) may be formed. Planar When the planarization insulating layer 409 is provided, the distance between the gate wiring layer 421 and the source wiring layers 422 and 423 becomes longer, so that the parasitic capacitance can be further reduced.

[0177] Next, a resist mask is formed by a fifth photolithography process, and selective etching is performed to remove a part of the protective insulating layer 408, and openings 467a and 467b reaching the source electrode layer 455a and the drain electrode layer 455b are formed (see FIG. 4(E)).

[0178] Laminated conductive layers are formed in openings 467a and 467b so as to be in contact with the source electrode layer 455a and the drain electrode layer 455b by sputtering or vacuum evaporation, and a resist mask is formed by a sixth photolithography process. The laminated conductive layers are selectively etched to form wiring layers 4 57a, 457b, 458a, 458b. At the intersections, source wiring layers 422 and 423 are formed (see FIG. 4(F)).

[0179] Wiring layers 457a, 457b, 458a, and 458b use a conductive film with lower resistance than the source electrode layer and the drain electrode layer. Specifically, metal materials such as aluminum, copper, chromium, tantalum, molybdenum denum, tungsten, titanium, neodymium, scandium, etc. or alloy materials having these as main components can be used to form them in a single layer or in a laminated manner. In this embodiment

[0180] a laminated structure is used as the wiring layer, and wiring layers 457a and 457b, which are the first wiring layers, are made of aluminum

[0180] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, it is possible to provide a semiconductor device with reduced parasitic capacitance and low power consumption.

[0181] Also, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, a semiconductor device with high reliability can be provided.

[0182] (Embodiment 3) In this embodiment, a part of the manufacturing process of a semiconductor device having a thin film transistor is different from that of Embodiment 1, and another example is shown in FIG. 5. FIG. 5 is the same as FIGS. 1 and 2 except that the process is partially different. Therefore, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted. In this embodiment, in the photolithography process, a mask layer formed by a multi-tone mask is used.

[0183] The mask layer formed using the multi-tone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing etching on the mask layer. Therefore, it can be used in a plurality of etching steps for processing different patterns. Thus, with a single multi-tone mask, mask layers corresponding to at least two different patterns can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced. As a result, the process can be simplified. According to Embodiment 1, a gate wiring layer 421 and a gate electrode layer 481 are formed on a substrate 400 by a first photolithography process, and a gate insulating layer 402 is laminated. An oxide semiconductor film is formed on the gate insulating

[0184] layer 402. In this embodiment, as the oxide semiconductor film, In is used. A film is formed by a sputtering method using a -Ga-Zn-O-based oxide semiconductor target.

[0185] As dehydration or dehydrogenation, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is heat-treated at 450 °C for 1 hour in a nitrogen atmosphere, and then, without being exposed to the air, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented to obtain an oxide semiconductor film 465.

[0186] Next, a metal conductive film 466 is formed on the oxide semiconductor film 465 by a sputtering method or a vacuum evaporation method (see Fig. 5(A)).

[0187] The metal conductive film 466 is a conductive film that becomes a source electrode layer and a drain electrode layer. The source electrode layer and the drain electrode layer preferably have a thin film with a film thickness of 0.1 nm or more and 50 nm or less, and a film thinner than the wiring layer is used. Since the source electrode layer and the drain electrode layer are thin conductive films, the parasitic capacitance with the gate electrode layer can be reduced.

[0188] It is preferable to use a material containing a metal with high oxygen affinity for the source electrode layer and the drain electrode layer. Further, the metal with high oxygen affinity is preferably a material selected from any one or more of titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as the source electrode layer and the drain electrode layer.

[0189] When the oxide semiconductor layer and the metal layer with high oxygen affinity are brought into contact and heat-treated, oxygen atoms move from the oxide semiconductor layer to the metal layer, and the carrier density increases in the vicinity of the interface. Therefore, ​​​​​​​​Thereby, a low-resistance region is formed in the vicinity of the interface, and the contact resistance between the oxide semiconductor layer and the source electrode layer and the drain electrode layer can be reduced.

[0190] Further, a heat-resistant conductive material may be used for the source electrode layer and the drain electrode layer. When a heat-resistant conductive material is used, deterioration and degradation of the source electrode layer and the drain electrode layer can be prevented even if a heat treatment is performed after the formation of the source electrode layer and the drain electrode layer.

[0191] Examples of the heat-resistant conductive material include elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), alloys containing the above-described elements as components, alloy films combining the above-described elements, nitrides containing the above-described elements as components, and the like. Further, a conductive film having improved heat resistance by combining the above-described heat-resistant conductive material with a low-resistance conductive material such as aluminum (Al) or copper (Cu) may be used.

[0192] Further, the source electrode layer and the drain electrode layer may include a metal oxide layer. For example, a structure having a titanium oxide film between the oxide semiconductor layer and the titanium film, or a structure having a titanium oxide film (for example, a film thickness of 1 nm or more and 20 nm or less) between a titanium film (for example, a film thickness of 0.1 nm or more and 5 nm or less) and an oxide insulating layer may be used.

[0193] Further, when the source electrode layer and the drain electrode layer have a thin film thickness that allows light to pass through, the source electrode layer and the drain electrode layer have light transmittance.

[0194] A second photolithography process is performed on the oxide semiconductor film 465 and the metal conductive film 466. A resist mask 460 is formed thereon.

[0195] In this embodiment, an example is shown in which exposure using a halftone mask is performed to form the resist mask 460. To form the resist mask 460, a resist is formed. The resist can be a positive resist or a negative resist. Here, a positive resist is used for illustration. The resist may be formed by the spin coating method or selectively formed by the inkjet method. When the resist is selectively formed by the inkjet method, formation of the resist on unnecessary portions can be reduced, so that waste of materials can be reduced.

[0196] Next, using the halftone mask 81 as an exposure mask, the resist is irradiated with light to expose the resist.

[0197] Here, the exposure using the halftone mask 81 will be described with reference to FIG. 25.

[0198] A halftone mask is a mask capable of performing three exposure levels on an exposed portion, an intermediate exposure portion, and an unexposed portion, and is an exposure mask in which the transmitted light has a plurality of intensities. By one exposure and development process, it is possible to form a resist mask having regions of a plurality (typically two types) of thicknesses. Therefore, by using a halftone mask, it is possible to reduce the number of exposure masks.

[0199] Typical examples of the halftone mask include a grayscale mask 81a as shown in FIG. 25(A), and a halftone mask 81b as shown in FIG. 25(C).

[0200] As shown in FIG. 25(A), the grayscale mask 81a includes a light-transmissive substrate 83 and thereon It is composed of a light-shielding portion 84 and a diffraction grating 85 formed thereon. In the light-shielding portion 84, the light transmittance is 0%. On the other hand, for the diffraction grating 85, by setting the interval between light-transmitting portions such as slits, dots, and meshes to be equal to or less than the resolution limit of the light used for exposure, the light transmittance can be controlled. Note that the diffraction grating 85 can be either a periodic slit, dot, mesh, or an aperiodic slit, dot, or mesh. As the light-transmissive substrate 83, a light-transmissive substrate such as quartz can be used. The light-shielding portion 84 and the diffraction grating 85 can be formed using a light-absorbing light-shielding material such as chromium or chromium oxide. When the gray-tone mask 81a is irradiated with exposure light, as shown in FIG. 25(B), in the light-shielding portion 84, the light transmittance 86 is 0%, and in the region where the light-shielding portion 84 and the diffraction grating 85 are not provided, the light transmittance 86 is 100%. Also, in the diffraction grating 85, it can be adjusted within the range of 10 to 70%. The adjustment of the light transmittance in the diffraction grating 85 can be achieved by adjusting the interval and pitch of the slits, dots, or meshes of the diffraction grating. As shown in FIG. 25(C), the half-tone mask 81b is composed of a light-transmissive substrate 83 and a semi-transmissive portion 87 and a light-shielding portion 88 formed thereon. For the semi-transmissive portion 87, MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light-shielding portion 88 can be formed using a light-absorbing light-shielding material such as chromium or chromium oxide.

[0201]

[0202]

[0203]

[0204] When the halftone mask 81b is irradiated with exposure light, as shown in FIG. 25(D), in the light-shielding portion 88, the light transmittance 89 is 0%, and in the region where the light-shielding portion 88 and the semi-transmissive portion 87 are not provided, the light transmittance 89 is 100%. Also, in the semi-transmissive portion 87, it can be adjusted within the range of 10 to 70%. The adjustment of the light transmittance in the semi-transmissive portion 87 can be adjusted by the material of the semi-transmissive portion 8 7. 7.

[0205] After exposure using a multi-tone mask and development, a resist mask 460 having regions with different film thicknesses can be formed as shown in FIG. 5(B). After exposure using a multi-tone mask and development, a resist mask 460 having regions with different film thicknesses can be formed as shown in FIG. 5(B).

[0206] Next, a first etching process is performed using the resist mask 460 to etch the oxide semiconductor film 46 5 and the metal conductive film 466 into an island shape. As a result, an oxide semiconductor layer 461 and a metal conductive layer 462 can be formed (see FIG. 5(B)).

[0207] Next, the resist mask 460 is ashed. As a result, the area (volume when viewed three-dimensionally) of the resist mask is reduced and the thickness becomes thinner. At this time, the resist of the resist mask in the region with a thin film thickness (the region overlapping with a part of the gate electrode layer 481) is removed, and separated resist masks 463a and 463b can be formed. Next, the resist mask 460 is ashed. As a result, the area (volume when viewed three-dimensionally) of the resist mask is reduced and the thickness becomes thinner. At this time, the resist of the resist mask in the region with a thin film thickness (the region overlapping with a part of the gate electrode layer 481) is removed, and separated resist masks 463a and 463b can be formed. Next, the resist mask 460 is ashed. As a result, the area (volume when viewed three-dimensionally) of the resist mask is reduced and the thickness becomes thinner. At this time, the resist of the resist mask in the region with a thin film thickness (the region overlapping with a part of the gate electrode layer 481) is removed, and separated resist masks 463a and 463b can be formed. Next, the resist mask 460 is ashed. As a result, the area (volume when viewed three-dimensionally) of the resist mask is reduced and the thickness becomes thinner. At this time, the resist of the resist mask in the region with a thin film thickness (the region overlapping with a part of the gate electrode layer 481) is removed, and separated resist masks 463a and 463b can be formed.

[0208] Using the resist masks 463a and 463b, unnecessary portions are removed by etching to form a source electrode layer 485a and a drain electrode layer 485b (see FIG. 5(C)). Using the resist masks 463a and 463b, unnecessary portions are removed by etching to form a source electrode layer 485a and a drain electrode layer 485b (see FIG. 5(C)).

[0209] Note that when etching the metal conductive layer 462, the oxide semiconductor layer 461 is not removed, and the respective materials and etching conditions are appropriately adjusted. Note that when etching the metal conductive layer 462, the oxide semiconductor layer 461 is not removed, and the respective materials and etching conditions are appropriately adjusted.

[0210] In this embodiment, a Ti film is used as the metal conductive layer 462, and an In-Ga-Zn-O based oxide is used for the oxide semiconductor layer 461, and an aqueous solution of aqueous ammonia peroxide (a mixture of aqueous ammonia, water, and aqueous hydrogen peroxide) is used as the etchant.

[0211] Note that the etching of the metal conductive film and the oxide semiconductor film here is not limited to wet etching, and dry etching may also be used. Dry etching may be used.

[0212] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl 4), etc.) is preferable.

[0213] In addition, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF 6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. can be used. Dry etching methods such as parallel plate type RIE (Reactive Ion Etch

[0214] ing) method or ICP (Inductively Coupled Plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that etching can be performed to obtain a desired processed shape. ing) method or ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that etching can be performed to obtain a desired processed shape.

[0215] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2), etc. can be used. Further, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used. Also, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced.

[0216] Also, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material is purified, and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced.

[0217] The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that etching can be performed into a desired processed shape.

[0218] Next, the resist masks 463a and 463b are removed, and an oxide insulating layer 407 serving as a protective insulating layer in contact with the oxide semiconductor layer 461 is formed. In the present embodiment, a silicon oxide film having a film thickness of 200 nm is formed by a sputtering method as the oxide insulating layer 407.

[0219] Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part (channel formation region) of the oxide semiconductor layer is heated in a state of being in contact with the oxide insulating layer 407.

[0220] ​By going through the above steps, dehydration or dehydrogenation is performed on the oxide semiconductor film after film formation followed by heat treatment for reducing the resistance. Then, a part of the oxide semiconductor film is selectively made into an oxygen-excessive state. As a result, the channel formation region 483 overlapping with the gate electrode layer 481 becomes of type I and a high-resistance source region 484a overlapping with the source electrode layer 485a and a high-resistance drain region 484b overlapping with the drain electrode layer 48 5b are self-alignedly formed. The thin-film transistor 480 is formed through the above steps.

[0221] Furthermore, heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or longer and 30 hours or shorter. In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeating the temperature increase from room temperature to a heating temperature of 100°C or higher and 200°C and the temperature decrease from the heating temperature to room temperature a plurality of times. Also, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. When heat treatment is performed under reduced pressure, the heating time can be shortened. By this heat treatment, hydrogen is taken into the oxide insulating layer from the oxide semiconductor layer, and a normally-off thin-film transistor can be obtained. Thus, the reliability of the semiconductor device can be improved.

[0222] A protective insulating layer 408 is formed on the oxide insulating layer 407. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film as the protective insulating layer (see Fig. 5(D)).

[0223] Next, a resist mask is formed by a third photolithography process, and selective etching is performed to remove a part of the oxide insulating layer 407 and the protective insulating layer 408, and the source electrode layer 4 is formed. 85a. Form openings 464a and 464b that reach the drain electrode layer 485b (see Fig. 5(E ).).

[0224] Form conductive layers in the openings 464a and 464b by sputtering or vacuum evaporation so as to be in contact with the source electrode layer 485a and the drain electrode layer 485b and form a resist mask by a fourth photolithography process. Selectively etch the laminated conductive layer to form wiring layers 4 87a, 487b, 488a, 488b, and at the intersections, source wiring layers 422 and 423 are formed (see Fig. 5(F).).

[0225] The wiring layers 487a, 487b, 488a, and 488b use a conductive film with lower resistance than the source electrode layer and the drain electrode layer. Specifically, metal materials such as aluminum, copper, chromium, tantalum, molyb denum, tungsten, titanium, neodymium, scandium, or alloy materials having these as main components can be used to form them in a single layer or by lamination. In this embodiment , a laminated structure is used as the wiring layer, and the wiring layers 487a and 487b, which are the first wiring layers, are made of aluminum films, and the wiring layers 488a and 488b, which are the second wiring layers, are made of titanium films.

[0226] As described above, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer , it is possible to provide a semiconductor device with reduced parasitic capacitance and low power consumption.

[0227] Also, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, a semiconductor device with high reliability can be provided.

[0228] This embodiment can be implemented in appropriate combination with other embodiments.

[0229] ​ (Embodiment 4) In this embodiment, an example in which a conductive material having translucency is used for the gate electrode layer in Embodiment 1 is shown in FIG. 7. Therefore, other operations can be performed in the same manner as in Embodiment 1, and descriptions of the same parts or parts having similar functions and repeated processes are omitted. Also, since FIG. 7 is the same as FIGS. 1 and 2 except for a partial difference in the process, the same reference numerals are used for the same locations, and detailed descriptions of the same locations are omitted.

[0230] The thin film transistor 430 shown in FIG. 7 is a channel etch type thin film transistor, and includes a gate electrode layer 431, a gate insulating layer 402, at least a channel formation region 433, a high resistance source region 434a, and a high resistance drain region 434b on a substrate 400 having an insulating surface, an oxide semiconductor layer 432, a source electrode layer 435a, and a drain electrode layer 435b. Also, an oxide insulating layer 407 that covers the thin film transistor 430 and is in contact with the channel formation region 433 is provided, and a protective insulating layer 408 is further provided thereon. Openings (contact holes) reaching the source electrode layer 435a are formed in the oxide insulating layer 407 and the protective insulating layer 408, and wiring layers 437 and 438 are formed in the openings. On the other hand, in the overlapping portion, the gate wiring layer 421 and the source wiring layers 422 and 423 are laminated with the gate insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408 interposed therebetween. Note that the openings and the wiring layers such as the openings reaching the source electrode layer 435a shown in FIG. 7 and the wiring layers 437 and 438 provided in the openings may be provided in a region that does not overlap with the oxide semiconductor layer 432.

[0231]

[0232] ​​​​​​​​​​​​Thus, the gate electrode layer (gate wiring layer), the source electrode layer or the drain electrode layer, and the wiring layer electrically connected thereto have a structure that crosses with an insulating layer covering the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Except for partially overlapping on the oxide semiconductor layer, the gate electrode layer of the thin film transistor, the source electrode layer and the drain electrode layer do not have a stacked structure of a gate electrode layer, a gate insulating layer, and a source electrode layer or a drain electrode layer.

[0233] Therefore, the parasitic capacitance formed by the stacked structure of the gate electrode layer, the gate insulating layer, and the source electrode layer or the drain electrode layer can be reduced, and low power consumption of the semiconductor device can be realized.

[0234] A planarization insulating layer 409 is formed on the wiring layer 438, the source wiring layer 423, and the protective insulating layer 408, and a pixel electrode layer 427 is provided on the planarization insulating layer 409. The pixel electrode layer 427 is in contact with the wiring layer 438 through an opening formed in the planarization insulating layer 409, and the thin film transistor 430 and the pixel electrode layer 427 are electrically connected through the wiring layers 437 and 438.

[0235] Since the source electrode layer 435a and the drain electrode layer 435b are thin film metal conductive films, they can be made into conductive films having translucency.

[0236] Also, in FIG. 7, a conductive film having translucency is also used for the gate electrode layer 431 of the thin film transistor 430.

[0237] The material of the gate electrode layer 431 is a conductive material having translucency with respect to visible light, for example, In-S n-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system , metal oxides of Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn- O system, Al-Zn-O system, In-O system, Sn-O system, and Zn-O system can be applied appropriately, and the film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. The metal oxide used for the gate electrode layer 431 can be formed by sputtering, vacuum evaporation (such as electron beam evaporation method), arc discharge ion plating method, or spraying method. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation to include SiOx (X>0) that inhibits crystallization in the conductive film having light transmittance, and it is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in the subsequent process.

[0238] Therefore, the thin film transistor 430 can be a thin film transistor having light transmittance.

[0239] In addition, for the pixel where the thin film transistor 430 is disposed, a conductive film having light transmittance to visible light is used for the pixel electrode layer 427, or other electrode layers (such as a capacitive electrode layer) or other wiring layers (such as a capacitive wiring layer) to realize a display device having a high aperture ratio. Of course, it is also preferable that the gate insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408 are films having light transmittance to visible light.

[0240] In this specification, a film having light transmittance to visible light refers to a film having a film thickness with a visible light transmittance of 75 to 100 %, and when the film has conductivity, it is also called a transparent conductive film. In addition, the gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrodes As the metal oxide applied to the layer or other wiring layers, a conductive film that is translucent to visible light may be used. To be translucent to visible light means that the transmittance of visible light is 50 - 75%. .

[0241] Since the thin film transistor 430 has light transmittance, the aperture ratio can be improved. In particular, In a small liquid crystal display panel of 10 inches or less, in order to increase the number of gate wirings and achieve higher definition of the displayed image, even if the pixel size is miniaturized, a high aperture ratio can be achieved. Also, by using a film with light transmittance for the constituent members of the thin film transistor 430, in order to achieve a wide viewing angle, even if one pixel is divided into a plurality of sub-pixels, a high aperture ratio can be achieved. That is, even if a high-density thin film transistor group is arranged, the aperture ratio can be increased, and a sufficient area of the display region can be secured. For example, when one pixel has 2 - 4 sub-pixels, since the thin film transistor has light transmittance, the aperture ratio can be improved. Also, if the storage capacitor is formed using the same material in the same process as the constituent members of the thin film transistor, the storage capacitor can also have light transmittance, so that the aperture ratio can be further improved. This embodiment can be implemented in appropriate combination with other embodiments.

[0242]

[0243] (Embodiment 5) In this embodiment, an example in which a part of the manufacturing process of the thin film transistor is different from that of Embodiment 1 is shown in FIG. 8. Since FIG. 8 is the same as FIGS. 1 and 2 except for the part where the process is different, the same reference numerals are used for the same parts, and the detailed description of the same parts is omitted.

[0244] According to Embodiment 1, a gate wiring layer 421 and a gate electrode layer 471 are formed on a substrate 400 and a gate insulating layer 402 is laminated.

[0245] Next, an oxide semiconductor film is formed and the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer by a photolithography process.

[0246] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or higher and 750°C or lower of the substrate, preferably 425°C or higher to be. If it is 425°C or higher, the heat treatment time may be 1 hour or less, but if it is less than 425°C the heat treatment time will be longer than 1 hour. Here, the substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and the heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere, and then, without being exposed to the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented, and an oxide semiconductor layer is obtained. Thereafter, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower) is introduced into the same furnace for cooling. It is preferable that water, hydrogen, etc. are not contained in the oxygen gas or N2O gas. Alternatively, the purity of the oxygen gas or N2O gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher, (that is, the impurity concentration in the oxygen gas or N2O gas is 1 ppm or lower, preferably 0.1 ppm or lower).

[0247] Note that the heat treatment apparatus is not limited to an electric furnace, for example, a GRTA (Gas Rapid Th ermal Anneal) apparatus, an LRTA (Lamp Rapid Thermal ​​​It is possible to use an RTA (Rapid Thermal Anneal) apparatus such as an anneal apparatus. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with an apparatus that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element, in addition to the lamp. GRTA is a method of performing heat treatment using a high-temperature gas. As the gas, a noble gas such as argon or an inert gas that does not react with the object to be processed by heat treatment, such as nitrogen, is used. Using the RTA method, heat treatment may be performed at 600 °C to 750 °C for several minutes. It is possible. The LRTA apparatus is an apparatus that heats the object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Moreover, the LRTA apparatus may be provided with an apparatus that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element, in addition to the lamp. GRTA is a method of performing heat treatment using a high-temperature gas. As the gas, a noble gas such as argon or an inert gas that does not react with the object to be processed by heat treatment, such as nitrogen, is used. Using the RTA method, heat treatment may be performed at 600 °C to 750 °C for several minutes. Moreover, after the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed at a temperature of 200 °C or higher and 400 °C or lower, preferably 200 °C or higher and 300 °C or lower, in an oxygen gas or N2O gas atmosphere. Moreover, the first heat treatment of the oxide semiconductor layer may be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed. By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, thereby achieving high resistance, that is, type I conversion. Thus, an oxide semiconductor layer 472 that is entirely type I converted is obtained. Next, a resist mask is formed on the oxide semiconductor layer 472 by a photolithography process.

[0248] Moreover, after the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed at a temperature of 200 °C or higher and 400 °C or lower, preferably 200 °C or higher and 300 °C or lower, in an oxygen gas or N2O gas atmosphere. Moreover, the first heat treatment of the oxide semiconductor layer may be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed. By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, thereby achieving high resistance, that is, type I conversion. Thus, an oxide semiconductor layer 472 that is entirely type I converted is obtained.

[0249] Moreover, the first heat treatment of the oxide semiconductor layer may be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed. Moreover, after the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed at a temperature of 200 °C or higher and 400 °C or lower, preferably 200 °C or higher and 300 °C or lower, in an oxygen gas or N2O gas atmosphere. By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, thereby achieving high resistance, that is, type I conversion. Thus, an oxide semiconductor layer 472 that is entirely type I converted is obtained.

[0250] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, thereby achieving high resistance, that is, type I conversion. Thus, an oxide semiconductor layer 472 that is entirely type I converted is obtained. Next, a resist mask is formed on the oxide semiconductor layer 472 by a photolithography process.

[0251] Next, a resist mask is formed on the oxide semiconductor layer 472 by a photolithography process. Form and selectively etch to form the source electrode layer 475a and the drain electrode layer 475b. Form the oxide insulating layer 407 by sputtering.

[0252] Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, heat treatment (preferably at 150°C or higher and lower than 350°C) is performed in an inert gas atmosphere or in a nitrogen gas atmosphere. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

[0253] Alternatively, heat treatment may be performed in the air at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeatedly raising the temperature from room temperature to a heating temperature of 100°C or higher and 200°C and then lowering the temperature from the heating temperature to room temperature a plurality of times. Also, this heat treatment may be performed under reduced pressure before forming the oxide insulating film. Performing heat treatment under reduced pressure can shorten the heating time. By this heat treatment, hydrogen is incorporated into the oxide insulating layer from the oxide semiconductor layer, and a normally-off thin film transistor can be obtained. Therefore, the reliability of the semiconductor device can be improved.

[0254] Next, a protective insulating layer 408 is formed on the oxide insulating layer 407.

[0255] Next, a resist mask is formed by a photolithography process, and selective etching is performed to remove a part of the oxide insulating layer 407 and the protective insulating layer 408 to form an opening reaching the source electrode layer 475a and the drain electrode layer 475b.

[0256] A conductive layer is formed by sputtering or vacuum evaporation so as to be in contact with the source electrode layer 475a and the drain electrode layer 475b, and a resist mask is formed by a photolithography process. The laminated conductive layer is selectively etched to form wiring layers 477a, 477b, 478a, 478b, and source wiring layers 422 and 423 are formed at the intersections (see FIG. 8).

[0257] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, a semiconductor device with reduced parasitic capacitance and low power consumption can be provided.

[0258] Also, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, a highly reliable semiconductor device can be provided.

[0259] This embodiment can be implemented in appropriate combination with other embodiments.

[0260] (Embodiment 6) In this embodiment, in Embodiment 1, an example in which an oxide conductive layer is provided as a source region and a drain region between the oxide semiconductor layer and the source electrode layer or the drain electrode layer is shown in FIG. 9. Therefore, the other operations can be performed in the same manner as in Embodiment 1, and the description of the same parts or parts having the same functions as those in Embodiment 1 and the repetition of the processes are omitted. Also, since FIG. 9 is the same as FIGS. 1 and 2 except that the processes are partly different, the same reference numerals are used for the same parts, and the detailed description of the same parts is omitted.

[0261] The thin film transistor 469 shown in FIG. 9 is a channel etch type thin film transistor, and on a substrate 400 having an insulating surface, a gate electrode layer 411, a gate insulating layer 402, and at least a channel ​​​​​​​​​ It has a channel formation region 413, a high-resistance source region 414a, and a high-resistance drain region 414b and includes an oxide semiconductor layer 412, oxide conductive layers 416a and 416b, a source electrode layer 415a , and a drain electrode layer 415b. Also, an oxide insulating layer 407 that covers the thin film transistor 469 and is in contact with the channel formation region 413 is provided, and further, a protective insulating layer 40 8 is provided thereon.

[0262] According to Embodiment 1, a gate wiring layer 421 and a gate electrode layer 411 are formed on a substrate 400 , and a gate insulating layer 402 is laminated. An oxide semiconductor film is formed on the gate insulating layer 402, and a dehydrated or dehydrogenated oxide semiconductor layer is formed.

[0263] Oxide conductive layers 416a and 416b are formed on the dehydrated or dehydrogenated oxide semiconductor layer . In this embodiment, an example in which the oxide conductive layers 416a and 416b are shaped by the same photolithography process as the oxide semiconductor layer is shown, but the oxide conductive layers 416a and 416b may be shaped by the same photolithography process as the source electrode layer and the drain electrode layer.

[0264] As a method for forming the oxide conductive layers 416a and 416b, a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method is used. For the oxide conductive layers 416a and 416b, those containing zinc oxide as a component are preferred , and those not containing indium oxide are preferably used. As such oxide conductive layers 416 a and 416b, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, and oxide Zinc, gallium, etc. can be applied. The film thickness is in the range of 50 nm or more and 300 nm or less. It is appropriately selected. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the oxide conductive film, and crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process is preferably suppressed.

[0265] In this embodiment, after the oxide conductive layers 416a and 416b are shaped by the same photolithography process as the oxide semiconductor layer, the source electrode layer 415a and the drain electrode layer 415b are used as masks, and the oxide conductive layer is further etched to form the oxide conductive layers 416a and 416b. The oxide conductive layers 41, formed of zinc oxide, can be easily etched using an alkaline solution such as a resist stripping solution.

[0266] An etching process for dividing the oxide conductive layer to form the channel region is performed by utilizing the difference in etching rate between the oxide semiconductor layer and the oxide conductive layer. The oxide conductive layer is selectively etched by utilizing the fact that the etching rate of the oxide conductive layer is faster than that of the oxide semiconductor layer.

[0267] Therefore, the removal of the resist mask used for forming the source electrode layer 415a and the drain electrode layer 415b is preferably removed by an ashing process. In the case of etching using a stripping solution, the etching conditions (type of etchant, concentration, etching time) are appropriately adjusted so that the oxide conductive layer and the oxide semiconductor layer are not over-etched.

[0268] The oxide conductive layer 416b provided between the oxide semiconductor layer 412 and the drain electrode layer 415b made of a metal material also functions as a low resistance drain region (also referred to as an LRN (Low Resistance N-type conductivity) region or an LRD (Low Resistance Drain) region). Similarly, the oxide conductive layer 416a provided between the oxide semiconductor layer 412 and the source electrode layer 415a made of a metal material also functions as a low resistance drain region (also referred to as an LRN (Low Resistance N-type conductivity) region or an LRS (Low Resistance Source) region). By configuring the oxide semiconductor layer, the low resistance drain region, and the drain electrode layer made of a metal material, the breakdown voltage of the transistor can be further improved. Specifically, the carrier concentration in the low resistance drain region is larger than that in the high resistance drain region (HRD region), and is preferably in the range of, for example, 1×10 / cm or more and 1×10 / cm or less. By providing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer as the source region and the drain region, the low resistance of the source region and the drain region can be achieved, and the transistor can operate at high speed. Using the oxide conductive layer as the source region and the drain region is effective for improving the frequency characteristics of the peripheral circuit (driving circuit). This is because the contact resistance between the metal electrode (such as Ti) and the oxide conductive layer can be reduced compared to the contact between the metal electrode (such as Ti ) and the oxide semiconductor layer. The structure of the oxide semiconductor layer, the low resistance drain region, and the drain electrode layer made of a metal material can further improve the breakdown voltage of the transistor. Specifically, the carrier concentration in the low resistance drain region is larger than that in the high resistance drain region (HRD region), and is preferably in the range of, for example, 1×10 / cm or more and 1×10 / cm 20 or less. 3 As the source region and the drain region, by providing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the low resistance of the source region and the drain region can be achieved, and the transistor can operate at high speed. Using the oxide conductive layer as the source region and the drain region is effective for improving the frequency characteristics of the peripheral circuit (driving circuit). This is because the contact resistance between the metal electrode (such as Ti) and the oxide conductive layer can be reduced compared to the contact between the metal electrode (such as Ti 21 / cm 3 ) and the oxide semiconductor layer. Preferably.

[0269] By using the oxide conductive layer as the source region and the drain region, the low resistance of the source region and the drain region can be achieved, and the transistor can operate at high speed. Using the oxide conductive layer as the source region and the drain region is effective for improving the frequency characteristics of the peripheral circuit (driving circuit). This is because the contact resistance between the metal electrode (such as Ti) and the oxide conductive layer can be reduced compared to the contact between the metal electrode (such as Ti ) and the oxide semiconductor layer. The oxide conductive layer provided between the oxide semiconductor layer and the source electrode layer and the drain electrode layer also functions as a low resistance drain region (also referred to as an LRN (Low Resistance N-type conductivity) region or an LRS (Low Resistance Source) region). By configuring the oxide semiconductor layer, the low resistance drain region, and the drain electrode layer made of a metal material, the breakdown voltage of the transistor can be further improved. Specifically, the carrier concentration in the low resistance drain region is larger than that in the high resistance drain region (HRD region), and is preferably in the range of, for example, 1×10 / cm or more and 1×10 / cm

[0270] In addition, molybdenum (Mo), which is used as part of the wiring material in a semiconductor device, has a problem in that (for example , Mo / Al / Mo) has a high contact resistance with the oxide semiconductor layer. This is because Mo is less likely to oxidize than Ti, so the action of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between Mo and the oxide semiconductor layer does not become n-type. However, even in such a case, by interposing an oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (drive circuit) can be improved.

[0271] Since the channel length of the thin film transistor is determined during the etching of the oxide conductive layer, shorter channel formation can be achieved. For example, by making the channel length as short as 0.1 μm or more and 2 μm or less, the operating speed can be increased.

[0272] Although Embodiment 1 has been described as an example, this embodiment can be implemented in appropriate combination with other embodiments.

[0273] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, a semiconductor device with reduced parasitic capacitance and low power consumption can be provided.

[0274] Also, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, a semiconductor device with high reliability can be provided.

[0275] (Embodiment 7) In this embodiment, an example in which the oxide semiconductor layer is surrounded by a nitride insulating film as seen in cross section is shown in FIG. 10. FIG. 10 shows the points where the upper surface shape and the position of the end portion of the oxide insulating layer are different from those in FIG. 1, and the Since they are the same except for the different configurations, the same reference numerals are used for the same parts, and detailed description of the same parts is omitted.

[0276] The thin film transistor 410 is a channel-etch type thin film transistor, and has an insulating surface On the substrate 400, a gate electrode layer 411, a first gate insulating layer 49 2a made of a nitride insulating film, a second gate insulating layer 492b made of an oxide insulating film, at least a channel formation region 413, an oxide semiconductor layer 412 having a high-resistance source region 414a and a high-resistance drain region 414b, a source electrode layer 415a, and a drain electrode layer 415b are included. Further, an oxide insulating layer 497b that covers the thin film transistor 410 and is in contact with the channel formation region of the oxide semiconductor layer 412 is provided. A protective insulating layer 498 is further formed on the oxide insulating layer 497b. An opening (contact hole) that reaches the source electrode layer 415a and the drain electrode layer 415b is formed in the oxide insulating layer 497b and the protective insulating layer 498, and wiring layers 417a, 417b, 418a, and 418b are formed in the opening. On the other hand, at the intersection, the gate wiring layer

[0277] 421 and the source wiring layers 422 and 423 are laminated with the gate insulating layer 402, the oxide insulating layer 497a and the protective insulating layer 498 interposed therebetween. In this embodiment, in the thin film transistor 410, the gate insulating layer has a laminated structure of a nitride insulating film and an oxide insulating film from the gate electrode layer side. Also, when forming the opening of the oxide insulating layer, the oxide insulating film of the second gate insulating layer is also selectively removed so that the nitride insulating film is exposed and processed.

[0278] In this embodiment, in the thin film transistor 410, the gate insulating layer has a laminated structure of a nitride insulating film and an oxide insulating film from the gate electrode layer side. Also, when forming the opening of the oxide insulating layer, the oxide insulating film of the second gate insulating layer is also selectively removed so that the nitride insulating film is exposed and processed. and processed so that the nitride insulating film is exposed.

[0279] ​​At least the upper surface shape of the oxide insulating layer 497b and the second gate insulating layer 492b is wider than the upper surface shape of the oxide semiconductor layer 412 and has an upper surface shape that covers the thin film transistor 410. This is preferable.

[0280] Furthermore, a protective insulating layer 498 made of a nitride insulating film is formed so as to cover the upper surface and the side surface of the oxide insulating layer 497b and to be in contact with the nitride insulating film of the first gate insulating layer 492a.

[0281] The protective insulating layer 498 made of a nitride insulating film and the first gate insulating layer 492a are inorganic insulating films that do not contain impurities such as moisture, hydrogen ions, and OH, etc., and block these from entering from the outside. These are silicon nitride films, silicon oxynitride films, aluminum nitride films, aluminum oxynitride films, etc. obtained by sputtering or plasma CVD methods. - These are used to block the entry of these from the outside.

[0282] In the present embodiment, as the protective insulating layer 498 made of a nitride insulating film, an RF sputtering method is used to surround the upper surface and the side surface of the oxide semiconductor layer 412, and a silicon nitride film with a film thickness of 100 nm is provided. Also, the protective insulating layer 498 is configured to be in contact with the first gate insulating layer 492a made of a nitride insulating film.

[0283] By adopting the structure shown in FIG. 10, it is possible to prevent the entry of moisture from the outside during the manufacturing process after the formation of the protective insulating layer 498 made of a nitride insulating film. Also, even after the device is completed as a semiconductor device, for example, a liquid crystal display device, it is possible to prevent the entry of moisture from the outside in the long term and improve the long-term reliability of the device.

[0284] In the present embodiment, although a configuration in which one thin film transistor is surrounded by a nitride insulating film is shown, It is not limited to this, and a configuration in which a plurality of thin film transistors are surrounded by a nitride insulating film may be adopted, or a configuration in which a plurality of thin film transistors in a pixel portion are collectively surrounded by a nitride insulating film may be adopted. At least a protective insulating layer 498 and a first gate insulating layer 492a are provided in a region where they are in contact with each other so as to surround the periphery of the pixel portion of the active matrix substrate.

[0285] This embodiment can be implemented in appropriate combination with other embodiments.

[0286] (Embodiment 8) In this embodiment, in the semiconductor device shown in Embodiments 1 to 7, a thin film transistor and a light emitting element using electroluminescence are used to show an example of manufacturing an active matrix type light emitting display device.

[0287] A light emitting element using electroluminescence is classified according to whether the light emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element and is so called.

[0288] In an organic EL element, when a voltage is applied to the light emitting element, electrons and holes are respectively injected into a layer containing a light emitting organic compound from a pair of electrodes, and a current flows. Then, these carriers (electrons and holes) recombine to form an excited state of the light emitting organic compound and emit light when the excited state returns to the ground state. From such a mechanism, such a light emitting element is called a current excitation type light emitting element.

[0289] An inorganic EL element is classified into a dispersed inorganic EL element and a thin film inorganic EL element according to its element configuration. It is classified. The distributed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. It is a device that uses a donor-acceptor recombination type of light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is a localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used as the light-emitting element for explanation. It is a localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used as the light-emitting element for explanation. Here, an organic EL element is used as the light-emitting element for explanation.

[0290] FIG. 11 is a diagram showing an example of a pixel configuration to which digital time-graded driving can be applied as an example of a semiconductor device.

[0291] The configuration and operation of a pixel to which digital time-graded driving can be applied will be described. Here, an n-channel transistor using an oxide semiconductor layer in a channel formation region is used for one pixel. An example of using two such transistors in one pixel is shown.

[0292] Pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitive element 6403. The switching transistor 64 01 has its gate connected to the scanning line 6406, and one of the first electrodes (either the source electrode or the drain electrode) is connected to the signal line 6405, and the other of the second electrodes (either the source electrode or the drain electrode) is connected to the gate of the driving transistor 6402. The driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitive element 6403, the first electrode is connected to the power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is the same The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is the same ​​​​It is electrically connected to a common potential line formed on the substrate.

[0293] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0294] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0295] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0296] Also, when analog grayscale driving is performed instead of digital time grayscale driving, the signal input is different. By doing so, the same pixel configuration as in FIG. 11 can be used.

[0297] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0298] Note that the pixel configuration shown in Fig. 11 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0299] Next, the configuration of the light emitting element will be described with reference to FIG. 12. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 12(A), (B), and (C). The driving TFTs 7001, 7011, and 7021 used in the semiconductor device are the same as those in the fourth embodiment. The thin film transistor can be manufactured in the same manner as the thin film transistor shown in FIG. Here is an example using the data.

[0300] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate. There are light-emitting elements with an upward emission structure for extracting light, a downward emission structure for extracting light from the surface on the substrate side, and a double-sided emission structure for extracting light from the surface on the substrate side and the surface opposite to the substrate. The pixel configuration can be applied to light-emitting elements of any emission structure.

[0301] The light-emitting element with the downward emission structure will be described with reference to Fig. 12(A).

[0302] A cross-sectional view of a pixel is shown when the driving TFT 7011 is of the n-type and the light emitted from the light-emitting element 7012 is emitted to the side of the first electrode 7013. In Fig. 12(A), wiring layers 7018a and 7018b electrically connected to the drain electrode layer of the driving TFT 7011 are formed, and a planarization insulating layer 7036 is formed thereon. The wiring layer 7018b is in contact with a conductive film 7017 having translucency at an opening formed in the planarization insulating layer 7036, and electrically connects the driving TFT 7011 and the conductive film 7017 having translucency. On the conductive film 7017 having translucency, the first electrode 7013 of the light-emitting element 7012 is formed, and an EL layer 7014 and a second electrode 7015 are sequentially laminated on the first electrode 7013.

[0303] As the conductive film 7017 having translucency, a conductive film having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can be used.

[0304] Also, various materials can be used for the first electrode 7013 of the light-emitting element. For example, the first When using the electrode 7013 as the cathode, materials with a small work function are preferred. Specifically, for example, alkali metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these elements (such as Mg:Ag and Al:Li), as well as rare earth metals such as Yb and Er are preferred. In Fig. 12(A), the film thickness of the first electrode 7013 is set to a level that allows light transmission (preferably, about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm is used as the first electrode 7013.

[0305] In addition, after laminating and forming a conductive film with light transmissibility and an aluminum film, they may be selectively etched to form a conductive film 7017 with light transmissibility and the first electrode 7013. In this case, since etching can be performed using the same mask, it is preferred.

[0306] Also, the peripheral portion of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane and is formed using a material such as an organic resin film, an inorganic insulating film, or an organic polysiloxane. The partition wall 7019 is preferably formed using a photosensitive resin material to form an opening on the first electrode 70 13, and the side wall of the opening is formed as an inclined surface with a continuous curvature. When using a photosensitive resin material for the partition wall 7019 , the process of forming a resist mask can be omitted.

[0307] In addition, the EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 only needs to include at least a light-emitting layer, and it may be composed of a single layer or multiple layers laminated. When the EL layer 7014 is composed of multiple layers, as the cathode it may be either case. When the EL layer 7014 is composed of multiple layers, On the first electrode 7013 that functions as such, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. These layers do not necessarily all have to be provided.

[0308] Also, it is not limited to the above lamination order. The first electrode 7013 can be made to function as an anode, and a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer can be laminated on the first electrode 7013 in this order. However, when comparing power consumption, it is preferable to make the first electrode 7013 function as a cathode and laminate an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer on the first electrode 7013 in this order. This is because it can suppress the voltage rise in the drive circuit section and reduce power consumption. Also, as the second electrode 7015 formed on the EL layer 7014, various materials can be used. For example, when the second electrode 7015 is used as an anode, materials with a large work function, such as ZrN, Ti, W, Ni, Pt, Cr, etc., or transparent conductive materials such as ITO, IZO, ZnO are preferable. Also, a shielding film 7016, for example, a metal that blocks light, a metal that reflects light, etc. is used on the second electrode 7015. In this embodiment, an ITO film is used as the second electrode 7015 and a Ti film is used as the shielding film 7016.

[0309] The region where the EL layer 7014 including the light-emitting layer is sandwiched between the first electrode 7013 and the second electrode 7015 corresponds to the light-emitting element 7012. In the case of the element structure shown in Fig. 12(A), the light emitted from the light-emitting element 7012 is emitted toward the first electrode 7013 side as indicated by the arrow.

[0310]

[0311] In Fig. 12(A), a conductive film having translucency is used as the gate electrode layer, and the source electrode ​​​​​​​​​​​An example is shown in which a thin film having translucency is used for the cathode layer and the drain electrode layer, and the light-emitting element The light emitted from 7012 passes through the color filter layer 7033 and is emitted through the substrate It can be made to do.

[0312] The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method using a photolithography graphy technique, etc. respectively.

[0313] Also, the color filter layer 7033 is covered with an overcoat layer 7034 and further covered with a protective insulating layer 7035. In FIG. 12(A), the overcoat layer 7034 is shown with a thin film thickness However, the overcoat layer 7034 has a function of flattening the unevenness caused by the color filter layer 7033.

[0314] Also, the contact holes formed in the protective insulating layer 7035, the insulating layer 7032, and the insulating layer 7031 and reaching the drain electrode layer are arranged at positions overlapping the partition wall 7019.

[0315] Next, the light-emitting element having a double-sided emission structure will be described with reference to FIG. 12(B).

[0316] In FIG. 12(B), wiring layers 7028a and 7028b electrically connected to the drain electrode layer of the driving TFT 7021 are formed, and a planarization insulating layer 7046 is formed thereon There is. The wiring layer 7028b is in contact with a conductive film 7027 having translucency at an opening formed in the planarization insulating layer 7046, and the driving TFT 7021 and the conductive film 702 7 having translucency are electrically connected. On the conductive film 7027 having translucency, the first electrode 7023 of the light-emitting element 7022 is formed, and on the first electrode 7023, an EL layer 7024, a second 7 and are electrically connected. On the conductive film 7027 having translucency, the first electrode 7023 of the light-emitting element 7022 is formed, and on the first electrode 7023, an EL layer 7024, a second electrode 7025, and a cathode layer 7026 are formed in this order. The electrodes 7025 are laminated in sequence.

[0317] As the conductive film 7027 having translucency, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, silicon oxide added indium tin oxide and other conductive films having translucency can be used.

[0318] Also, various materials can be used for the first electrode 7023. For example, when using the first electrode 7023 as a cathode, materials with a small work function, specifically, for example, alkali metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (Mg:Ag, Al:Li, etc.), as well as rare earth metals such as Yb and Er are preferable. In this embodiment, the first electrode 7023 is used as a cathode, and its film thickness is set to a degree that allows light to pass through (preferably about 5 nm to 30 nm).

[0319] Note that after laminating and forming the conductive film having translucency and the aluminum film, they may be selectively etched to form the conductive film 7027 having translucency and the first electrode 7023. In this case, etching can be

[0320] performed using the same mask, which is preferable. Also, the peripheral portion of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is an organic resin film such as polyimide,It is formed using light. The partition wall 7029 is formed using a photosensitive resin material in particular, and an opening is formed on the first electrode 70 23, and it is preferable that the side wall of the opening is formed as an inclined surface having a continuous curvature and is formed in such a manner. When using a photosensitive resin material as the partition wall 7029 , the process of forming a resist mask can be omitted.

[0321] Also, the EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 contains a light-emitting layer and may be composed of a single layer or may be configured such that a plurality of layers are laminated either way. When the EL layer 7024 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the first electrode 7023 that functions as a cathode . Note that it is not necessary to provide all of these layers.

[0322] Also, it is not limited to the above lamination order. Using the first electrode 7023 as an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer may be laminated in this order on the anode . However, when comparing power consumption, it is preferable to use the first electrode 7023 as a cathode and laminate an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer in this order on the cathode because the power consumption is less.

[0323] For the second electrode 7025 formed on the EL layer 7024, various materials can be used . For example, when using the second electrode 7025 as an anode, materials with a large work function, such as transparent conductive materials such as ITO, IZO, and ZnO, can be preferably used . In this embodiment, using the second electrode 7025 as an anode, an ITO film containing silicon oxide is formed

[0324] The first electrode 7023 and the second electrode 7025 sandwich an EL layer 7024 including a light-emitting layer. The region where the EL layer 7024 is sandwiched corresponds to the light-emitting element 7022. In the case of the element structure shown in Fig. 12(B), the light emitted from the light-emitting element 7022 is emitted to both the second electrode 7025 side and the first electrode 70 23 side as indicated by the arrows.

[0325] Note that in Fig. 12(B), a conductive film having translucency is used as the gate electrode layer, and an example using a thin film having translucency for the source electrode layer and the drain electrode layer is shown. The light emitted from the light-emitting element 7022 to the first electrode 7023 side can pass through the color filter layer 7043 and pass through the substrate and be emitted.

[0326] The color filter layer 7043 is formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using a photolithography graphy technique, etc., respectively.

[0327] Also, the color filter layer 7043 is covered with an overcoat layer 7044 and further covered with a protective insulating layer 7045.

[0328] Also, the contact holes formed in the protective insulating layer 7045, the insulating layer 7042, and the insulating layer 7041 and reaching the drain electrode layer are arranged at positions overlapping the partition wall 7029.

[0329] However, when using a light-emitting element with a double-sided emission structure and making both display surfaces full-color displays, since the light from the second electrode 7025 side does not pass through the color filter layer 7043, it is preferable to provide a sealing substrate with a separate color filter layer above the second electrode 7025.

[0330] Next, a light emitting element with a top emission structure will be described with reference to FIG.

[0331] In FIG. 12(C), the driving TFT 7001 is an n-type, and the light emitted from the light emitting element 7002 is FIG. 12C shows a cross-sectional view of a pixel when the second electrode 7005 is exposed. Wiring layers 7008a and 7008b electrically connected to the drain electrode layer of the TFT 7001 are A planarization insulating layer 7056 is formed on the wiring layer 7008b. In the opening formed in the planarization insulating layer 7056, the first electrode 700 of the light emitting element 7002 is 3, and connects the driving TFT 7001 and the first electrode 7003 of the light emitting element 7002 to each other. An EL layer 7004 and a second electrode 7005 are formed on a first electrode 7003 in this order. are stacked on top of each other.

[0332] In addition, various materials can be used for the first electrode 7003. For example, When using 03 as a cathode, a material with a small work function, specifically, Li or Cs, Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, including these In addition to alloys (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred.

[0333] The periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxane The partition wall 7009 is formed by using a photosensitive resin material, and the first electrode 70 03, an opening is formed on the surface, and the side wall of the opening is an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7009, The step of forming a resist mask can be omitted.

[0334] Also, the EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 may include at least a light-emitting layer, and may be composed of a single layer or may be configured such that a plurality of layers are stacked. When the EL layer 7004 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the first electrode 7003 used as the cathode. Note that it is not necessary to provide all of these layers.

[0335] Also, it is not limited to the above stacking order, and a hole injection layer , a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order on the first electrode 7003 used as the anode.

[0336] In FIG. 12(C), a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer are stacked in this order on a stacked film formed by stacking a Ti film, an aluminum film, and a Ti film in this order, and a stack of an Mg:Ag alloy thin film and ITO is formed thereon.

[0337] However, when the driving TFT 7001 is of the n-type, it is preferable to stack an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer in this order on the first electrode 7003, because it is possible to suppress the voltage increase in the driving circuit and reduce the power consumption.

[0338] The second electrode 7005 is formed using a conductive material having light-transmitting properties, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium , indium tin oxide containing titanium oxide, indium A conductive film having light transmissivity such as a tin oxide, an indium zinc oxide, or an indium tin oxide added with silicon oxide may be used.

[0339] An EL layer 7004 including a light emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. The region corresponds to a light emitting element 7002. In the case of the element structure shown in Fig. 12(C), the light emitted from the light emitting element 7 002 is emitted toward the second electrode 7005 as indicated by the arrow.

[0340] In Fig. 12(C), the drain electrode layer of the driving TFT 7001 is electrically connected to the first electrode 7003 through a contact hole provided in an oxide insulating layer 7051, a protective insulating layer 7052, a planarizing insulating layer 7056, a planarizing insulating layer 7053, and an insulating layer 7055. The planarizing insulating layers 7036, 7046, 7053, and 7056 can be formed of resin materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above resin materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. Note that the planarizing insulating layers 7036, 7046, 70 53, and 7056 may be formed by laminating a plurality of insulating films formed of these materials. The planarizing insulating layers 7036, 7046, 7053, and 705 6 are not particularly limited in the formation method, and depending on the material, a sputtering method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a roll coating method, a curtain coating method, a knife coating method, etc. can be used.

[0341] Further, a partition wall 7009 is provided to insulate the first electrode 7003 from the first electrodes of adjacent pixels. The partition wall 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. The partition wall 7009 is preferably formed using a photosensitive resin material to form an opening on the first electrode 7003, and the side wall of the opening is formed as an inclined surface having a continuous curvature. When a photosensitive resin material is used for the partition wall 7009, the step of forming a resist mask can be omitted.

[0342] In addition, in the structure of FIG. 12(C), when performing full-color display, for example, the light-emitting element 7002 is a green light-emitting element, one of the adjacent light-emitting elements is a red light-emitting element, and the other light-emitting element is a blue light-emitting element. Moreover, a light-emitting display device capable of full-color display may be manufactured using four types of light-emitting elements including not only three types of light-emitting elements but also a white element.

[0343] In addition, in the structure of FIG. 12(C), all of the plurality of light-emitting elements to be arranged are white light-emitting elements, and a sealing substrate having a color filter or the like is arranged above the light-emitting element 7002. A light-emitting display device capable of full-color display may be manufactured. By forming a material that exhibits single-color light emission such as white and combining a color filter or a color conversion layer, full-color display can be performed.

[0344] The source electrode layer or the drain electrode layer can be formed by the same processes and materials as the source electrode layer 415a and the drain electrode layer 415b shown in Embodiment 1. Also, the wiring layers 7008a, 7008b, 7018a, 7018b, 7028a, 7028b are also in Embodiment 1 ​ It can be formed by the same processes and materials as the wiring layers 417a, 417b, 418a, and 418b shown. This is possible.

[0345] The source electrode layer and the drain electrode layer are preferably thin films with a film thickness of 0.1 nm or more and 50 nm or less. A thinner film than the wiring layer is used. Since the source electrode layer and the drain electrode layer are thin conductive films, the parasitic capacitance with the gate electrode layer can be reduced. Therefore, a low-power semiconductor device having a thin-film transistor using an oxide semiconductor layer can be obtained.

[0346] Of course, single-color emission display may be performed. For example, an illumination device may be formed using white light emission, or an area color type light-emitting device may be formed using single-color emission.

[0347] Also, if necessary, an optical film such as a polarizing film such as a circular polarizing plate may be provided.

[0348] Here, the organic EL element has been described as the light-emitting element, but it is also possible to provide an inorganic EL element as the light-emitting element.

[0349] Note that an example in which a thin-film transistor (TFT for driving) that controls the driving of the light-emitting element and the light-emitting element are electrically connected has been shown, but a configuration in which a current control TFT is connected between the TFT for driving and the light-emitting element may also be used.

[0350] This embodiment can be implemented in appropriate combination with other embodiments.

[0351] (Embodiment 9) In this embodiment, regarding the appearance and cross-section of a light-emitting display panel (also referred to as a light-emitting panel), FIGS. 13 is a diagram showing a thin film transistor and a light emitting element formed on a first substrate. FIG. 13 is a plan view of a panel in which an element is sealed between a second substrate and the panel by a sealing material. (B) corresponds to a cross-sectional view taken along line HI in FIG. 13(A).

[0352] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0353] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 13B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0354] The highly reliable thin film transistor including the oxide semiconductor layer described in any of Embodiments 1 to 7 may be used as a pixel transistor. It can be used as a thin film transistor 4510 for a driver circuit. As the transistor 4509, a structure is adopted in which a conductive layer is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the thin film transistor shown in Embodiment 1. In this embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors. On the oxide insulating layer 4542, a conductive layer 4540 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the thin film transistor 4509 for the driving circuit. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, it is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4509 before and after the BT test. Also, the potential of the conductive layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509, or different, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state.

[0355] On the oxide insulating layer 4542, a conductive layer 4540 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the thin film transistor 4509 for the driving circuit. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, it is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4509 before and after the BT test. Also, the potential of the conductive layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509, or different, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state.

[0356] Also, an oxide insulating layer 4542 covering the oxide semiconductor layer of the thin film transistor 4510 is formed. The source electrode layer or drain electrode layer of the thin film transistor 4510 is electrically connected to the wiring layer 4550 at an opening formed in the oxide insulating layer 4542 and the insulating layer 4551 provided on the thin film transistor. The wiring layer 4550 is formed in contact with the first electrode 4517, and the thin film transistor 4510 and the first electrode 4517 are electrically connected via the wiring layer 4550.

[0357] The source electrode layer or drain electrode layer can be formed by the same processes and materials as the source electrode layer 415a and the drain electrode layer 415b shown in Embodiment 1. Also, the wiring layer 455 ​ The same processes as the wiring layers 417a, 417b, 418a, and 418b shown in Embodiment 1 and materials can be used to form them.

[0358] The source electrode layer and the drain electrode layer preferably have a thin film with a film thickness of 0.1 nm or more and 50 nm or less. A thinner film than the wiring layer is used. Since the source electrode layer and the drain electrode layer are thin conductive films, the parasitic capacitance with the gate electrode layer can be reduced. Therefore, a low-power semiconductor device having a thin-film transistor using an oxide semiconductor layer can be obtained.

[0359] The oxide insulating layer 4542 may be formed of the same materials and by the same method as the oxide insulating layer 407 shown in Embodiment 1. It may be formed in the same manner.

[0360] A color filter layer 4545 is formed on the insulating layer 4551 so as to overlap with the light-emitting region of the light-emitting element 4511. It is formed on the insulating layer 4551.

[0361] In addition, it is configured to be covered with an overcoat layer 4543 that functions as a planarizing insulating film to reduce surface irregularities of the color filter layer 4545. It is covered with an overcoat layer 4543.

[0362] An insulating layer 4544 is formed on the overcoat layer 4543. The insulating layer 4544 may be formed in the same manner as the protective insulating layer 408 shown in Embodiment 1. For example, a silicon nitride film may be formed by sputtering.

[0363] In addition, 4511 corresponds to a light-emitting element, and a first electrode 4517, which is a pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin-film transistor 4510 via a wiring layer 4550. The configuration of the light-emitting element 4511 is such that the first electrode 451 7 is electrically connected to the source electrode layer or the drain electrode layer of the thin-film transistor 4510 via a wiring layer 4550. 7. It has a stacked structure of an electroluminescent layer 4512 and a second electrode 4513, but is not limited to the shown configuration. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like. It is not limited. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like. It can be changed as appropriate.

[0364] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode 4517 so that the side wall of the opening becomes an inclined surface formed with a continuous curvature. It is preferably formed so as to be an inclined surface formed with a continuous curvature.

[0365] The electroluminescent layer 4512 may be composed of a single layer or may be configured by laminating a plurality of layers. Either is acceptable.

[0366] A protective film may be formed on the second electrode 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed. A protective film may be formed on the second electrode 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed. It can be formed.

[0367] Also, various signals and potentials applied to the signal line drive circuits 4503a, 4503b, the scan line drive circuits 4504a, 4504b, or the pixel portion 4502 are supplied from the FPCs 4518a, 4518b. Also, various signals and potentials applied to the signal line drive circuits 4503a, 4503b, the scan line drive circuits 4504a, 4504b, or the pixel portion 4502 are supplied from the FPCs 4518a, 4518b. It is supplied from.

[0368] The connection terminal electrode 4515 is formed from the same conductive film as the first electrode 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed from the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistor 4509. The connection terminal electrode 4515 is formed from the same conductive film as the first electrode 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed from the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistor 4509. It is formed.

[0369] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. It is electrically connected.

[0370] The second substrate positioned in the light extraction direction from the light-emitting element 4511 must be translucent. Otherwise, a translucent material such as a glass plate, plastic plate, polyester film, or acrylic film is used.

[0371] In addition, as the filler 4507, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. That's all.

[0372] Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element. Also, an antireflection film may be provided on the polarizing plate or circular polarizing plate. For example, due to the unevenness of the surface diffuse the reflected light and reduce the reflection, and an antiglare treatment can be performed.

[0373] The signal line drive circuits 4503a, 4503b, and the scan line drive circuits 4504a, 4504b may be mounted on a drive circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line drive circuit, or a part thereof, or only the scan line drive circuit, or a part thereof may be separately formed and mounted, and is not limited to the configuration of FIG. 13.

[0374] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. That's all.​

[0375] This embodiment can be implemented in appropriate combination with other embodiments.

[0376] (Embodiment 10) Regarding the appearance and cross-section of a liquid crystal display panel corresponding to one form of a semiconductor device, it will be described with reference to FIG. 14. FIG. 14 shows thin film transistors 4010, 4011, and a liquid crystal element 4013 sealed between a first substrate 4001 and a second substrate 4006 by a sealing material 4005. FIG. 14(A) is a plan view of the panel, and FIG. 14(B) corresponds to a cross-sectional view taken along M-N in FIG. 14(A) or FIG. 14(C).

[0377] The sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Further, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0378] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method, etc. can be used. FIG. 14(A) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 14(C) is an example of mounting the signal line driving circuit 4003 by the TAB method.

[0379] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 have a plurality of thin film transistors. In FIG. 14(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. Insulating layers 4041, 404 2, 4020, and 4021 are provided on the thin film transistors 4010 and 4011.

[0380] As the thin film transistors 4010 and 4011, highly reliable thin film transistors including the oxide semiconductor layer shown in Embodiments 1 to 7 can be applied. As the thin film transistor 4011 for the driving circuit and the thin film transistor 4010 for the pixel, the thin film transistors shown in Embodiments 1 to 7 can be used. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0381] On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the thin film transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4011 before and after the BT test can be reduced. Further,

[0382] the potential of the conductive layer 4040 may be the same as that of the gate electrode layer of the thin film transistor 4011, or different, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state.

[0382] The pixel electrode layer 4030 of the liquid crystal element 4013 is The source electrode layer or the drain electrode layer is electrically connected to the source electrode layer or the drain electrode layer through a wiring layer 4050 . The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The overlapping portion of the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 is The pixel electrode layer 4030 and the counter electrode layer 4031 correspond to the liquid crystal element 4013. Insulating layers 4032 and 4033 are provided to function as alignment films. The liquid crystal layer 4008 is sandwiched between the two layers 3 .

[0383] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film Films can be used.

[0384] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrode layer 40 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0385] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. Since it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small.

[0386] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0387] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In this example, the polarizing plate is provided on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment, and the materials of the polarizing plate and the colored layer and The conditions may be appropriately set depending on the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0388] An insulating layer 4041 is provided over the thin film transistors 4011 and 4010 in contact with the oxide semiconductor layer. The insulating layer 4041 is formed using a material similar to that of the oxide insulating layer 407 described in Embodiment 1. Here, the insulating layer 4041 may be formed by the same material and method as in Embodiment 1. A silicon oxide film is formed by sputtering. The protective insulating layer 4042 is formed by the same method as in the first embodiment. It may be formed in the same manner as 408, and for example, a silicon nitride film may be used. It is configured to be covered with an insulating layer 4021 that functions as a planarization insulating film to reduce the surface unevenness of the thin-film transistor on the edge layer 4042.

[0389] Further, the insulating layer 4021 is formed as a planarization insulating film. As the insulating layer 4021, heat-resistant organic materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low-dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials.

[0390] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, sputtering method, spin coating method, dipping method, spray coating method, droplet ejection method (inkjet method, screen printing, offset printing, etc.), roll coating method, curtain coating method, knife coating method, etc. can be used. By combining the firing process of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device.

[0391] The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed of a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc.

[0392] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0393] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0394] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0395] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0396] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0397] In FIG. 14, a signal line driver circuit 4003 is separately formed and mounted on a first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0398] In addition, the liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical A lignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc.

[0399] In addition, an example of a VA type liquid crystal display device is shown below.

[0400] The VA type liquid crystal display device is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. The VA type liquid crystal display device is a method in which liquid crystal molecules face the panel surface in the vertical direction when no voltage is applied. In this embodiment, in particular, pixels are divided into several regions (sub-pixels), and the molecules are arranged to be tilted in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device considering multi-domain design will be described.

[0401]

[0401] Figures 15 and 16 show the pixel structure of a VA type liquid crystal display panel. Figure 16 shows the substrate 600. is a plan view, and the cross-sectional structure corresponding to the cutting line Y-Z shown in the figure is shown in FIG. 15. In the following explanation, both of these two figures will be referred to for the explanation.

[0402] This pixel structure has a plurality of pixel electrodes in one pixel, and each pixel electrode is connected to a TFT subsequently. Each TFT is configured to be driven by a different gate signal. That is, in the pixels designed with multi-domain, the signals applied to the individual pixel electrodes have a configuration of being independently controlled.

[0403] The pixel electrode layer 624 is connected to the source electrode layer or drain electrode layer 618 of the TFT 628 via the wiring 6 62 at the contact hole 623 and the contact hole 660. Also, the pixel electrode layer 626 is provided with a contact hole 627 provided in the insulating layer 620 and the insulating layer 622 covering the insulating layer 620 and the contact hole 661, and is connected to the source electrode layer or drain electrode layer 619 of the TFT 6 29 via the wiring 663. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are separated so that different gate signals can be applied thereto. On the other hand, the source electrode layer or drain electrode layer 616 that functions as a data line is commonly used by the TFT 628 and the TFT 629. The TFT 628 and the TFT 629 can appropriately use any one of the thin film transistors of Embodiments 1 to 7. The TFT 629 can appropriately use any one of the thin film transistors of Embodiments 1 to 7. The TFT 628 and the TFT 629 can appropriately use any one of the thin film transistors of Embodiments 1 to 7. can be.

[0404] The source electrode layer or drain electrode layers 616, 618, and 619 can be formed by the same processes and materials as the source electrode layer 415a and the drain electrode layer 415b shown in Embodiment 1. Also, the wirings 662 and 663 are also the wiring layers 417a, 417b, and 41 shown in Embodiment 1 The source electrode layer or drain electrode layers 616, 618, and 619 can be formed by the same processes and materials as the source electrode layer 415a and the drain electrode layer 415b shown in Embodiment 1. shown in Embodiment 1. It can be formed by the same processes and materials as 8a and 418b.

[0405] The source electrode layer and the drain electrode layer are preferably thin films with a film thickness of 0.1 nm or more and 50 nm or less. A film thinner than the wiring is used. Since the source electrode layer and the drain electrode layer are thin conductive films, the parasitic capacitance with the gate electrode layer can be reduced. Therefore, a low-power semiconductor device having a thin-film transistor using an oxide semiconductor layer can be obtained.

[0406] In addition, a capacitive wiring 690 is provided, and a holding capacitance is formed with a dielectric being the stack of the gate insulating layer 606 and a capacitive electrode that is electrically connected to the pixel electrode or the pixel electrode.

[0407] The shapes of the pixel electrode layer 624 and the pixel electrode layer 626 are different and are separated by a slit 625. The pixel electrode layer 626 is formed so as to surround the outside of the pixel electrode layer 624 that spreads in a V shape. By making the timing of the voltages applied to the pixel electrode layer 624 and the pixel electrode layer 626 different by the TFTs 628 and 629, the alignment of the liquid crystal is controlled. The equivalent circuit of this pixel structure is shown in FIG. 18. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. By applying different gate signals to the gate wiring 602 and the gate wiring 603, the operation timings of the TFT 628 and the TFT 629 can be made different.

[0408] On the counter substrate 601, a light-shielding film 632, a second colored film 636, and a counter electrode layer 640 are formed. Further, a planarization film 637, also called an overcoat film, is formed between the second colored film 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. On the counter substrate side in FIG. 17 The structure is shown. The counter electrode layer 640 is an electrode that is shared among different pixels, but there is a slit 641 formed. By arranging this slit 641 and the slit 625 on the side of the pixel electrode layer 624 and the pixel electrode layer 6 26 to alternately engage with each other, an oblique electric field can be effectively generated to control the alignment of the liquid crystal. As a result, the direction in which the liquid crystal aligns can be made different depending on the location , thus widening the viewing angle.

[0409] The first liquid crystal element is formed by the overlapping of the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640. Also, the second liquid crystal element is formed by the overlapping of the pixel electrode layer 626, the liquid crystal layer 650, and the counter electrode layer 640. Moreover, it is a multi-domain structure in which the first liquid crystal element and the second liquid crystal element are provided in one pixel.

[0410] This embodiment can be implemented in appropriate combination with other embodiments.

[0411] (Embodiment 11) In this embodiment, an example of an electronic paper is shown as a semiconductor device which is one embodiment of the present invention.

[0412] FIG. 19 shows an active matrix type electronic paper as an example of a semiconductor device to which one embodiment of the present invention is applied. As the thin film transistor 581 used in the semiconductor device, any one of the thin film transistors of Embodiments 1 to 7 can be appropriately used.

[0413] The electronic paper in FIG. 19 is an example of a display device using the twist ball display method. The twist ball display method uses spherical particles painted white and black as display elements and is an electrode layer is disposed between the first electrode layer and the second electrode layer, and a potential difference is applied between the first electrode layer and the second electrode layer to control the orientation of the spherical particles, thereby performing display.

[0414] The thin film transistor 581 provided on the substrate 580 is a thin film transistor having a bottom gate structure and the source electrode layer or the drain electrode layer is electrically connected to the wiring layers 589a and 589b at an opening formed in the oxide insulating layer 583 and the protective insulating layer 584 . The wiring layer 5 89b is provided in contact with the first electrode layer 587 at an opening formed in the insulating layer 585 provided above, and the thin film transistor 581 and the first electrode layer 587 are electrically connected via the wiring layers 58 9a and 589b .

[0415] The source electrode layer or the drain electrode layer can be formed by the same processes and materials as the source electrode layer 415a and the drain electrode layer 415b shown in Embodiment 1. Further, the wiring layers 589 a and 589b can also be formed by the same processes and materials as the wiring layers 417a, 417b, 418a, and 418b shown in Embodiment 1 .

[0416] The source electrode layer and the drain electrode layer are preferably thin films having a film thickness of 0.1 nm or more and 50 nm or less , and a thinner film than the wiring layer is used. Since the source electrode layer and the drain electrode layer are thin conductive films , the parasitic capacitance with the gate electrode layer can be reduced. Therefore, a low power consumption semiconductor device having a thin film transistor using an oxide semiconductor layer can be obtained .

[0417] Between the first electrode layer 587 and the second electrode layer 588, there are a black region 590a and a white region 59 ​There is provided a spherical particle having 0b and including a cavity 594 filled with a liquid around it. The periphery of the spherical particle is filled with a filler 595 such as resin (see Fig. 19). In this embodiment, the first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 provided on the counter substrate 596 corresponds to the common electrode.

[0418] Also, instead of the twist ball, it is also possible to use an electrophoretic element. A transparent liquid and microcapsules with a diameter of about 10 μm to 20 0 μm, which encapsulate positively charged white fine particles and negatively charged black fine particles, are used. The microcapsules provided between the first electrode layer and the second electrode layer will cause the white fine particles and the black fine particles to move in opposite directions when an electric field is applied by the first electrode layer and the second electrode layer, and can display white or black. The display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required and the power consumption is small, and it is possible to recognize the display portion even in a dim place. Also when the power is not supplied to the display portion, it is possible to hold the image once displayed so that even when the semiconductor device with a display function (also simply called a display device or a semiconductor device having a display device) is separated from the radio wave transmission source it is possible to save the displayed image.

[0419] Through the above steps, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0420] This embodiment can be implemented in appropriate combination with other embodiments.

[0421] (Embodiment 12) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as TVs or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large gaming machines such as pachinko machines.

[0422] FIG. 20(A) shows an example of a mobile phone 1100. The mobile phone 1100 includes a display unit 1102 incorporated in a housing 1101, operation buttons 1103, an external connection port 1104, a speaker 1105, a microphone 1106, and the like.

[0423] For the mobile phone 1100 shown in FIG. 20(A), information can be input by touching the display unit 1102 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 1102 with a finger or the like.

[0424] The screen of the display unit 1102 mainly has three modes. The first is a display mode mainly for displaying images, the second is an input mode mainly for inputting information such as characters, and the third is a display + input mode in which the two modes of the display mode and the input mode are mixed.

[0425] For example, when making a call or creating an email, the display unit 1102 can be set to the character input mode mainly for inputting characters, and an input operation on the characters displayed on the screen can be performed. In this case ​​​​​​​​​​​It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1102. Preferably.

[0426] Also, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1100, the orientation (portrait or landscape) of the mobile phone 1100 can be determined, and the screen display of the display unit 1102 can be automatically switched.

[0427] Also, the switching of the screen mode is performed by touching the display unit 1102 or operating the operation button 1103 of the housing 1101. Also, it can be switched according to the type of image displayed on the display unit 1102. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0428] Also, in the input mode, the signal detected by the optical sensor of the display unit 1102 is detected, and when there is no input by touch operation of the display unit 1102 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode.

[0429] The display unit 1102 can also function as an image sensor. For example, by touching the palm or finger on the display unit 11 02, fingerprint, palmprint, etc. can be imaged to perform personal authentication. Also, by using a backlight that emits near-infrared light or a light source for a sensor that emits near-infrared light on the display unit, finger vein, palm vein, etc. can also be imaged.

[0430] A plurality of thin film transistors shown in Embodiment 1 are arranged as pixel switching elements on the display unit 1102.

[0431] Figure 20(B) is also an example of a mobile phone. The portable information terminal using Figure 20(B) as an example can be equipped with multiple functions. For example, in addition to the telephone function, it can incorporate a computer and be equipped with various data processing functions.

[0432] The portable information terminal shown in Figure 20(B) is composed of two housings, namely housing 1800 and housing 1801. Housing 1800 is equipped with a display panel 1802, a speaker 1803, a microphone 1804, a pointing device 1806, a camera lens 1807, an external connection terminal 1808, etc. Housing 1801 is equipped with a keyboard 1810, an external memory slot 1811, etc. Also, the antenna is built inside housing 1801.

[0433] In addition, the display panel 1802 is equipped with a touch panel, and a plurality of operation keys 1805 that are being video-displayed in Figure 20(B) are shown by dotted lines.

[0434] In addition to the above configuration, a non-contact IC chip, a small recording device, etc. may be incorporated.

[0435] The light-emitting device can be used for the display panel 1802, and the display direction changes appropriately according to the usage form. Also, since the camera lens 1807 is provided on the same surface as the display panel 1802, a videophone is possible. The speaker 1803 and the microphone 1804 are not limited to voice calls, and videophone, recording, playback, etc. are possible. Furthermore, the housing 1800 and the housing 1801 can slide and change from the unfolded state as shown in Figure 20(B) to an overlapping state, enabling miniaturization suitable for portability.

[0436] The external connection terminal 1808 can be connected to various cables such as an AC adapter and a USB cable and is capable of charging and data communication with a personal computer or the like. Also, an external recording medium can be inserted into the external memory slot 1811 to support storage and transfer of a larger amount of data .

[0437] In addition to the above functions, it may also be provided with an infrared communication function, a television receiving function, etc. .

[0438] FIG. 21(A) shows an example of a television apparatus 9600. The television apparatus 96 00 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display an image . Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown .

[0439] The operation of the television apparatus 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation unit 9610. Channel and volume operations can be performed by operation keys 9609 provided in the remote control operation unit 9610, and the image displayed on the display unit 9603 can be operated . Also, the remote control operation unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control operation unit 9610 .

[0440] Note that the television apparatus 9600 has a configuration including a receiver, a modem, etc. The receiver can receive more general television broadcasts, and can further be connected to a communication network by wire or wirelessly via the modem to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication is also possible .

[0441] In the display unit 9603, a plurality of thin film transistors shown in Embodiment 1 are arranged as pixel switching elements.

[0442] FIG. 21(B) shows a digital photo frame 9700 as an example of a digital photo frame. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and for example, by displaying image data taken with a digital camera or the like, it can function in the same way as a normal photo stand.

[0443] In the display unit 9703, a plurality of thin film transistors shown in Embodiment 1 are arranged as pixel switching elements.

[0444] Note that the digital photo frame 9700 includes an operation unit, external connection terminals (such as USB terminals and terminals connectable to various cables such as USB cables), a recording medium insertion unit, and the like. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because it improves the design. For example, by inserting a memory storing image data taken with a digital camera into the recording medium insertion unit of the digital photo frame 9700, the image data can be captured and the captured image data can be displayed on the display unit 9703.

[0445] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly.

[0446] ​​​​​​​​FIG. 22 shows a portable gaming machine, which is composed of two casings, a casing 9881 and a casing 9891, and is connected in an openable and closable manner by a connecting portion 9893. A display portion 9882 is incorporated in the casing 9881, and a display portion 9883 is incorporated in the casing 9891. A plurality of thin film transistors shown in the first embodiment are arranged as pixel switching elements in the display portion 9883.

[0447]

[0448] In addition, the portable gaming machine shown in FIG. 22 further includes a speaker portion 9884, a recording medium insertion portion 9886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9888 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration including at least the thin film transistor disclosed in this specification, and other accessory equipment may be provided as appropriate. The portable gaming machine shown in FIG. 22 has a function of reading a program or data recorded on a recording medium and displaying it on the display portion, and a function of wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in FIG. 22 are not limited to this, and it can have various functions.

[0449] FIG. 24 shows an example in which a light emitting device formed by applying the above embodiment is used as an indoor lighting device 3001. The light emitting device shown in the fourth embodiment or the fifth embodiment can also be made larger in area. Since it has such capabilities, it can be used as a large-area lighting device. Also, the light-emitting device shown in the above embodiment can also be used as a desktop lighting fixture 3000. Note that lighting fixtures include ceiling-mounted lighting fixtures, desktop lighting fixtures, wall-mounted lighting fixtures, in-vehicle lighting, induction lamps, and the like.

[0450] As described above, the thin-film transistors shown in any one of Embodiments 1 to 7 can be arranged on the display panels of various electronic devices as described above in this way. By using the thin-film transistor as a switching element of the display panel , a highly reliable electronic device can be provided.

[0451] (Embodiment 13) The semiconductor device disclosed in this specification can be applied as an electronic paper. The electronic paper can be used in electronic devices in any field as long as it can display information . For example, using the electronic paper, it can be applied to displays in electronic books (e-books), posters, in-vehicle advertisements on vehicles such as trains, and various cards such as credit cards . An example of an electronic device is shown in FIG. 23.

[0452] FIG. 23 shows an e-book 2700 as an example of an e-book. For example, the e-book 27 00 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can perform an opening and closing operation around the shaft portion 2711 . With such a configuration, it is possible to perform operations similar to those of a paper book .

[0453] A display portion 2705 is incorporated in the housing 2701, and a display portion 2707 is incorporated in the housing 2703 The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 23) and An image can be displayed on the display unit 2707 in FIG.

[0454] 23 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a board, a pointing device, etc. Also, the back and sides of the housing may be On the front, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable). The configuration includes a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. Good too.

[0455] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0456] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

Claims

【Claim 1】 a gate electrode layer; a gate insulating layer on the gate electrode layer; an oxide semiconductor layer on the gate insulating layer; a source electrode layer and a drain electrode layer on the oxide semiconductor layer; an oxide insulating layer in contact with the oxide semiconductor layer on the source electrode layer and the drain electrode layer; a wiring layer electrically connected to the source electrode layer or the drain electrode layer on the oxide insulating layer, wherein the oxide insulating layer is provided with an opening reaching the source electrode layer or the drain electrode layer, the wiring layer is in contact with the source electrode layer or the drain electrode layer at the opening, and the gate electrode layer and the wiring layer partially overlap with each other via the gate insulating layer and the oxide semiconductor layer. A semiconductor device characterized by this.

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