Display device

Abstract

To suppress the decrease in reliability.SOLUTION: In an embodiment, a display device includes a substrate, a first lower electrode disposed over the substrate, an inorganic insulating layer covering a peripheral edge part of the first lower electrode, a partition wall including a lower part disposed on the inorganic insulating layer and formed of a conductive material and an upper part disposed on the lower part and projecting from a first side surface of the lower part and a second side surface on the opposite side of the first side surface, a first multilayer film including a first organic layer in contact with the first lower electrode and a first upper electrode disposed on the first organic layer and in contact with the lower part, a first barrier layer disposed on the first multilayer film, in contact with the first side surface, extending over the partition wall, forming a space from the upper part, and formed of a first inorganic insulating material, a first sealing layer overlapping with the first barrier layer and formed of a second inorganic insulating material that is different from the first inorganic insulating material, and a resin layer covering the first sealing layer and filling the space.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, a display device includes a substrate, a first lower electrode disposed above the substrate, an inorganic insulating layer covering a peripheral portion of the first lower electrode, a lower portion formed of a conductive material disposed on the inorganic insulating layer, a partition wall having an upper portion disposed on the lower portion and protruding from a first side surface of the lower portion and a second side surface opposite to the first side surface, a first organic layer in contact with the first lower electrode, and a first upper electrode disposed on the first organic layer and in contact with the lower portion, a first stacked film including the above; a first barrier layer formed of a first inorganic insulating material, disposed on the first stacked film, in contact with the first side surface, extending above the partition wall, and forming a gap with the upper portion; a first sealing layer formed of a second inorganic insulating material different from the first inorganic insulating material and overlapping the first barrier layer; and a resin layer covering the first sealing layer and filling the gap.

[0006] According to one embodiment, a display device includes a substrate, a first lower electrode disposed above the substrate, an inorganic insulating layer covering a peripheral portion of the first lower electrode, a lower portion formed of a conductive material disposed on the inorganic insulating layer, a partition wall having an upper portion disposed on the lower portion and protruding from a first side surface of the lower portion and a second side surface opposite to the first side surface, a first organic layer in contact with the first lower electrode, and a first upper electrode disposed on the first organic layer and in contact with the lower portion, a first stacked film including the above; a resin layer disposed on the upper portion; a first barrier layer formed of a first inorganic insulating material and overlapping the resin layer; and a first sealing layer formed of a second inorganic insulating material different from the first inorganic insulating material and overlapping the first barrier layer.

Brief Description of the Drawings

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[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually perpendicular X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0010] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0011] FIG. 1 is a diagram showing an example of the configuration of a display device DSP.

[0012] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, second color, and third color are different from each other. Note that the pixel PX may include subpixels SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] The element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be referred to as an organic EL element.

[0019] The peripheral region SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along the first direction X. Each of the terminals TE extends in the second direction Y, but is not limited thereto. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0020] FIG. 2 is a diagram showing an example of the layout of the sub-pixels SP1, SP2, and SP3.

[0021] In the illustrated example, the sub-pixels SP2 and SP3 are arranged in the second direction Y. The sub-pixels SP1 and SP2 are arranged in the first direction X, and the sub-pixels SP1 and SP3 are arranged in the first direction X.

[0022] When the sub-pixels SP1, SP2, and SP3 have such a layout, in the display area DA, a column in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y and a column in which a plurality of sub-pixels SP1 are arranged in the second direction Y are formed. These columns are alternately arranged in the first direction X.

[0023] Note that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example of FIG. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0024] An inorganic insulating layer 5 and a partition wall 6 are arranged in the display area DA. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0025] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the inorganic insulating layer 5. The partition wall 6 is conductive and electrically connected to the terminal TE of the common potential among the multiple terminals TE shown in FIG. 1 .

[0026] The subpixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0027] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each overlapping with the aperture AP1. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a planar view. The peripheries of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR1 includes a light-emitting layer that emits light in, for example, a blue wavelength region.

[0028] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the aperture AP2. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a planar view. The peripheries of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0029] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each overlapping with the aperture AP3. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a planar view. The peripheries of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR3 includes a light-emitting layer that emits light in the red wavelength range, for example.

[0030] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect their exact shapes.

[0031] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or common electrodes, and are in contact with the partition walls 6.

[0032] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the subpixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the subpixel SP3.

[0033] In the illustrated example, the areas of openings AP1, AP2, and AP3 are different from one another. The area of opening AP1 is larger than the area of opening AP2, and the area of opening AP2 is larger than the area of opening AP3. In other words, the area of the lower electrode LE1 exposed through opening AP1 is larger than the area of the lower electrode LE2 exposed through opening AP2, and the area of the lower electrode LE2 exposed through opening AP2 is larger than the area of the lower electrode LE3 exposed through opening AP3.

[0034] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0035] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1 and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens unevenness caused by the circuit layer 11.

[0036] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and spaced apart from one another. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the inorganic insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted from FIG. 3 .

[0037] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the respective side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0038] In the illustrated example, the lower portion 61 has a first conductive layer 63 disposed on the inorganic insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. The first conductive layer 63 is formed thinner than the second conductive layer 64. Both end portions of the first conductive layer 63 protrude from each side surface of the second conductive layer 64. The upper portion 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both ends of the first thin film 65 and the second thin film 66 protrude from each side of the second conductive layer 64.

[0039] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0040] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral portion located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower portion 61.

[0041] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral portion located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower portion 61.

[0042] In the illustrated example, the sub-pixel SP1 has a cap layer CP1, a barrier layer BL1, and a sealing layer SE1, the sub-pixel SP2 has a cap layer CP2, a barrier layer BL2, and a sealing layer SE2, and the sub-pixel SP3 has a cap layer CP3, a barrier layer BL3, and a sealing layer SE3. The cap layers CP1, CP2, and CP3 each serve as an optical adjustment layer for improving the light extraction efficiency of the light emitted from the organic layers OR1, OR2, and OR3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0043] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0044] The barrier layer BL1 is disposed on the cap layer CP1, is in contact with the lower portion 61, extends above the upper portion 62, and forms a gap GP1 between it and the upper portion 62. The barrier layer BL2 is disposed on the cap layer CP2, is in contact with the lower portion 61, extends above the upper portion 62, and forms a gap GP2 between it and the upper portion 62. Above the upper portion 62, the barrier layer BL2 is spaced apart from the barrier layer BL1. The barrier layer BL3 is disposed on the cap layer CP3, contacts the lower portion 61, extends above the upper portion 62, and forms a gap GP3 with the upper portion 62. Above the upper portion 62, the barrier layer BL3 is spaced apart from the barrier layers BL1 and BL2.

[0045] The sealing layer SE1 overlaps the barrier layer BL1, does not contact the partition wall 6, and extends above the partition wall 6. In the example shown, the void CV1 surrounded by the sealing layer SE1 is formed below the upper part 62 at a position facing the lower part 61. The sealing layer SE2 overlaps the barrier layer BL2, does not contact the partition wall 6, extends above the partition wall 6, and is spaced apart from the sealing layer SE1. In the illustrated example, the void CV2 surrounded by the sealing layer SE2 is formed below the upper part 62 at a position facing the lower part 61. The sealing layer SE3 overlaps the barrier layer BL3, does not contact the partition wall 6, extends above the partition wall 6, and is spaced apart from the sealing layers SE1 and SE2. In the example shown, the void CV3 surrounded by the sealing layer SE3 is formed below the upper part 62 at a position facing the lower part 61.

[0046] In the following description, the multilayer structure including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer structure including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer structure including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0047] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. As shown in the figure, the resin layer 13 contacts the upper part of the partition wall 6 between the sealing layer SE1 and the sealing layer SE2, and between the sealing layer SE1 and the sealing layer SE3. The resin layer 13 also fills a gap GP1 surrounded by the upper part 62 and the barrier layer BL1, a gap GP2 surrounded by the upper part 62 and the barrier layer BL2, and a gap GP3 surrounded by the upper part 62 and the barrier layer BL3. Note that there may be cases where the gaps GP1, GP2, and GP3 are not completely filled with the resin layer 13, and air bubbles may be present.

[0048] The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with an overcoat layer 15.

[0049] The inorganic insulating layer 5, the barrier layers BL1, BL2, and BL3, the sealing layers SE1, SE2, and SE3, and the sealing layer 14 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). The second inorganic insulating material for forming the sealing layers SE1, SE2, and SE3 is a material different from the first inorganic insulating material for forming the barrier layers BL1, BL2, and BL3. Furthermore, when the sealing layers SE1, SE2, and SE3 are dry-etched, the etching rate of the first inorganic insulating material is smaller than the etching rate of the second inorganic insulating material.

[0050] For example, the barrier layers BL1, BL2, and BL3 are formed of silicon oxynitride as a first inorganic insulating material, and the sealing layers SE1, SE2, and SE3 are formed of silicon nitride as a second inorganic insulating material. The inorganic insulating layer 5 is formed of silicon oxynitride, which is the same inorganic insulating material as the barrier layers BL1, BL2, and BL3. The sealing layer 14 is formed of silicon nitride, which is the same inorganic insulating material as the sealing layers SE1, SE2, and SE3.

[0051] The overcoat layer 15 is made of the same resin material as the resin layer 13 .

[0052] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0053] The upper portion 62 of the partition 6 is formed of, for example, a conductive material, but may be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The first thin film 65 is formed of a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of an oxide conductive material such as indium tin oxide (ITO).

[0054] The lower electrodes LE1, LE2, and LE3 are a multilayer body including, for example, a transparent layer formed of an oxide conductive material such as ITO and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are a multilayer body including a reflective layer between a pair of transparent layers.

[0055] The organic layer OR1 includes the light-emitting layer EM1. The organic layer OR2 includes the light-emitting layer EM2. The organic layer OR3 includes the light-emitting layer EM3. The light-emitting layers EM1, EM2, and EM3 are formed of different materials from each other. In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength range. Also, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0056] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0057] The cap layers CP1, CP2, and CP3 are a multilayer body of a plurality of thin films. The plurality of thin films are all transparent and have different refractive indices from each other.

[0058] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are arranged across the display area DA and the peripheral area SA.

[0059] Next, a method for manufacturing a display device DSP will be described. Note that illustrations below the insulating layer 12 are omitted in each figure for explaining the manufacturing method.

[0060] First, as shown in FIG. 4, a processing substrate SUB having lower electrodes LE1, LE2, LE3, an inorganic insulating layer 5, and a partition wall 6 is prepared. The step of preparing the processing substrate SUB includes the following steps. That is, on the substrate 10, a circuit layer 11 and an insulating layer 12 are formed across the display area DA and the peripheral area SA. Then, on the insulating layer 12, the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 are formed. Then, an inorganic insulating layer 5 covering the peripheral portions of the lower electrodes LE1, LE2, LE3 is formed. Then, a partition wall 6 having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61 is formed. The first conductive layer 63 and the upper portion 62 of the lower portion 61 protrude from respective side surfaces of the second conductive layer 64 of the lower portion 61. Note that the step of forming openings AP1, AP2, and AP3 in the inorganic insulating layer 5 may be performed before or after forming the partition wall 6.

[0061] Subsequently, a display element DE1 is formed.

[0062] First, as shown in FIG. 5, a laminated film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The step of forming the laminated film FL1 includes the following steps. That is, in the opening AP1, an organic layer OR1 in contact with the lower electrode LE1 is formed. The step of forming the organic layer OR1 includes steps of forming a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like, respectively. Then, an upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6 is formed. Then, a cap layer CP1 located on the upper electrode UE1 is formed.

[0063] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by vapor deposition using the partition wall 6 as a mask. The laminated film FL1 is divided into a plurality of portions by the overhanging partition wall 6. These organic layer OR1, upper electrode UE1, and cap layer CP1 are continuously formed while maintaining a vacuum environment. Such a laminated film FL1 is formed not only on the lower electrode LE1 but also on the partition wall 6, the lower electrode LE2, and the lower electrode LE3.

[0064] Subsequently, as shown in FIG. 6, a barrier layer BL1 is formed by depositing silicon oxynitride as the first inorganic insulating material. The barrier layer BL1 continuously covers each divided portion of the laminated film FL1 and the partition wall 6. Such a barrier layer BL1 is formed by CVD (Chemical Vapor Deposition).

[0065] Subsequently, as shown in FIG. 7, a sealing layer SE1 is formed by depositing silicon nitride as the second inorganic insulating material. The sealing layer SE1 overlaps so as to cover the barrier layer BL1. At this time, a gap CV1 surrounded by the sealing layer SE1 is formed around the partition wall 6. Such a sealing layer SE1 is formed by CVD.

[0066] Subsequently, as shown in FIG. 8, a resist RS1 patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS1 overlaps a part of the sub-pixel SP1 and the surrounding partition wall 6.

[0067] Subsequently, as shown in FIG. 9, dry etching is performed using the resist RS1 as a mask to remove the sealing layer SE1 and the barrier layer BL1 exposed from the resist RS1. As a result, a part of the laminated film FL1 is exposed on the partition wall 6, and the laminated film FL1 on the lower electrode LE2 and the laminated film FL1 on the lower electrode LE3 are also exposed. Also, portions of the partition wall 6 facing the lower electrode LE2 and the lower electrode LE3 are also exposed.

[0068] Subsequently, as shown in FIG. 10, the stacked film FL1 exposed from the resist RS1 is removed. At this time, in the stacked film FL1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 are removed in this order. As a result, the stacked film FL1 covered with the resist RS1 remains in the sub-pixel SP1. In addition, a part of the upper portion 62 of the partition wall 6 is exposed, and the lower electrode LE2 and the lower electrode LE3 are exposed.

[0069] Subsequently, as shown in FIG. 11, the resist RS1 is removed. As a result, the display element DE1 is formed in the sub-pixel SP1. When removing the resist RS1, the stacked film FL1 on the partition wall 6 is also removed. As a result, a gap GP1 is formed above the partition wall 6. The gap GP1 is open facing the lower electrode LE2 and is also open facing the lower electrode LE3.

[0070] Subsequently, the display element DE2 is formed. The procedure for forming the display element DE2 is the same as the procedure for forming the display element DE1. This will be briefly described below.

[0071] First, as shown in FIG. 12, a stacked film FL2 including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 is formed on the lower electrode LE2. The stacked film FL2 is also formed on the sealing layer SE1, the partition wall 6, and the lower electrode LE3.

[0072] Subsequently, as shown in FIG. 13, a barrier layer BL2 is formed by depositing silicon oxynitride as the first inorganic insulating material. The barrier layer BL2 continuously covers each divided portion of the stacked film FL2, the sealing layer SE1, and the partition wall 6.

[0073] Subsequently, as shown in FIG. 14, a sealing layer SE2 is formed by depositing silicon nitride as the second inorganic insulating material. The sealing layer SE2 overlaps so as to cover the barrier layer BL2. At this time, a void CV2 surrounded by the sealing layer SE2 is formed around the partition wall 6.

[0074] 15, a resist RS2 patterned into a predetermined shape is formed on the sealing layer SE2. The resist RS2 overlaps the subpixel SP2 and part of the partition wall 6 around it.

[0075] 16, dry etching is performed using the resist RS2 as a mask to remove the sealing layer SE2 and barrier layer BL2 exposed from the resist RS2. This exposes the stacked film FL2 on the sealing layer SE1, the stacked film FL2 on the partition wall 6, and the stacked film FL2 on the lower electrode LE3. In addition, the portion of the partition wall 6 facing the lower electrode LE3 is also exposed.

[0076] When dry etching the sealing layer SE2 and the barrier layer BL2, the sealing layer SE1 formed earlier is also susceptible to damage. However, the gap GP1 is surrounded by the barrier layer BL1, which has a lower etching rate than the sealing layer SE1. This prevents the gap GP1 from penetrating the void CV1 due to recession of the sealing layer SE1. In other words, the barrier layer BL1 and the sealing layer SE1 are interposed between the gap GP1 and the void CV1.

[0077] Therefore, it is possible to suppress undesired expansion of the gap CV1 caused by the etching gas entering the gap CV1, and further to suppress exposure of the laminated film FL1 from the sealing layer SE1. 17, the laminated film FL2 exposed from the resist RS2 is removed. At this time, in the laminated film FL2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are removed in this order. As a result, the laminated film FL2 covered with the resist RS2 remains in the subpixel SP2. In addition, a part of the upper portion 62 of the partition wall 6 and the lower electrode LE3 are exposed.

[0078] 18, the resist RS2 is removed. As a result, a display element DE2 is formed in the subpixel SP2. When the resist RS2 is removed, the stacked film FL2 on the partition wall 6 is also removed. As a result, a gap GP2 is formed above the partition wall 6.

[0079] Next, as shown in FIG. 19, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, a stacked film FL3 including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 is formed on the lower electrode LE3. Then, a barrier layer BL3 is formed on the stacked film FL3, and then a sealing layer SE3 is formed. When the sealing layer SE3 is formed, a gap CV3 surrounded by the sealing layer SE3 is formed around the partition wall 6. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the barrier layer BL3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. At this time, a gap GP3 is formed above the partition wall 6. This forms a display element DE3 in the subpixel SP3.

[0080] Next, as shown in Fig. 20, a resin layer 13 is formed. The resin layer 13 covers the sealing layers SE1, SE2, and SE3, fills the gaps GP1, GP2, and GP3, and contacts the barrier layers BL1, BL2, and BL3. Thereafter, as shown in Fig. 3, a sealing layer 14 and an overcoat layer 15 are formed in this order. This completes the display device DSP.

[0081] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order in which display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0082] In the display device DSP manufactured in this manner, penetration between the void CV1 and the gap GP1, penetration between the void CV2 and the gap GP2, and penetration between the void CV3 and the gap GP3 are suppressed. This suppresses the resin layer 13 from flowing into the voids CV1, CV2, and CV3. This also suppresses poor sealing of the stacked film FL1 by the sealing layer SE1, poor sealing of the stacked film FL2 by the sealing layer SE2, and poor sealing of the stacked film FL3 by the sealing layer SE3. This suppresses moisture-induced deterioration of the stacked films FL1, FL2, and FL3, and reduces deterioration in reliability.

[0083] Here, the characteristics of the display device DSP manufactured through the above processes will be described with reference to FIG. 20.

[0084] The barrier layer BL1 overlaps the laminated film FL1 and is in contact with the side surface SS1 of the second conductive layer 64 of the lower part 61. The resin layer 13 is disposed on substantially the entire upper surface of the upper part 62. Immediately above the partition wall 6, the barrier layer BL1 overlaps the resin layer 13, and the sealing layer SE1 overlaps the barrier layer BL1. The sealing layer SE1 is covered with the resin layer 13.

[0085] Regarding the thickness of the barrier layer BL1, the thickness T11 immediately above the laminated film FL1 is smaller than the thickness T1 of the sealing layer SE1 (T11 < T1). In one example, the thickness T11 is 50 to 150 nm, and the thickness T1 is 1000 to 3000 nm. The barrier layer BL1 immediately above the partition wall 6 can be thinned when exposed to the etching gas during the dry etching of the sealing layers SE2 and SE3. For this reason, in the barrier layer BL1, the thickness T11 is larger than the thickness T12 immediately above the partition wall 6 (T11 > T12). Also, the thickness T12 is smaller than the height H of the gap GP1 (or the thickness of the resin layer 13 filled in the gap GP1) (H > T12).

[0086] The barrier layer BL2 overlaps the laminated film FL2 and is in contact with the side surface SS2 opposite to the side surface SS1 of the second conductive layer 64 of the lower part 61. Immediately above the partition wall 6, the barrier layer BL2 overlaps the resin layer 13, and the sealing layer SE2 overlaps the barrier layer BL2. However, the barrier layers BL1 and BL2 are separated from each other, and the sealing layers SE1 and SE2 are separated from each other. The sealing layer SE2 is covered with the resin layer 13.

[0087] Regarding the thickness of the barrier layer BL2, the thickness T21 immediately above the laminated film FL2 is smaller than the thickness T2 of the sealing layer SE2 (T21 < T2). In one example, the thickness T21 is equivalent to the thickness T11, and the thickness T2 is equivalent to the thickness T1. The barrier layer BL2 directly above the partition wall 6 may be thinned when exposed to etching gas during dry etching of the sealing layer SE3. Therefore, in the barrier layer BL2, the thickness T21 is greater than the thickness T22 directly above the partition wall 6 (T21>T22). Furthermore, the thickness T22 is different from the thickness T12 and is greater than the thickness T12 (T22>T12).

[0088] The barrier layer BL3 overlaps the stacked film FL3 and is in contact with the side surface SS3 of the second conductive layer 64 of the lower portion 61. Directly above the partition wall 6, the barrier layer BL3 overlaps the resin layer 13, and the sealing layer SE3 overlaps the barrier layer BL3. However, the barrier layers BL1 and BL3 are spaced apart, and the sealing layers SE1 and SE3 are also spaced apart. The sealing layer SE3 is covered with the resin layer 13.

[0089] Regarding the thickness of the barrier layer BL3, the thickness T31 immediately above the stacked film FL3 is smaller than the thickness T3 of the sealing layer SE3 (T31 <T3)。一例では、厚さT31は厚さT11と同等であり、厚さT3は厚さT1と同等である。 The barrier layer BL3 directly above the partition wall 6 is not exposed to the etching gas used to etch other sealing layers. Therefore, in the barrier layer BL3, the thickness T31 is equal to the thickness T32 directly above the partition wall 6 (T31 ≈ T32). Furthermore, the thickness T32 is greater than the thickness T12 (T32 > T12).

[0090] Next, another configuration example will be described.

[0091] FIG. 21 is a cross-sectional view showing another example of the configuration of the display device DSP.

[0092] The configuration example shown in FIG. 21 differs from the configuration example shown in FIG. 20 in that the thicknesses T11, T21, and T31 are different from each other. In the illustrated example, it is assumed that the display elements DE1, DE2, and DE3 are formed in this order, the thickness T21 is smaller than the thickness T11, and the thickness T31 is smaller than the thickness T21 (T11>T21>T31). Immediately above the partition wall 6, the thicknesses T12, T22, and T32 are equal (T12≒T22≒T32). Note that the thickness T11 is greater than the thickness T12 (T11>T12), the thickness T21 is greater than the thickness T22 (T21>T22), and the thickness T31 is equal to the thickness T32 (T31≒T32).

[0093] Even in such a configuration example, similar to the configuration example shown in FIG. 20, the resin layer 13 is filled in the gaps GP1, GP2, and GP3, respectively. Also, a barrier layer BL1 and a sealing layer SE1 are interposed between the gap GP1 and the void CV1, a barrier layer BL2 and a sealing layer SE2 are interposed between the gap GP2 and the void CV2, and a barrier layer BL3 and a sealing layer SE3 are interposed between the gap GP3 and the void CV3. Therefore, the same effects as those of the above-described configuration example can be obtained.

[0094] FIG. 22 is a cross-sectional view showing another configuration example of the display device DSP.

[0095] The configuration example shown in FIG. 22 differs from the configuration example shown in FIG. 20 in that the barrier layer BL1 is separated into a first portion BL11 in contact with the side surface SS1 and a second portion (or a portion overlapping the resin layer 13) BL12 extending above the partition wall 6. That is, the resin layer 13 filled in the gap GP1 is in contact with the sealing layer SE1 between the first portion BL11 and the second portion BL12. Such a feature is formed by removing a part of the barrier layer BL1 surrounding the gap GP1 (a portion with a locally thin thickness) during the dry etching of the sealing layers SE2 and SE3.

[0096] In the illustrated example, the barrier layer BL2 is separated into a first portion BL21 in contact with the side surface SS2 and a second portion BL22 (or a portion overlapping the resin layer 13) extending above the partition wall 6. The resin layer 13 is in contact with the sealing layer SE2 between the first portion BL21 and the second portion BL22. This feature is formed by removing a portion (a locally thin portion) of the barrier layer BL2 surrounding the gap GP2 during dry etching of the sealing layer SE3.

[0097] In the barrier layer BL3, the portion in contact with the side surface SS3 and the portion extending above the partition wall 6 are formed continuously without being separated.

[0098] 20, in this configuration example, resin layer 13 is filled into gaps GP1, GP2, and GP3, and sealing layer SE1 is interposed between gap GP1 and void CV1, sealing layer SE2 is interposed between gap GP2 and void CV2, and sealing layer SE3 is interposed between gap GP3 and void CV3, thereby achieving the same effects as in the above configuration example.

[0099] FIG. 23 is a cross-sectional view showing another example of the configuration of the display device DSP.

[0100] The configuration example shown in FIG. 23 differs from the configuration example shown in FIG. 20 in that the barrier layer BL3 is omitted. As described above, when the display elements DE1, DE2, and DE3 are formed in this order, the sealing layer SE3 is not exposed to the etching gas used to etch the other sealing layers. Therefore, even if the barrier layer BL3 is omitted, undesired recession of the sealing layer SE3 is prevented, and penetration between the gap GP3 and the void CV3 and exposure of the stacked film FL3 from the sealing layer SE3 are prevented. Therefore, this configuration example also achieves the same effects as the above configuration example.

[0101] FIG. 24 is a cross-sectional view showing another example of the configuration of the display device DSP.

[0102] The configuration example shown in FIG. 24 is different from the configuration example shown in FIG. 23 in that not only the barrier layer BL3 but also the barrier layer BL2 is omitted. Even in such a configuration example, the same effects as those of the above-described configuration example can be obtained.

[0103] In the above embodiment, for example, the lower electrode LE1 corresponds to the first lower electrode, and the lower electrode LE2 corresponds to the second lower electrode. The organic layer OR1 corresponds to the first organic layer, and the organic layer OR2 corresponds to the second organic layer. The upper electrode UE1 corresponds to the first upper electrode, and the upper electrode UE2 corresponds to the second upper electrode. In the partition wall 6, the side surface SS1 corresponds to the first side surface, and the side surface SS2 corresponds to the second side surface. The stacked film FL1 corresponds to the first stacked film, and the stacked film FL2 corresponds to the second stacked film. The barrier layer BL1 corresponds to the first barrier layer, and the barrier layer BL2 corresponds to the second barrier layer. The sealing layer SE1 corresponds to the first sealing layer, and the sealing layer SE2 corresponds to the second sealing layer.

[0104] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability.

[0105] Based on the display device described as an embodiment of the present invention above, all display devices that those skilled in the art can appropriately modify the design and implement also belong to the scope of the present invention as long as they include the gist of the present invention.

[0106] Within the scope of the idea of the present invention, those skilled in the art can conceive various modifications, and those modifications are also understood to belong to the scope of the present invention. For example, with respect to the above-described embodiment, those obtained by appropriately adding, deleting, or modifying components, or adding, omitting, or changing conditions of processes by those skilled in the art also belong to the scope of the present invention as long as they have the gist of the present invention.

[0107] Also, with respect to other operational effects brought about by the aspects described in the above embodiment, those that are obvious from the description of this specification or can be appropriately conceived by those skilled in the art are naturally understood to be brought about by the present invention.

Explanation of Reference Numerals

[0108] DSP… indicates device 10… substrate 5… inorganic insulating layers AP1, AP2, AP3… openings 6… partition walls 61… lower part 62… upper part 63… first conductive layer 64… second conductive layer SP1, SP2, SP3… sub-pixels DE1, DE2, DE3… display elements (organic EL elements) LE1, LE2, LE3… lower electrodes UE1, UE2, UE3… upper electrodes OR1, OR2, OR3… organic layers CP1, CP2, CP3… cap layers FL1, FL2, FL3… laminated films BL1, BL2, BL3… barrier layers SE1, SE2, SE3… sealing layers DA… display area SA… peripheral area

Claims

1. A substrate, a first lower electrode disposed above the substrate, an inorganic insulating layer covering a peripheral portion of the first lower electrode, a lower portion disposed on the inorganic insulating layer and formed of a conductive material, and an upper portion disposed on the lower portion and protruding from a first side surface of the lower portion and a second side surface opposite to the first side surface, a partition wall having; a first organic layer in contact with the first lower electrode, and a first upper electrode disposed on the first organic layer and in contact with the lower portion, a first stacked film including; a first barrier layer disposed on the first stacked film, in contact with the first side surface, extending above the partition wall, forming a gap with the upper portion, and formed of a first inorganic insulating material; a first sealing layer overlapping the first barrier layer and formed of a second inorganic insulating material different from the first inorganic insulating material; a resin layer covering the first sealing layer and filling the gap; A display device comprising.

2. The etching rate of the first inorganic insulating material is smaller than the etching rate of the second inorganic insulating material, The display device according to claim 1.

3. The first inorganic insulating material is silicon oxynitride, The second inorganic insulating material is silicon nitride, The display device according to claim 1.

4. In the first barrier layer, the thickness directly above the first stacked film is larger than the thickness directly above the partition wall, The display device according to claim 1.

5. In the first barrier layer, the thickness directly above the partition wall is smaller than the height of the gap, The display device according to claim 1.

6. Furthermore, a second lower electrode disposed above the substrate and having a peripheral portion covered with the inorganic insulating layer, a second organic layer in contact with the second lower electrode, and a second upper electrode disposed on the second organic layer and in contact with the lower portion, a second stacked film including; a second barrier layer disposed on the second stacked film, in contact with the second side surface, extending above the partition wall, forming a gap with the upper portion, separated from the first barrier layer, and formed of the first inorganic insulating material; a second sealing layer overlapping the second barrier layer, separated from the first sealing layer, and formed of the second inorganic insulating material, comprising; The thickness of the second barrier layer directly above the partition wall is larger than the thickness of the first barrier layer directly above the partition wall, The display device according to claim 1.

7. The thickness of the second barrier layer directly above the second stacked film is substantially equal to the thickness of the first barrier layer directly above the first stacked film, The display device according to claim 6.

8. Furthermore, a second lower electrode disposed above the substrate and having a peripheral portion covered with the inorganic insulating layer; a second organic layer in contact with the second lower electrode; and a second upper electrode disposed on the second organic layer and in contact with the lower portion, including a second stacked film; a second barrier layer disposed on the second stacked film, in contact with the second side surface, extending above the partition wall, forming a gap with the upper portion, separated from the first barrier layer, and formed of the first inorganic insulating material; a second sealing layer overlapping the second barrier layer, separated from the first sealing layer, and formed of the second inorganic insulating material; The thickness of the second barrier layer immediately above the second stacked film is smaller than the thickness of the first barrier layer immediately above the first stacked film. The display device according to claim 1.

9. The thickness of the second barrier layer immediately above the partition wall is substantially equal to the thickness of the first barrier layer immediately above the partition wall. The display device according to claim 8.

10. Furthermore, it includes a gap surrounded by the first sealing layer and facing the first side surface. The first barrier layer and the first sealing layer are interposed between the gap and the void. The display device according to claim 1.

11. The first barrier layer is separated into a first portion in contact with the first side surface and a second portion extending above the partition wall. The resin layer filled in the gap is in contact with the first sealing layer between the first portion and the second portion. The display device according to claim 1.

12. Furthermore, it includes a gap surrounded by the first sealing layer and facing the first side surface. The first sealing layer is interposed between the gap and the void. The display device according to claim 11.

13. A substrate, a first lower electrode disposed above the substrate, an inorganic insulating layer covering the peripheral portion of the first lower electrode, a partition wall disposed on the inorganic insulating layer and having a lower portion formed of a conductive material and an upper portion protruding from the first side surface of the lower portion and the second side surface opposite to the first side surface, a first organic layer in contact with the first lower electrode; and a first upper electrode disposed on the first organic layer and in contact with the lower portion, including a first stacked film; a resin layer disposed on the upper portion, a first barrier layer overlapping the resin layer and formed of a first inorganic insulating material, a first sealing layer overlapping the first barrier layer and formed of a second inorganic insulating material different from the first inorganic insulating material. A display device comprising

14. Furthermore, a second barrier layer that overlaps the resin layer, is separated from the first barrier layer, and is formed of the first inorganic insulating material; and a second encapsulation layer that overlaps the second barrier layer, is separated from the first encapsulation layer, and is formed of the second inorganic insulating material. The display device according to claim 13, comprising

15. The thickness of the first barrier layer is different from the thickness of the second barrier layer. The display device according to claim 14.

16. The first encapsulation layer and the second encapsulation layer are covered with the resin layer. The display device according to claim 14.

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