Nitride semiconductor device

Abstract

To stabilize the on-off operation of a nitride semiconductor device.SOLUTION: A nitride semiconductor device 10 includes: a substrate 40 including a first surface 41 with insulating properties; a first metal layer 50A provided on the first surface 41; a first transistor 20 provided on the first metal layer 50A and having a first nitride semiconductor layer 24, a first source electrode 22, a first drain electrode 23, and a first gate electrode 21; an insulation layer 140 covering the first transistor 20; and a first electrode 130 provided on the insulation layer 140 and electrically connected to the first source electrode 22. There is provided, in the insulation layer 140, a first opening 141 penetrating through the insulation layer 140 in a Z-axis direction to reach a first connection area 52A of the first metal layer 50A. There is provided, within the first opening 141, a first connection 131 electrically connecting the first electrode 130 and the first connection area 52A.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device.

Background Art

[0002] Currently, the commercialization of high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) is progressing. Patent Document 1 discloses an example of a normally-off HEMT using a nitride semiconductor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] Stabilization of the on-off operation of a nitride semiconductor device is desired.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate including a first surface having insulating properties, a first metal layer provided on the first surface, a first transistor provided on the first metal layer and having a first nitride semiconductor layer, a first source electrode, a first drain electrode, and a first gate electrode, an insulating layer covering the first transistor, and a first electrode provided on the insulating layer and electrically connected to the first source electrode. The first nitride semiconductor layer is in contact with the first metal layer, the first metal layer has a first connection region protruding in a first direction from the first transistor when viewed from above, the insulating layer is provided with a first opening penetrating the insulating layer in the thickness direction of the substrate and reaching the first connection region, and a first connection portion for electrically connecting the first electrode and the first connection region is provided in the first opening.

Brief Description of the Drawings

[0006]

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[0007] [Detailed Description] Hereinafter, embodiments of the nitride semiconductor device in the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to a fixed scale. Also, for ease of understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0008] As used in this disclosure, terms such as "first," "second," "third," etc. are used to clearly distinguish the components of an object and do not rank the object. Also, the expression "at least one" used in this disclosure means one or more of a plurality of desired options. As an example, if the number of options is two, the expression "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the expression "at least one" means only one option or any combination of two or more options.

[0009] As used in this disclosure, "the dimension (depth, width, length, height) of A is equal to the dimension (depth, width, length, height) of B" or "the dimension (depth, width, length, height) of A and the dimension (depth, width, length, height) of B are equal to each other" includes a relationship in which the difference between the dimension (depth, width, length, height) of A and the dimension (depth, width, length, height) of B is within 10% of the dimension (depth, width, length, height) of A, for example.

[0010] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of this disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of this disclosure or the application and use of such embodiments.

[0011] <First Embodiment> [Schematic Overall Configuration of Nitride Semiconductor Device] With reference to FIGS. 1 to 5, the schematic overall configuration of a nitride semiconductor device 10 according to the first embodiment will be described. FIG. 1 shows a schematic planar structure of an exemplary nitride semiconductor device 10 according to the first embodiment. FIG. 2 shows a schematic planar structure inside the nitride semiconductor device 10 of FIG. 1. FIG. 3 shows a schematic planar structure inside the nitride semiconductor device 10 of FIG. 2. FIG. 4 shows an enlarged view of a part of the nitride semiconductor device 10 of FIG. 2. FIG. 5 shows an enlarged view of a part of the nitride semiconductor device 10 of FIG. 2 different from FIG. 4.

[0012] As shown in FIG. 1, the nitride semiconductor device 10 includes a hexahedral chip body 11. The chip body 11 may have, for example, a rectangular flat plate shape. Note that the Z-axis direction of the XYZ axes orthogonal to each other shown in FIG. 1 and other drawings is a direction orthogonal to the main surface of the chip body 11 (chip upper surface 11A in FIG. 1). The term "plan view" used in the present disclosure means viewing the nitride semiconductor device 10 from above in the Z-axis direction unless otherwise explicitly stated.

[0013] The chip body 11 includes a chip lower surface 11B (see FIG. 6) on the side opposite to the chip upper surface 11A, and first to fourth chip side surfaces 11C to 11F that connect the chip upper surface 11A and the chip lower surface 11B. The first chip side surface 11C and the second chip side surface 11D constitute both end faces of the chip body 11 in the X-axis direction, and the third chip side surface 11E and the fourth chip side surface 11F constitute both end faces of the chip body 11 in the Y-axis direction.

[0014] The chip body 11 includes a first transistor 20 and a second transistor 30. Each of the transistors 20 and 30 is configured as a high electron mobility transistor (HEMT) using a nitride semiconductor. The first transistor 20 and the second transistor 30 are arranged side by side in the X-axis direction. The first transistor 20 is arranged closer to the first chip side surface 11C than the second transistor 30. The first transistor 20 and the second transistor 30 are connected in series to form a half-bridge circuit.

[0015] The nitride semiconductor device 10 includes at least one first gate pad 12A, at least one second gate pad 12B, at least one first source pad 13A, at least one second source pad 13B, at least one first drain pad 14A, and at least one second drain pad 14B. The nitride semiconductor device 10 shown in FIG. 1 includes one first gate pad 12A, one second gate pad 12B, a plurality of first source pads 13A, one second source pad 13B, one first drain pad 14A, and a plurality of second drain pads 14B. Each of the gate pads 12A, 12B, each of the source pads 13A, 13B, and each of the drain pads 14A, 14B is provided on the upper surface 11A of the chip. These pads 12A, 12B, 13A, 13B, 14A, 14B can be used as external connection terminals of the nitride semiconductor device 10.

[0016] In each of the source pads 13A, 13B and each of the drain pads 14A, 14B, in the X-axis direction, the source pads and the drain pads are alternately arranged one by one. Each of the source pads 13A, 13B and each of the drain pads 14A, 14B extend in a direction (Y-axis direction) orthogonal to the arrangement direction (X-axis direction) of these pads in a plan view.

[0017] Each of the gate pads 12A, 12B, each of the source pads 13A, 13B, and each of the drain pads 14A, 14B may be, for example, rectangular in a plan view. In the example shown in FIG. 1, each of the gate pads 12A, 12B, each of the source pads 13A, 13B, and each of the drain pads 14A, 14B may be rectangular with the Y-axis direction as the longitudinal direction and the X-axis direction as the short side direction in a plan view. The dimension of each of the gate pads 12A, 12B in the X-axis direction is larger than the dimension of each of the source pads 13A, 13B and each of the drain pads 14A, 14B in the X-axis direction. The dimension of each of the gate pads 12A, 12B in the Y-axis direction is smaller than the dimension of each of the source pads 13A, 13B and each of the drain pads 14A, 14B in the X-axis direction.

[0018] Each gate pad 12A, 12B is arranged closer to the fourth chip side surface 11F than the third chip side surface 11E. The first gate pad 12A is arranged at the corner of the first chip side surface 11C and the fourth chip side surface 11F on the chip upper surface 11A. The second gate pad 12B is arranged near the center of the chip upper surface 11A in the X-axis direction. Note that the arrangement mode of each gate pad 12A, 12B can be arbitrarily changed.

[0019] The first gate pad 12A, the first source pad 13A, and the first drain pad 14A are pads electrically connected to the first transistor 20. The first gate pad 12A, the first source pad 13A, and the first drain pad 14A are arranged at positions overlapping the first transistor 20 in a plan view. The first source pad 13A closest to the first chip side surface 11C is arranged at a position overlapping the first gate pad 12A when viewed from the Y-axis direction. For this reason, the dimension of the first source pad 13A closest to the first chip side surface 11C in the Y-axis direction is smaller than the dimension of the other first source pads 13A in the Y-axis direction. In the example shown in FIG. 1, the other first source pads 13A are arranged closest to the second transistor 30 among the plurality of first source pads 13A, first drain pads 14A, and first gate pads 12A.

[0020] The second gate pad 12B, the second source pad 13B, and the second drain pad 14B are pads electrically connected to the second transistor 30. The second gate pad 12B, the second source pad 13B, and the second drain pad 14B are arranged at positions overlapping the second transistor 30 in a plan view. The second drain pad 14B closest to the first transistor 20 is arranged at a position overlapping the second gate pad 12B when viewed from the Y-axis direction. For this reason, the dimension of the second drain pad 14B closest to the first transistor 20 in the Y-axis direction is smaller than the dimension of the other second drain pads 14B in the Y-axis direction.

[0021] As shown in FIG. 2, the chip body 11 of the nitride semiconductor device 10 includes a substrate 40 having an insulating first surface 41, and a first metal layer 50A and a second metal layer 50B provided on the first surface 41. Both the first metal layer 50A and the second metal layer 50B are in contact with the first surface 41.

[0022] The substrate 40 has a hexahedral shape. The substrate 40 has an insulating property at least in the surface layer portion near the first surface 41. As the substrate 40, a semi-insulating substrate or an insulating substrate may be used. In one example, the substrate 40 can be made of silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. In the first embodiment, the substrate 40 is a semi-insulating SiC substrate. The thickness of the substrate 40 can be, for example, 200 μm or more and 1500 μm or less. Note that the Z-axis direction corresponds to the thickness direction of the substrate 40.

[0023] The substrate 40 includes a second surface 42 (see FIG. 6) opposite to the first surface 41, and first to fourth side surfaces 43 to 46 connecting the first surface 41 and the second surface 42. In one example, the second surface 42 constitutes the lower surface 11B of the chip (see FIG. 6). The first side surface 43 and the second side surface 44 constitute both end faces of the substrate 40 in the X-axis direction. The third side surface 45 and the fourth side surface 46 constitute both end faces of the substrate 40 in the Y-axis direction. The first side surface 43 constitutes a part of the first chip side surface 11C in the Z-axis direction, and the second side surface 44 constitutes a part of the second chip side surface 11D in the Z-axis direction. The third side surface 45 constitutes a part of the third chip side surface 11E in the Z-axis direction, and the fourth side surface 46 constitutes a part of the fourth chip side surface 11F in the Z-axis direction.

[0024] Both the first metal layer 50A and the second metal layer 50B are arranged to be spaced apart from each other in the X-axis direction on the first surface 41. The first metal layer 50A is arranged closer to the first side surface 43 (the first chip side surface 11C) than the second metal layer 50B. Both the first metal layer 50A and the second metal layer 50B may be rectangular in a plan view. In one example, the area of the first metal layer 50A in the plan view is equal to the area of the second metal layer 50B in the plan view. In one example, the thickness of the first metal layer 50A is equal to the thickness of the second metal layer 50B. The thickness of each of the first metal layer 50A and the second metal layer 50B may be, for example, 200 nm or more and 300 nm or less. The first metal layer 50A and the second metal layer 50B include, for example, at least one of aluminum (Al) and platinum (Pt).

[0025] Note that the shapes and areas of the first metal layer 50A and the second metal layer 50B in the plan view can be arbitrarily changed. Also, the thickness of each of the first metal layer 50A and the second metal layer 50B can be arbitrarily changed.

[0026] The first transistor 20 is provided on the first metal layer 50A. In the plan view, the first transistor 20 may be a rectangular shape that is slightly smaller than the first metal layer 50A. In other words, in the plan view, the first metal layer 50A includes a first protruding portion 51A that protrudes from the first transistor 20.

[0027] The second transistor 30 is provided on the second metal layer 50B. In the plan view, the second transistor 30 may be a rectangular shape that is slightly smaller than the second metal layer 50B. In other words, in the plan view, the second metal layer 50B includes a second protruding portion 51B that protrudes from the second transistor 30.

[0028] As shown in FIG. 3, the first transistor 20 includes a plurality (12 in the example shown in FIG. 3) of first transistor cells TA, a plurality (12 in the example shown in FIG. 3) of first transistor cells TB, and a plurality (8 in the example shown in FIG. 3) of first transistor cells TC.

[0029] The plurality of first transistor cells TA are arranged along the X-axis direction. The plurality of first transistor cells TB are arranged closer to the fourth side surface 46 (the fourth chip side surface 11F) than the plurality of first transistor cells TA.

[0030] The plurality of first transistor cells TB are arranged adjacent to the plurality of first transistor cells TA in the Y-axis direction. The plurality of first transistor cells TB are arranged along the X-axis direction.

[0031] The plurality of first transistor cells TC are arranged adjacent to the plurality of first transistor cells TB on the side opposite to the plurality of first transistor cells TA in the Y-axis direction. The plurality of first transistor cells TC are arranged along the X-axis direction. The plurality of first transistor cells TC are arranged closer to the second transistor 30 in the X-axis direction.

[0032] A first gate pad 12A is provided at a position adjacent to the first transistor cell TB and the first transistor cell TC. It can also be said that the first gate pad 12A is arranged at a corner portion of the first surface 41 of the substrate 40 closer to the first side surface 43 and the fourth side surface 46.

[0033] Each of the first transistor cells TA, TB, and TC includes a first gate electrode 21, a first source electrode 22, and a first drain electrode 23. The first source electrode 22 and the first drain electrode 23 may be strip-shaped extending in the Y-axis direction in plan view. The first gate electrode 21 may be annular surrounding the first drain electrode 23 in plan view.

[0034] The first source electrodes 22 and the first drain electrodes 23 of the plurality of first transistor cells TA are alternately arranged one by one and spaced apart from each other in the X-axis direction. Each annular first gate electrode 21 of the plurality of first transistor cells TA includes a portion arranged between the first source electrode 22 and the first drain electrode 23 of each of the plurality of first transistor cells TA in the X-axis direction.

[0035] The arrangement modes of the first gate electrodes 21, the first source electrodes 22, and the first drain electrodes 23 of the plurality of first transistor cells TB are the same as those of the plurality of first transistor cells TA. The first gate electrodes 21, the first source electrodes 22, and the first drain electrodes 23 of the plurality of first transistor cells TB are arranged at the same positions in the X-axis direction as the first gate electrodes 21, the first source electrodes 22, and the first drain electrodes 23 of the first transistor cells TA adjacent to each other in the Y-axis direction. The first gate electrodes 21 of the plurality of first transistor cells TB are integrated with the first gate electrodes 21 of the first transistor cells TA adjacent to each other in the Y-axis direction.

[0036] The arrangement modes of the first gate electrodes 21, the first source electrodes 22, and the first drain electrodes 23 of the plurality of first transistor cells TC are the same as those of the plurality of first transistor cells TB. The first gate electrodes 21, the first source electrodes 22, and the first drain electrodes 23 of the plurality of first transistor cells TC are arranged at the same positions in the X-axis direction as the first gate electrodes 21, the first source electrodes 22, and the first drain electrodes 23 of the first transistor cells TB adjacent to each other in the Y-axis direction. The first gate electrodes 21 of the plurality of first transistor cells TC are integrated with the first gate electrodes 21 of the first transistor cells TB adjacent to each other in the Y-axis direction.

[0037] The second transistor 30 includes a plurality (12 in the example shown in FIG. 3) of second transistor cells TD, a plurality (12 in the example shown in FIG. 3) of second transistor cells TE, and a plurality (8 in the example shown in FIG. 3) of second transistor cells TF. Each of the second transistor cells TD, TE, TF includes a second gate electrode 31, a second source electrode 32, and a second drain electrode 33.

[0038] The arrangement mode of the plurality of second transistor cells TD is the same as that of the plurality of first transistor cells TA. The arrangement modes of the second gate electrodes 31, the second source electrodes 32, and the second drain electrodes 33 of the plurality of second transistor cells TD are the same as those of the first gate electrodes 21, the first source electrodes 22, and the first drain electrodes 23 of the plurality of first transistor cells TA.

[0039] A plurality of second transistor cells TE are arranged to be adjacent to a plurality of second transistor cells TD in the Y-axis direction. The arrangement pattern of the plurality of second transistor cells TE is the same as that of the plurality of first transistor cells TB. The arrangement patterns of the second gate electrode 31, the second source electrode 32, and the second drain electrode 33 of each second transistor cell TE are the same as those of the first gate electrode 21, the first source electrode 22, and the first drain electrode 23 of each first transistor cell TB.

[0040] A plurality of second transistor cells TF are arranged to be adjacent to a plurality of second transistor cells TE in the Y-axis direction. The arrangement pattern of the plurality of second transistor cells TF is the same as that of the plurality of first transistor cells TC. The arrangement patterns of the second gate electrode 31, the second source electrode 32, and the second drain electrode 33 of each second transistor cell TF are the same as those of the first gate electrode 21, the first source electrode 22, and the first drain electrode 23 of each first transistor cell TC. A second gate pad 12B is provided at a position adjacent to the second transistor cell TF and the second transistor cell TE.

[0041] As shown in FIG. 2, the nitride semiconductor device 10 includes a first gate wiring 70A, a second gate wiring 70B, at least one first source wiring 80A, at least one second source wiring 80B, at least one first drain wiring 90A, and at least one second drain wiring 90B. Each gate wiring 70A, 70B, each source wiring 80A, 80B, and each drain wiring 90A, 90B are provided on an insulating layer 140, which will be described later, covering each transistor 20, 30.

[0042] The first gate wiring 70A is a wiring electrically connected to the first gate pad 12A (see FIG. 1). The first gate wiring 70A includes first outer peripheral gate wirings 71, 72 and first intermediate gate wirings 73, 74.

[0043] The first outer peripheral gate wirings 71 and 72 are wirings that surround a plurality of first transistor cells TA, TB, and TC. The first outer peripheral gate wiring 71 includes a first portion extending in the Y-axis direction and a second portion extending in the X-axis direction. The first portion is disposed closer to the first side surface 43 than the first transistor cells TA, TB, and TC. The first portion is connected to the first gate pad 12A. The second portion is disposed closer to the third side surface 45 than the plurality of first transistor cells TA. The second portion includes a portion that overlaps with the first gate electrodes 21 of the plurality of first transistor cells TA in a plan view. As shown in FIG. 4, the first outer peripheral gate wiring 71 is electrically connected to the first gate electrodes 21 of the plurality of first transistor cells TA by the first outer peripheral gate vias 101 in the second portion.

[0044] As shown in FIG. 2, the first outer peripheral gate wiring 72 includes a first portion extending in the X-axis direction and a second portion extending in the Y-axis direction. The first portion is disposed closer to the fourth side surface 46 than the plurality of first transistor cells TC. The first portion is connected to the first gate pad 12A. The second portion is disposed closer to the second transistor cells TD, TE, and TF than the first transistor cells TA, TB, and TC. The first portion includes a portion that overlaps with the first gate electrodes 21 of the plurality of first transistor cells TC in a plan view. The first outer peripheral gate wiring 72 is electrically connected to the first gate electrodes 21 of the plurality of first transistor cells TC by the first outer peripheral gate vias 102 in the first portion.

[0045] The first outer peripheral gate wiring 71 and the first outer peripheral gate wiring 72 are not connected at their tip portions. In other words, the tip portion of the first outer peripheral gate wiring 71 and the tip portion of the first outer peripheral gate wiring 72 are separated from each other. For this reason, the first gate wiring 70A includes an opening 70AA. The opening 70AA is formed by the tip portion of the first outer peripheral gate wiring 71 and the tip portion of the first outer peripheral gate wiring 72. The opening 70AA is provided at a position closer to the second transistor cell TD than the first transistor cell TA and adjacent to the first transistor cell TA in the X-axis direction.

[0046] The plurality of first intermediate gate wirings 73 and 74 connect the first outer peripheral gate wiring 71 and the first outer peripheral gate wiring 72 in the X-axis direction. The first intermediate gate wiring 73 is provided between the first drain electrodes 23 (first source electrodes 22) of the plurality of first transistor cells TA and the first drain electrodes 23 (first source electrodes 22) of the plurality of first transistor cells TB in the Y-axis direction. The first intermediate gate wiring 73 includes a portion overlapping with the first gate electrodes 21 of the plurality of first transistor cells TA and TB. The first intermediate gate wiring 73 is electrically connected to the first gate electrodes 21 of the plurality of first transistor cells TA and TB by first intermediate gate vias 103.

[0047] The first intermediate gate wiring 74 is provided between the first drain electrodes 23 (first source electrodes 22) of the plurality of first transistor cells TB and the first drain electrodes 23 (first source electrodes 22) of the plurality of first transistor cells TC in the Y-axis direction. The first intermediate gate wiring 74 includes a portion overlapping with the first gate electrodes 21 of the plurality of first transistor cells TB and TC. The first intermediate gate wiring 74 is electrically connected to the first gate electrodes 21 of the plurality of first transistor cells TB and TC by first intermediate gate vias 104.

[0048] The plurality of first source wirings 80A are arranged at intervals from each other in the Y-axis direction. Each first source wiring 80A may be strip-shaped extending in the X-axis direction in plan view. The plurality of first source wirings 80A include a first source wiring 81 corresponding to the plurality of first transistor cells TA, a first source wiring 82 corresponding to the plurality of first transistor cells TB, and a first source wiring 83 corresponding to the plurality of first transistor cells TC. The first source wirings 81 to 83 (80A) are arranged so as not to overlap the first gate wiring 70A in plan view.

[0049] The first source wiring 81 is arranged so as to overlap with the first source electrodes 22 of a plurality of first transistor cells TA in a plan view. As shown in FIG. 4, the first source wiring 81 is electrically connected to the first source electrodes 22 of a plurality of first transistor cells TA by a plurality of first source vias 105. The first source wiring 81 is arranged at a position overlapping with the opening 70AA of the first gate wiring 70A when viewed from the X-axis direction.

[0050] The first source wiring 82 is arranged so as to overlap with the first source electrodes 22 of a plurality of first transistor cells TB in a plan view. The first source wiring 82 is electrically connected to the first source electrodes 22 of a plurality of first transistor cells TB by a plurality of first source vias 105, similarly to the first source wiring 81.

[0051] The first source wiring 83 is arranged so as to overlap with the first source electrodes 22 of a plurality of first transistor cells TC in a plan view. The first source wiring 83 is electrically connected to the first source electrodes 22 of a plurality of first transistor cells TC by a plurality of first source vias 105, similarly to the first source wiring 81.

[0052] A plurality of first drain wirings 90A are arranged to be spaced apart from each other in the Y-axis direction. Each first drain wiring 90A may be in a strip shape extending in the X-axis direction in a plan view. The plurality of first drain wirings 90A include a first drain wiring 91 corresponding to a plurality of first transistor cells TA, a first drain wiring 92 corresponding to a plurality of first transistor cells TB, and a first drain wiring 93 corresponding to a plurality of first transistor cells TC. The first drain wirings 91 to 93 (90A) are arranged so as not to overlap with the first gate wiring 70A in a plan view. The first drain wirings 91 to 93 (90A) are insulated from the first metal layer 50A. Also, the first drain wirings 91 to 93 (90A) are insulated from the second metal layer 50B. Here, the first drain wirings 91 to 93 (90A) are an example of the "third electrode".

[0053] The first drain wiring 91 is arranged so as to overlap with the first drain electrodes 23 of a plurality of first transistor cells TA in a plan view. The first drain wiring 91 is arranged at a position adjacent to the first source wiring 81 in the Y-axis direction. Both the first source wiring 81 and the first drain wiring 91 are arranged so as to overlap with both the first source electrodes 22 and the first drain electrodes 23 of a plurality of first transistor cells TA in a plan view. As shown in FIG. 4, the first drain wiring 91 is electrically connected to the first drain electrodes 23 of a plurality of first transistor cells TA by a plurality of first drain vias 106. As shown in FIG. 2, the first drain wiring 91 is arranged closer to the first transistor cell TB (closer to the fourth side surface 46) than the opening 70AA of the first gate wiring 70A in the Y-axis direction.

[0054] The first drain wiring 92 is arranged so as to overlap with the first drain electrodes 23 of a plurality of first transistor cells TB in a plan view. The first drain wiring 92 is arranged at a position adjacent to the first source wiring 82 in the Y-axis direction. Both the first source wiring 82 and the first drain wiring 92 are arranged so as to overlap with both the first source electrodes 22 and the first drain electrodes 23 of a plurality of first transistor cells TB in a plan view. Similar to the first drain wiring 91, the first drain wiring 92 is electrically connected to the first drain electrodes 23 of a plurality of first transistor cells TB by a plurality of first drain vias 106.

[0055] The first drain wiring 93 is arranged so as to overlap with the first drain electrodes 23 of a plurality of first transistor cells TC in a plan view. The first drain wiring 93 is arranged at a position adjacent to the first source wiring 83 in the Y-axis direction. Both the first source wiring 83 and the first drain wiring 93 are arranged so as to overlap with both the first source electrodes 22 and the first drain electrodes 23 of a plurality of first transistor cells TC in a plan view. Similar to the first drain wiring 91, the first drain wiring 93 is electrically connected to the first drain electrodes 23 of a plurality of first transistor cells TC by a plurality of first drain vias 106.

[0056] The second gate wiring 70B is a wiring electrically connected to the second gate pad 12B. The second gate wiring 70B includes second outer peripheral gate wirings 75 to 77 and second intermediate gate wirings 78 and 79.

[0057] The second outer peripheral gate wirings 75 to 77 are wirings surrounding a plurality of second transistor cells TD, TE, and TF. The second outer peripheral gate wiring 75 is a wiring extending in the Y-axis direction from the second gate pad 12B. The second outer peripheral gate wiring 75 is arranged closer to the first transistor cells TA, TB, and TC than the second transistor cells TD and TE in the X-axis direction.

[0058] The second outer peripheral gate wiring 76 is a wiring extending in the X-axis direction from the second gate pad 12B. The second outer peripheral gate wiring 76 is arranged closer to the fourth side surface 46 than a plurality of second transistor cells TF in the Y-axis direction. The second outer peripheral gate wiring 76 includes a portion overlapping with the second gate electrodes 31 of a plurality of second transistor cells TF in a plan view. As shown in FIG. 2, the second outer peripheral gate wiring 76 is electrically connected to the second gate electrodes 31 of a plurality of second transistor cells TF by the second outer peripheral gate vias 111.

[0059] As shown in FIG. 2, the second outer peripheral gate wiring 77 includes a first portion extending along the X-axis direction and a second portion extending along the Y-axis direction. The first portion is arranged closer to the third side surface 45 than a plurality of second transistor cells TD. The second portion is arranged closer to the second side surface 44 than the second transistor cells TD, TE, and TF. The first portion includes a portion overlapping with the second gate electrodes 31 of a plurality of second transistor cells TD in a plan view. The second outer peripheral gate wiring 77 is electrically connected to the second gate electrodes 31 (see FIG. 3) of a plurality of second transistor cells TD by the second outer peripheral gate vias 112 in the first portion.

[0060] The second intermediate gate wirings 78 and 79 connect the second outer peripheral gate wiring 75 and the second outer peripheral gate wiring 77 in the X-axis direction. The second intermediate gate wiring 78 is provided between the second drain electrodes 33 (second source electrodes 32) of the plurality of second transistor cells TD and the second drain electrodes 33 (second source electrodes 32) of the plurality of second transistor cells TE in the Y-axis direction. The second intermediate gate wiring 78 includes a portion overlapping with the second gate electrodes 31 of the plurality of second transistor cells TD and TE. The second intermediate gate wiring 78 is electrically connected to the second gate electrodes 31 of the plurality of second transistor cells TD and TE by the second intermediate gate vias 113.

[0061] The second intermediate gate wiring 79 is provided between the second drain electrodes 33 (second source electrodes 32) of the plurality of second transistor cells TE and the second drain electrodes 33 (second source electrodes 32) of the plurality of second transistor cells TF in the Y-axis direction. The second intermediate gate wiring 79 includes a portion overlapping with the second gate electrodes 31 of the plurality of second transistor cells TE and TF. The second intermediate gate wiring 79 is electrically connected to the second gate electrodes 31 of the plurality of second transistor cells TE and TF by the second intermediate gate vias 114.

[0062] The second outer peripheral gate wiring 75 and the second outer peripheral gate wiring 76 are not connected to the second outer peripheral gate wiring 77 at their tip portions. In other words, the tip portion of the second outer peripheral gate wiring 75 and the first end of the second outer peripheral gate wiring 77 are separated from each other. The tip portion of the second outer peripheral gate wiring 76 and the second end of the second outer peripheral gate wiring 77 are separated from each other. For this reason, the second gate wiring 70B includes the first opening 70BA and the second opening 70BB.

[0063] The first opening 70BA is formed by the tip of the second outer peripheral gate wiring 75 and the first end of the second outer peripheral gate wiring 77. The first opening 70BA is provided closer to the first transistor cell TA than the plurality of second transistor cells TD and adjacent to the second transistor cells TD in the X-axis direction. The first opening 70BA faces the opening 70AA of the first gate wiring 70A in the X-axis direction.

[0064] The second opening 70BB is formed by the tip of the second outer peripheral gate wiring 76 and the second end of the second outer peripheral gate wiring 77. The second opening 70BB is provided closer to the second side surface 44 than the plurality of second transistor cells TF and adjacent to the second transistor cells TF in the X-axis direction.

[0065] The plurality of second source wirings 80B are arranged spaced apart from each other in the Y-axis direction. Each second source wiring 80B may be strip-shaped extending in the X-axis direction in plan view. The plurality of second source wirings 80B include a second source wiring 84 corresponding to the plurality of second transistor cells TD, a second source wiring 85 corresponding to the plurality of second transistor cells TE, and a second source wiring 86 corresponding to the plurality of second transistor cells TF. The second source wirings 84 to 86 (80B) are arranged so as not to overlap the second gate wiring 70B in plan view.

[0066] The second source wiring 84 is arranged to overlap the second source electrodes 32 of the plurality of second transistor cells TD in plan view. As shown in FIG. 5, the second source wiring 84 is electrically connected to the second source electrodes 32 of the plurality of second transistor cells TD by a plurality of second source vias 115. The second source wiring 84 is arranged closer to the second transistor cells TE (closer to the fourth side surface 46) than the opening 70BA of the second gate wiring 70B in the Y-axis direction.

[0067] The second source wiring 85 is arranged so as to overlap with the second source electrodes 32 of a plurality of second transistor cells TE in a plan view. Similar to the second source wiring 84, the second source wiring 85 is electrically connected to the second source electrodes 32 of a plurality of second transistor cells TE by a plurality of second source vias 115.

[0068] The second source wiring 86 is arranged so as to overlap with the second source electrodes 32 of a plurality of second transistor cells TF in a plan view. Similar to the second source wiring 84, the second source wiring 86 is electrically connected to the second source electrodes 32 of a plurality of second transistor cells TF by a plurality of second source vias 115.

[0069] A plurality of second drain wirings 90B are arranged at intervals from each other in the Y-axis direction. Each second drain wiring 90B may be strip-shaped extending in the X-axis direction in a plan view. The plurality of second drain wirings 90B include a second drain wiring 94 corresponding to a plurality of second transistor cells TD, a second drain wiring 95 corresponding to a plurality of second transistor cells TE, and a second drain wiring 96 corresponding to a plurality of second transistor cells TF. The second drain wirings 94 to 96 (90B) are arranged so as not to overlap with the second gate wiring 70B in a plan view.

[0070] The second drain wiring 94 is arranged so as to overlap with the second drain electrodes 33 of a plurality of second transistor cells TD in a plan view. The second drain wiring 94 is arranged at a position adjacent to the second source wiring 84 in the Y-axis direction. Both the second source wiring 84 and the second drain wiring 94 are arranged so as to overlap with both the second source electrodes 32 and the second drain electrodes 33 of a plurality of second transistor cells TD in a plan view. As shown in FIG. 5, the second drain wiring 94 is electrically connected to the second drain electrodes 33 of a plurality of second transistor cells TD by a plurality of second drain vias 116.

[0071] The second drain wiring 95 is arranged so as to overlap with the second drain electrodes 33 of a plurality of second transistor cells TE in a plan view. The second drain wiring 95 is arranged at a position adjacent to the second source wiring 85 in the Y-axis direction. Both the second source wiring 85 and the second drain wiring 95 are arranged so as to overlap with both the second source electrodes 32 and the second drain electrodes 33 of a plurality of second transistor cells TE in a plan view. Similar to the second drain wiring 94, the second drain wiring 95 is electrically connected to the second drain electrodes 33 of a plurality of second transistor cells TE by a plurality of second drain vias 116.

[0072] The second drain wiring 96 is arranged so as to overlap with the second drain electrodes 33 of a plurality of second transistor cells TF in a plan view. The second drain wiring 96 is arranged at a position adjacent to the second source wiring 86 in the Y-axis direction. Both the second source wiring 86 and the second drain wiring 96 are arranged so as to overlap with both the second source electrodes 32 and the second drain electrodes 33 of a plurality of second transistor cells TF in a plan view. Similar to the second drain wiring 94, the second drain wiring 96 is electrically connected to the second drain electrodes 33 of a plurality of second transistor cells TF by a plurality of second drain vias 116.

[0073] As shown in FIG. 2, the arrangement modes of the second source wirings 84 to 86 and the second drain wirings 94 to 96 in the Y-axis direction are different from those of the first source wirings 81 to 83 and the first drain wirings 91 to 93 in the Y-axis direction. Specifically, the first source wirings 81 to 83 and the second drain wirings 94 to 96 are arranged at the same positions in the Y-axis direction. The first drain wirings 91 to 93 and the second source wirings 84 to 86 are arranged at the same positions in the Y-axis direction.

[0074] The first source wiring 81 and the second drain wiring 94 are connected to each other. In one example, the first source wiring 81 and the second drain wiring 94 are integrated. It can be said that the first source wiring 81 and the second drain wiring 94 are electrically and mechanically connected. The integrated first source wiring 81 and second drain wiring 94 constitute the first electrode 130. It can be said that the first electrode 130 is electrically connected to the first source electrode 22 of the first transistor cell TA. It can be said that the first electrode 130 is electrically connected to the second drain electrode 33 of the second transistor cell TD.

[0075] [Schematic cross-sectional structure of nitride semiconductor device] Referring to FIGS. 6 to 8, the schematic cross-sectional structure of the nitride semiconductor device 10 will be described. FIGS. 6 to 8 show a simplified cross-sectional structure of the main part of the nitride semiconductor device 10 to facilitate understanding of the structure of the nitride semiconductor device 10. FIGS. 6 to 8 do not show the cross-sectional structure at a specific cut surface of the nitride semiconductor device 10. For convenience, FIGS. 6 to 8 schematically show the configuration of one transistor cell for each of the first transistor 20 and the second transistor 30. Also, FIGS. 6 to 8 schematically show the configuration related to the external connection to the first transistor 20 and the second transistor 30.

[0076] (First transistor) As shown in FIGS. 6 and 7, the first transistor 20 includes a first nitride semiconductor layer 24 provided on the first metal layer 50A. The first nitride semiconductor layer 24 includes a first substrate-side nitride semiconductor layer 25, a first electron supply layer 26, and a first gate layer 27.

[0077] The first substrate-side nitride semiconductor layer 25 is a nitride semiconductor layer in contact with the first metal layer 50A. The first metal layer 50A and the first substrate-side nitride semiconductor layer 25 are joined, for example, by an intermolecular bond. More specifically, the first metal layer 50A and the first substrate-side nitride semiconductor layer 25 are joined by a hydrogen bond between OH groups.

[0078] The nitride semiconductor layer 25 on the first substrate side may be composed of, for example, a single material. In the first embodiment, the nitride semiconductor layer 25 on the first substrate side is a GaN layer. The nitride semiconductor layer 25 on the first substrate side can also be called an electron traveling layer. The nitride semiconductor layer 25 on the first substrate side can be, for example, 1.5 μm or more and 5 μm or less. In order to suppress the leakage current in the nitride semiconductor layer 25 on the first substrate side, impurities may be introduced into a part of the nitride semiconductor layer 25 on the first substrate side to make the part other than the surface layer portion of the nitride semiconductor layer 25 on the first substrate side semi-insulating. In this case, the impurity is, for example, carbon (C). The impurity concentration of the carbon is, for example, 1×10 19 cm -3 or more.

[0079] The first electron supply layer 26 is composed of a nitride semiconductor having a larger bandgap than the nitride semiconductor layer 25 on the first substrate side. The first electron supply layer 26 may be, for example, an aluminum gallium nitride (AlGaN layer). Since the larger the Al composition, the larger the bandgap, the first electron supply layer 26 which is an AlGaN layer has a larger bandgap than the nitride semiconductor layer 25 on the first substrate side which is a GaN layer. In one example, the first electron supply layer 26 is composed of Al x Ga 1-x N. In this case, x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the first electron supply layer 26 can be, for example, 5 nm or more and 20 nm or less.

[0080] The nitride semiconductor layer 25 on the first substrate side and the first electron supply layer 26 have different lattice constants in the bulk region. Therefore, the nitride semiconductor (e.g., GaN) constituting the nitride semiconductor layer 25 on the first substrate side and the nitride semiconductor (e.g., AlGaN) constituting the first electron supply layer 26 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the nitride semiconductor layer 25 on the first substrate side and the first electron supply layer 26 and the piezo-polarization caused by the compressive stress received by the hetero-junction portion of the nitride semiconductor layer 25 on the first substrate side, the energy level of the conduction band of the nitride semiconductor layer 25 on the first substrate side near the hetero-junction interface between the nitride semiconductor layer 25 on the first substrate side and the first electron supply layer 26 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 29 is formed in the nitride semiconductor layer 25 on the first substrate side at a position close to the hetero-junction interface between the nitride semiconductor layer 25 on the first substrate side and the first electron supply layer 26 (for example, at a distance of about several nm from the interface).

[0081] The first gate layer 27 is composed of a nitride semiconductor. In one example, the first gate layer 27 has a smaller band gap than the first electron supply layer 26 and is composed of a nitride semiconductor containing acceptor-type impurities. In one example, the first gate layer 27 is GaN doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurities in the first gate layer 27 is, for example, 7×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0082] On the upper surface 27A of the first gate layer 27, a first gate electrode 21 is disposed. In one example, the first gate electrode 21 may be a titanium nitride (TiN) layer. In another example, the first gate electrode 21 may be composed of a first metal layer made of Ti and a second metal layer provided on the first metal layer and made of TiN. The first gate electrode 21 may be composed of, for example, a material that forms a Schottky junction with the gate layer 27. An example of such a material is TiN. The thickness of the first gate electrode 21 can be, for example, 50 nm or more and 200 nm or less.

[0083] As shown in FIG. 3, the first gate layer 27 is formed in an annular shape in plan view. Similarly, the first gate electrode 21 disposed on the upper surface 27A of the first gate layer 27 is also formed in an annular shape in plan view.

[0084] As shown in FIGS. 6 and 7, the first transistor 20 includes a first passivation layer 28. The first passivation layer 28 covers the first electron supply layer 26, the first gate layer 27, and the first gate electrode 21. The first passivation layer 28 may be composed of, for example, one or any combination of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al2O3), aluminum nitride (AlN), and aluminum oxynitride (AlON). The thickness of the first passivation layer 28 can be, for example, 50 nm or more and 200 nm or less, preferably 80 nm or more and 150 nm or less. The first passivation layer 28 includes a first source opening 28A and a first drain opening 28B that respectively expose a part of the upper surface 26A of the first electron supply layer 26.

[0085] A first source electrode 22 is provided in the first source opening 28A, and a first drain electrode 23 is provided in the first drain opening 28B. The first source electrode 22 includes a first source contact portion 22A that contacts the first electron supply layer 26 within the first source opening 28A. The first drain electrode 23 includes a first drain contact portion 23A that contacts the first electron supply layer 26 within the first drain opening 28B.

[0086] The first source opening 28A is provided inside the annular first gate layer 27 in a plan view. The first drain opening 28B is provided outside the annular first gate layer 27 in a plan view. For this reason, the first source electrode 22 provided in the first source opening 28A is provided inside the annular first gate layer 27 in a plan view. The first drain electrode 23 provided in the first drain opening 28B is provided outside the annular first gate layer 27 in a plan view. In this way, the first source electrode 22 and the first drain electrode 23 are arranged to face each other with the first gate layer 27 interposed therebetween on the first electron supply layer 26.

[0087] The first source electrode 22 and the first drain electrode 23 include one or more metal layers. In one example, the first source electrode 22 and the first drain electrode 23 can be composed of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, both the first source electrode 22 and the first drain electrode 23 are composed of a first metal layer that contacts the first electron supply layer 26, a second metal layer laminated on the second metal layer, a third metal layer laminated on the third metal layer, and a fourth metal layer laminated on the fourth metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

[0088] The first source contact portion 22A of the first source electrode 22 is filled in the first source opening 28A. The first source contact portion 22A makes an ohmic contact with the 2DEG 29 directly under the first electron supply layer 26. The first drain contact portion 23A of the first drain electrode 23 is filled in the first drain opening 28B. The first drain contact portion 23A makes an ohmic contact with the 2DEG 29 directly under the first electron supply layer 26.

[0089] In a structure in which the first gate layer 27 is formed of a nitride semiconductor containing acceptor-type impurities, when a voltage is not applied to the first gate electrode 21, the 2DEG 29 in the region directly under the first gate layer 27 is depleted, thereby blocking the conduction path (channel). As a result, a normally-off type HEMT with a positive gate threshold voltage is realized.

[0090] The first transistor 20 includes a first field plate electrode 22F provided on the first passivation layer 28. The first field plate electrode 22F is electrically connected to the first source electrode 22. In the examples shown in FIGS. 6 and 7, the first field plate electrode 22F is formed integrally with the first source electrode 22. That is, a part of the first source electrode 22 is provided as the first field plate electrode 22F. Therefore, a voltage having the same potential as the first source electrode 22 is applied to the first field plate electrode 22F. The first field plate electrode 22F is also called a source field plate. The first field plate electrode 22F covers the entire first gate layer 27 in plan view.

[0091] The first field plate electrode 22F is separated from the first drain electrode 23. The first field plate electrode 22F includes an end portion located between the first gate layer 27 and the first drain electrode 23 in a plan view. When a drain voltage is applied to the first drain electrode 23 in a zero-bias state where no voltage is applied to the first gate electrode 21, the first field plate electrode 22F serves to relieve the electric field concentration in the vicinity of the end portion of the first gate electrode 21 and the vicinity of the end portion of the first gate layer 27.

[0092] (Second transistor) As shown in FIGS. 6 and 8, the second transistor 30 includes a second nitride semiconductor layer 34 provided on the second metal layer 50B. The second nitride semiconductor layer 34 includes a second substrate-side nitride semiconductor layer 35, a second electron supply layer 36, and a second gate layer 37. In one example, the thickness of the second nitride semiconductor layer 34 is equal to the thickness of the first nitride semiconductor layer 24 (see FIG. 7).

[0093] The second substrate-side nitride semiconductor layer 35 is provided on the second metal layer 50B. The second substrate-side nitride semiconductor layer 35 is composed of a nitride semiconductor. The second metal layer 50B and the second substrate-side nitride semiconductor layer 35 are joined by, for example, an intermolecular bond. More specifically, the second metal layer 50B and the second substrate-side nitride semiconductor layer 35 are joined by a hydrogen bond between OH groups.

[0094] The second electron supply layer 36 is provided on the second substrate-side nitride semiconductor layer 35. The second electron supply layer 36 is composed of a nitride semiconductor having a larger bandgap than the second substrate-side nitride semiconductor layer 35.

[0095] The second gate layer 37 is partially provided on the second electron supply layer 36. The second gate layer 37 is composed of a nitride semiconductor layer containing acceptor-type impurities. A second gate electrode 31 is disposed on the upper surface 37A of the second gate layer 37. The second source electrode 32 and the second drain electrode 33 are disposed opposite to each other with the second gate layer 37 interposed therebetween on the second electron supply layer 36.

[0096] In the second transistor 30, similar to the first transistor 20, a two-dimensional electron gas (2DEG) 39 is formed in the second substrate-side nitride semiconductor layer 35 at a position close to the hetero-junction interface between the second substrate-side nitride semiconductor layer 35 and the second electron supply layer 36 (for example, at a distance of about several nm from the interface). As shown in FIG. 6, since the configuration of the second substrate-side nitride semiconductor layer 35, the second electron supply layer 36, and the second gate layer 37 is the same as that of the first substrate-side nitride semiconductor layer 25, the first electron supply layer 26, and the first gate layer 27 of the first transistor 20, a detailed description thereof will be omitted. Further, since the configurations of the second gate electrode 31, the second source electrode 32, and the second drain electrode 33 are the same as those of the first gate electrode 21, the first source electrode 22, and the first drain electrode 23, a detailed description thereof will be omitted.

[0097] The second transistor 30 includes a second passivation layer 38 that covers the second electron supply layer 36, the second gate layer 37, and the second gate electrode 31. The configuration of the second passivation layer 38 is the same as that of the first passivation layer 28. The second passivation layer 38 includes a second source opening 38A and a second drain opening 38B that expose the upper surface 36A of the second electron supply layer 36.

[0098] The second source electrode 32 is provided in the second source opening 38A, and the second drain electrode 33 is provided in the second drain opening 38B. The second source electrode 32 includes a second source contact portion 32A that contacts the second electron supply layer 36 within the second source opening 38A. The second drain electrode 33 includes a second drain contact portion 33A that contacts the second electron supply layer 36 within the second drain opening 38B. The configurations of the second source electrode 32 and the second drain electrode 33 are the same as those of the first source electrode 22 and the first drain electrode 23. Each of the second source contact portion 32A and the second drain contact portion 33A is in ohmic contact with the second electron supply layer 36. Thus, since the second transistor 30 has the same configuration as the first transistor 20, a normally-off type HEMT having a positive gate threshold voltage is realized.

[0099] The second transistor 30 includes a second field plate electrode 32F. In the examples shown in FIGS. 6 and 8, the second field plate electrode 32F is integrated with the second source electrode 32. The configuration of the second field plate electrode 32F is the same as that of the first field plate electrode 22F. Therefore, when a drain voltage is applied to the second drain electrode 33 in a zero bias state where no voltage is applied to the second gate electrode 31, the second field plate electrode 32F serves to mitigate the electric field concentration near the ends of the second gate electrode 31 and near the ends of the second gate layer 37.

[0100] [Electrical connection structure of the transistor] With reference to FIGS. 2 and 5, an example of the electrical connection structure between the first transistor 20 and the second transistor 30 will be described.

[0101] As shown in FIG. 5, the nitride semiconductor device 10 includes an insulating layer 140. The insulating layer 140 covers both the first transistor 20 and the second transistor 30. The insulating layer 140 covers the first metal layer 50A and the second metal layer 50B and is filled between the first metal layer 50A and the second metal layer 50B. Therefore, the insulating layer 140 is in contact with the first surface 41 of the substrate 40.

[0102] Each of the first source wiring 80A, the second source wiring 80B, the first drain wiring 90A, and the second drain wiring 90B is provided on the insulating layer 140. In the examples shown in FIGS. 2 and 6, the first electrode 130 is formed by the first source wiring 80A and the second drain wiring 90B. That is, the first source wiring 80A and the second drain wiring 90B are integrated as the first electrode 130.

[0103] The first source via 105 that electrically connects the first source wiring 80A and the first source electrode 22 is provided to penetrate in the Z-axis direction through a portion of the insulating layer 140 that covers the first source electrode 22. The first source via 105 is in contact with both the first source wiring 80A and the first source electrode 22.

[0104] The first drain via 106 that electrically connects the first drain wiring 90A and the first drain electrode 23 is provided so as to penetrate in the Z-axis direction a portion of the insulating layer 140 that covers the first drain electrode 23. The first drain via 106 is in contact with both the first drain wiring 90A and the first drain electrode 23.

[0105] The second source via 115 that electrically connects the second source wiring 80B and the second source electrode 32 is provided so as to penetrate in the Z-axis direction a portion of the insulating layer 140 that covers the second source electrode 32. The second source via 115 is in contact with both the second source wiring 80B and the second source electrode 32.

[0106] The second drain via 116 that electrically connects the second drain wiring 90B and the second drain electrode 33 is provided so as to penetrate in the Z-axis direction a portion of the insulating layer 140 that covers the second drain electrode 33. The second drain via 116 is in contact with both the second drain wiring 90B and the second drain electrode 33.

[0107] The first electrode 130 is electrically connected to the first metal layer 50A. More specifically, the first protruding portion 51A of the first metal layer 50A includes a first connection region 52A that protrudes in the X-axis direction from the first transistor 20 in a plan view. The first connection region 52A is a portion of the first protruding portion 51A that protrudes from the first transistor 20 toward the second transistor 30 in a plan view. Here, the X-axis direction is an example of the "first direction".

[0108] The insulating layer 140 is provided with a first opening 141 that penetrates the insulating layer 140 in the Z-axis direction and reaches the first connection region 52A. That is, the first opening 141 is provided between the first transistor 20 and the second transistor 30 in the X-axis direction. More specifically, the first opening 141 is provided between the first source electrode 22 of the first transistor 20 and the second drain electrode 33 of the second transistor 30 in a plan view.

[0109] In the first opening 141, a first connection portion 131 that electrically connects the first electrode 130 and the first connection region 52A is provided. Thereby, the first electrode 130 and the first metal layer 50A are electrically connected. For this reason, it can be said that the first connection portion 131 is provided between the first source electrode 22 of the first transistor 20 and the second drain electrode 33 of the second transistor 30 in the X-axis direction in a plan view. Since there is one first opening 141, there is one first connection portion 131.

[0110] In one example, the first connection portion 131 fills the first opening 141. Note that the configuration of the first connection portion 131 can be arbitrarily changed. In one example, a recessed space extending in the Z-axis direction may be formed by the first connection portion 131 provided on the inner surface of the first opening 141. Also, the first connection portion 131 may be formed of the same material as the first electrode 130, or may be formed of a material different from that of the first electrode 130.

[0111] The first electrode 130 extends across the first transistor 20 and the second transistor 30. The first electrode 130 covers the first opening 141. The first connection portion 131 is in contact with the portion of the first electrode 130 that covers the first opening 141. The first source electrode 22 and the second drain electrode 33 are electrically connected to the first metal layer 50A through the first electrode 130 and the first connection portion 131.

[0112] As shown in FIG. 2, the first electrode 130 is a wiring in which the first source wiring 81 and the second drain wiring 94 are integrated. In a plan view, the first electrode 130 extends in the X-axis direction so as to cross the opening 70AA of the first gate wiring 70A and the first opening 70BA of the second gate wiring 70B.

[0113] The first connection portion 131 is provided at a position overlapping the first electrode 130 and the first connection region 52A of the first metal layer 50A in a plan view. In one example, the shape of the first connection portion 131 in the plan view may be an oval shape extending in the Y-axis direction. Note that the shape of the first connection portion 131 in the plan view and the number of the first connection portions 131 can be arbitrarily changed. In one example, when a plurality of first connection portions 131 are provided, the plurality of first connection portions 131 may be arranged at intervals in the Y-axis direction at a position overlapping the first electrode 130 and the first connection region 52A of the first metal layer 50A in the plan view.

[0114] The thickness of the first electrode 130 is thicker than the thickness of the first metal layer 50A. In other words, the thickness of the first metal layer 50A is thinner than the thickness of the first electrode 130. Also, the thickness of the second metal layer 50B is thinner than the thickness of the first electrode 130.

[0115] The second source wiring 80B is electrically connected to the second metal layer 50B. More specifically, the second protruding portion 51B of the second metal layer 50B includes a second connection region 52B protruding in the X-axis direction from the second transistor 30 in a plan view. In the first embodiment, the second connection region 52B is a portion of the second protruding portion 51B that protrudes on the side opposite to the first transistor 20 with respect to the second transistor 30.

[0116] The insulating layer 140 is provided with a second opening 142 that penetrates the insulating layer 140 in the Z-axis direction and reaches the second connection region 52B. That is, the second opening 142 is provided on the side opposite to the first transistor 20 with respect to the second transistor 30.

[0117] A second connection portion 132 that electrically connects the second source wiring 80B and the second connection region 52B is provided in the second opening 142. Thereby, the second source wiring 80B and the second metal layer 50B are electrically connected. In one example, the second connection portion 132 fills the second opening 142.

[0118] As shown in FIG. 2, the second source wiring 80B electrically connected to the second metal layer 50B is the second source wiring 86. The second source wiring 86 is disposed closer to the fourth side surface 46 than the second source wirings 84 and 85 as the second source wiring 80B. In a plan view, the second source wiring 86 extends closer to the second side surface 44 than the second source wirings 84 and 85. In a plan view, the second source wiring 86 extends in the X-axis direction so as to cross the second opening 70BB of the second gate wiring 70B. Here, the second source wiring 86 is an example of the "second electrode".

[0119] The second connection portion 132 is provided at a position overlapping the second source wiring 86 and the second connection region 52B of the second metal layer 50B in a plan view. In one example, the shape of the second connection portion 132 in a plan view may be an oval shape extending in the Y-axis direction. Note that the shape of the second connection portion 132 in a plan view and the number of the second connection portions 132 can be arbitrarily changed. In one example, when a plurality of second connection portions 132 are provided, the plurality of second connection portions 132 may be arranged at intervals in the Y-axis direction at a position overlapping the second source wiring 86 and the second connection region 52B of the second metal layer 50B in a plan view.

[0120] Next, the connection structure between each of the source wirings 80A and 80B and each of the source pads 13A and 13B, and the connection structure between each of the drain wirings 90A and 90B and each of the drain pads 14A and 14B will be described.

[0121] Each of the source wirings 80A and 80B and each of the drain wirings 90A and 90B provided on the insulating layer 140 are covered with an interlayer insulating layer (not shown). And, each of the source pads 13A and 13B and each of the drain pads 14A and 14B are provided on the interlayer insulating layer. This interlayer insulating layer is provided on the insulating layer 140. The interlayer insulating layer may be formed of a material containing at least one of, for example, SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the interlayer insulating layer is formed of SiO2.

[0122] The first source wirings 81 to 83 as the first source wiring 80A and the first source pad 13A are electrically connected by a first source connection portion 151. The first source connection portion 151 is provided at a position overlapping both the first source wirings 81 to 83 and the first source pad 13A in a plan view. The first source connection portion 151 penetrates the interlayer insulating layer in the Z-axis direction. In one example, the first source connection portion 151 is provided for each of the first transistor cells TA to TC provided at a position overlapping the first source pad 13A in a plan view. The first source connection portion 151 is provided, for example, at a position overlapping the first drain electrode 23 of the first transistor cells TA to TC.

[0123] The first drain wirings 91 to 93 as the first drain wiring 90A and the first drain pad 14A are electrically connected by a first drain connection portion 152. The first drain connection portion 152 is provided at a position overlapping both the first drain wirings 91 to 93 and the first drain pad 14A in a plan view. The first drain connection portion 152 penetrates the interlayer insulating layer in the Z-axis direction. In one example, the first drain connection portion 152 is provided for each of the first transistor cells TA to TC provided at a position overlapping the first drain pad 14A in a plan view. The first drain connection portion 152 is provided, for example, at a position overlapping the first drain electrode 23 of the first transistor cells TA to TC.

[0124] The second source wirings 84 to 86 as the second source wiring 80B and the second source pad 13B are electrically connected by a second source connection portion 153. The second source connection portion 153 is provided at a position overlapping both the second source wirings 84 to 86 and the second source pad 13B in a plan view. The second source connection portion 153 penetrates the interlayer insulating layer in the Z-axis direction. In one example, the second source connection portion 153 is provided for each of the second transistor cells TD to TF provided at a position overlapping the second source pad 13B in a plan view. The second source connection portion 153 is provided, for example, at a position overlapping the second drain electrode 33 of the second transistor cells TD to TF.

[0125] The second drain wirings 94 to 96 as the second drain wiring 90B and the second drain pad 14B are electrically connected by a second drain connection portion 154. The second drain connection portion 154 is provided at a position overlapping both the second drain wirings 94 to 96 and the second drain pad 14B in a plan view. The second drain connection portion 154 penetrates through the interlayer insulating layer in the Z-axis direction. In one example, the second drain connection portion 154 is provided for each of the second transistor cells TD to TF provided at a position overlapping the second drain pad 14B in a plan view. The second drain connection portion 154 is provided, for example, at a position overlapping the second drain electrode 33 of the second transistor cells TD to TF.

[0126] Each of the source connection portions 151 and 153 and each of the drain connection portions 152 and 154 may be formed of a material containing at least one of, for example, Ti, TiN, Al, AlSiCu, and AlCu. Note that each of the source connection portions 151 and 153 and each of the drain connection portions 152 and 154 may be formed of the same material as each of the source pads 13A and 13B and each of the drain pads 14A and 14B. Note that the arrangement modes of each of the source connection portions 151 and 153 and each of the drain connection portions 152 and 154 can be arbitrarily changed. Also, the sizes of each of the source connection portions 151 and 153 and each of the drain connection portions 152 and 154 can be arbitrarily changed.

[0127] The first source wirings 82 and 83 are electrically connected to the first source wiring 81 by the first source connection portion 151 and the first source pad 13A. The second drain wirings 95 and 96 are electrically connected to the second drain wiring 94 by the second drain connection portion 154 and the second drain pad 14B. The first source wiring 81 and the second drain wiring 94 are integrated and constitute the first electrode 130. Therefore, the first source electrodes 22 of the first transistor cells TA to TC of the first transistor 20 are electrically connected to the second drain electrodes 33 of the second transistor cells TD to TF of the second transistor 30.

[0128] [Method for manufacturing a nitride semiconductor device] With reference to FIGS. 9 to 19, an example of a method for manufacturing a nitride semiconductor device 10 will be schematically described. FIGS. 9 to 19 show schematic cross-sectional structures indicating exemplary manufacturing steps of the nitride semiconductor device 10. FIGS. 9 to 19 correspond to the cross-sectional structure of the nitride semiconductor device 10 shown in FIG. 6.

[0129] As shown in FIG. 9, the method for manufacturing the nitride semiconductor device 10 includes forming a nitride semiconductor layer 210 on a support substrate 200. The support substrate 200 includes, for example, a composite base material having a thermal expansion coefficient equal to that of the nitride semiconductor layer 210. In one example, the thermal expansion coefficient of the nitride semiconductor layer 210 is determined based on AlN. Therefore, a composite base material containing AlN is used for the support substrate 200. In one example, the support substrate 200 includes a core 201 serving as a core material, a sealing layer 202 covering the core 201, and a seed crystal (not shown) provided on the upper surface of the sealing layer 202. The seed crystal can also be referred to as a seed layer.

[0130] The core 201 is made of a material containing polycrystalline ceramics of group III nitrides. In one example, AlN ceramics are used for the core 201. The sealing layer 202 is made of an insulating material containing SiO2, SiN, etc. In one example, the sealing layer 202 is a buried oxide layer (BOX oxide layer). The seed crystal is Si.

[0131] The nitride semiconductor layer 210 is formed, for example, by epitaxial growth from the seed crystal side using metalorganic chemical vapor deposition (MOCVD). The nitride semiconductor layer 210 is a layer constituting the first nitride semiconductor layer 24 and the second nitride semiconductor layer 34. The nitride semiconductor layer 210 includes a substrate-side nitride semiconductor layer 211, an electron supply layer 212, and a nitride semiconductor layer 213 from the seed crystal side.

[0132] The substrate-side nitride semiconductor layer 211 is a GaN layer, and the electron supply layer 212 is an AlGaN layer. The nitride semiconductor constituting the electron supply layer 212 has a larger bandgap than the substrate-side nitride semiconductor layer 211. The substrate-side nitride semiconductor layer 211 is a layer that constitutes the first substrate-side nitride semiconductor layer 25 (see FIG. 6) of the first transistor 20 and the second substrate-side nitride semiconductor layer 35 (see FIG. 6) of the second transistor 30. The electron supply layer 212 is a layer that constitutes the first electron supply layer 26 (see FIG. 6) of the first transistor 20 and the second electron supply layer 36 (see FIG. 6) of the second transistor 30.

[0133] The nitride semiconductor layer 213 is a p-type GaN layer. The nitride semiconductor layer 213 is a layer that constitutes the first gate layer 27 and the second gate layer 37 (both see FIG. 6). The nitride semiconductor layer 213 is formed by doping an acceptor-type impurity after the GaN layer is formed. In one example, a nitride semiconductor layer 213 containing an acceptor-type impurity can be formed by doping Mg during the growth of the nitride semiconductor layer 213. In this process, for example, an SOI (Silicon on Insulator) substrate may be used as the support substrate 200.

[0134] As shown in FIG. 10, the manufacturing method of the nitride semiconductor device 10 includes peeling the nitride semiconductor layer 210 from the support substrate 200 (see FIG. 9). In this process, the support substrate 200 and the nitride semiconductor layer 210 are immersed in an etching solution such as hydrofluoric acid. As a result, the sealing layer 202 of the support substrate 200 is removed, so that the nitride semiconductor layer 210 is peeled from the support substrate 200.

[0135] As shown in FIG. 11, the manufacturing method of the nitride semiconductor device 10 includes preparing a substrate 40, forming a metal layer 220, and bonding the nitride semiconductor layer 210 to the metal layer 220.

[0136] The substrate 40 is, for example, a semi-insulating SiC substrate. The metal layer 220 is formed on the first surface 41 of the substrate 40, for example, by sputtering. The metal layer 220 is formed, for example, over the entire first surface 41. The metal layer 220 contains, for example, at least one of Al and Pt. The metal layer 220 is a layer that constitutes the first metal layer 50A and the second metal layer 50B (both see FIG. 6).

[0137] Subsequently, a nitride semiconductor layer 210 is bonded onto the metal layer 220. More specifically, the metal layer 220 and the substrate-side nitride semiconductor layer 211 of the nitride semiconductor layer 210 are bonded. The metal layer 220 and the substrate-side nitride semiconductor layer 211 are bonded by an intermolecular bond. More specifically, the metal layer 220 and the substrate-side nitride semiconductor layer 211 are bonded by a hydrogen bond between OH groups.

[0138] As shown in FIGS. 12 to 15, the method for manufacturing the nitride semiconductor device 10 includes forming a first transistor 20 and a second transistor 30. First, as shown in FIG. 12, forming each transistor 20, 30 includes forming a gate electrode layer 230. The gate electrode layer 230 is formed on the nitride semiconductor layer 213, for example, by sputtering. The gate electrode layer 230 is, for example, a TiN layer. The gate electrode layer 230 is a metal layer that constitutes the first gate electrode 21 and the second gate electrode 31 (both see FIG. 6).

[0139] Next, as shown in FIG. 13, forming each transistor 20, 30 includes forming a first gate layer 27 and a second gate layer 37 and the first gate electrode 21 and the second gate electrode 31.

[0140] In this step, first, a mask (not shown) that covers the portions that will become the first gate electrode 21 and the second gate electrode 31 on the gate electrode layer 230 shown in FIG. 12 is formed. Subsequently, the gate electrode layer 230 exposed from the mask is removed. Thereby, the first gate electrode 21 and the second gate electrode 31 shown in FIG. 13 are formed.

[0141] Next, a mask (not shown) that covers the portions of the upper surface of the nitride semiconductor layer 213 shown in FIG. 12 that will become the first gate layer 27 and the second gate layer 37 and the first gate electrode 21 and the second gate electrode 31 is formed. Subsequently, the nitride semiconductor layer 213 exposed from the mask is removed. Thereby, the first gate layer 27 and the second gate layer 37 shown in FIG. 13 are formed.

[0142] Next, as shown in FIG. 14, forming each transistor 20, 30 includes forming a first passivation layer 28 and a second passivation layer 38. The first passivation layer 28 includes a first source opening 28A and a first drain opening 28B. The second passivation layer 38 includes a second source opening 38A and a second drain opening 38B.

[0143] The first passivation layer 28 and the second passivation layer 38 are formed by etching a SiN film after forming a SiN film that covers the electron supply layer 212, the first gate layer 27 and the second gate layer 37, and the first gate electrode 21 and the second gate electrode 31. The SiN film is formed using, for example, a low-pressure chemical vapor deposition (LPCVD) method. Then, the electron supply layer 212 is exposed through each source opening 28A, 38A and each drain opening 28B, 38B.

[0144] Next, forming each transistor 20, 30 includes forming a first source electrode 22, a second source electrode 32, a first drain electrode 23, a second drain electrode 33, a first field plate electrode 22F, and a second field plate electrode 32F.

[0145] In this step, first, an electrode layer is formed on each of the passivation layers 28 and 38 and on the electron supply layer 212 exposed from each of the passivation layers 28 and 38. The electrode layer is a metal layer that constitutes each source electrode 22 and 32, each drain electrode 23 and 33, and each field plate electrode 22F and 32F. The electrode layer is filled in each source opening 28A and 38A and each drain opening 28B and 38B and is in contact with the electron supply layer 212. In one example, the electrode layer may include at least one of Ti, TiN, Al, AlSiCu, and AlCu. Subsequently, the electrode layer is selectively removed by lithography and etching. Thereby, the first source electrode 22, the second source electrode 32, the first drain electrode 23, the second drain electrode 33, the first field plate electrode 22F, and the second field plate electrode 32F are formed.

[0146] Next, as shown in FIG. 15, forming each of the transistors 20 and 30 includes cutting the nitride semiconductor layer 210. In this step, for example, the electron supply layer 212 and the substrate-side nitride semiconductor layer 211 are selectively removed by dry etching. Thereby, the first substrate-side nitride semiconductor layer 25 and the second substrate-side nitride semiconductor layer 35 are formed from the substrate-side nitride semiconductor layer 211, and the first electron supply layer 26 and the second electron supply layer 36 are formed from the electron supply layer 212. Through the above steps, the first transistor 20 and the second transistor 30 are formed.

[0147] As shown in FIG. 16, the method for manufacturing the nitride semiconductor device 10 includes forming a first metal layer 50A and a second metal layer 50B from a metal layer 220. In this step, for example, by dry etching, a portion of the metal layer 220 exposed from the first nitride semiconductor layer 24 and the second nitride semiconductor layer 34 is selectively removed. Thereby, the first metal layer 50A and the second metal layer 50B are formed. The first metal layer 50A includes an overhanging portion 51A that protrudes from the first nitride semiconductor layer 24 in plan view. A portion of the overhanging portion 51A between the first transistor 20 and the second transistor 30 in the X-axis direction constitutes a first connection region 52A. The second metal layer 50B includes an overhanging portion 51B that protrudes from the second nitride semiconductor layer 34 in plan view. A portion of the overhanging portion 51B on the side opposite to the first transistor 20 with respect to the second transistor 30 constitutes a second connection region 52B.

[0148] As shown in FIG. 17, the method for manufacturing the nitride semiconductor device 10 includes forming an insulating layer 140. The insulating layer 140 is formed to cover the first metal layer 50A, the second metal layer 50B, the first transistor 20, and the second transistor 30, for example, by the LPCVD method. The insulating layer 140 may be formed of a material including at least one of, for example, SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the insulating layer 140 is formed of SiO2.

[0149] Subsequently, a first opening 141 and a second opening 142 are formed in the insulating layer 140, for example, by dry etching. The first opening 141 penetrates the insulating layer 140 in the Z-axis direction and reaches the first connection region 52A of the first metal layer 50A. The second opening 142 penetrates the insulating layer 140 in the Z-axis direction and reaches the second connection region 52B of the second metal layer 50B.

[0150] Similarly, electrode openings 143 to 146 are formed to partially expose each source electrode 22, 32 and each drain electrode 23, 33, for example, by dry etching. Similarly, electrode openings (not shown) are formed to partially expose each gate electrode 21, 31, for example, by dry etching.

[0151] As shown in FIGS. 18 and 19, the method for manufacturing the nitride semiconductor device 10 includes forming a first gate wiring 70A, a second gate wiring 70B, a first source wiring 80A, a second source wiring 80B, a first drain wiring 90A, and a second drain wiring 90B.

[0152] As shown in FIG. 18, first, a wiring layer 240 is formed on the insulating layer 140. The wiring layer 240 is a metal layer that constitutes each gate wiring 70A, 70B, each source wiring 80A, 80B, and each drain wiring 90A, 90B. In one example, the wiring layer 240 may be formed of a material containing at least one of Ti, TiN, Al, AlSiCu, and AlCu. The wiring layer 240 is filled in the first opening 141, the second opening 142, the electrode openings 143 to 146, and the electrode openings that partially expose each gate electrode 21, 31. Thereby, a first connection portion 131, a second connection portion 132, first outer peripheral gate vias 101, 102, first intermediate gate vias 103, 104, a first source via 105, a first drain via 106, second outer peripheral gate vias 111, 112, second intermediate gate vias 113, 114, a second source via 115, and a second drain via 116 (all shown in FIG. 2) are formed. That is, the method for manufacturing the nitride semiconductor device 10 includes forming the first connection portion 131 in the first opening 141 so as to be electrically connected to the first connection region 52A, and forming the second connection portion 132 in the second opening 142 so as to be electrically connected to the second connection region 52B.

[0153] Note that the first connection part 131, the second connection part 132, the first outer peripheral gate vias 101 and 102, the first intermediate gate vias 103 and 104, the first source via 105, the first drain via 106, the second outer peripheral gate vias 111 and 112, the second intermediate gate vias 113 and 114, the second source via 115, and the second drain via 116 may be formed by a process different from the process of forming the wiring layer 240. That is, the manufacturing method of the nitride semiconductor device 10 includes a process of forming the first connection part 131, the second connection part 132, the first outer peripheral gate vias 101 and 102, the first intermediate gate vias 103 and 104, the first source via 105, the first drain via 106, the second outer peripheral gate vias 111 and 112, the second intermediate gate vias 113 and 114, the second source via 115, and the second drain via 116. Therefore, the first connection part 131, the second connection part 132, the first outer peripheral gate vias 101 and 102, the first intermediate gate vias 103 and 104, the first source via 105, the first drain via 106, the second outer peripheral gate vias 111 and 112, the second intermediate gate vias 113 and 114, the second source via 115, and the second drain via 116 may be formed of a material different from that of the wiring layer 240.

[0154] Subsequently, as shown in FIG. 19, the wiring layer 240 is selectively removed by lithography and etching. Thereby, the first source wiring 80A, the second source wiring 80B, the first drain wiring 90A, and the second drain wiring 90B are formed on the insulating layer 140. In addition, a first electrode 130 in which the first source wiring 80A and the second drain wiring 90B are integrated is formed. Although not shown, the first gate wiring 70A and the second gate wiring 70B are formed.

[0155] Note that although not shown, the manufacturing method of the nitride semiconductor device 10 includes forming an interlayer insulating layer covering each gate wiring 70A and 70B, each source wiring 80A and 80B, and each drain wiring 90A and 90B. This interlayer insulating layer is formed on the insulating layer 140. The interlayer insulating layer may be formed of a material including at least one of, for example, SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the interlayer insulating layer is formed of SiO2.

[0156] Subsequently, openings are formed to partially expose each gate wiring 70A, 70B, each source wiring 80A, 80B, and each drain wiring 90A, 90B. These openings are formed in the interlayer insulating layer by, for example, dry etching.

[0157] Then, the method for manufacturing the nitride semiconductor device 10 includes forming a first gate pad 12A, a second gate pad 12B, a first source pad 13A, a second source pad 13B, a first drain pad 14A, and a second drain pad 14B. Each gate pad 12A, 12B, each source pad 13A, 13B, and each drain pad 14A, 14B are formed on the interlayer insulating layer. In this step, first, a metal layer is formed on the interlayer insulating layer. The metal layer is a layer that constitutes each gate pad 12A, 12B, each source pad 13A, 13B, and each drain pad 14A, 14B. In this step, vias (not shown) that are in contact with each gate wiring 70A, 70B, each source wiring 80A, 80B, and each drain wiring 90A, 90B are formed by filling the metal layer into each opening of the interlayer insulating layer. Subsequently, the metal layer is selectively removed by lithography and etching. Thereby, the first gate pad 12A, the second gate pad 12B, the first source pad 13A, the second source pad 13B, the first drain pad 14A, and the second drain pad 14B are formed. Through the above steps, the nitride semiconductor device 10 is manufactured.

[0158] [Operation of the First Embodiment] The operation of the nitride semiconductor device 10 of the first embodiment will be described. In a nitride semiconductor device, for the purpose of stabilizing the gate threshold, a configuration is adopted in which the source electrode is electrically connected to a substrate (for example, a semiconductor substrate such as an Si substrate) so that the source electrode and the substrate are at the same potential. In a nitride semiconductor device, since the electrical resistance of the substrate is large, it is difficult for the potential to be stable over the entire second surface of the substrate, which is opposite to the first surface on which the nitride semiconductor layer is provided. As a result, it becomes difficult to stabilize the gate threshold.

[0159] In this regard, in the first embodiment, the first source electrode 22 of the first transistor 20 is connected to the first metal layer 50A provided on the substrate 40. Therefore, for the first nitride semiconductor layer 24 of the first transistor 20, the portion on the side of the first metal layer 50A can be stabilized as the source potential. Thereby, the gate threshold value of the first transistor 20 can be stabilized.

[0160] The second source electrode 32 of the second transistor 30 is connected to the second metal layer 50B provided on the substrate 40. Therefore, for the second nitride semiconductor layer 34 of the second transistor 30, the portion on the side of the second metal layer 50B can be stabilized as the source potential. Thereby, the gate threshold value of the second transistor 30 can be stabilized.

[0161] In addition, when providing the first transistor and the second transistor that form a half-bridge circuit on one substrate, it is necessary to make the source of the first transistor independent from the source of the second transistor. In this case, it is necessary to provide an insulator between the first region and the second region so as to electrically insulate the substrate between the first region of the first transistor and the second region of the second transistor. However, the configuration of providing an insulator on the substrate complicates the configuration of the substrate and increases the cost. Also, because the electrical resistance of the substrate is large, the potentials of the first region and the second region of the substrate are difficult to be stable throughout each region. As a result, it becomes difficult to stabilize each of the gate threshold value of the first transistor and the gate threshold value of the second transistor.

[0162] In this regard, in the first embodiment, a first metal layer 50A corresponding to the first transistor 20 and a second metal layer 50B corresponding to the second transistor 30 are provided on the first surface 41 of the substrate 40. Since the first metal layer 50A and the second metal layer 50B are arranged to be separated from each other, they are insulated from each other. The first source electrode 22 of the first transistor 20 is electrically connected to the first metal layer 50A. The second source electrode 32 of the second transistor 30 is electrically connected to the second metal layer 50B. Thus, since the first metal layer 50A and the second metal layer 50B are provided on the first surface 41 of the substrate 40, the number of man-hours in the manufacturing process is reduced as compared with a configuration in which an insulator is provided in the substrate 40. Therefore, the manufacturing cost of the nitride semiconductor device 10 can be reduced. In addition, since both the first metal layer 50A and the second metal layer 50B are provided separately on the insulating first surface 41 of the substrate 40, the potential is likely to be stable. Therefore, each of the gate threshold value of the first transistor 20 and the gate threshold value of the second transistor 30 is likely to be stabilized.

[0163] [Effects of the First Embodiment] According to the nitride semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The nitride semiconductor device 10 includes a substrate 40 including an insulating first surface 41, a first metal layer 50A provided on the first surface 41, a first transistor 20 provided on the first metal layer 50A and having a first nitride semiconductor layer 24, a first source electrode 22, a first drain electrode 23, and a first gate electrode 21, an insulating layer 140 covering the first transistor 20, and a first electrode 130 provided on the insulating layer 140 and electrically connected to the first source electrode 22. The first nitride semiconductor layer 24 is in contact with the first metal layer 50A. The first metal layer 50A has a first connection region 52A that protrudes in a first direction (the X-axis direction in the first embodiment) from the first transistor 20 in a plan view. The insulating layer 140 is provided with a first opening 141 that penetrates the insulating layer 140 in the Z-axis direction and reaches the first connection region 52A. A first connection portion 131 that electrically connects the first electrode 130 and the first connection region 52A is provided in the first opening 141.

[0164] According to this configuration, the first source electrode 22 and the first metal layer 50A are electrically connected through the first connection portion 131 and the first electrode 130. Therefore, for the first nitride semiconductor layer 24 of the first transistor 20, the portion on the side of the first metal layer 50A can be stabilized as the source potential. Thereby, the gate threshold value of the first transistor 20 can be stabilized. Therefore, the on / off operation of the nitride semiconductor device 10 can be stabilized.

[0165] (1-2) The nitride semiconductor device 10 includes a second metal layer 50B provided on the first surface 41 and separated from the first metal layer 50A, and a second transistor 30 provided on the second metal layer 50B and having a second nitride semiconductor layer 34, a second source electrode 32, a second drain electrode 33, and a second gate electrode 31, and covered by an insulating layer 140. The second transistor 30 is provided at a distance from the first transistor 20 in the first direction (X-axis direction) by the first opening 141. The second drain electrode 33 is electrically connected to the first electrode 130.

[0166] According to this configuration, the first transistor 20 and the second transistor 30 that form a half-bridge circuit can be provided on the first surface 41 of the substrate 40. That is, the nitride semiconductor device 10 as a half-bridge circuit with a stable gate threshold value of the first transistor 20 can be realized.

[0167] (1-3) The second drain electrode 33 is arranged closer to the first opening 141 than the second gate electrode 31 in the X-axis direction (the first direction). The first connection portion 131 is arranged between the first source electrode 22 and the second drain electrode 33 in the X-axis direction (the first direction). According to this configuration, since there is no need to provide a dedicated configuration for the first electrode 130 for connecting the first connection portion 131, the configuration of the first electrode 130 can be simplified.

[0168] (1-4) The nitride semiconductor device 10 is provided on the insulating layer 140 and includes a second source wiring 80B (86) as a second electrode electrically connected to the second source electrode 32. The second metal layer 50B has a second connection region 52B protruding from the side opposite to the first transistor 20 among the second transistors 30 in a plan view. The insulating layer 140 is provided with a second opening 142 that penetrates the insulating layer 140 in the Z-axis direction and reaches the second connection region 52B. A second connection portion 132 that electrically connects the second source wiring 80B (86) and the second connection region 52B is provided in the second opening 142.

[0169] According to this configuration, the second source electrode 32 and the second metal layer 50B are electrically connected through the second connection portion 132 and the second source wiring 80B (86). Therefore, for the second nitride semiconductor layer 34 of the second transistor 30, the portion on the side of the second metal layer 50B can be stabilized as the source potential. Therefore, the gate threshold value of the second transistor 30 can be stabilized. Thereby, the on-off operation of the nitride semiconductor device 10 can be stabilized.

[0170] (1-5) The first nitride semiconductor layer 24 is provided on the first metal layer 50A and includes a first substrate-side nitride semiconductor layer 25 composed of a nitride semiconductor, a first electron supply layer 26 provided on the first substrate-side nitride semiconductor layer 25 and composed of a nitride semiconductor having a larger bandgap than the first substrate-side nitride semiconductor layer 25, and a first gate layer 27 partially provided on the first electron supply layer 26 and composed of a nitride semiconductor containing acceptor-type impurities. The first gate electrode 21 is disposed on the first gate layer 27. The first source electrode 22 and the first drain electrode 23 are disposed opposite to each other with the first gate layer 27 interposed therebetween on the first electron supply layer 26.

[0171] According to this configuration, the first transistor 20 can be configured as a normally-off transistor. The first transistor 20 can be configured as a lateral transistor in which a first gate electrode 21, a first source electrode 22, and a first drain electrode 23 are provided on the first electron supply layer 26. In this way, the first transistor 20 and the second transistor 30 that form a half-bridge circuit can be easily formed on the same substrate 40.

[0172] (1-6) The second nitride semiconductor layer 34 is provided on the second metal layer 50B and includes a second substrate-side nitride semiconductor layer 35 formed of a nitride semiconductor, a second electron supply layer 36 formed of a nitride semiconductor provided on the second substrate-side nitride semiconductor layer 35 and having a larger bandgap than the second substrate-side nitride semiconductor layer 35, and a second gate layer 37 formed of a nitride semiconductor partially provided on the second electron supply layer 36 and containing acceptor-type impurities. The second gate electrode 31 is disposed on the second gate layer 37. The second source electrode 32 and the second drain electrode 33 are disposed opposite to each other with the second gate layer 37 interposed therebetween on the second electron supply layer 36.

[0173] According to this configuration, the second transistor 30 can be configured as a normally-off transistor. The second transistor 30 can be configured as a lateral transistor in which a second gate electrode 31, a second source electrode 32, and a second drain electrode 33 are provided on the second electron supply layer 36. In this way, the first transistor 20 and the second transistor 30 that form a half-bridge circuit can be easily formed on the same substrate 40.

[0174] (1-7) The thickness of the first metal layer 50A is thinner than the thickness of the first electrode 130. According to this configuration, the height of the nitride semiconductor device 10 can be reduced as compared with the case where the thickness of the first metal layer 50A is thicker than the thickness of the first electrode 130. The same effect can be obtained even when the thickness of the second metal layer 50B is thinner than the thickness of the first electrode 130.

[0175] (1-8) The nitride semiconductor layer 25 on the first substrate side is composed of a single material. According to this configuration, warping of the nitride semiconductor layer 25 on the first substrate side during the manufacture of the nitride semiconductor device 10 can be suppressed as compared with the case where the nitride semiconductor layer 25 on the first substrate side is composed of a stacked structure of a plurality of layers.

[0176] (1-9) A part of the portion of the nitride semiconductor layer 25 on the first substrate side closer to the first metal layer 50A than the surface layer portion contains carbon with a concentration of 1×10 19 cm -3 or more as an impurity. According to this configuration, the insulating property of the portion of the nitride semiconductor layer 25 on the first substrate side closer to the first metal layer 50A can be enhanced. Therefore, the breakdown voltage of the first transistor 20 can be improved.

[0177] (1-10) The nitride semiconductor layer 35 on the second substrate side is composed of a single material. According to this configuration, warping of the nitride semiconductor layer 35 on the second substrate side during the manufacture of the nitride semiconductor device 10 can be suppressed as compared with the case where the nitride semiconductor layer 35 on the second substrate side is composed of a stacked structure of a plurality of layers.

[0178] (1-11) A part of the portion of the nitride semiconductor layer 35 on the second substrate side closer to the second metal layer 50B than the surface layer portion contains carbon with a concentration of 1×10 19 cm -3 or more as an impurity. According to this configuration, the insulating property of the portion of the nitride semiconductor layer 35 on the second substrate side closer to the second metal layer 50B can be enhanced. Therefore, the breakdown voltage of the second transistor 30 can be improved.

[0179] (1-12) The substrate 40 is a sapphire substrate or a semi-insulating SiC substrate. According to this configuration, the insulating property in the path through the substrate 40 between the first metal layer 50A and the second metal layer 50B can be enhanced as compared with the case where the substrate 40 is an Si substrate.

[0180] (1-13) The thickness of the second metal layer 50B is equal to the thickness of the first metal layer 50A. According to this configuration, the first metal layer 50A and the second metal layer 50B can be formed in a common process. Therefore, the manufacturing process of the nitride semiconductor device 10 can be simplified.

[0181] (1-14) The thickness of the second nitride semiconductor layer 34 is equal to the thickness of the first nitride semiconductor layer 24. According to this configuration, the first nitride semiconductor layer 24 and the second nitride semiconductor layer 34 can be formed in a common process. Therefore, the manufacturing process of the nitride semiconductor device 10 can be simplified.

[0182] (1-15) The number of first connection portions 131 that connect the first electrode 130 and the first metal layer 50A is one. According to this configuration, since the potential of the first metal layer 50A is stable as a whole, if the first connection portion 131 is connected at one location, the gate threshold of the first transistor 20 can be stabilized. Therefore, compared with the case where a plurality of first connection portions 131 are provided, the gate threshold of the first transistor 20 can be stabilized and the configuration of the nitride semiconductor device 10 can be simplified.

[0183] (1-16) The number of second connection portions 132 that connect the second source wiring 80B and the second metal layer 50B is one. According to this configuration, since the potential of the second metal layer 50B is stable as a whole, if the second connection portion 132 is connected at one location, the gate threshold of the second transistor 30 can be stabilized. Therefore, compared with the case where a plurality of second connection portions 132 are provided, the gate threshold of the second transistor 30 can be stabilized and the configuration of the nitride semiconductor device 10 can be simplified.

[0184] (1-17) The manufacturing method of the nitride semiconductor device 10 includes forming a nitride semiconductor layer 210 on a support substrate 200, preparing a substrate 40 having a first surface 41 with insulation property, forming a metal layer 220 on the first surface 41, peeling the nitride semiconductor layer 210 from the support substrate 200, bonding the nitride semiconductor layer 210 to the metal layer 220, forming a first transistor 20 having a first source electrode 22, a first drain electrode 23, and a first gate electrode 21, forming an insulating layer 140 to cover the first transistor 20, and forming a first electrode 130 on the insulating layer 140 so as to be electrically connected to the first source electrode 22. When forming the metal layer 220, a first connection region 52A is formed in the metal layer 220 so as to protrude from the first transistor 20 in a plan view. When forming the insulating layer 140, a first opening 141 is formed so as to penetrate the insulating layer 140 in the Z-axis direction and reach the first connection region 52A. The manufacturing method of the nitride semiconductor device 10 includes forming a first connection portion 131 in the first opening 141 so as to be electrically connected to the first connection region 52A. When forming the first electrode 130, the first electrode 130 is formed on the insulating layer 140 so as to contact the first connection portion 131.

[0185] According to this configuration, the first source electrode 22 and the first metal layer 50A are electrically connected through the first connection portion 131 and the first electrode 130. Therefore, for the first nitride semiconductor layer 24 of the first transistor 20, the portion on the side of the first metal layer 50A can be stabilized as a source potential. Thereby, the gate threshold value of the first transistor 20 can be stabilized. Therefore, the on-off operation of the nitride semiconductor device 10 can be stabilized.

[0186] (1-18) The manufacturing method of the nitride semiconductor device 10 includes forming a nitride semiconductor layer 210 on a support substrate 200, preparing a substrate 40 having a first surface 41 with insulation, forming a metal layer 220 on the first surface 41, peeling the nitride semiconductor layer 210 from the support substrate 200, bonding the nitride semiconductor layer 210 to the metal layer 220, forming a first source electrode 22, a first drain electrode 23, and a first gate electrode 21, and a second source electrode 32, a second drain electrode 33, and a second gate electrode 31 on the nitride semiconductor layer 210, forming a first nitride semiconductor layer 24 and a second nitride semiconductor layer 34 spaced apart from the first nitride semiconductor layer 24 from the nitride semiconductor layer 210, forming an insulating layer 140 to cover a first transistor 20 including the first source electrode 22, the first drain electrode 23, the first gate electrode 21, and the first nitride semiconductor layer 24, and a second transistor 30 including the second source electrode 32, the second drain electrode 33, the second gate electrode 31, and the second nitride semiconductor layer 34, and forming a first electrode 130 on the insulating layer 140 so as to be electrically connected to both the first source electrode 22 and the second drain electrode 33. Forming the metal layer 220 includes forming a first metal layer 50A to which the first nitride semiconductor layer 24 is bonded and a second metal layer 50B which is disposed spaced apart from the first metal layer 50A and to which the second nitride semiconductor layer 34 is bonded from the metal layer 220. By forming the metal layer 220, a first connection region 52A is formed in the first metal layer 50A so as to protrude from the first transistor 20 in a plan view. By forming the insulating layer 140, a first opening 141 is formed so as to penetrate the insulating layer 140 in the Z-axis direction and reach the first connection region 52A. The manufacturing method of the nitride semiconductor device 10 includes forming a first connection portion 131 in the first opening 141 so as to be electrically connected to the first connection region 52A. By forming the first electrode 130, the first electrode 130 is formed on the insulating layer 140 so as to contact the first connection portion 131.

[0187] According to this configuration, the first transistor 20 and the second transistor 30 that form a half-bridge circuit can be manufactured in a common process on the substrate 40. Therefore, the manufacturing process of the nitride semiconductor device 10 can be simplified. In addition, the first source electrode 22 and the first metal layer 50A are electrically connected via the first connection portion 131 and the first electrode 130. Therefore, for the first nitride semiconductor layer 24 of the first transistor 20, the portion on the side of the first metal layer 50A can be stabilized as the source potential. Thereby, the gate threshold value of the first transistor 20 can be stabilized. Therefore, the on / off operation of the nitride semiconductor device 10 can be stabilized.

[0188] (1-19) By forming the metal layer 220, in a plan view, the second connection region 52B is formed in the second metal layer 50B so as to protrude from the second transistor 30. The manufacturing method of the nitride semiconductor device 10 includes forming the second source wiring 80B(86) as the second electrode on the insulating layer 140 so as to be electrically connected to the second source electrode 32, forming the second opening 142 so as to penetrate the insulating layer 140 in the Z-axis direction and reach the second connection region 52B, and forming the second connection portion 132 in the second opening 142 so as to be electrically connected to the second connection region 52B. By forming the second source wiring 80B(86), the second source wiring 80B(86) is formed on the insulating layer 140 so as to be in contact with the second connection portion 132.

[0189] According to this configuration, the second source electrode 32 and the second metal layer 50B are electrically connected through the second connection portion 132 and the second source wiring 80B(86). Therefore, for the second nitride semiconductor layer 34 of the second transistor 30, the portion on the side of the second metal layer 50B can be stabilized as the source potential. Therefore, the gate threshold value of the second transistor 30 can be stabilized. Thereby, the on / off operation of the nitride semiconductor device 10 can be stabilized.

[0190] In addition, when the second opening 142 is formed in the same process as the first opening 141, the manufacturing process of the nitride semiconductor device 10 can be simplified. Further, when the second connection portion 132 is formed in the same process as the first connection portion 131, the manufacturing process of the nitride semiconductor device 10 can be simplified. Furthermore, when the second source wiring 80B(86) is formed in the same process as the first electrode 130, the manufacturing process of the nitride semiconductor device 10 can be simplified.

[0191] <Second Embodiment> Referring to FIG. 20, the nitride semiconductor device 10 according to the second embodiment will be described. In the nitride semiconductor device 10 of the second embodiment, it is mainly different from the nitride semiconductor device 10 of the first embodiment in that a substrate 160 is provided instead of the substrate 40. In the following description, components common to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0192] As shown in FIG. 20, the substrate 160 includes a first surface 161 and a second surface 162 opposite to the first surface 161. The substrate 160 includes an Si substrate 163 and a substrate-side insulating layer 164 provided on the Si substrate 163. The Si substrate 163 is configured to include the second surface 162. The substrate-side insulating layer 164 includes the first surface 161.

[0193] The substrate-side insulating layer 164 is provided over the entire upper surface of the Si substrate 163. The substrate-side insulating layer 164 is made of, for example, SiO2. In one example, the substrate-side insulating layer 164 is formed by thermally oxidizing the Si substrate 163. In one example, the substrate-side insulating layer 164 is made of the same material as the insulating layer 140. Note that the insulating material constituting the substrate-side insulating layer 164 and the insulating material constituting the insulating layer 140 can be arbitrarily changed, respectively. In one example, the substrate-side insulating layer 164 may be made of a material different from that of the insulating layer 140.

[0194] The thickness of the substrate-side insulating layer 164 is greater than the thickness of the first metal layer 50A. The thickness of the substrate-side insulating layer 164 is greater than the thickness of the second metal layer 50B. In one example, the thickness of the substrate-side insulating layer 164 is about 600 nm. Here, the thickness of the substrate-side insulating layer 164 can be defined by the distance in the Z-axis direction between the boundary between the Si substrate 163 and the substrate-side insulating layer 164 and the first surface 161 of the substrate 160. Note that the thickness of the substrate-side insulating layer 164 may be set according to the breakdown voltage of the nitride semiconductor device 10.

[0195] The first metal layer 50A and the second metal layer 50B are provided on the first surface 161 of the substrate 160. In other words, the first metal layer 50A and the second metal layer 50B are provided on the substrate-side insulating layer 164. Therefore, the substrate-side insulating layer 164 is exposed in the portion between the first metal layer 50A and the second metal layer 50B. The insulating layer 140 is in contact with the substrate-side insulating layer 164 in the portion between the first metal layer 50A and the second metal layer 50B.

[0196] Note that the configurations of the first transistor 20 provided on the first metal layer 50A and the second transistor 30 provided on the second metal layer 50B are the same as those in the first embodiment. Also, the configurations of the first gate wiring 70A, the second gate wiring 70B, the first source wiring 80A, the second source wiring 80B, the first drain wiring 90A, the second drain wiring 90B (both refer to FIG. 2), and the insulating layer 140 are the same as those in the first embodiment.

[0197] [Effects of the Second Embodiment] According to the nitride semiconductor device 10 of the second embodiment, in addition to the effects of (1-1) to (1-11), (1-13) to (1-19) of the first embodiment, the following effects can be obtained.

[0198] (2-1) The substrate 160 includes an Si substrate 163 and a substrate-side insulating layer 164 provided on the Si substrate 163. The substrate-side insulating layer 164 includes the first surface 161 of the substrate 160. According to this configuration, since the Si substrate 163 is used as the substrate 160, the cost of the substrate 160 can be reduced as compared with the case where a sapphire substrate or a SiC substrate is used.

[0199] (2-2) The thickness of the substrate-side insulating layer 164 is thicker than the thickness of the first metal layer 50A. According to this configuration, the first metal layer 50A and the second metal layer 50B can be more reliably insulated. Thereby, the first nitride semiconductor layer 24 of the first transistor 20 and the second nitride semiconductor layer 34 of the second transistor 30 can be more reliably insulated.

[0200] <Third Embodiment> Referring to FIG. 21, the nitride semiconductor device 10 of the third embodiment will be described. In the nitride semiconductor device 10 of the third embodiment, the configuration of the first substrate-side nitride semiconductor layer 25 of the first transistor 20 and the configuration of the second substrate-side nitride semiconductor layer 35 of the second transistor 30 are mainly different from those of the nitride semiconductor device 10 of the first embodiment. In the following description, the same reference numerals are given to the components common to the first embodiment, and the description thereof will be omitted.

[0201] As shown in FIG. 21, the first substrate-side nitride semiconductor layer 25 of the first transistor 20 is formed of a stacked structure of a plurality of layers. More specifically, in the third embodiment, the first substrate-side nitride semiconductor layer 25 is formed of a stacked structure including a first buffer layer 25A and a first electron traveling layer 25B provided on the first buffer layer 25A.

[0202] The first buffer layer 25A is provided on the first metal layer 50A. The first buffer layer 25A is in contact with the first metal layer 50A. In the third embodiment, the first buffer layer 25A includes one nitride semiconductor layer. The first buffer layer 25A includes, for example, a single AlN layer or a single AlGaN layer.

[0203] The thickness of the first buffer layer 25A is thinner than that of the first electron traveling layer 25B. Here, the thickness of the first buffer layer 25A can be defined by the distance in the Z-axis direction between the lower surface of the first substrate-side nitride semiconductor layer 25 (the surface in contact with the first metal layer 50A) and the boundary between the first buffer layer 25A and the first electron traveling layer 25B. The thickness of the first electron traveling layer 25B can be defined by the distance in the Z-axis direction between the boundary between the first buffer layer 25A and the first electron traveling layer 25B and the boundary between the first electron traveling layer 25B and the first electron supply layer 26.

[0204] The first electron traveling layer 25B is composed of a GaN layer, for example, in the same manner as the first substrate-side nitride semiconductor layer 25 of the first embodiment. In order to suppress the leakage current in the first electron traveling layer 25B, impurities may be introduced into a part of the first electron traveling layer 25B to make the portion other than the surface layer portion of the first electron traveling layer 25B semi-insulating. In this case, the impurity is, for example, C. The impurity concentration of the carbon is, for example, 1×10 19 cm -3 or more.

[0205] The second substrate-side nitride semiconductor layer 35 of the second transistor 30 is configured by a stacked structure of a plurality of layers. More specifically, in the third embodiment, the second substrate-side nitride semiconductor layer 35 is configured by a stacked structure of a second buffer layer 35A provided on the second metal layer 50B and a second electron traveling layer 35B provided on the second buffer layer 35A. In the third embodiment, the configurations of the second buffer layer 35A and the second electron traveling layer 35B are the same as those of the first buffer layer 25A and the first electron traveling layer 25B. Therefore, the thickness of the second buffer layer 35A is thinner than that of the second electron traveling layer 35B. The thickness of the second buffer layer 35A is equal to the thickness of the first buffer layer 25A. The thickness of the second electron traveling layer 35B is equal to the thickness of the first electron traveling layer 25B.

[0206] [Effect of the Third Embodiment] According to the nitride semiconductor device 10 of the third embodiment, in addition to the effects of (1-1) to (1-7), (1-9), (1-11) to (1-19) of the first embodiment, the following effects can be obtained.

[0207] (3-1) The first substrate-side nitride semiconductor layer 25 of the first transistor 20 is formed by a stacked structure of a plurality of layers. The first substrate-side nitride semiconductor layer 25 is provided on the first metal layer 50A, and is formed by a stacked structure of a first buffer layer 25A containing Al and N and a first electron traveling layer 25B provided on the first buffer layer 25A and formed of a GaN layer.

[0208] According to this configuration, the breakdown voltage of the first transistor 20 can be improved as compared with the case where the first substrate-side nitride semiconductor layer 25 is formed of a single layer of, for example, a layer containing GaN.

[0209] (3-2) The second substrate-side nitride semiconductor layer 35 of the second transistor 30 is formed by a stacked structure of a plurality of layers. The second substrate-side nitride semiconductor layer 35 is provided on the second metal layer 50B, and is formed by a stacked structure of a second buffer layer 35A containing Al and N and a second electron traveling layer 35B provided on the second buffer layer 35A and formed of a GaN layer.

[0210] According to this configuration, the breakdown voltage of the second transistor 30 can be improved as compared with the case where the second substrate-side nitride semiconductor layer 35 is formed of a single layer of, for example, a layer containing GaN.

[0211] <Modification Example> Each of the above embodiments can be modified and implemented as follows. Also, each of the above embodiments and the following modification examples can be implemented in combination with each other within a technically consistent range.

[0212] · In the third embodiment, the configuration of the first buffer layer 25A of the first substrate-side nitride semiconductor layer 25 can be arbitrarily changed. In one example, as shown in FIG. 22, the first buffer layer 25A may have a superlattice structure. The superlattice structure may be, for example, a structure in which AlGaN layers and GaN layers are alternately stacked. The superlattice structure may be, for example, a structure in which AlN layers and AlGaN layers are alternately stacked. The superlattice structure may be, for example, a structure in which AlN layers and GaN layers are alternately stacked. Also, as shown in FIG. 22, the second buffer layer 35A of the second substrate-side nitride semiconductor layer 35 may also have a superlattice structure similar to the first buffer layer 25A.

[0213] · In the third embodiment, the thickness of the first buffer layer 25A can be arbitrarily changed. In one example, the thickness of the first buffer layer 25A may be equal to or greater than the thickness of the first electron traveling layer 25B. Also, the thickness of the second buffer layer 35A can be arbitrarily changed. In one example, the thickness of the second buffer layer 35A may be equal to or greater than the thickness of the second electron traveling layer 35B.

[0214] · In each embodiment, the bonding structure between the first metal layer 50A and the first nitride semiconductor layer 24 is not limited to intermolecular bonding and can be arbitrarily changed. · In each embodiment, the bonding structure between the second metal layer 50B and the second nitride semiconductor layer 34 is not limited to intermolecular bonding and can be arbitrarily changed.

[0215] · In each embodiment, the positions and numbers of the first opening 141 and the first connection portion 131 of the insulating layer 140 can be arbitrarily changed. The first connection portion 131 may be provided to connect a plurality of the first source wirings among the first source wirings 80A (8l to 83) and the first metal layer 50A. In one example, the first connection portion 131 may include a first connection portion that connects the first source wiring 81 and the first connection region 52A of the first metal layer 50A, and a first connection portion that connects the first source wiring 82 and the first connection region 52A of the first metal layer 50A. The first opening 141 of the insulating layer 140 is provided according to the number of the first connection portions 131. In this case, the first source wirings 81 and 82 are an example of the "first electrode".

[0216] Further, the first connection portion 131 connected to the first source wiring 82 may be connected to the protruding portion 51A of the first metal layer 50A that is different from the first connection region 52A. In one example, the first connection portion 131 connected to the first source wiring 82 may be connected to the protruding portion 51A that protrudes toward the first side surface 43 side of the first metal layer 50A. In this case, the protruding portion 51A that protrudes toward the first side surface 43 side is an example of the "first connection region". Further, the first connection portion 131 may be connected to the protruding portion 51A that protrudes toward the third side surface 45 side of the first metal layer 50A. In this case, the protruding portion 51A that protrudes toward the third side surface 45 side is an example of the "first connection region". And the Y-axis direction is an example of the "first direction".

[0217] Also, in each embodiment, the first opening 141 and the first connection portion 131 of the insulating layer 140 may be provided at positions different from those between the first transistor 20 and the second transistor 30 in the X-axis direction.

[0218] ·In each embodiment, the positions and the number of the second opening 142 and the second connection portion 132 of the insulating layer 140 can be arbitrarily changed. In one example, as shown in FIG. 23, the second connection portion 132 may be connected to the second source wiring 84 among the second source wirings 80B. In this case, the second connection portion 132 may be connected to the protruding portion 51B of the second metal layer 50B that protrudes toward the first metal layer 50A. Here, the protruding portion 51B that protrudes toward the first metal layer 50A becomes the second connection region 52B. Further, the second source wiring 84 is an example of the "second electrode".

[0219] Further, the second connection portion 132 may be provided to connect a plurality of the second source wirings among the second source wirings 80B (84 to 86) to the second metal layer 50B. In one example, the second connection portion 132 may include a second connection portion that connects the second source wiring 84 to the second connection region 52B of the second metal layer 50B, and a second connection portion that connects the second source wiring 86 to the second connection region 52B of the second metal layer 50B. The second opening 142 of the insulating layer 140 is provided according to the number of the second connection portions 132. In this case, the second source wirings 84 and 86 are an example of the "second electrode".

[0220] · In each embodiment, the second connection portion 132 may be omitted. In this case, the second opening 70BB may be omitted from the second gate wiring 70B. That is, the second outer peripheral gate wiring 76 and the second outer peripheral gate wiring 77 may be connected. Also in this case, the second metal layer 50B may not have the overhang portion 51B. That is, the second connection region 52B may be omitted from the second metal layer 50B.

[0221] · In each embodiment, the thickness of the first metal layer 50A can be arbitrarily changed. In one example, the thickness of the first metal layer 50A may be equal to the thickness of the first electrode 130. In one example, the thickness of the first metal layer 50A may be greater than the thickness of the first electrode 130. In one example, in the second embodiment, the thickness of the first metal layer 50A may be greater than the thickness of the substrate-side insulating layer 164 of the substrate 160. In one example, the thickness of the first metal layer 50A may be equal to the thickness of the substrate-side insulating layer 164.

[0222] · In each embodiment, the thickness of the second metal layer 50B can be arbitrarily changed. In one example, the thickness of the second metal layer 50B and the thickness of the first metal layer 50A may be different from each other. In one example, in the second embodiment, the thickness of the second metal layer 50B may be greater than the thickness of the substrate-side insulating layer 164 of the substrate 160. In one example, the thickness of the second metal layer 50B may be equal to the thickness of the substrate-side insulating layer 164.

[0223] · In each embodiment, the material constituting the first metal layer 50A is not limited to Al and Pt, and can be arbitrarily changed. · In each embodiment, the material constituting the second metal layer 50B is not limited to Al and Pt, and can be arbitrarily changed.

[0224] · In each embodiment, the thickness of the first nitride semiconductor layer 24 of the first transistor 20 and the thickness of the second nitride semiconductor layer 34 of the second transistor 30 can each be arbitrarily changed. In one example, the thickness of the first nitride semiconductor layer 24 and the thickness of the second nitride semiconductor layer 34 may be different from each other.

[0225] · In each embodiment, carbon as an impurity may be removed from the first substrate-side nitride semiconductor layer 25. Also, carbon as an impurity may be removed from the second substrate-side nitride semiconductor layer 35.

[0226] · In each embodiment, the number of first transistor cells in the first transistor 20 and the number of second transistor cells in the second transistor 30 can each be arbitrarily changed. In one example, the first transistor 20 may be constituted by one first transistor cell. In one example, the second transistor 30 may be constituted by one second transistor cell.

[0227] · In each embodiment, the second transistor 30 may be omitted. In this case, as shown in FIGS. 24 and 25, on the substrate 40, the first metal layer 50A is provided. On the first metal layer 50A, the first nitride semiconductor layer 24 is provided. The first metal layer 50A includes the protruding portion 51A as in the first embodiment. And the protruding portion 51A includes the first connection region 52A as in the first embodiment.

[0228] The structure of the first nitride semiconductor layer 24 is the same as that of the first embodiment. A plurality of first transistor cells TA to TC are provided in the first nitride semiconductor layer 24. As shown in FIG. 25, the structure of the first transistor 20 is the same as that of the first embodiment. The first transistor 20 is covered by the insulating layer 140 in the same manner as in the first embodiment.

[0229] Among the first source wirings 80A provided on the insulating layer 140, the first source wiring 81 is electrically connected to the first metal layer 50A. Therefore, the first source wiring 81 constitutes the first electrode 130. The insulating layer 140 is provided with a first opening 141 in the same manner as in the first embodiment. The first opening 141 penetrates the insulating layer 140 in the Z-axis direction and reaches the first connection region 52A. A first connection portion 131 is provided in the first opening 141. The first connection portion 131 is provided at a position overlapping both the first source wiring 81 and the first connection region 52A in plan view.

[0230] The manufacturing method of the nitride semiconductor device 10 shown in FIGS. 24 and 25 can be described in the same manner as the first embodiment with reference to FIGS. 9 to 19. The manufacturing method of the nitride semiconductor device 10 includes forming a nitride semiconductor layer 210 on a support substrate 200, preparing a substrate 40 having a first surface 41 with insulating properties, forming a metal layer 220 on the first surface 41, peeling the nitride semiconductor layer 210 from the support substrate 200, and bonding the nitride semiconductor layer 210 to the metal layer 220. By forming the metal layer 220, the first connection region 52A is formed in the metal layer 220 so as to protrude from the nitride semiconductor layer 210 in plan view.

[0231] Further, the method of manufacturing the nitride semiconductor device 10, similar to the first embodiment, includes forming a first transistor 20 having a first source electrode 22, a first drain electrode 23, and a first gate electrode 21, forming an insulating layer 140 so as to cover the first transistor 20, and forming a first electrode 130 on the insulating layer 140 so as to be electrically connected to the first source electrode 22. When forming the insulating layer 140, a first opening 141 is formed so as to penetrate the insulating layer 140 in the Z-axis direction and reach the first connection region 52A. Then, a first connection portion 131 is formed in the first opening 141 so as to be electrically connected to the first connection region 52A. Subsequently, the first electrode 130 is formed on the insulating layer 140 so as to contact the first connection portion 131. Through the above steps, the nitride semiconductor device 10 is manufactured.

[0232] One or more of the various examples described in this disclosure can be combined within a technically non - conflicting range. As used in this disclosure, the term "on" includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" may, in one embodiment, mean that the first element is directly disposed on the second element in contact with the second element, but in other embodiments, it is intended that the first element can be disposed above the second element without contacting the second element. That is, the term "on" does not exclude a structure in which other elements are formed between the first element and the second element.

[0233] The Z - axis direction used in this disclosure does not necessarily have to be the vertical direction and does not have to exactly coincide with the vertical direction. Thus, various structures according to this disclosure are not limited to the "up" and "down" in the Z - axis direction described in this disclosure being the "up" and "down" in the vertical direction. For example, the X - axis direction may be the vertical direction, or the Y - axis direction may be the vertical direction.

[0234] <Appendix> The technical idea that can be grasped from the present disclosure is described below. Note that, for the purpose of assisting understanding rather than for the purpose of limitation, the reference signs of the corresponding components in the above-described embodiments are attached to the components described in the appended claims. The reference signs are shown as examples for assisting understanding, and the components described in each appended claim should not be limited to the components indicated by the reference signs.

[0235] [Appendix 1] A substrate (40) including a first surface (41) having insulating properties, A first metal layer (50A) provided on the first surface (41), A first transistor (20) provided on the first metal layer (50A) and having a first nitride semiconductor layer (24), a first source electrode (22), a first drain electrode (23), and a first gate electrode (21), An insulating layer (140) covering the first transistor (20), A first electrode (130) provided on the insulating layer (140) and electrically connected to the first source electrode (22), Comprising, The first nitride semiconductor layer (24) is in contact with the first metal layer (50A), The first metal layer (50A) has a first connection region (52A) that protrudes in a first direction (X) from the first transistor (20) when viewed from above, The insulating layer (140) is provided with a first opening (141) that penetrates the insulating layer (140) in the thickness direction (Z) of the substrate (40) and reaches the first connection region (52A), A first connection portion (131) for electrically connecting the first electrode (130) and the first connection region (52A) is provided in the first opening (141) A nitride semiconductor device (10).

[0236] [Appendix 2] A second metal layer (50B) provided on the first surface (41) and separated from the first metal layer (50A), Provided on the second metal layer (50B), having a second nitride semiconductor layer (34), a second source electrode (32), a second drain electrode (33), and a second gate electrode (31), and covered by the insulating layer (140), a second transistor (30); comprising; The second transistor (30) is provided at a distance from the first transistor (20) in the first direction (X) by the first opening (141); The second drain electrode (33) is electrically connected to the first electrode (130) The nitride semiconductor device according to Supplementary Note 1.

[0237] [Supplementary Note 3] The first connection portion (131) is disposed between the first source electrode (22) and the second drain electrode (33) in the first direction (X); The nitride semiconductor device according to Supplementary Note 2.

[0238] [Supplementary Note 4] Provided on the insulating layer (140), comprising a second electrode (80B / 86) electrically connected to the second source electrode (32); The second metal layer (50B) has a second connection region (52B) protruding from the side opposite to the first transistor (20) among the second transistors (30) when viewed from above; The insulating layer (140) is provided with a second opening (142) penetrating the insulating layer (140) in the thickness direction (Z) and reaching the second connection region (52B); A second connection portion (132) for electrically connecting the second electrode (80B / 86) and the second connection region (52B) is provided in the second opening (142); The nitride semiconductor device according to Supplementary Note 2 or 3.

[0239] [Supplementary Note 5] Provided on the insulating layer (140), comprising a second electrode (80B / 84) electrically connected to the second source electrode (32); The second metal layer (50B) has a second connection region (52B) that protrudes toward the first transistor (20) among the second transistors (30) when viewed from above. A second connection portion (132) for electrically connecting the second electrode (80B / 84) and the second connection region (52B) is provided in the second opening (142). The nitride semiconductor device according to Supplementary Note 4.

[0240] [Supplementary Note 6] The first nitride semiconductor layer (24) is provided on the first metal layer (50A), and includes a first substrate-side nitride semiconductor layer (25) composed of a nitride semiconductor, a first electron supply layer (26) provided on the first substrate-side nitride semiconductor layer (25) and composed of a nitride semiconductor having a larger bandgap than the first substrate-side nitride semiconductor layer (25), and a first gate layer (27) partially provided on the first electron supply layer (26) and composed of a nitride semiconductor containing acceptor-type impurities. The first gate electrode (21) is disposed on the first gate layer (27), and the first source electrode (22) and the first drain electrode (23) are disposed to face each other with the first gate layer (27) interposed therebetween on the first electron supply layer (26). The nitride semiconductor device according to any one of Supplementary Notes 1 to 5. The nitride semiconductor device according to any one of Supplementary Notes 1 to 5.

[0241] [Supplementary Note 7] The second nitride semiconductor layer (34) is provided on the second metal layer (50B), and includes a second substrate-side nitride semiconductor layer (35) composed of a nitride semiconductor, a second electron supply layer (36) provided on the second substrate-side nitride semiconductor layer (35) and composed of a nitride semiconductor having a larger bandgap than the second substrate-side nitride semiconductor layer (35), A second gate layer (37) that is partially provided on the second electron supply layer (36) and is composed of a nitride semiconductor containing acceptor-type impurities; including; The second gate electrode (31) is disposed on the second gate layer (37); The second source electrode (32) and the second drain electrode (33) are disposed to face each other with the second gate layer (37) interposed therebetween on the second electron supply layer (36). The nitride semiconductor device according to any one of Appendices 2 to 5.

[0242] [Appendix 8] The thickness of the first metal layer (50A) is thinner than the thickness of the first electrode (130). The nitride semiconductor device according to any one of Appendices 1 to 7.

[0243] [Appendix 9] The first metal layer (50A) contains at least one of Al and Pt. The nitride semiconductor device according to any one of Appendices 1 to 8.

[0244] [Appendix 10] The first substrate-side nitride semiconductor layer (25) is composed of a single material. The nitride semiconductor device according to Appendix 6.

[0245] [Appendix 11] The first substrate-side nitride semiconductor layer (25) is composed of a laminated structure of a plurality of layers. The nitride semiconductor device according to Appendix 6.

[0246] [Appendix 12] The first substrate-side nitride semiconductor layer (25) is provided on the first metal layer (50A) and is composed of a laminated structure of a first buffer layer (25A) containing Al and N and a first electron traveling layer (25B) provided on the first buffer layer (25A) and composed of a GaN layer. The nitride semiconductor device according to Appendix 11.

[0247] [Supplementary Note 13] The thickness of the first buffer layer (25A) is thinner than the thickness of the first electron traveling layer (25B). The nitride semiconductor device according to Supplementary Note 12.

[0248] [Supplementary Note 14] A part of the portion of the first substrate-side nitride semiconductor layer (25) closer to the first metal layer (50A) than the surface layer portion contains carbon with a concentration of 1×10 19 cm -3 or more as an impurity. The nitride semiconductor device according to Supplementary Note 6.

[0249] [Supplementary Note 15] The substrate (160) is an Si substrate (163), and a substrate-side insulating layer (164) composed of SiO2 provided on the Si substrate (163), and includes the substrate-side insulating layer (164) includes the first surface (161). The nitride semiconductor device according to any one of Supplementary Notes 1 to 14.

[0250] [Supplementary Note 16] The thickness of the first metal layer (50A) is thinner than the thickness of the substrate-side insulating layer (164). The nitride semiconductor device according to Supplementary Note 15.

[0251] [Supplementary Note 17] The substrate (40) is a sapphire substrate or a semi-insulating SiC substrate. The nitride semiconductor device according to any one of Supplementary Notes 1 to 14.

[0252] [Supplementary Note 18] The thickness of the second metal layer (50B) is equal to the thickness of the first metal layer (50A). The nitride semiconductor device according to any one of Supplementary Notes 2 to 5.

[0253] [Supplementary Note 19] The thickness of the second nitride semiconductor layer (35) is equal to the thickness of the first nitride semiconductor layer (25). The nitride semiconductor device according to any one of Appendices 2 to 5.

[0254] [Appendix 20] Comprising a third electrode (90A) provided on the insulating layer (140) and electrically connected to the first drain electrode (23). The third electrode (90A) is insulated from the first metal layer (50A). The nitride semiconductor device according to any one of Appendices 1 to 19.

[0255] [Appendix 21] The thickness of the second metal layer (50B) is thinner than the thickness of the first electrode (130). The nitride semiconductor device according to any one of Appendices 2 to 5.

[0256] [Appendix 22] The second metal layer (50B) contains at least one of Al and Pt. The nitride semiconductor device according to any one of Appendices 2 to 5.

[0257] [Appendix 23] The second substrate-side nitride semiconductor layer (35) is composed of a single material. The nitride semiconductor device according to Appendix 7.

[0258] [Appendix 24] The second substrate-side nitride semiconductor layer (35) is composed of a laminated structure of multiple layers. The nitride semiconductor device according to Appendix 7.

[0259] [Appendix 25] The second substrate-side nitride semiconductor layer (35) is provided on the second metal layer (50B), and is composed of a laminated structure of a second buffer layer (35A) containing Al and N and a second electron traveling layer (35B) provided on the second buffer layer (35A) and composed of a GaN layer. The nitride semiconductor device according to Appendix 24.

[0260] [Appendix 26] The thickness of the second buffer layer (35A) is thinner than the thickness of the second electron traveling layer (35B). The nitride semiconductor device according to Appendix 25.

[0261] [Appendix 27] A part of the portion of the second substrate-side nitride semiconductor layer (35) closer to the second metal layer (50B) than the surface layer portion has a carbon concentration of 1×10 19 cm -3 or more and contains carbon. The nitride semiconductor device according to Appendix 7.

[0262] [Appendix 28] The substrate (160) is an Si substrate (163), a substrate-side insulating layer (164) composed of SiO2 provided on the Si substrate (163), and includes the substrate-side insulating layer (164) includes the first surface (161), The thickness of the second metal layer (50B) is thinner than the thickness of the substrate-side insulating layer (164). The nitride semiconductor device according to any one of Appendices 2 to 5.

[0263] [Appendix 29] A third electrode (90B) is provided on the insulating layer (140) and is electrically connected to the first drain electrode (53), the third electrode (90B) is insulated from both the first metal layer (50A) and the second metal layer (50B). The nitride semiconductor device according to any one of Appendices 2 to 5.

[0264] [Appendix 30] The first nitride semiconductor layer (24) and the first metal layer (50A) are joined by an intermolecular bond. The nitride semiconductor device according to any one of Appendices 1 to 29.

[0265] [Appended Note 31] The second nitride semiconductor layer (34) and the second metal layer (50B) are joined by an intermolecular bond. The nitride semiconductor device according to any one of Appended Notes 2 to 5.

[0266] [Appended Note 32] The first connection portion (131) is one in number. The nitride semiconductor device according to any one of Appended Notes 1 to 31.

[0267] [Appended Note 33] The second connection portion (132) is one in number. The nitride semiconductor device according to Appended Note 4.

[0268] [Appended Note 34] A substrate (40) including a first surface (41) having insulating properties, A first metal layer (50A) provided on the first surface (41), A second metal layer (50B) provided on the first surface (41) and arranged spaced apart from the first metal layer (50A) in a first direction (X), A first transistor (20) provided on the first metal layer (50A) and having a first nitride semiconductor layer (24), a first source electrode (22), a first drain electrode (23), and a first gate electrode (21), A second transistor (30) provided on the second metal layer (50B) and having a second nitride semiconductor layer (34), a second source electrode (32), a second drain electrode (33), and a second gate electrode (31), An insulating layer (140) covering both the first transistor (20) and the second transistor (30), A first electrode (130) provided on the insulating layer (140) and electrically connected to both the first source electrode (22) and the second drain electrode (33), A second electrode (80B / 86) provided on the insulating layer (140) and electrically connected to the second source electrode (32), comprising The first nitride semiconductor layer (24) is in contact with the first metal layer (50A), The second nitride semiconductor layer (34) is in contact with the second metal layer (50B), The first metal layer (50A) has a first connection region (52A) that protrudes from the first transistor (20) when viewed from above, The second metal layer (50B) has a second connection region (52B) that protrudes from the second transistor (30) when viewed from above, In the insulating layer (140), a first opening (141) that penetrates the insulating layer (140) in the thickness direction (Z) of the substrate (40) and reaches the first connection region (52A), a second opening (142) that penetrates the insulating layer (140) in the thickness direction (Z) and reaches the second connection region (52B), are provided, In the first opening (141), a first connection portion (131) that electrically connects the first electrode (130) and the first connection region (52A) is provided, In the second opening (142), a second connection portion (132) that electrically connects the second electrode (80B) and the second connection region (52B) is provided Nitride semiconductor device (10).

[0269] [Appendix 35] Forming a nitride semiconductor layer (210) on a support substrate (200), Preparing a substrate (40) having an insulating first surface (41), Forming a metal layer (220) on the first surface (41), Peeling the nitride semiconductor layer (210) from the support substrate (200), Bonding the nitride semiconductor layer (210) to the metal layer (220), Forming a first transistor (20) having a first source electrode (22), a first drain electrode (23), and a first gate electrode (21), Forming an insulating layer (140) so as to cover the first transistor (20); Forming a first electrode (130) on the insulating layer (140) so as to be electrically connected to the first source electrode (22); comprising; By forming the metal layer (220), a first connection region (52A) is formed in the metal layer (220) so as to protrude from the nitride semiconductor layer (210) when viewed from above; By forming the insulating layer (140), a first opening (141) is formed so as to penetrate the insulating layer (140) in the thickness direction (Z) of the substrate (40) and reach the first connection region (52A); including forming a first connection portion (131) in the first opening (141) so as to be electrically connected to the first connection region (52A); By forming the first electrode (130), the first electrode (130) is formed on the insulating layer (140) so as to contact the first connection portion (131); A method for manufacturing a nitride semiconductor device (10).

[0270] [Appendix 36] Forming a nitride semiconductor layer (210) on a support substrate (200); Preparing a substrate (40) having a first surface (41) with insulating properties; Forming a metal layer (220) on the first surface (41); Peeling the nitride semiconductor layer (210) from the support substrate (200); Bonding the nitride semiconductor layer (210) to the metal layer (220); Forming a first source electrode (22), a first drain electrode (23), and a first gate electrode (21), and a second source electrode (32), a second drain electrode (33), and a second gate electrode (31) in the nitride semiconductor layer (210); Forming a first nitride semiconductor layer (24) and a second nitride semiconductor layer (34) spaced apart from the first nitride semiconductor layer (24) from the nitride semiconductor layer (210); Forming an insulating layer (140) so as to cover a first transistor (20) including the first source electrode (22), the first drain electrode (23), the first gate electrode (21), and the first nitride semiconductor layer (24), and a second transistor (30) including the second source electrode (32), the second drain electrode (33), the second gate electrode (31), and the second nitride semiconductor layer (34). Forming a first electrode (130) on the insulating layer (140) so as to be electrically connected to both the first source electrode (22) and the second drain electrode (33). Comprising Forming the metal layer (220) includes forming, from the metal layer (220), a first metal layer (50A) to which the first nitride semiconductor layer (24) is joined, and a second metal layer (50B) which is disposed at a distance from the first metal layer (50A) and to which the second nitride semiconductor layer (34) is joined. When forming the metal layer (220), a first connection region (52A) is formed in the first metal layer (50A) so as to protrude from the first transistor (20) when viewed from above. When forming the insulating layer (140), a first opening (141) is formed so as to penetrate the insulating layer (140) in the thickness direction (Z) of the substrate (40) and reach the first connection region (52A). Forming a first connection portion (131) in the first opening (141) so as to be electrically connected to the first connection region (52A). When forming the first electrode (130), the first electrode (130) is formed on the insulating layer (140) so as to be in contact with the first connection portion (131). A method for manufacturing a nitride semiconductor device (10).

[0271] [Appendix 37] When forming the metal layer (220), a second connection region (52B) is formed in the second metal layer (50B) so as to protrude from the second transistor (30) when viewed from above. Forming a second electrode (80B) on the insulating layer (140) so as to be electrically connected to the second source electrode (32); Forming a second opening (142) that penetrates the insulating layer (140) in the thickness direction (Z) of the substrate (40) and reaches the second connection region (52B); Forming a second connection portion (132) in the second opening (142) so as to be electrically connected to the second connection region (52B); including; In forming the second electrode (80B), the second electrode (80B) is formed on the insulating layer (140) so as to contact the second connection portion (132). The method for manufacturing a nitride semiconductor device according to Supplementary Note 36.

[0272] The above description is merely illustrative. Those skilled in the art will recognize that there are many more possible combinations and substitutions other than the components and methods (manufacturing processes) listed for the purpose of explaining the technology of the present disclosure. The present disclosure is intended to encompass all alternatives, modifications, and variations included within the scope of the present disclosure, including the claims.

Explanation of Reference Numerals

[0273] 10…Nitride semiconductor device 11…Chip body 11A…Chip upper surface 11B…Chip lower surface 11C~11F…First to fourth chip side surfaces 12A…First gate pad 12B…Second gate pad 13A…First source pad 13B…Second source pad 14A…First drain pad 14B…Second drain pad 20…First transistor 21…First gate electrode 22…First source electrode 22F…First field plate electrode 23…First drain electrode 24…First nitride semiconductor layer 25…First substrate-side nitride semiconductor layer 25A…First buffer layer 25B…First electron traveling layer 26…First electron supply layer 26A…Upper surface 27…First gate layer 27A…Upper surface 28…First passivation layer 28A…First source opening 28B…First drain opening 29…2DEG 30…Second transistor 31…Second gate electrode 32…Second source electrode 33…Second drain electrode 34…Second nitride semiconductor layer 35…Second substrate-side nitride semiconductor layer 35A…Second buffer layer 35B…Second electron traveling layer 36…Second electron supply layer 36A…Upper surface 37…Second gate layer 37A…Upper surface 38…Second passivation layer 38A…Second source opening 38B…Second drain opening 39…2DEG 40…Substrate 41…First surface 42…Second surface 43~46…First to fourth side surfaces 50A…First metal layer 50B…Second metal layer 51A…First overhang portion 51B…Second overhang portion 52A…First connection region 52B…Second connection region 70A…First gate wiring 70B…Second gate wiring 70AA…Opening 70BA…First opening 70BB…Second opening 71, 72… The first peripheral gate wiring 73, 74… The first intermediate gate wiring 75~77… The second peripheral gate wiring 78, 79… The second intermediate gate wiring 80A… The first source wiring 80B… The second source wiring 81~83… The first source wiring 84~86… The second source wiring 90A… The first drain wiring 90B… The second drain wiring 91~93… The first drain wiring 94~96… The second drain wiring 101, 102… The first peripheral gate via 103, 104… The first intermediate gate via 105… The first source via 106… The first drain via 111, 112… The second peripheral gate via 113, 114… The second intermediate gate via 115… The second source via 116… The second drain via 130… The first electrode 131… The first connection part 132… The second connection part 140… The insulating layer 141… The first opening 142… The second opening 143~146… The electrode opening 151… The first source connection part 152… The first drain connection part 153… The second source connection part 154… The second drain connection part 160… The substrate 161… The first surface 162… The second surface 163… The Si substrate 164… The substrate-side insulating layer 200… The support substrate (QST) 201… The core 202… The sealing layer 210… The nitride semiconductor layer 211… The substrate-side nitride semiconductor layer 212... Electron supply layer 213... Nitride semiconductor layer 220... Metal layer 230... Gate electrode layer 240... Wiring layer TA~TC... First transistor cell TD~TF... Second transistor cell

Claims

1. A substrate including a first surface having insulation properties, a first metal layer provided on the first surface, a first transistor provided on the first metal layer and having a first nitride semiconductor layer, a first source electrode, a first drain electrode, and a first gate electrode, an insulating layer covering the first transistor, a first electrode provided on the insulating layer and electrically connected to the first source electrode, comprising: the first nitride semiconductor layer is in contact with the first metal layer, the first metal layer has a first connection region protruding in a first direction from the first transistor when viewed from above, the insulating layer is provided with a first opening penetrating the insulating layer in the thickness direction of the substrate and reaching the first connection region, a first connection portion for electrically connecting the first electrode and the first connection region is provided in the first opening A nitride semiconductor device.

2. a second metal layer provided on the first surface and spaced apart from the first metal layer, a second transistor provided on the second metal layer and having a second nitride semiconductor layer, a second source electrode, a second drain electrode, and a second gate electrode, and covered by the insulating layer, comprising: the second transistor is provided at a distance from the first transistor in the first direction by the first opening, the second drain electrode is electrically connected to the first electrode The nitride semiconductor device according to claim 1.

3. the first connection portion is disposed between the first source electrode and the second drain electrode in the first direction The nitride semiconductor device according to claim 2.

4. comprising a second electrode provided on the insulating layer and electrically connected to the second source electrode, the second metal layer has a second connection region protruding from the side of the second transistor opposite to the first transistor when viewed from above, the insulating layer is provided with a second opening penetrating the insulating layer in the thickness direction and reaching the second connection region, a second connection portion for electrically connecting the second electrode and the second connection region is provided in the second opening The nitride semiconductor device according to claim 2.

5. comprising a second electrode provided on the insulating layer and electrically connected to the second source electrode, the second metal layer has a second connection region protruding toward the first transistor among the second transistors when viewed from above, The insulating layer is provided with a second opening that penetrates the insulating layer in the thickness direction and reaches the second connection region. A second connection portion for electrically connecting the second electrode and the second connection region is provided in the second opening. The nitride semiconductor device according to claim 2.

6. The first nitride semiconductor layer includes a first substrate-side nitride semiconductor layer provided on the first metal layer and composed of a nitride semiconductor, and a first electron supply layer provided on the first substrate-side nitride semiconductor layer and composed of a nitride semiconductor having a larger bandgap than the first substrate-side nitride semiconductor layer, and a first gate layer partially provided on the first electron supply layer and composed of a nitride semiconductor containing acceptor-type impurities. The first gate electrode is disposed on the first gate layer. The first source electrode and the first drain electrode are disposed opposite to each other with the first gate layer interposed therebetween on the first electron supply layer. The nitride semiconductor device according to claim 1.

7. The second nitride semiconductor layer includes a second substrate-side nitride semiconductor layer provided on the second metal layer and composed of a nitride semiconductor, and a second electron supply layer provided on the second substrate-side nitride semiconductor layer and composed of a nitride semiconductor having a larger bandgap than the second substrate-side nitride semiconductor layer, and a second gate layer partially provided on the second electron supply layer and composed of a nitride semiconductor containing acceptor-type impurities. The second gate electrode is disposed on the second gate layer. The second source electrode and the second drain electrode are disposed opposite to each other with the second gate layer interposed therebetween on the second electron supply layer. The nitride semiconductor device according to claim 2.

8. The thickness of the first metal layer is thinner than the thickness of the first electrode. The nitride semiconductor device according to claim 1.

9. The first metal layer contains at least one of Al and Pt. The nitride semiconductor device according to claim 1.

10. The first substrate-side nitride semiconductor layer is composed of a single material. The nitride semiconductor device according to claim 6.

11. The first substrate-side nitride semiconductor layer is composed of a laminated structure of a plurality of layers. The nitride semiconductor device according to claim 6.

12. ​ ​ The nitride semiconductor layer on the first substrate side is provided on the first metal layer and is composed of a stacked structure including a first buffer layer containing Al and N and a first electron traveling layer composed of a GaN layer provided on the first buffer layer. The nitride semiconductor device according to claim 11.

13. The thickness of the first buffer layer is thinner than the thickness of the first electron traveling layer. The nitride semiconductor device according to claim 12.

14. A portion of the first substrate-side nitride semiconductor layer closer to the first metal layer than the surface layer portion has an impurity concentration of 1×10 １９ cm －３ Contains more than The nitride semiconductor device according to claim 6.

15. The substrate includes a Si substrate The SiO provided on the Si substrate ２ and the substrate-side insulating layer formed thereby and the insulating layer on the substrate side includes the first surface. The nitride semiconductor device according to claim 1.

16. The thickness of the first metal layer is thinner than the thickness of the insulating layer on the substrate side. The nitride semiconductor device according to claim 15.

17. The substrate is a sapphire substrate or a semi-insulating SiC substrate. The nitride semiconductor device according to claim 1.

18. The thickness of the second metal layer is equal to the thickness of the first metal layer. The nitride semiconductor device according to claim 2.

19. The thickness of the second nitride semiconductor layer is equal to the thickness of the first nitride semiconductor layer. The nitride semiconductor device according to claim 2.

20. It includes a third electrode provided on the insulating layer and electrically connected to the first drain electrode, and the third electrode is insulated from the first metal layer. The nitride semiconductor device according to any one of claims 1 to 19.

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