Semiconductor packaging and method for manufacturing semiconductor packaging

Abstract

To provide semiconductor packaging and a method for manufacturing a semiconductor packaging.SOLUTION: A half-groove portion 125 is provided between a first surface 121 and a side surface 123 of an encapsulation layer 120, and attached to a carrier by the first surface 121, whereby the half-groove portion 125 is formed as a shielded space between the encapsulation layer 120 and the carrier. Next, a heat dissipation layer 130 is formed on the second surface 122 of the encapsulation layer 120, thereby constructing a semiconductor packaging 100B. When forming the heat dissipation layer 130, the shielded space prevents metal residues from accumulating in a gap between the first surface 121 and the carrier, thereby preventing contamination of the semiconductor packaging 100B.SELECTED DRAWING: Figure 9A

Description

Technical Field

[0001] The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package in which a heat dissipation layer is formed on the surface of a sealing layer and a method of manufacturing the same.

Background Art

[0002] Conventional methods of manufacturing semiconductor packages involve attaching a plurality of encapsulants 10A to a carrier 20, where each encapsulant 10A has a die 11 and a sealing layer 12 (see FIG. 10). Each encapsulant 10A is attached to the carrier 20 by the active surface 11a of the die 11 and the first surface 12a of the sealing layer 12, and a heat dissipation layer 13 is formed on the second surface 12b of the sealing layer 12 by a sputtering process to constitute a semiconductor package 10.

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, in the conventional technology described above, when the heat dissipation layer 13 is formed on the second surface 12b by a sputtering process, a gap 30 is generated between the sealing layer 12 and the carrier 20 due to the physical properties of the die 11, the sealing layer 12, and the carrier 20 and / or the process environment (e.g., temperature). In the sputtering process, when scattered target atoms accumulate in the carrier 20 and the gap 30 to form metal residues 40, the metal residues 40 contaminate the die 11, affecting the quality and yield of the semiconductor package 10.

[0004] Therefore, the inventor of the present invention considered that the above-mentioned drawbacks could be improved, and as a result of intensive studies, reached the proposal of the present invention that rationally and effectively improves the problems.

[0005] The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor packaging and a method for manufacturing the same. That is, when forming the heat dissipation layer, the semi-grooves provided in the sealing layer prevent metal residues from accumulating in the gap between the sealing layer and the carrier, so as not to affect the quality and yield of the semiconductor packaging.

Means for Solving the Problems

[0006] To achieve the above object, a semiconductor packaging according to an aspect of the present invention includes a die, a sealing layer, and a heat dissipation layer. The sealing layer covers the die, and the sealing layer has a first surface, a second surface, a side surface, and a semi-groove. The semi-groove surrounds the first surface and is located between the first surface and the side surface. The semi-groove has a first edge adjacent to the first surface and a second edge adjacent to the side surface, and the heat dissipation layer covers the second surface.

[0007] Further, a method for manufacturing a semiconductor packaging according to another aspect of the present invention first attaches a plurality of package units to a third carrier. Each of the package units has a die and a sealing layer. The sealing layer covers the die, and the sealing layer has a first surface, a second surface, a side surface, and a semi-groove. The semi-groove surrounds the first surface and is located between the first surface and the side surface. The semi-groove has a first edge adjacent to the first surface and a second edge adjacent to the side surface. Each of the package units is attached to the third carrier by the first surface of the sealing layer, and the semi-groove is formed as a shielding space located between the sealing layer and the third carrier. Next, a heat dissipation layer is formed on the second surface to constitute a plurality of semiconductor packagings.

[0008] When forming the heat dissipation layer on the second surface of the sealing layer, the shielding space formed by the semi-groove portion that surrounds the first surface and is located between the first surface and the side surface prevents metal residues from accumulating in the gap between the first surface and the third carrier, thus preventing contamination of the die.

[0009] Other features of the present invention will be clarified by the description in this specification and the accompanying drawings.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described in detail. However, the present invention is not limited thereto, and various modifications are possible within the described scope. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention.

[0012] As shown in FIGS. 9A to 9D, the semiconductor packaging 100B includes a die 110, a sealing layer 120, and a heat dissipation layer 130. Preferably, the semiconductor packaging 100B further includes at least one electronic element 150 (for example, another die or a passive element). The die 110 has an active surface 111 and a back surface 112. The sealing layer 120 covers the die 110 and the electronic element 150. The sealing layer 120 has a first surface 121, a second surface 122, a side surface 123, and a semi-groove portion 125. The active surface 111 is exposed on the first surface 121.

[0013] In other embodiments, a redistribution layer is provided on the active surface 111, or redistribution layers are provided on the active surface 111 and the first surface 121. The semi-groove portion 125 surrounds the first surface 121 and is located between the first surface 121 and the side surface 123. The semi-groove portion 125 has a first edge end 124b adjacent to the first surface 121 and a second edge end 124c adjacent to the side surface 123. The heat dissipation layer 130 covers the second surface 122. Preferably, the back surface 112 is exposed from the second surface 122, the heat dissipation layer 130 covers the back surface 112, and the heat dissipation layer 130 covers the side surface 123.

[0014] Referring to FIGS. 9A to 9D again, a first virtual line X extending along the first surface 121 passes through the first edge end 124b, and a second virtual line Y extending along the side surface 123 passes through the second edge end 124c. A first distance S1 between the first edge end 124b and the second virtual line Y is 3 μm or more and 10 μm or less (3 μm ≤ S1 ≤ 10 μm). A second distance S2 between the second edge end 124c and the first virtual line X is 5 μm or more and 120 μm or less (5 μm ≤ S2 ≤ 120 μm). A ratio (S2 / S1) of the second distance S2 to the first distance S1 is 0.5 or more and 40 or less (0.5 ≤ S2 / S1 ≤ 40).

[0015] The semiconductor packaging 100B shown in FIGS. 9A to 9D differs in the cross-sectional shape of the semi-groove 125. The semi-groove 125 has a groove side surface 124d and a groove bottom surface 124e. The groove side surface 124d is an arc surface. The groove side surface 124d is connected to the groove bottom surface 124e, and the second edge end 124c is located on the groove bottom surface 124e (see FIG. 9A). In this embodiment, the groove side surface 124d is connected to the first surface 121, and the first edge end 124b is located on the groove side surface 124d.

[0016] Refer to FIGS. 9B to 9C. The groove side surface 124d is connected to the first surface 121 and the groove bottom surface 124e. It differs from FIG. 9A in that there is an included angle A between the groove side surface 124d and the groove bottom surface 124e, and the included angle A is 90 degrees or more. Referring to FIG. 9B, the groove side surface 124d is perpendicular to the groove bottom surface 124e, and the included angle A is 90 degrees. Referring to FIG. 9C, the included angle A is greater than 90 degrees.

[0017] In such a case, refer to FIG. 9D. The semi-groove 125 does not have a groove bottom surface 124e. The groove side surface 124d is an inclined surface. The groove side surface 124d is connected to the first surface 121 and the side surface 123. The first edge end 124b and the second edge end 124c are located on the groove side surface 124d, which is different from FIGS. 9A to 9C.

[0018] FIGS. 1 to 8D are cross-sectional views showing a method of manufacturing the semiconductor packaging 100B according to an embodiment of the present invention. In such a case, as shown in FIG. 1, first, a packaging process is executed, and the active surfaces 111 of a plurality of dies 110 are attached to the first carrier T1. In this embodiment, a plurality of electronic elements 150 are attached to the first carrier T1.

[0019] Next, each die 110 and each electronic element 150 are covered with a sealing layer 120 to form a sealing body 100 (see FIG. 2). The sealing body 100 includes a plurality of unseparated package units 100A, and each package unit 100A has a die 110, an electronic element 150, and a sealing layer 120.

[0020] In such a case, as shown in FIG. 3, in this embodiment, after the encapsulation layer 120 covers each die 110 and each electronic element 150, the encapsulation layer 120 is thinned. The thinned encapsulation layer 120 covers or exposes the back surface 112 of each die 110. In other embodiments, the encapsulation layer 120 and each die 110 are thinned simultaneously to expose the back surface 112.

[0021] In such a case, as shown in FIG. 4, next, the encapsulation body 100 is attached to the second carrier T2, the encapsulation body 100 is attached to the second carrier T2 by the second surface 122 of the encapsulation layer 120, and the first carrier T1 is removed to expose the first surface 121 and the active surface 111.

[0022] Refer to FIGS. 5A to 5D. A groove portion 124 is formed on the first surface 121. The groove portion 124 surrounds the first surface 121, the groove portion 124 has a bottom surface 124a and two opposing first edge ends 124b, and each first edge end 124b is adjacent to the first surface 121. FIGS. 5A to 5D are different in the cross-sectional shape of the groove portion 124.

[0023] Refer to FIG. 5A. The groove portion 124 further has two opposing groove side surfaces 124d, each groove side surface 124d is an arc surface, and each groove side surface 124d is connected to the bottom surface 124a. In this embodiment, each groove side surface 124d is connected to the first surface 121, and each first edge end 124b is located on each groove side surface 124d.

[0024] Subsequently, refer to FIGS. 5B to 5D. There is an included angle A between each groove side surface 124d and the bottom surface 124a, and it is different from FIG. 5A in that the included angle A is 90 degrees or more. Referring to FIG. 5B, each groove side surface 124d is perpendicular to the bottom surface 124a, and the included angle A is 90 degrees. Referring to FIGS. 5C and 5D, the included angle A is greater than 90 degrees.

[0025] Next, refer to FIGS. 6A to 6D. The sealing body 100 is cut along the bottom surface 124a of the groove portion 124, and each package unit 100A is separated to expose the side surface 123 of the sealing layer 120, and the groove portion 124 is made into a semi-groove portion 125. The semi-groove portion 125 surrounds the first surface 121 and is located between the first surface 121 and the side surface 123. The semi-groove portion 125 has a first edge end 124b adjacent to the first surface 121 and a second edge end 124c adjacent to the side surface 123.

[0026] Next, refer to FIGS. 6A to 6D. A first virtual line X extending along the first surface 121 passes through the first edge end 124b, and a second virtual line Y extending along the side surface 123 passes through the second edge end 124c. A first distance S1 between the first edge end 124b and the second virtual line Y is 3 μm or more and 10 μm or less, a second distance S2 between the second edge end 124c and the first virtual line X is 5 μm or more and 120 μm or less, and a ratio (S2 / S1) of the second distance S2 to the first distance S1 is 0.5 or more and 40 or less. FIGS. 6A to 6D are different in the cross-sectional shape of the semi-groove portion 125.

[0027] Refer to FIG. 6A. After separating each package unit 100A, the bottom surface 124a is made into two groove bottom surfaces 124e. The second edge end 124c is located on the groove bottom surface 124e, the groove side surface 124d is an arc surface and is connected to the groove bottom surface 124e, and the groove side surface 124d is located between the groove bottom surface 124e and the first surface 121. In this embodiment, the groove side surface 124d is connected to the first surface 121 and the groove bottom surface 124e, and the first edge end 124b is located on the groove side surface 124d.

[0028] Refer to FIGS. 6B and 6C. It is different from FIG. 6A in that there is an included angle A between the groove side surface 124d and the groove bottom surface 124e, and the included angle A is 90 degrees or more. Referring to FIG. 6B, the groove side surface 124d is perpendicular to the groove bottom surface 124e, and the included angle A is 90 degrees. Referring to FIG. 6C, the included angle A is more than 90 degrees.

[0029] Refer to FIG. 6D. When each package unit 100A is separated, the bottom surface 124a is removed, and the groove side surface 124d remains in the semi-groove portion 125. Different from FIGS. 6B and 6C, the groove side surface 124d is connected to the first surface 121 and the side surface 123, and the first edge 124b and the second edge 124c are located on the groove side surface 124d.

[0030] Subsequently, refer to FIGS. 7A to 7D. Each package unit 100A is attached to the third carrier T3. Each package unit 100A is attached to the third carrier T3 by the first surface 121, and the semi-groove portion 125 is made into a shielding space B located between the sealing layer 120 and the third carrier T3. There is a gap G between adjacent package units 100A, and the gap G is 20 μm or more and 1 mm or less (20 μm ≤ G ≤ 1 mm). Next, the second carrier T2 is removed to expose the second surface 122. In other embodiments, the back surface 112 is exposed on the second surface 122. Preferably, the first carrier T1, the second carrier T2, and the third carrier T3 are selected from adhesive tapes, glass substrates, or silicon substrates.

[0031] Subsequently, refer to FIGS. 8A to 8D. A plurality of semiconductor packagings 100B are formed by forming a heat dissipation layer 130 on the second surface 122. The heat dissipation layer 130 covers the second surface 122. Preferably, the heat dissipation layer 130 covers the side surface 123. When the back surface 112 of the die 110 is exposed on the second surface 122, the heat dissipation layer 130 covers the back surface 112. The heat dissipation layer 130 is formed by a sputtering process, and the shielding space B located between the sealing layer 120 and the third carrier T3 prevents the situation where the scattered target atoms accumulate in the gap between the third carrier T3 and the first surface 121.

[0032] Subsequently, refer to FIGS. 9A to 9D. The apparatus executes a pick and place process to detach each semiconductor packaging 100B from the third carrier T3.

[0033] Before separating each package unit 100A, a groove portion 124 surrounding the first surface 121 is formed on the first surface 121. After separating each package unit 100A, the groove portion 124 is made into a semi-groove portion 125 that surrounds the first surface 121 and is located between the first surface 121 and the side surface 123. The shielding space B formed by the semi-groove portion 125 is located between the sealing layer 120 and the third carrier T3. When forming the heat dissipation layer 130, the scattered target atoms do not accumulate in the gap between the third carrier T3 and the first surface 121, and metal residues that contaminate the die 110 are not formed.

[0034] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

Explanation of Reference Numerals

[0035] 10 Semiconductor Packaging 10A Sealing Body 11 Die 11a Active Surface 12 Sealing Layer 12a First Surface 12b Second Surface 13 Heat Dissipation Layer 20 Carrier 30 Gap 40 Metal Residue 100 Sealing Body 100A Package Unit 100B Semiconductor Packaging 110 Die 111 Active Surface 112 Back Surface 120 Sealing Layer 121 First Surface 122 Second Surface 123 Side Surface 124 Groove Portion 124a Bottom Surface 124b First edge end 124c Second edge end 124d Groove side surface 124e Groove bottom surface 125 Half-groove part 130 Heat dissipation layer 150 Electronic element A Included angle B Shielding space G Spacing S1 First distance S2 Second distance T1 First carrier T2 Second carrier T3 Third carrier X First virtual line Y Second virtual line

Claims

1. A die, A sealing layer covering the die, having a first surface, a second surface, a side surface, and a semi-groove portion, wherein the semi-groove portion surrounds the first surface and is located between the first surface and the side surface, and the semi-groove portion has a first edge adjacent to the first surface and a second edge adjacent to the side surface; A heat dissipation layer covering the second surface, characterized in that the semiconductor packaging comprises the above.

2. The semiconductor packaging according to claim 1, wherein the back surface of the die is exposed from the second surface, and the heat dissipation layer covers the back surface.

3. A first virtual line extending along the first surface passes through the first edge, a second virtual line extending along the side surface passes through the second edge, a first distance between the first edge and the second virtual line is 3 μm or more and 10 μm or less, a second distance between the second edge and the first virtual line is 5 μm or more and 120 μm or less, and a ratio of the first distance to the second distance is 0.5 or more and 40 or less. The semiconductor packaging according to claim 1 is characterized by the above.

4. The semiconductor packaging according to claim 1, wherein the semi-groove portion further has a groove side surface and a groove bottom surface, the groove side surface is an arc surface, the groove side surface is connected to the groove bottom surface, and the second edge is located on the groove bottom surface.

5. The semiconductor packaging according to claim 1, wherein the semi-groove portion further has a groove side surface and a groove bottom surface, the groove side surface is connected to the first surface and the groove bottom surface, there is an included angle between the groove side surface and the groove bottom surface, the included angle is 90 degrees or more, the first edge is located on the groove side surface, and the second edge is located on the groove bottom surface.

6. The semiconductor packaging according to claim 1, wherein the semi-groove portion further has a groove side surface, the groove side surface is an inclined surface, the groove side surface is connected to the first surface and the side surface, and the first edge and the second edge are located on the groove side surface.

7. Attaching a plurality of package units having dies and a sealing layer to a third carrier, wherein the sealing layer covers the die, the sealing layer has a first surface, a second surface, a side surface, and a semi-groove, the semi-groove surrounds the first surface and is located between the first surface and the side surface, the semi-groove has a first edge adjacent to the first surface and a second edge adjacent to the side surface, attaching the package unit to the third carrier by the first surface of the sealing layer, and making the semi-groove a shielding space located between the sealing layer and the third carrier; Forming a heat dissipation layer on the second surface to constitute a plurality of semiconductor packagings. A method for manufacturing a semiconductor packaging, characterized by including these steps.

8. Attaching the active surfaces of a plurality of dies to a first carrier, forming a sealing body including a plurality of unseparated package units by covering each die with the sealing layer, attaching the sealing body to a second carrier by the second surface of the sealing layer, removing the first carrier to expose the first surface of the sealing layer, forming a groove on the first surface, the groove surrounds the first surface, the groove has a bottom surface and two opposing first edges, cutting the sealing body along the bottom surface of the groove to separate each package unit and expose the side surface of the sealing layer, making the groove the semi-groove, and further including a packaging process of attaching each package unit to the third carrier and then removing the second carrier to expose the second surface. The method for manufacturing a semiconductor packaging according to claim 7, characterized by this.

9. The method for manufacturing a semiconductor packaging according to claim 8, characterized in that after the sealing layer covers each die, the sealing layer is thinned.

10. The method for manufacturing a semiconductor packaging according to claim 8, characterized in that there is a gap between each adjacent package unit attached to the third carrier, and the gap is 20 μm or more and 1 mm or less.

11. The first virtual line extending along the first surface passes through the first edge, the second virtual line extending along the side surface passes through the second edge, the first distance between the first edge and the second virtual line is 3 μm or more and 10 μm or less, the second distance between the second edge and the first virtual line is 5 μm or more and 120 μm or less, and the ratio of the first distance to the second distance is 0.5 or more and 40 or less. The method for manufacturing a semiconductor packaging according to claim 7 or 10, characterized in that.

12. The groove portion has two opposing groove side surfaces, each of the groove side surfaces is an arc surface, each of the groove side surfaces is connected to the bottom surface, and after separating each of the package units, the bottom surface is used as two groove bottom surfaces, each of the groove side surfaces is connected to each of the groove bottom surfaces, each of the groove side surfaces is located between each of the groove bottom surfaces and the first surface, and the second edge is located on each of the groove bottom surfaces. The method for manufacturing a semiconductor packaging according to claim 8, characterized in that.

13. Each of the groove side surfaces is connected to the first surface, and the first edge is located on each of the groove side surfaces. The method for manufacturing a semiconductor packaging according to claim 12, characterized in that.

14. The groove portion further has two opposing groove side surfaces, each of the groove side surfaces is connected to the first surface and the bottom surface, and there is an included angle between each of the groove side surfaces and the bottom surface, the included angle is 90 degrees or more, and after separating each of the package units, the bottom surface is used as two groove bottom surfaces, each of the groove side surfaces is connected to the first surface and each of the groove bottom surfaces, and there is an included angle between each of the groove side surfaces and each of the groove bottom surfaces, the first edge is located on each of the groove side surfaces, and the second edge is located on each of the groove bottom surfaces. The method for manufacturing a semiconductor packaging according to claim 8, characterized in that.

15. The groove portion further has two opposing groove side surfaces, each of the groove side surfaces is connected to the bottom surface, and there is an included angle between each of the groove side surfaces and the bottom surface, the included angle is more than 90 degrees, and when each of the package units is separated, the bottom surface is removed, each of the groove side surfaces is retained in the semi-groove portion, each of the groove side surfaces is connected to the first surface and the side surface, and the first edge is located on each of the groove side surfaces. The method for manufacturing a semiconductor packaging according to claim 8, characterized in that.

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