Member for semiconductor manufacturing device

Abstract

To provide a member for a semiconductor manufacturing device having a wafer mounting surface that is less likely to generate particles even when a wafer slides on it.SOLUTION: A ceramic substrate has an upper surface with a plurality of protrusions for placing a wafer thereon, and the plurality of protrusions each have an upper end surface, the upper end surface is made of ceramic particles having an average particle size of 20 μm or less, and the fracture toughness value (KIC) of the plurality of protrusions is 2 MPa m1 / 2 or more.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a member for a semiconductor manufacturing device. [Background technology]

[0002] Conventionally, semiconductor manufacturing equipment components have been known that are used for holding wafers, controlling their temperature, transporting them, etc. These types of semiconductor manufacturing equipment components are also called wafer mounting tables, electrostatic chucks, susceptors, etc., and generally have the function of applying electrostatic attraction power to a built-in electrode to attract the wafer by electrostatic force, and some are also known to have the function of controlling the wafer temperature by flowing gas between the wafer mounting surface and the wafer to be attracted.

[0003] A known example of a semiconductor manufacturing equipment component is a ceramic substrate having an upper surface on which a wafer can be placed and a lower surface, and incorporating electrodes, and a base plate located on the lower surface of the ceramic substrate and incorporating a coolant flow path. The upper surface on which the wafer can be placed is provided with multiple protrusions for supporting the wafer.

[0004] Patent Document 1 describes that a plurality of convex portions (corresponding to "protrusions") are formed on a substrate-facing surface (corresponding to an "upper surface on which a wafer can be placed") of a chuck body (corresponding to a "ceramic substrate") formed of first ceramic particles. Patent Document 1 also describes that at least the portions of the convex portions, excluding the tip-side layer, are formed of second ceramic particles having a particle major axis of 20 μm to 2000 μm and have a porosity of 0.1% to 1.0%. Patent Document 1 further describes that the surface roughness of the tip-end surface of the convex portions is 0.01 μm or less in arithmetic mean roughness Ra, that the tip-side layer of each convex portion is a light-transmitting single crystal plate or polycrystalline plate, and that each convex portion, including the tip-side layer, is entirely formed of second ceramic particles having a particle major axis of 20 μm to 2000 μm and have a porosity of 0.1% to 1.0%.

[0005] Patent Document 1 describes the effects of the invention as follows: The base-side layer of each protrusion is densely formed from large ceramic particles. Large ceramic particles have wide particle interfaces, and dense particles with low porosity provide strong bonds between the ceramic particles. Therefore, when dry cleaning is performed inside a plasma processing chamber using plasma, the ceramic particles constituting the base-side layer can be prevented from falling off, thereby suppressing particle generation from the electrostatic chuck. If the surface roughness of the leading edge surface serving as the substrate support surface is 0.01 μm or less in arithmetic mean roughness Ra, when the substrate W is electrostatically attracted to the electrostatic chuck, a large force is locally applied from the substrate W to the substrate support surface, which can prevent damage to the protrusions. In addition, it can prevent a change in the contact state between the protrusions and the substrate W due to damage, which can prevent a change in the thermal conductivity between the substrate W and the electrostatic chuck. When the convex portion, including the leading edge surface, is formed of relatively large second ceramic particles having a particle major axis of 20 μm or more and 2000 μm or less, the particle interface of the ceramic particles is wide, which makes it possible to suppress particle shedding from the leading edge surface due to contact between the leading edge surface and the substrate W or dry cleaning inside the plasma processing chamber using plasma. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2023-31112 Summary of the Invention [Problem to be solved by the invention]

[0007] When the wafer is in contact with the upper end surfaces of the protrusions, thermal expansion or the like can cause the wafer to slide against the upper end surfaces of the protrusions, which can result in the ceramic particles that make up the upper end surfaces of the protrusions falling off. When the ceramic particles fall off, they adhere to the wafer as particles, which can affect the quality of the semiconductor and reduce the yield. Patent Document 1 aims to suppress the generation of particles from the electrostatic chuck by focusing on the surface roughness of the leading edge of the protrusions (protrusions) that support the wafer, the major axis of the particles in the protrusions, and the porosity of the protrusions, but there is still room for improvement.

[0008] In view of the above circumstances, an object of one embodiment of the present invention is to provide a semiconductor manufacturing equipment member having a wafer mounting surface that is less likely to generate particles even when a wafer slides on it. [Means for solving the problem]

[0009] The present inventors have conducted extensive research to solve the above problems and have created the present invention, which is exemplified below.

[0010] [Aspect 1] A ceramic substrate having an upper surface with a plurality of protrusions for mounting a wafer, the plurality of protrusions each having an upper end surface, the upper end surface being made of ceramic particles having an average particle size of 20 μm or less; The fracture toughness value (KIC) of the plurality of protrusions is 2 MPa m 1 / 2 The semiconductor manufacturing equipment component is as described above. [Aspect 2] 2. The semiconductor manufacturing equipment member according to claim 1, wherein the ceramic particles contain one or two kinds of particles selected from alumina and aluminum nitride. [Aspect 3] 3. A member for a semiconductor manufacturing equipment according to aspect 1 or 2, wherein the upper end surfaces of the plurality of protrusions have an arithmetic mean roughness Ra of 0.8 μm or less. [Effects of the Invention]

[0011] According to a semiconductor manufacturing equipment member according to one embodiment of the present invention, particles are unlikely to be generated even when a wafer slides on a wafer-mounting surface, which contributes to improving the stability of semiconductor quality and increasing yield. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic partial vertical cross-sectional view of a semiconductor manufacturing equipment member according to one embodiment of the present invention (a partial cross-sectional view taken along a plane including the central axis of the semiconductor manufacturing equipment member). [Figure 2] FIG. 2 is a schematic enlarged partial view of the vicinity of the circle shown in FIG. 1. [Figure 3] FIG. 2 is a schematic plan view of a wafer mounting surface of a ceramic substrate according to one embodiment. [Figure 4] 1A to 1C are diagrams showing a manufacturing process of a semiconductor manufacturing equipment member according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] Next, embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate design changes, improvements, and the like may be made based on the common knowledge of those skilled in the art without departing from the spirit of the present invention. Furthermore, in this specification, "upper" and "lower" are used for convenience to represent the relative positional relationship when the semiconductor manufacturing equipment component's ceramic substrate is placed on a horizontal surface with the upper surface facing up, and do not represent absolute positional relationships. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0014] <1. Composition of semiconductor manufacturing equipment components> 1 , a semiconductor manufacturing equipment member 10 according to one embodiment of the present invention can be used when performing processes such as CVD and etching on a wafer W using plasma. The semiconductor manufacturing equipment member 10 includes a ceramic substrate 20 having an upper surface 21 on which the wafer W can be placed and a lower surface 23, and incorporating an electrode 26. The semiconductor manufacturing equipment member 10 also includes a base plate 30 located on the lower surface 23 of the ceramic substrate 20 and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded together via a bonding layer 40.

[0015] The ceramic substrate 20 includes a central portion 20a having a circular upper surface 21 in a planar view, and an outer peripheral portion 20b having an annular upper surface 27 in a planar view around the central portion 20a. The central portion 20a of the ceramic substrate 20 may have a diameter of 190 to 450 mm and a thickness of 1 to 5 mm, for example. A wafer W can be placed on the upper surface 21 of the central portion 20a, and a focus ring can be placed on the upper surface 27 of the outer peripheral portion 20b. Hereinafter, the focus ring may be abbreviated as "FR." The upper surface 27 of the outer peripheral portion 20b is one step lower than the upper surface 21 of the central portion 20a. The lower surfaces 23 of the central portion 20a and the outer peripheral portion 20b may be flush with each other. The illustrated ceramic substrate 20 may have the central portion 20a but not the outer peripheral portion 20b, i.e., it may not have the one-step lower upper surface 27.

[0016] The upper surface 21 of the ceramic substrate 20, on which the wafer W can be placed, is provided with a plurality of protrusions 22 for placing the wafer W. A seal band 25 may also be formed along the outer edge of the upper surface 21. In this case, the wafer W may be supported by the upper end surface 21c of the seal band 25 and the upper end surfaces 21a of the plurality of protrusions 22. It is preferable that the seal band 25 and the plurality of protrusions 22 have the same height. As shown in FIG. 3, in one embodiment, a ring-shaped seal band 25 is formed along the outer edge of the upper surface 21 of the ceramic substrate 20, and a plurality of protrusions 22 are formed over the entire inner surface of the seal band 25.

[0017] FIG. 2 is a schematic enlarged view of the area surrounded by a circle in FIG. 1, showing the schematic structure of protrusions 22 provided on the upper surface 21 of the ceramic substrate 20. The shape of the protrusions 22 is not limited, but may be, for example, a cylindrical shape such as a cylinder or a rectangular pillar. The height h of the protrusions 22 is, for example, 5 to 100 μm, and typically 10 to 30 μm. The diameter d of the protrusions 22 is, for example, 0.3 to 3.0 mm, and typically 0.8 to 2.2 mm. Here, the diameter d of the protrusions 22 refers to the circle-equivalent diameter when the protrusions 22 are viewed from above. The portion of the upper surface 21 of the central portion 20a of the ceramic substrate 20 where the seal band 25 and the protrusions 22 are not provided is referred to as the reference surface 21b.

[0018] Each of the plurality of protrusions 22 has an upper end surface 21a, which is made up of fine ceramic particles. Because the upper end surface 21a is made up of fine ceramic particles, shedding of the ceramic particles is suppressed when the wafer W, which is in contact with the upper end surface 21a of the protrusions 22, slides against the upper end surface 21a of the protrusions 22 due to thermal expansion or the like, thereby suppressing the generation of particles. Although the present invention is not intended to be limited by theory, it is presumed that as the ceramic particles making up the upper end surface 21a become finer, the contact area of the grain boundaries (the contact area between grains) increases and the grains become denser, which results in less shedding of the grains.

[0019] Specifically, the average particle size of the ceramic particles constituting the upper end surfaces 21a of the plurality of protrusions 22 is preferably 20 μm or less, may be less than 20 μm, is more preferably 5 μm or less, and is even more preferably 1 μm or less. While no particular lower limit is set for the average particle size of the ceramic particles, from the viewpoint of ease of manufacture, it is preferably 0.1 μm or more, more preferably 0.3 μm or more, and even more preferably 0.5 μm or more. Therefore, the average particle size of the ceramic particles constituting the upper end surfaces 21a of the plurality of protrusions 22 is preferably 0.1 to 20 μm, more preferably 0.3 to 5 μm, and even more preferably 0.5 to 1 μm.

[0020] For the same reasons, the average particle size of the ceramic particles constituting the upper end surface 21c of the seal band 25 is preferably 20 μm or less, may be less than 20 μm, more preferably 5 μm or less, and even more preferably 1 μm or less. While no particular lower limit is set for the average particle size of the ceramic particles, from the viewpoint of ease of manufacture, it is preferably 0.1 μm or more, more preferably 0.3 μm or more, and even more preferably 0.5 μm or more. Therefore, the average particle size of the ceramic particles constituting the upper end surface 21c of the seal band 25 is preferably 0.1 to 20 μm, more preferably 0.3 to 5 μm, and even more preferably 0.5 to 1 μm.

[0021] The average particle size of the ceramic particles that make up the upper end surfaces 21a of the plurality of protrusions 22 and the upper end surface 21c of the seal band 25 is measured by the intercept method. First, a method for measuring the average particle size of the ceramic particles constituting the upper end surfaces 21a of the multiple protrusions 22 will be described. The upper end surfaces 21a of the protrusions 22 to be measured are polished to make the grain boundaries more visible, and the center of the polished surface is observed using an SEM at 1000x magnification. Two parallel lines (length L) are drawn on the SEM image, and the number n of crystal particles intersected by each line of length L is determined. If the end of a line is located within a crystal particle, that crystal particle is counted as 1 / 2. The length L of each line is divided by n (L / n) for all lines, and the average value is calculated. The average value obtained is multiplied by a coefficient of 1.5 to determine the average particle size of the ceramic particles on the upper end surfaces 21a of the protrusions 22. Similar measurements are performed on the upper end surfaces 21a of all protrusions 22 to calculate the overall average particle size, which is used as the measurement value. However, if it is known that the average particle size of the upper end surface 21a of each protrusion 22 is substantially the same, for example, if they are manufactured using the same manufacturing method, it is not necessary to measure the upper end surfaces 21a of all protrusions 22, and some measurements may be omitted. Next, we will explain how to measure the average particle size of the ceramic particles that make up the upper end surface 21c of the seal band 25. The measurement point on the upper end surface 21c of the seal band 25 is polished to make the grain boundaries more visible, and the resulting polished surface is observed using an SEM at 1000x magnification. Two parallel lines (length L) are drawn on the SEM image, and the number n of crystal particles that each line of length L intersects is determined. If the end of a line is located within a crystal particle, that crystal particle is counted as 1 / 2. The length L of each line is divided by n (L / n) for all lines, and the average value is calculated. The average value obtained is multiplied by a coefficient of 1.5 to determine the average particle size of the ceramic particles at the measurement point on the upper end surface 21c of the seal band 25. Similar measurements are performed evenly on the upper end surface 21c of the seal band 25, and the overall average particle size is calculated and used as the measurement value.

[0022] In order to suppress the generation of particles, it is desirable that the plurality of protrusions 22 have a high fracture toughness value (KIC). A high fracture toughness value (KIC) improves wear resistance, and therefore it is possible to suppress the generation of particles due to wear of the protrusions 22 caused by sliding with the wafer W.

[0023] Specifically, the fracture toughness value (KIC) of the plurality of protrusions 22 is 2 MPa·m 1 / 2 It is preferable that the pressure is 3 MPa m or more. 1 / 2 More preferably, it is 4 MPa m 1 / 2 Although no particular upper limit is set for the fracture toughness value (KIC) of the plurality of protrusions 22, from the viewpoint of ease of manufacture, it is preferable that the upper limit be 7 MPa m 1 / 2 Preferably, it is 6 MPa m 1 / 2 More preferably, it is 5 MPa m or less. 1 / 2 Therefore, the fracture toughness value (KIC) of the plurality of protrusions 22 is 2 to 7 MPa m 1 / 2 Preferably, the pressure is 3 to 6 MPa m 1 / 2 More preferably, it is 4 to 5 MPa m 1 / 2 It is even more preferable that:

[0024] For the same reason, the fracture toughness value (KIC) of Seal Band 25 is 2 MPa m 1 / 2 It is preferable that the pressure is 3 MPa m or more. 1 / 2 More preferably, it is 4 MPa m 1 / 2 Although there is no particular upper limit set for the fracture toughness value (KIC) of the seal band 25, from the viewpoint of ease of manufacture, it is preferable that the KIC be 7 MPa·m 1 / 2 Preferably, it is 6 MPa m 1 / 2 More preferably, it is 5 MPa m or less. 1 / 2 Therefore, the fracture toughness value (KIC) of the seal band 25 is 2 to 7 MPa m 1 / 2 Preferably, the pressure is 3 to 6 MPa m 1 / 2 More preferably, it is 4 to 5 MPa m 1 / 2 It is even more preferable that:

[0025] The fracture toughness (KIC) of the plurality of protrusions 22 and the seal band 25 is measured in accordance with the SEPB method (Separately Ejected Pre-crack Method) defined in JIS R1607:2015.

[0026] In order to suppress the generation of particles, it is desirable that the arithmetic mean roughness Ra of the upper end surfaces 21a of the plurality of protrusions 22 is small. When the arithmetic mean roughness Ra of the upper end surfaces 21a of the plurality of protrusions 22 is small, there are fewer microscopic convex portions that are easily chipped, which makes it possible to suppress the generation of particles.

[0027] Specifically, the arithmetic mean roughness Ra of the upper end surfaces 21a of the plurality of protrusions 22 is preferably 0.8 μm or less, more preferably 0.6 μm or less, and even more preferably 0.4 μm or less. From the viewpoint of ease of manufacture, the arithmetic mean roughness Ra of the upper end surfaces 21a of the plurality of protrusions 22 is preferably 0.1 μm or more, more preferably 0.2 μm or more, and even more preferably 0.3 μm or more. Therefore, the arithmetic mean roughness Ra of the upper end surfaces 21a of the plurality of protrusions 22 is preferably 0.1 to 0.8 μm, more preferably 0.2 to 0.6 μm, and even more preferably 0.3 to 0.4 μm.

[0028] For the same reasons, the arithmetic mean roughness Ra of the upper end surface 21c of the seal band 25 is preferably 0.8 μm or less, more preferably 0.6 μm or less, and even more preferably 0.4 μm or less. From the viewpoint of ease of manufacture, the arithmetic mean roughness Ra of the upper end surface 21c of the seal band 25 is preferably 0.1 μm or more, more preferably 0.2 μm or more, and even more preferably 0.3 μm or more. Therefore, the arithmetic mean roughness Ra of the upper end surface 21c of the seal band 25 is preferably 0.1 to 0.8 μm, more preferably 0.2 to 0.6 μm, and even more preferably 0.3 to 0.4 μm.

[0029] The arithmetic mean roughness Ra of the upper end surfaces 21a of the multiple protrusions 22 and the upper end surface 21c of the seal band 25 is measured using a contact roughness meter in accordance with JIS B0633: 2001. The measurement conditions are as follows: reference length: 0.8 mm, evaluation length: 4.8 mm, cutoff λc: 0.8 mm, λs: 0.0025 mm, and stylus tip diameter: 2 μm.

[0030] At least the upper end surfaces of the plurality of protrusions 22 may be covered with a coating film, such as a coating film containing at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0031] The ceramic substrate 20, including the protrusions 22 and the seal band 25, can be formed from a ceramic material such as alumina or aluminum nitride. In a preferred embodiment, the ceramic particles constituting the plurality of protrusions 22 contain one or two types selected from alumina and aluminum nitride. In a more preferred embodiment, the ceramic particles constituting the plurality of protrusions 22 contain 80 mass % or more of one or two types selected from alumina and aluminum nitride. In an even more preferred embodiment, the ceramic particles constituting the plurality of protrusions 22 contain 95 mass % or more of one or two types selected from alumina and aluminum nitride.

[0032] The electrode 26 is a planar electrode used as an electrostatic electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26 is formed of a material containing, for example, W, Mo, WC, or MoC. A low-pass filter may be disposed midway along the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26, the wafer W is attracted and fixed to the wafer mounting surface, specifically, the upper end surface 21 c of the seal band 25 and the upper end surface 21 a of the protrusion 22, by electrostatic attraction. When the application of the DC voltage is stopped, the wafer W is released from the attraction and fixation to the wafer mounting surface.

[0033] Instead of or in addition to the electrode for electrostatic attraction, a heater electrode (resistance heating element) or an RF electrode for generating plasma may be built in as electrode 26. In this case, a heater power supply is connected to the heater electrode, and an RF power supply is connected to the RF electrode. Ceramic substrate 20 may have one layer of electrode 26 built in, or two or more layers of electrode 26 built in with gaps between them.

[0034] The base plate 30 may be, for example, disk-shaped. The base plate 30 may have an annular flange portion on its lower surface that is used to clamp the semiconductor manufacturing equipment member 10 to a jig in the chamber. The thickness of the base plate 30 may be 20 to 40 mm, typically 25 to 35 mm. The base plate 30 is connected to a radio frequency (RF) power source and can also be used as an RF electrode.

[0035] The base plate 30 may be a circular plate (having the same diameter as or larger than the ceramic substrate 20) with good electrical and thermal conductivity. A refrigerant flow path 32 through which a refrigerant circulates may be formed within the base plate 30. The refrigerant flowing through the refrigerant flow path 32 is preferably a liquid, preferably electrically insulating. Examples of electrically insulating liquids include fluorine-based inert liquids. The refrigerant flow path 32 may be formed, for example, in a single stroke across the entire base plate 30 in a plan view from one end (inlet) to the other end (outlet). One end and the other end of the refrigerant flow path 32 are connected to a supply port and a recovery port, respectively, of an external refrigerant device (not shown). The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0036] The base plate 30 can be made of, for example, a metal material or a composite material of metal and ceramic. Examples of metal materials include Al, Ti, Mo, and alloys thereof. Examples of composite materials of metal and ceramic include metal matrix composites (MMCs) and ceramic matrix composites (CMCs). Specific examples of such composite materials include a material containing Si, SiC, and Ti (also called SiSiCTi), a material in which porous SiC is impregnated with Al and / or Si, and a composite material of Al2O3 and TiC. A material in which porous SiC is impregnated with Al is called AlSiC, and a material in which porous SiC is impregnated with Si is called SiSiC. It is preferable to select a material for the base plate 30 that has a thermal expansion coefficient similar to that of the material for the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, the base plate 30 is preferably made of SiSiCTi or AlSiC, which have a thermal expansion coefficient similar to that of alumina.

[0037] As shown in FIG. 1 , the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may be formed, for example, by a metal layer made of solder or a metal brazing material. The bonding layer 40 is formed, for example, by thermal compression bonding (TCB). TCB is a known method in which a metal bonding material is sandwiched between two components to be bonded and the two components are pressure-bonded while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of the metal layer. The resin bonding layer may be formed, for example, by a cured product of a silicone resin adhesive, an epoxy resin adhesive, an acrylic resin adhesive, or a urethane resin adhesive.

[0038] At least one of the side surface of the ceramic substrate 20, the outer periphery of the bonding layer 40, and the side surface of the base plate 30 can be covered with an insulating film 60. Examples of the insulating film 60 include a thermally sprayed film of alumina, yttria, or the like.

[0039] In the above-described embodiment, the semiconductor manufacturing equipment component 10 may have a plurality of holes penetrating the semiconductor manufacturing equipment component 10 in the vertical direction. Examples of such holes include a plurality of gas holes 50 opening in the upper surface 21 and lift pin holes for inserting lift pins that move the wafer W up and down relative to the upper surface 21. A plurality of gas holes 50 may be provided at appropriate positions when the upper surface 21 is viewed from above (see FIG. 3 ). A thermally conductive gas such as He gas is supplied to the gas holes 50. Typically, the gas holes 50 are provided so as to open to a portion of the upper surface 21 where the seal band 25 and the plurality of protrusions 22 are not provided (reference surface 21b). When the thermally conductive gas is supplied to the gas holes 50, the thermally conductive gas fills the space on the backside of the wafer W placed on the upper surface 21. A plug 55 having a gas flow path may be embedded in the gas holes 50. A plurality of lift pin holes can be provided at equal intervals along concentric circles on the upper surface 21 when the upper surface 21 is viewed in plan view.

[0040] <2. How to use semiconductor manufacturing equipment parts> Next, an example of how to use the semiconductor manufacturing equipment member 10 will be described. First, with the semiconductor manufacturing equipment member 10 installed in a chamber (not shown), a wafer W is placed on the upper surface 21 of the ceramic substrate 20. Then, the chamber is depressurized using a vacuum pump to adjust the chamber to a predetermined degree of vacuum, and a voltage is applied to the electrodes 26 of the ceramic substrate 20 to generate an electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface (specifically, the upper end surfaces 21c of the seal bands 25 and the upper end surfaces 21a of the protrusions 22).

[0041] Next, the chamber is filled with a reactive gas atmosphere at a predetermined pressure (for example, several tens to several hundreds of Pa), and in this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) provided on the ceiling of the chamber and the base plate 30 of the semiconductor manufacturing equipment member 10 to generate plasma. The surface of the wafer W is processed by the generated plasma.

[0042] <3. Manufacturing examples of semiconductor manufacturing equipment components> Next, a manufacturing example of the semiconductor manufacturing equipment member 10 will be described with reference to FIG. 4. First, a disk-shaped ceramic sintered body 120, which is the base of the ceramic substrate 20, is produced by hot-press sintering a ceramic powder compact (FIG. 4A). The compact may be produced by stacking multiple tape compacts, by mold casting, or by compressing ceramic powder. The ceramic sintered body 120 has an electrode 26 built in.

[0043] Next, the upper surface of the ceramic sintered body 120 is laser-processed to form the plurality of protrusions 22 and the seal band 25 (FIG. 4B). The timing for forming the plurality of protrusions 22 and the seal band 25 may be after the ceramic substrate 20 and the base plate 30 are joined. The average grain size of the ceramic particles constituting the upper end surfaces 21a of the plurality of protrusions 22 and the upper end surface 21c of the seal band 25 and the fracture toughness value (KIC) of the plurality of protrusions 22 can be controlled, for example, by the particle size of the raw material powder and the firing conditions. The arithmetic mean roughness Ra of the upper end surfaces 21a of the plurality of protrusions 22 and the upper end surface 21c of the seal band 25 can be controlled, for example, by polishing before the laser processing.

[0044] In parallel with this, two MMC disk members 131 and 136 are fabricated (FIG. 4C). Then, grooves 132 that will ultimately become the coolant flow paths 32 are formed in the lower surface of the upper MMC disk member 131 by machining (FIG. 4D). Through holes 133 for introducing the coolant and through holes 134 for discharging the coolant are drilled in the lower MMC disk member 136. When the ceramic sintered body 120 is made of alumina, the MMC disk members 131 and 136 are preferably made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is roughly the same as that of SiSiCTi or AlSiC.

[0045] The SiSiCTi disk member can be fabricated, for example, as follows: First, silicon carbide, metallic Si, and metallic Ti are mixed to produce a powder mixture. Next, the resulting powder mixture is uniaxially pressed to produce a disk-shaped compact, which is then hot-press sintered in an inert atmosphere to obtain the SiSiCTi disk member.

[0046] Next, a metal bonding material 135 is placed between the lower surface of the upper MMC disk member 131 and the upper surface of the lower MMC disk member 136, and a metal bonding material 137 is placed on the upper surface of the upper MMC disk member 131. The ceramic sintered body 120 is then placed on the metal bonding material 137 placed on the upper surface of the upper MMC disk member 131. This results in a laminate 110 in which the lower MMC disk member 136, the metal bonding material 135, the upper MMC disk member 131, the metal bonding material 137, and the ceramic sintered body 120 are stacked in this order from bottom to top (FIG. 4E). This laminate 110 is then heated and pressurized (TCB) to obtain a bonded body. The bonded body is formed by bonding the ceramic sintered body 120 to the upper surface of the MMC block 130, which will become the base plate 30, via a metal bonding layer. The MMC block 130 is formed by joining an upper MMC disk member 131 and a lower MMC disk member 136 via a metal joining layer. The MMC block 130 has a coolant flow path 32, a coolant inlet 36, and a coolant outlet 38.

[0047] TCB is performed, for example, as follows. That is, the laminate is pressed and bonded at a temperature below the solidus temperature of the metal bonding material (for example, a temperature equal to or higher than the solidus temperature minus 20°C and lower than the solidus temperature), and then returned to room temperature. This causes the metal bonding material to become a metal bonding layer. An Al-Mg based bonding material or an Al-Si-Mg based bonding material can be used as the metal bonding material in this case. For example, when TCB is performed using an Al-Si-Mg based bonding material, the laminate is pressed while heated in a vacuum atmosphere. It is preferable to use a metal bonding material with a thickness of about 100 μm.

[0048] Next, the outer periphery of the ceramic sintered body 120 is cut to form a step, thereby forming a ceramic substrate 20 having a central portion 20a and an outer periphery 20b, thereby obtaining a semiconductor manufacturing equipment member 10 (FIG. 4F).

[0049] 1 is shown as a single unit, it may alternatively have a structure in which two members are joined with a metal joining layer, as shown in FIG. 4F, or a structure in which three or more members are joined with a metal joining layer. When forming the joining layer 40 using a metal joining material 137, the insulating film 60 can be formed on the base plate 30 by thermal spraying either before or after joining with the ceramic substrate 20. When forming the joining layer 40 using a resin adhesive sheet, the resin melts, so the insulating film 60 is formed by thermal spraying before joining with the ceramic substrate 20. [Explanation of symbols]

[0050] 10: Semiconductor manufacturing equipment components 20: Ceramic substrate 20a: Central section 20b: Outer periphery 21: Top of the center 21a: Upper end surface of the protrusion 21b: Reference plane 21c: Upper end surface of seal band 22: Protrusion 23: Bottom surface of ceramic substrate 25: Seal band 26: Electrode 27: Top surface of outer periphery 30: Base plate 31: Top surface of base plate 32: Coolant flow path 36: Refrigerant introduction section 38: Refrigerant discharge part 40: Bonding layer 50: Gas hole 55: Plug 60: insulating film 110: Laminate 120: Sintered ceramics 130: MMC block 131:MMC disk member 132: Groove 133:Through hole 134:Through hole 135: Metal bonding material 136:MMC disk member 137: Metal bonding material W: Wafer

Claims

1. A ceramic substrate having an upper surface with a plurality of protrusions for mounting a wafer, the plurality of protrusions each having an upper end surface, the upper end surface being made of ceramic particles having an average particle size of 20 μm or less; The fracture toughness value (KIC) of the plurality of protrusions is 2 MPa m 1 / 2 The semiconductor manufacturing equipment component is as described above.

2. 2. The semiconductor manufacturing equipment member according to claim 1, wherein the ceramic particles contain one or two types selected from the group consisting of alumina and aluminum nitride.

3. 3. A semiconductor manufacturing equipment member according to claim 1, wherein the arithmetic mean roughness Ra of the upper end surfaces of the plurality of protrusions is 0.8 [mu]m or less.

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