Structure and operation method of semiconductor memory

Abstract

To provide a DRAM capable of retaining data for a long period of time and capable of increasing the capacity, and the DRAM including only a MOS transistor, and provide a method of manufacturing the same.SOLUTION: In a memory cell array structure, a group of MOS transistors insulated from a substrate 211 and horizontally arranged is vertically stacked in multiple layers, an insulating film is laid between transistor layers, each MOS transistor forms one memory cell, one silicon channel layer and source and drain diffusion layers are placed in each memory cell, and a source line and a bit line are connected to a source diffusion layer 205 and a drain diffusion layer 204, respectively. A pair of source lines 208 and bit lines 206 and 207 are extend in parallel, a gate conductor layer is formed of vertical columns, two gate conductor layers 201 are disposed on one MOS transistor via a gate insulating film 202 so as to sandwich the channel layer, a gate end of one gate conductor layer extends to the source diffusion layer and the drain diffusion layer, and the other gate conductor layer has a short length.SELECTED DRAWING: Figure 1-1

Description

[Technical Field]

[0001] The present invention relates to semiconductor memory devices and the operation of semiconductor memory devices. [Background technology]

[0002] In recent years, there has been a demand for higher integration and performance of memory elements in LSI (Large Scale Integration). Capacitor-connected dynamic random access memories (DRAMs, e.g., Non-Patent Document 1) have difficulty achieving high integration because memory cells cannot be stacked three-dimensionally. Meanwhile, a method has been proposed for creating capacitor-free DRAM cells using a single MOS transistor with a silicon film (SOI: Silicon On Insulator) formed on an insulating film (Non-Patent Documents 2 and 3). However, this method has problems with data retention and has not yet been put to practical use.

[0003] Figure 12-1 shows the write operation of a "1" in a DRAM cell without a capacitor, Figure 12-2 shows the state of the cell after writing "1", and Figure 12-3 shows the write operation of a "0" (see Non-Patent Document 2). 12-1 shows a "1" write operation. Here, the memory cell is formed on the SOI substrate 300, and has a source N + The layer 303 (hereinafter, the semiconductor region containing a high concentration of donor impurities is referred to as "N + The semiconductor region containing the acceptor impurities is called the "P layer." The drain N +The memory cell of the DRAM is composed of a layer 304, a gate conductive layer 305 to which a word line WL is connected, and a floating body 302 which is the P layer of the MOS transistor 310-1. There is no capacitor, and a single MOS transistor 310-1 constitutes the memory cell of the DRAM. The SiO2 layer 301 of the SOI substrate is in contact directly below the floating body 302. When writing "1" to a memory cell composed of this single MOS transistor 310-1, the MOS transistor 310-1 is operated in the saturation region. That is, the source N + An inversion layer 307 extending from layer 303 is connected to the drain N + The drain N + When the bit line BL connected to the layer 304 and the word line WL connected to the gate conductive layer 305 are both set to a high voltage and the gate voltage is set to about 2 / 3 of the drain voltage to operate the MOS transistor 310-1, the drain N + The electric field intensity is at a maximum at the pinch-off point where there is no inversion layer near the layer 304. + Layer 303 to drain N + The electrons flowing toward the layer 304 are accelerated and collide with the Si lattice, and the kinetic energy lost at that time generates electron-hole pairs (impact ionization phenomenon). Most of the generated electrons (not shown) are transported to the drain N + The generated holes 306 contribute to the increase in the number of majority carriers because the floating body 302 is made of P-type Si. The floating body 302 is filled with the generated holes 306, and the voltage of the floating body 302 rises to the source N + When the potential of the layer 303 becomes higher than the built-in potential (Vb), the generated holes are transported to the source N + discharges into layer 103, where Vb is the source N +This is the built-in voltage of the PN junction between the layer 303 and the floating body 302 of the P layer, and is approximately 0.7 V. Figure 12-2 shows the floating body 302 saturated with generated holes 306.

[0004] Next, the "0" write operation of the memory cell 310 will be explained using Figure 12-3. For a common selected word line WL, there are randomly "1" written memory cell 310-1 and "0" written memory cell 310-2. Figure 12-3 shows how the "1" write state is rewritten to the "0" write state. When writing "0", the voltage of the bit line BL is set to -0.9V, the source line SL is set to 0V, and the word line WL is set to 1V, thereby + The PN junction between the layer 104 and the floating body 302 of the P layer is forward biased. As a result, holes 306 generated in the floating body 302 in the previous cycle are transferred to the drain N connected to the bit line BL. + The potential of the floating body 302 of the memory cell 310-1 filled with holes 306 (Fig. 12-2) is higher than that of the floating body 302-2, which does not contain any holes. Therefore, the threshold voltage of the memory cell 310-1 is lower than that of the memory cell 310-2. This is shown in Fig. 12-4.

[0005] FIG. 13 shows the read operation (see Non-Patent Document 2). FIG. 13-1 shows the "0" write state, and FIG. 13-2 shows the "1" write state. The voltage of the bit line BL is set to a positive voltage (for example, 0.2 V), and the source N + Apply 0V to layer 303 and a positive bias (e.g., 0.8V) to gate conductive layer 305. Because the thresholds are different between the "0" write state and the "1" write state, the cell current (Icell) during readout is detected to be different between the two, as shown in Figure 13-3, and the state is judged to be "1" or "0."

[0006] One of the problems with memory cells using SOI is their short data retention time after data is written (see Non-Patent Document 2). Figure 14 shows an example of the problem with the data retention characteristics of a "0" state memory cell. Figure 14-1 shows two memory cells, one above the other, sharing a bit line. When writing a "0" to the upper cell, -0.9V is applied to the bit line BL, 0V to the source line, and 1V to the word line WL. Meanwhile, the lower cell is a non-selected cell for writing a "0." Even if the bit line is -0.9V and the source line is 0V, -1.5V is applied to the word line to turn off the memory transistor. To quickly apply -1.5V to all non-selected word lines when writing a "0," the bit line and source line are kept at 0V while the memory cell array is in standby mode (not performing write or read operations), and -1.5V is steadily applied to the word line. By applying -1.5V to the word line during standby, holes stored in the channel of a memory cell in the "1" state gather directly below the gate, suppressing recombination of holes and electrons, allowing the holes to remain in the channel for a long time. Therefore, if the memory cell is read after waiting one second after writing data, Icell in the "1" state remains almost unchanged compared to immediately after writing. On the other hand, for a memory cell in the "0" state, Icell gradually increases during standby. For example, if the standby temperature is 85°C, Icell reaches approximately the same value as the "1" state in about 100 ms. Since the smaller the difference between Icell ("1") and Icell ("0") becomes, the greater the risk of misreading data, so the upper limit of standby time is set at around 50 ms. However, in large-scale LSIs, variations between memory cells must be taken into account, and the upper limit of standby time is likely to be lower. Short data retention requires frequent data rewriting and increases standby current consumption, making it unsuitable for mass production.

[0007] The reason why the read current of a "0" cell increases during standby is shown in Figure 14-2. When a negative voltage of -1.5V is applied to the gate 305, the silicon electric field under the gate insulating film increases at the boundary between the source 303 and channel 302 and the boundary between the drain 304 and channel 302, causing a breakdown in the silicon and generating electron-hole pairs. The generated electrons are absorbed by the source and drain, and holes accumulate in the channel, increasing Icell. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] H. Ishiuchi, T. Yoshida, H. Takato, K. Tomioka, K. Matsuo, H. Momose, S. Sawada, K. Yamazaki and K. Maeguchi: International Electron Devices Meeting, pp. 33-36 (1997) [Non-patent document 2] T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory Design Using(a) One-Transistor Gain Cell on SOI,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 1510-1522 (2002) [Non-patent document 3] MG Ertosun, K. Lim, C. Park, J. Oh, P. Kirsch, and KC Saraswat: “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electrons,” IEEE Device Letter, Vol. 31, No.5, pp. 405-407 (2010) Summary of the Invention [Problem to be solved by the invention]

[0009] DRAMs consisting only of MOS transistors without capacitors have shorter data retention times than DRAMs that use capacitors, making them difficult to put into practical use. Also, the area of each memory cell in MOS transistors on SOI is large, making it difficult to increase capacity. [Means for solving the problem]

[0010] To solve the above problems, the present invention provides a method for manufacturing a memory device using semiconductor elements. A group of horizontally arranged MOS transistors, insulated from a substrate, is vertically stacked in multiple layers, with an insulating film laid between each transistor layer. Each horizontally arranged MOS transistor group is several tens of nanometers thick. Each MOS transistor forms a memory cell, and each memory cell has a silicon channel layer and a pair of source and drain diffusion layers sandwiching the silicon channel layer. A metal source line is connected to the source diffusion layer, and a metal bit line is connected to the drain diffusion layer, each of which has the same thickness. The pair of source and bit lines extends long and parallel to each other, connecting to the source and drain diffusion layers of multiple memory cells located on the same horizontal plane. In a plan view, a pair of elongated source and bit lines extends parallel to each other, but multiple similar source and bit line pairs exist in parallel to form a cell array. The upper and lower bit lines are electrically isolated and receive independent voltages from the column decoder at the edge of the memory cell array, while all source lines within a single cell array receive a common voltage from the column decoder. Furthermore, the gate conductor layer is formed as a vertical pillar so that it can be shared by MOS transistors from the top layer to the bottom layer, all of which are located in the same position in a planar view. Each MOS transistor has two gate conductor layers sandwiched between gate insulators, sandwiching the silicon channel layer. The channel layer of a single memory cell is sandwiched between source and drain diffusion layers at both ends, and the opposite ends of the channel layer, which are oriented 90 degrees apart, are surrounded by two gate conductor layers via gate insulators. The gate end of one gate conductor layer extends to the source and drain diffusion layers, sandwiching the gate insulator, and is known as the memory gate, as it switches the MOS transistor between on and off. The other gate conductor layer is shorter, and its ends do not extend to the source and drain diffusion layers. It retains holes accumulated in the channel, and is known as the storage gate. Two insulating film pillars different from the gate insulating film are separately arranged between the storage gate and the source diffusion layer and between the storage gate and the drain diffusion layer, so that the storage gate does not come into direct contact with the source diffusion layer and the drain diffusion layer.The insulating film pillars are thicker than the gate insulating film in plan view, and the width of the silicon channel layer perpendicular to the memory gate at the two locations where the insulating film pillars are present is narrower than at the locations without the insulating film pillars. Like the gate conductor layer, these insulating film pillars are formed so that they can be shared by MOS transistors from the top layer to the bottom layer, all of which are located in the same position in plan view. An interlayer insulating film is laid above the top MOS transistor layer, and the memory gate extends above this insulating film and connects to gate wiring called word lines. The storage gate also extends above this insulating film and connects to gate wiring called storage gate lines. These two gate wirings run parallel to each other and connect to the row decoder at the edge of the memory cell array. The two types of gate wiring are perpendicular to the bit lines and source lines, and the memory gates and storage gates in each memory cell are all connected to the gate wiring directly above them. In other words, the two types of gate wiring all run parallel to each other and connect to the row decoder, and each gate wiring is assigned an independent potential depending on its operation.

[0011] In one embodiment, the source line is always supplied with 0V. The storage gate line is supplied with a certain negative voltage except when "0" data is written to the memory cell connected to the storage gate line. When "0" data is written to the memory cell connected to the storage gate line, a certain positive voltage is applied. The word line is supplied with a certain positive voltage when "0" or "1" is written to the memory cell connected to the word line or when data is read, and is supplied with 0V during other standby periods. The bit line is supplied with a certain positive voltage when "1" data is written to the memory cell connected to the bit line or when data is read, and is supplied with 0V otherwise. [Effects of the Invention]

[0012] Because multiple memory cell layers are stacked vertically, the number of memory cells in a given memory area when viewed in a plane is proportional to the number of stacked memory cell layers. Increasing the number of memory cell layers increases the memory capacity, allowing the creation of large-capacity memory chips. Furthermore, when a memory cell is in the "1" state, holes accumulate in the silicon channel. However, by applying a certain negative voltage to the storage gate line except when the memory cell connected to the storage gate line is being written with "0" data, the holes remain near the storage gate in the silicon channel. On the other hand, since a negative voltage is never applied to the memory gate, even if electrons are present in the channel, they remain near the memory gate. Therefore, the opportunity for holes and electrons to meet in the channel is extremely low, reducing the probability of their recombination. Therefore, even if the memory cell is in the "1" state and holes accumulate in the silicon channel, the holes do not recombine with electrons for a long time, allowing the "1" state to be maintained. Furthermore, because the storage gate does not contact the source or drain diffusion layers and insulating film pillars are sandwiched between the storage gate and both diffusion layers, applying a certain negative voltage to the storage gate except when writing "0" data does not cause breakdown in the silicon channel layer near the storage gate, and electron-hole pairs are not generated. Therefore, the number of holes in a memory cell in which "0" data has been written is less likely to increase, and the "0" state can be maintained for a longer period of time, thereby extending the data retention time. [Brief explanation of the drawings]

[0013] [Figure 1-1] FIG. 1A is a perspective view showing the configuration of a memory cell array according to the first embodiment. [Figure 1-2] Figure 1-2 is a cross-sectional view taken along line AA of Figure 1-1. [Figure 1-3] Figure 1-3 is a cross-sectional view of Figure 1-1 taken along the line BB. [Figure 2-1] Figure 2-1 is a top view of Figure 1-1, with one memory cell shown as the area surrounded by a dashed line. [Figure 2-2] Figure 2-2 is the equivalent circuit diagram. [Figure 2-3] Figure 2-3 shows a top view of eight memory cells lined up. [Figure 2-4] Figure 2-4 is the equivalent circuit diagram. [Figure 3-1] Figure 3-1 is a perspective view showing the connection between the memory cell array and the peripheral core circuit section that drives the cell array. [Figure 3-2] Figure 3-2 is a cross-sectional view taken along the line AA in Figure 3-1. [Figure 4-1] Figure 4-1 shows the operation of a memory cell. [Figure 4-2] Figure 4-2 shows the state of the memory cell corresponding to Figure 4-1. [Figure 5-1] Figure 5-1 shows a top view of a memory cell, showing how to write a "0" [Figure 5-2] Figure 5-2 is a timing chart for writing "0". [Figure 6-1] Figure 6-1 is a top view of a memory cell showing how to write a "1". [Figure 6-2] Figure 6-2 is a timing chart for writing "1". [Figure 7-1] Figure 7-1 shows the cell array configuration and the voltage of each node when writing "0". [Figure 7-2] Figure 7-2 shows the cell array configuration and the voltage at each node when writing "1". [Figure 7-3] Figure 7-3 shows the cell array configuration and the voltage at each node when reading data. [Figure 8] 1 is a diagram and table showing the sizes of components of a memory cell; [Figure 9-1] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-2] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-3a] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-3b] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-4] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-5] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-6]2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-7] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-8] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-9] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-10] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-11] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-12] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-13] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-14] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-15] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-16] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-17] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-18] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-19] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-20] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-21] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-22]2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-23] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-24] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-25] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-26] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-27] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9-28] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 10-1] FIG. 10-1 is a perspective view showing the configuration of a memory cell array according to the second embodiment. [Figure 10-2] Figure 10-2 is a cross-sectional view taken along line AA of Figure 10-1. [Figure 10-3] FIG. 10-3 shows the area of one memory cell surrounded by a dashed line in the top view of FIG. 10-1. [Figure 10-4] Figure 10-4 is the equivalent circuit diagram. [Figure 10-5] Figure 10-5 is a top view of eight memory cells lined up. [Figure 10-6] Figure 10-6 is the equivalent circuit diagram. [Figure 10-7] FIG. 10-7 is a perspective view showing the connection between the memory cell array and the peripheral core circuit unit that drives the cell array. [Figure 10-8] Figure 10-8 is a cross-sectional view of Figure 10-7 taken along line A-A. [Figure 10-9] Figure 10-9 shows the cell array configuration and the voltage at each node when writing "0". [Figure 10-10] 10-10 are diagrams for explaining a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 10-11]10 and 11 are diagrams illustrating a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 11-1] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 11-2] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 11-3] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 11-4] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 11-5] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 11-6] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 11-7] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 12-1] FIG. 10 is a diagram for explaining a "1" write operation in a memory cell in a conventional example. [Figure 12-2] FIG. 10 is a diagram for explaining the state of a memory cell in a conventional example after "1" has been written. [Figure 12-3] FIG. 10 is a diagram for explaining a "0" write operation in a memory cell in a conventional example. [Figure 12-4] FIG. 10 is a diagram for explaining voltage-current characteristics of a memory cell in a conventional example. [Figure 13-1] FIG. 10 is a diagram for explaining the "0" state of a memory cell in a conventional example. [Figure 13-2] FIG. 10 is a diagram for explaining the “1” state of a memory cell in a conventional example. [Figure 13-3] FIG. 10 is a diagram for explaining a read operation in a conventional example. [Figure 14-1] FIG. 10 is a diagram showing voltages applied to two memory cells during a "0" write operation in a conventional example. [Figure 14-2] FIG. 10 is a diagram illustrating a problem in the operation of a memory cell in a conventional example. DETAILED DESCRIPTION OF THE INVENTION

[0014] The structure, driving method and manufacturing method of a semiconductor memory device according to the present invention will be described below with reference to the drawings. [Example]

[0015] First, the structure of a semiconductor memory device according to the present invention will be described with reference to the drawings. FIGS. 1, 2, and 3 show the structure of a memory cell according to the present invention and its equivalent circuit diagram. As shown in FIG. 1-1, an insulating film 209 and a silicon layer 203 are sequentially stacked on a substrate. While FIG. 1 shows a two-layer stack as an example, three or more layers are also possible. A memory gate 201 (MG) and a storage gate 200 (SG) are vertically arranged, penetrating from the top silicon layer 203 to the bottom silicon layer 203, and each gate is covered with a gate insulating film 202. An insulating film 210 is arranged on both ends of the storage gate, and the insulating film 210 extends vertically from the top silicon layer 203 to the bottom silicon layer 203. Diffusion layers 204 and 205 containing N-type or P-type impurities are arranged on both ends of the silicon layer 203. Although the silicon layer 203 does not contain impurities, N-type or P-type impurities are partially thermally diffused from the diffusion layer near the diffusion layer. A MOS transistor is formed by a memory gate 201, a silicon layer 203, and diffusion layers 204 and 205. The silicon layer 203 forms the channel portion, the diffusion layer 204 forms the drain of the MOS transistor, and the diffusion layer 205 forms the source. Low-resistance bit lines 206 and 207 are arranged adjacent to the diffusion layer 204. The top-layer bit line 206 and the bottom-layer bit line 207 are electrically independent. A low-resistance common source line 208 is arranged adjacent to the diffusion layer 205. A common potential is applied to the multiple source lines 208. Meanwhile, the silicon layer 203 is in contact with the storage gate 200 via a gate insulating film 202. The memory gate is in contact with the diffusion layers 204 and 205 via the gate insulating film 202, but the storage gate is not in contact. 1-2 is a cross-sectional view taken along the line AA in FIG. 1-1, showing a configuration in which the memory gate 201, storage gate 200, and gate insulating film 202 vertically penetrate partway through the lowest insulating film layer 209. FIG. 1-3 is a cross-sectional view taken along the line BB in FIG. 1-1, showing a configuration in which the storage gate 200, gate insulating film 202, and insulating film 210 vertically penetrate partway through the lowest insulating film layer 209. The layout of the source diffusion layer 205, common source line 208, and drain diffusion layer 204, and bit lines 206 and 207 is also shown.

[0016] Figure 2-2 is a plan view. Two memory cells are arranged with the storage gate 200 as the axis of inversion symmetry, and the rectangular area indicated by the dashed line corresponds to one memory cell. In other words, two memory cells share one storage gate 200. Furthermore, by vertically stacking the silicon layer 203, source diffusion layer 205, and drain diffusion layer 204 in an n-layer configuration, the number of memory cells can be n times the number of cells in the plan view. Note that Figure 2-1 is a diagram of the top silicon layer, and the bit line is 206. For the bottom silicon layer, the bit line is 207. Figure 2-2 shows the equivalent circuit of one memory cell. The memory cell has four terminals, with two gates: memory gate 201 and storage gate 200. The channel potential is determined by the voltages of the two gates, bit line 206 connected to drain 204, and common source line 208 connected to source 205.

[0017] Figure 2-3 shows the array structure when two pairs of memory cells on the top layer shown in Figure 2-1 are arranged side-by-side, resulting in a total of eight memory cells. Figure 2-4 is an equivalent circuit diagram, but the common source line 208 is shared by all eight memory cells. The two bit lines 206 are independent of each other, and the memory gates are connected to metal wiring word lines 212 (WL). The two word lines 212 are also independent. The storage gate 200 is connected to storage gate lines 213 (SGL). Each storage gate line 213 is also independent of each other. Figure 3-1 shows the connection of the word lines 212 and storage gate lines 213 from the memory cell array to the row decoder circuit, and the connection of the bit lines (BL) 206 and 207 and the common source line (CSL) 208 from the memory cell array to the column decoder circuit. This example shows a three-layer stack of memory transistors. Figure 3-2 shows the AA cross section of Figure 3-1. The bit lines (BL) are stacked in three layers and are independent of each other, and individual voltages are applied by the column decoder.

[0018] Next, Figure 4(a) shows the memory cell drain current (Icell) as a function of the voltage applied to the memory gate 201, assuming that the source diffusion layer 205 and drain diffusion layer 204 are N-type silicon. For example, a constant negative voltage is applied to the storage gate 200, the source diffusion layer 205 is at 0 V, and a positive voltage is applied to the drain diffusion layer 204. Figure 4-1 shows two curves with different threshold voltages (Vt). The difference depends on the presence or absence of holes in the channel region 203. Curve (A) corresponds to the case where holes are present, and curve (B) corresponds to the case where holes are absent. Figure 4-2 shows a cross-sectional view of a memory cell with holes present. Because a negative voltage is applied to the storage gate 200, holes are present near the storage gate. However, the presence of holes increases the potential of the channel region 203 near the memory gate 201 compared to when holes are absent. Therefore, the voltage of the memory gate due to the formation of an inversion layer near the memory gate 201 is lower when holes are present than when holes are absent. In other words, the threshold is lower when holes are present. This difference results in a difference between (A) and (B) in the I-V characteristics. Thus, the drain current (Icell) during readout differs depending on whether or not holes are present in the channel. Therefore, the difference in Icell when a certain positive voltage is applied to the memory gate is detected and used to represent data "1" or "0." Here, a cell with holes in the channel is called a "1" cell, and a cell without holes is called a "0" cell. Note that when the source and drain diffusion layers are P-type silicon, the threshold changes depending on whether or not electrons are present in the silicon channel layer, and the difference in threshold is used as data. Therefore, the voltage applied to each node is reversed in sign from when the source and drain diffusion layers are P-type silicon. The same applies to readout and writing of data "1" and "0." Below, we will explain operation when the source and drain diffusion layers are N-type silicon. In explaining operation, the memory gate will be referred to as MG and the storage gate as SG.

[0019] First, we will explain how to write a "0." Before writing "0" data, the memory cell is in the "1" state and there are holes in the channel region 203. For example, apply 0V to CSL and BL, 0.5V to MG, and 1V to SG. Since the channel region is made of intrinsic silicon without N-type or P-type impurities, the channel potential becomes higher than the source and drain potential, as shown in Figure 5-1, and holes migrate to the source or drain diffusion layer. The migrated holes recombine with electrons in the source or drain and disappear. Therefore, after writing "1," there are no holes in the channel region, resulting in a neutral state with no charge. If the memory cell was in the "0" state before writing "0," writing "0" leaves no holes in the channel, and no state change occurs. Figure 5-2 shows the voltage timing diagram for MG, SG, and BL when writing "0." Note that CSL is always fixed at 0V during write and read.

[0020] Next, we will explain how to write data "1." This assumes that the memory cell is in the "0" state before writing "1" and there are no holes in the channel portion 203. For example, apply 1V to BL, 1.1V to MG, -1V to SG, and 0V to CSL. As shown in Figure 6-1, the MG voltage is higher than the threshold of the memory cell in the "0" state, so an inversion layer 215 forms in the channel portion near MG, and electrons flow from the source to the drain. However, the potential at the drain end of the channel is high, causing depletion. This increases the lateral electric field, causing impact ionization of electrons and generating electron-hole pairs. The generated holes remain in the channel, and the memory cell state changes from "0" to "1." If the memory cell was in the "1" state before writing "1," the holes in the channel continue to exist, so there is no state change. Figure 6-2 shows the voltage timing diagram for MG, SG, and BL when writing "0."

[0021] Next, we will explain the read method. For example, apply 0.2V to BL, 1V to MG, -1V to SG, and fix CSL to 0V. As shown in Figure 4-1, there is a difference in the drain current between the "1" state and the "0" state, and this current difference is detected by the sense circuit in the column decoder.

[0022] Figure 7-1 shows the potentials applied to eight upper and eight lower memory cells when writing a "0." This figure shows the case where there is an upper silicon layer (Layer 1) and a lower silicon layer (Layer 2), with eight memory cells arranged on each of the upper and lower silicon layers. Assuming the upper and lower layers are in the same location in a plan view, the MG and SG are shared, and the CSL is shared by the left and right and upper and lower memory cells. The BLs connected to the upper memory cells (BL1,1 and BL2,1) and the BLs connected to the lower memory cells (BL1,2 and BL2,2) can take independent potentials, but in Layer 1 and Layer 2, all memory cells connected to SG1, enclosed by the dashed line, are simultaneously written to a "0." Memory cells not connected to SG1 are not written to a "0." A group of memory cells connected to a single SG line is called a block. The voltages applied to each node when writing a "0" are shown in the table on the right. A positive voltage between 0.2V and 0.8V is applied to the memory gates (MG1, MG2) connected to the selected block, and a positive voltage between 0.5V and 1.5V is applied to the storage gate (SG1). BL and CSL are set to 0V. As a result, as shown in Figure 5-1, holes in the channel move to the source diffusion layer (205) or drain diffusion layer (204). A negative voltage between -0.5V and -1.5V is applied to the storage gate (SG2) connected to the unselected block. As a result, holes in the channel remain near the storage gate, and "0" is not written.

[0023] Figure 7-2 shows the potentials applied to eight memory cells on each side when writing a "1." A "1" is written to all memory cells connected to MG1 in Layer 1 and Layer 2, enclosed by dashed lines. A group of memory cells connected to a single MG line is called a page. A block consists of two pages. A voltage between 0.8V and 1.5V is applied to MG in the selected page. Whether a memory cell is written to a "1" is determined by the voltage applied to BL. The left cell connected to MG1 in Layer 1 and the right cell in Layer 2 are written to a "1," while the other cells are not. In this case, a voltage between 0.8V and 1.5V is applied to BL1,1 and BL2,2, as shown in the table on the right, and 0V is applied to BL2,1, BL1,2, and CSL. As shown in Figure 6-1, applying a positive voltage to BL and a voltage above the memory cell's threshold to MG causes impact ionization of electrons near the drain, generating electron-hole pairs. The generated holes remain in the channel, and the state of the memory cell changes from "0" to "1." Note that 0V is applied to the unselected memory gates (MG2-MG4). A voltage between -0.5V and -1.5V is applied to all storage gates (SG1 and SG2). The "0" and "1" write operations were explained using Figures 7-1 and 7-2, but to rewrite the data of a memory cell on a certain page, the cell data of the block containing that page is temporarily stored in the latch circuit in the column decoder, and then "0" is written first. Next, the data stored in the latch circuit or new data is written to two memory gates in the block.

[0024] Figure 7-3 shows the voltages applied to eight memory cells on each side during data read. All memory cells on one page connected to MG1, enclosed by dashed lines in Layer 1 and Layer 2, are read simultaneously. Within the selected page, MG1 is applied with a voltage between 0.6V and 1.3V. All BLs connected to Layer 1 and Layer 2 (BL1,1, BL2,1, BL1,2, and BL2,2) are applied with a voltage between 0.2V and 0.6V. All storage gates SG (SG1 and SG2) are fixed at a voltage between -0.5V and -1.5V. When a memory cell is in a "1" or "0" state, there is a difference in the current flowing between the CSL and BL, which is detected by the sense amplifier circuit in the column decoder. When a block is in standby mode (not in write or read mode), a voltage between -0.5V and -1.5V is applied to SG, and the WL, BL, and CSL are all set to 0V. The write and read voltages also depend on the work functions of the memory gate and storage gate. The values shown in Figure 7 are for a work function of approximately 5.2 eV. For example, if the work function is lowered, the voltages applied to MG and SG must be lowered accordingly.

[0025] Figure 8 shows the gate length and gate insulating film thickness of the memory cell. MG is the length of the memory gate, L SG is the length of the storage gate, L Diff is the length of the drain diffusion layer 204 and the source diffusion layer 205 to the outer end of the insulating film 210, and L Si is the length of the channel region 203, and L OX indicates the length from the channel end to the inner end of the insulating film 210. Channel is the width of the channel region 203, and t Storage is the width from the end of the gate insulating film 202 to the end of the insulating film 210, and t Insulator indicates the width of the insulating film 209, and W indicates the width of the silicon 203. MG is 40 to 90 nanometers, L SG is 10 to 25 nanometers, L Diff is 10 to 30 nanometers, L Si is 36 to 80 nanometers, L OX is tChannel is 20 to 40 nanometers, Storage is 10 to 20 nanometers, W and t Insulator The gate insulating film 202 is preferably made of silicon oxide or hafnium oxide (HfO2), but the physical thickness of the gate insulating film (t Gate-Ox ) is preferably 3 to 7 nanometers when using HfO2.

[0026] t Channel / t Storage We compare Icell under three conditions: 10 nanometers / 5 nanometers, 30 nanometers / 15 nanometers, and 60 nanometers / 30 nanometers. For read conditions, a voltage between -0.5V and -1V is applied to SG, 1V to MG, and 0.2V to BL. The difference between Icell ("1") and Icell ("0") immediately after writing is approximately 0.01μA, 0.15μA, and 0.12μA for 10 / 5 nanometers, 30 / 15 nanometers, and 60 / 30 nanometers, respectively. In other words, the Icell data difference is small at 10 / 5 nanometers, making data readout difficult. On the other hand, the Icell difference is large at 15 / 30 nanometers and 30 / 60 nanometers, making data readout possible. Because a negative voltage is applied to SG, applying 1V to MG does not form a sufficient inversion layer in the silicon channel layer near MG in the 10 / 5 nanometer case, resulting in a small Icell ("1") value. However, if a higher voltage is applied to the SG, the holes will not remain near the SG but will diffuse to the MG area of the channel. If readout is repeated in this state, recombination of electrons and holes will occur, reducing the number of holes. This reduces the number of readout times. Channel / t Storage The size of the channel needs to be larger than 10 / 5 nanometers. Also, if the SG voltage is increased during standby, the recombination of electrons and holes becomes easier in the memory cell in the "1" state, and the number of holes in the channel decreases. Therefore, Icell ("1") decreases as the standby time passes. This phenomenon occurs when t Channel / t Storageoccurs in the same way under all three conditions. However, if the applied voltage to the SG is reduced to -0.5V or less, the change in the standby time of Icell ("1") decreases. This is because holes are localized only near the SG during the standby time, reducing the probability of recombining with electrons. Therefore, to improve data retention characteristics, it is desirable to apply a negative voltage of -0.5V or less to the SG.

[0027] On the other hand, Icell("0") increases with increasing standby time. This is due to weak junction breakdown in the silicon channel near the source and drain diffusion layers, generating electron-hole pairs. The generated holes gradually accumulate in the silicon channel, causing Icell("0") to increase. However, the rate of increase in Icell("0") does not depend much on the SG voltage. Even when a negative voltage between -0.5V and -1.5V is applied to the SG, there is little change in Icell("0") from writing a "0" to a standby time of approximately 3 seconds at 85°C. This is because the SG does not directly contact the source and drain diffusion layers, but rather a 10-nanometer-thick insulating film 210 is sandwiched between the diffusion layers and the SG. The presence of the insulating film 210 between the SG and the diffusion layers reduces the electric field in the silicon near the SG, even when a negative voltage is applied to the SG, reducing the generation of electron-hole pairs. Therefore, the standby time dependence of Icell("0") is reduced compared to the conventional example, demonstrating significant improvement in data retention characteristics. The data retention characteristics are Channel / t Storage There is not much difference between 15 / 30 nanometers and 30 / 60 nanometers. On the other hand, from the viewpoint of reducing cell size, Channel Therefore, in order to gain a read margin, the difference between Icell("1") and Icell("0") after writing data should be increased, and the waiting time should be increased. Channel is 18 to 55 nanometers, t Storage It is desirable to set the thickness to around 8 to 31 nanometers.

[0028] A manufacturing method of a memory device according to the first embodiment will be described with reference to Figures 9-1 to 10-28. As shown in Figure 9-1, an insulating film layer 2 and a silicon layer 3 are stacked on a substrate 1. The substrate 1 may be made of silicon. Here, a two-layer structure of a silicon layer 3 and an insulating film layer 2 is shown. An insulating film layer 4 is further deposited on the top silicon layer 3. The silicon layer 3 may contain no impurities. Methods for forming the silicon layer 3 on the insulating film 2 include depositing an amorphous or polycrystalline silicon film and then crystallizing the silicon by annealing in a later process.

[0029] Next, as shown in FIG. 9-2, the insulating film layer 2, the silicon layer 3 and the insulating film layer 4 are divided into a plurality of rectangular shapes. Figure 9-3a shows the next step, a cross-sectional view taken along the A-A line of the rectangle in Figure 9-2. Multiple silicon layers 3 are exposed in the spaces 6 between adjacent stacked films, and high-concentration N- or P-type impurities are implanted into the exposed silicon layers 3. While Figure 9-3a shows the bottom insulating film layer 2 completely removed by etching 6, partial removal is also possible. There are three methods for implanting high-concentration N- or P-type impurities. One method involves filling the spaces between stacked films with a silicon layer containing high-concentration N- or P-type impurities and allowing solid-phase diffusion, followed by removal of the silicon layer containing high-concentration phosphorus. The second method involves ion-implanting N- or P-type impurities through the spaces 6. The ion implantation is performed at an angle so that the impurities are implanted into the silicon layers 3. The third method, as shown in Figure 9-3b, involves partially removing the silicon layer 3 from the space 6 between the stacked films to create a void 5-1 in the silicon layer 3, and then depositing a silicon layer containing a high concentration of N-type or P-type impurities to fill the space 6 between the stacked films.Then, reactive ion etching is used to remove the silicon layer containing a high concentration of N-type or P-type impurities in the space 6 between the stacked films, leaving a silicon layer containing a high concentration of N-type or P-type impurities in the void 5-1.

[0030] Next, as shown in the plan view of Figure 9-4, insulating film layer 4, stacked silicon layer 3, and insulating film layer 2 are etched at locations 7 and 8, down to the middle of the bottom insulating film layer 2. Alternatively, substrate 1 is exposed. Both are possible, but Figure 9-4 and the subsequent figures show the case of removing the bottom insulating film layer 2 to the middle. Figure 9-5 shows a cross section B-B of Figure 9-4. Figure 9-6 shows a plan view of Figure 9-5, excluding insulating film layer 4. Figure 9-7 shows a cross section A-A of Figure 9-4. Next, gate insulating film 9 and then gate material 10 are deposited, and they are polished to expose the top of insulating film layer 4. Figure 9-8 shows the process up to this point. Figure 9-9 shows a cross section B-B of Figure 9-8.

[0031] Next, mask material 11 is deposited, and Figure 9-10 shows a plan view of the mask material after it has been patterned. Figure 9-11 shows the B-B cross section of Figure 9-10. Next, gate material 10 is etched using mask material 11 and insulating film 4 as etching-resistant materials. Gate insulating film 9 may also be etched at the same time as gate material 10, but it is not etched here. Figure 9-12 shows a plan view after mask material 11 has been removed after etching. Figure 9-13 shows the A-A cross section of Figure 9-12. In Figure 9-13, the gate etching parts are 15 and 16.

[0032] Next, an insulating film is deposited, and the surface is polished to expose the insulating film 4. The plan view is shown in Figure 9-14. Areas 17 and 18 are the remaining parts of this insulating film. Figure 9-15 is the A-A cross section of Figure 9-14. Next, both the remaining insulating film at location 18 in Figure 9-14 and the gate insulating film 9 are etched to expose the bottom insulating film 4. Figure 9-16 shows a plan view after the bottom insulating film 4 has been exposed. Figure 9-17 shows the A-A cross section of Figure 9-16. Next, in region 19 where the diffusion layer 5 is exposed in Figure 9-17, the diffusion layer 5 is partially etched. Figure 9-18 shows the shape after partial etching. Next, a metal material 21 is deposited, and the surface of the insulating film 4 is exposed by flat polishing, resulting in the shape shown in Figure 9-19.

[0033] Next, using the insulating film 4 as an etching-resistant material, reactive ion etching is used to remove the metal material 21 at location 22. The metal portion covered by the insulating film 4 and insulating film 2 is not etched, resulting in the shape shown in Figure 9-20. Next, insulating film 24 is deposited, and then the surface of insulating film 4 is exposed by flat polishing. As shown in the plan view of Figure 9-21, insulating film 24 remains only at location 22 in Figure 9-20. Note that gate material 10 (200) corresponds to the storage gate 200 in Figure 1(a). Gate material 10 (201) corresponds to the memory gate 200 in Figure 1(a). The A-A cross section of Figure 9-21 results in the shape shown in Figure 9-22. The plan view taken along the CC plane results in the shape shown in Figure 9-23. The B-B cross section of 10-23 results in the shape shown in Figure 9-24.

[0034] Next, an interlayer insulating film 25 is deposited, and then an opening is made in the interlayer insulating film 25 at the contact hole 26 to expose the gate 10. Figure 9-26 shows a plan view of the contact hole 26. Note that the interlayer insulating film 25 is not shown in Figure 9-25 to show that it is located over the contact hole 26 and both gates 200 and 201. Next, as shown in the plan view of Figure 9-26, a metal material is deposited, and then the metal material is patterned to form gate wiring 27 and 28. Figure 9-27 shows a cross-sectional view of Figure 9-26 taken along the line A-A. The gate wiring 27 extends up to the contact hole 26 and connects to the storage gate 200. As shown in Figure 9-25, the gate wiring 27 is connected to the storage gate 200, and the gate wiring 28 is connected to the memory gate 201. Next, as shown in Figure 9-28, an interlayer insulating film 29 is deposited on the gate wiring 27 and 28, completing the memory cell array fabrication process.

[0035] Other modifications of the present invention are shown using Figures 10-1 to 10-11. In the first embodiment, the SG is shared by two memory cells, but it is also possible for each memory cell to have its own individual SG. Figure 10-1 shows the structure of the memory cell of the present invention. The only difference from the first embodiment is that each memory cell has its own individual SG, and the rest is the same. Figure 10-2 shows the A-A cross section of Figure 10-1. Two adjacent SGs are separated by an insulating film 216. The B-B cross section of Figure 10-1 is the same as Figure 1-3.

[0036] Figure 10-3 is a plan view, in which two memory cells are arranged upside down, and the rectangular area indicated by the dashed line corresponds to one memory cell. Figure 10-4 shows the equivalent circuit of one memory cell, which is the same as that of the first embodiment. Figure 10-5 shows the array structure in which two sets of memory cells shown in Figure 10-1 are arranged side by side, resulting in a total of eight memory cells. Figure 10-6 is the equivalent circuit diagram, in which the common source line 208 is shared by the eight memory cells.

[0037] Figure 10-7 shows how word lines 212 and storage gate lines 213 are connected from the memory cell array to the row decoder circuit, and how bit lines (BL) 206 and 207 and common source lines (CSL) 208 are connected from the memory cell array to the column decoder circuit. This shows a case where three memory transistor groups are stacked. Figure 10-8 shows the AA cross section of Figure 10-7.

[0038] Figure 10-9 shows the potentials applied to eight memory cells in each of the two upper and lower layers when writing "0". Here too, the upper silicon layer (Layer 1) and the lower silicon layer (Layer 2) are assumed to be in the same location in a plan view, and MG and SG are shared. The CSL is shared by the left and right and the upper and lower memory cells. All memory cells connected to SG1, surrounded by dotted lines in Layer 1 and Layer 2, are simultaneously written to "0". Memory cells not connected to SG1 are not written to "0". A group of memory cells connected to a certain SG line is called a block here, and the number of memory cells connected to one block is the same as the group of memory cells in one page connected to one MG. The voltages applied to each node are shown in the table on the right and are the same as in the first embodiment.

[0039] In the manufacturing process of the second embodiment, only those differences from the manufacturing process of the first embodiment are listed. Figure 10-10 corresponds to the manufacturing process of the first embodiment of Figure 9-10, but a region 13-2 is provided to divide the gate material 10, which will later become the SG, into two. Figure 10-10 is a cross-sectional view taken along line B-B of Figure 10-10, and corresponds to the manufacturing process of Figure 9-11 of the first embodiment. The subsequent processes are the same as the manufacturing process of the first embodiment.

[0040] 11-1 to 11-7 show other embodiments of the present invention. In the first embodiment, the manufacturing process from FIG. 9-1 onward in which an insulating film and a silicon layer are stacked on a substrate is shown, but in the third embodiment, a method for stacking an insulating film and a silicon layer on a substrate is shown.

[0041] In Figure 11-1, a silicon germanium layer 101 and a silicon layer 102 are sequentially stacked on a silicon substrate 100. An insulating film 103 is then deposited on the top silicon layer, and a mask material 104 is then deposited on top of that. Next, as shown in Figure 11-2, the mask material 104 is patterned into multiple parallel strips. Using the mask material as a mask, the insulating film 103 and the stacked silicon germanium layer 101 and silicon layer 102 are etched, exposing the silicon substrate 100 at location 105. Next, a buffer film 106 is deposited, and the buffer film 106 is polished by surface polishing to expose the surface of the mask material 104, resulting in the shape shown in Figure 11-3. Next, only the even-numbered buffer layers from the left are etched to expose the silicon substrate surface, resulting in the shape shown in Figure 11-4. Location 107 in Figure 11-4 is etched. The silicon germanium layer 101 is then etched through the gaps in 107, resulting in the shape shown in Figure 11-5, which is an AA cross-sectional view of Figure 11-4. Here, the silicon germanium layer at 108 has been removed. Next, an insulating film 109 is deposited through the gap 107. Next, the insulating film at 107 is etched using the mask material 104 as a mask to expose the surface of the silicon substrate 100, resulting in the shape shown in FIG. 11-6. Next, the buffer layer at 106 is selectively etched to obtain the shape shown in FIG. 11-7. After this, the mask material 104 is removed, resulting in the same shape as that shown in FIG. 9-2 of the first embodiment 1. Alternatively, although not shown, both sides of each strip-shaped laminated film are sandwiched by buffer layers, and a mask material and the laminated film thereunder are patterned in the center of each strip-shaped laminated film, and the silicon substrate is exposed where the mask material and the laminated film are patterned. The silicon germanium compound layer is selectively removed from the etched portions, and then an insulating film is embedded in the gaps created by removing the silicon germanium compound layer from the spaces between the laminated strips. Furthermore, the insulating film deposited in areas other than the gaps in the laminated strips is removed by reactive ion etching, and then the remaining buffer layer is removed, thereby completing a plurality of strip-shaped laminated films of insulating films and silicon films on the silicon substrate. Thereafter, the source and drain diffusion layers, gate insulating films, memory gates, storage gates, source lines, bit lines, word lines, and storage gate lines are sequentially formed in this laminated film, thereby manufacturing a memory cell array. [Explanation of symbols]

[0042] 1 board 2. Insulating film 3. Intrinsic silicon semiconductor 4. Top insulating film 5 N-type or P-type silicon layer 6 Etching of the first laminated silicon layer and the insulating film layer 7 Etching of the second laminated silicon layer and insulating film layer 8 Etching of the third stacked silicon layer and insulating film layer 9 Gate insulating film 10 Gate material 11 Gate etching mask material 12 First gate material etching region 13 Second gate material etching region 14 First gate material removal section 15 Second gate material removal section 16 Third gate material removal section 17 Remaining first insulating film 18 Remaining second insulating film 19 Insulating film etching section 20 N-type or P-type silicon layer partial etching section 21 Metal layer formation 22 Metal layer removal section 23 Metal wiring 24 Insulating film forming section 25 Interlayer insulating film 26 Contact part 27 Storage gate wiring 28 Word line wiring 29 Interlayer insulating film 100 silicon substrate 101 Silicon germanium compound film 102 Intrinsic silicon membrane 103 Top insulating film 104 Mask material 105 Stacked film etching section 106 Buffer Film 107 Buffer film removal section 108 Silicon germanium compound film removal section 109 Insulating film deposit area 200 Storage Gate 201 Memory Gate 202 Gate insulating film 203 channel region 204 Drain diffusion layer 205 Source diffusion layer 206 upper bit line 207 bottom bit line 208 common source line 209 First insulating film 210 Second insulating film 211 Substrate 212 Word Line (WL) 213 Storage Gate Line (SGL) 300 SOI substrate 301 SiO2 layer 302 Floating Body 303 Source N + layer 304 Drain N + layer 305 Gate conductive layer 306 holes 307 Inversion Layer 309 Gate insulating film 310 memory cells 310-1 “1” state memory cell 310-2 “0” state memory cell

Claims

1. a semiconductor memory device comprising: two or more MOS transistors insulated from a substrate and arranged horizontally, stacked in multiple layers; an insulating film is laid between each transistor layer for insulation; each MOS transistor forms one memory cell; each memory cell has one silicon channel layer and a pair of source and drain diffusion layers made of N-type or P-type silicon sandwiching the silicon channel layer; the silicon channel layer, source and drain diffusion layers are all of the same thickness with no steps; a gate insulating film and gate conductor layer form a vertical pillar shared by each stacked MOS transistor layer, penetrating from the topmost MOS transistor layer to the bottommost MOS transistor; the gate conductor layer contacts the side of the silicon channel layer of each layer with a gate insulating film layer interposed therebetween; the threshold of the MOS transistor can be changed by whether or not a certain charge is stored in each silicon channel layer; and data can be read by detecting the threshold value.

2. 2. The semiconductor memory device according to claim 1, wherein the source diffusion layer of each layer is connected to a source line, while the drain diffusion layer is connected to a bit line, the source line and bit line pairs of each layer extend in parallel, the bit lines stacked in multiple layers are insulated from each other, the source lines and bit lines are connected to the source diffusion layers and drain diffusion layers of a plurality of memory cell groups, and the source lines and bit lines are connected to a column decoder that controls the bit lines and source lines of each layer at the end of the memory cell array.

3. 3. The semiconductor memory device according to claim 2, wherein two different gate conductor layers of vertical pillars sandwich two sides of a silicon channel layer of a MOS transistor on which a source diffusion layer and a drain diffusion layer are not disposed, an interlayer insulating film is provided on the MOS transistor in the uppermost layer, the gate conductor layers of the two different vertical pillars extend to an upper surface of the interlayer insulating film and are connected to two different gate wiring layers, respectively, the two gate wiring layers extend parallel to each other in a pair in a direction at an angle of 60 degrees to 90 degrees with respect to the bit line, the two gate wiring layers are connected to gates of a plurality of memory cell groups, and are connected to a row decoder at an end of the memory cell array that controls the voltage of the gate wiring.

4. 4. The semiconductor memory device according to claim 3, wherein the silicon channel layer of the MOS transistor stacked in multiple layers is sandwiched between the two gate conductor layers, and one of the gate conductor layers, which is the memory gate, extends to the ends of the source diffusion layer and the drain diffusion layer with the gate insulating film interposed therebetween, and the other gate conductor layer, which is the storage gate, has a shorter gate length and does not extend to the ends of the source diffusion layer and the drain diffusion layer.

5. 5. The semiconductor memory device according to claim 4, wherein the storage gate has two vertical pillar-shaped insulating films, different from the gate insulating film, disposed between the gate and the source diffusion layer and between the gate and the drain diffusion layer, respectively, so that the storage gate does not directly contact the source diffusion layer and the drain diffusion layer through the gate insulating film.

6. 6. The semiconductor memory device of claim 5, wherein each MOS transistor layer has a plurality of memory cells arranged in a row with a pair of source and bit lines sandwiched between them, two adjacent memory cells share one of the storage gates, the memory cell structure has the storage gate as an axis of inversion symmetry, the memory gates are arranged on both ends of the pair of memory cells, and another pair of memory cells are arranged further back, and a vertical pillar-shaped insulating film is sandwiched between the adjacent memory gates, insulating them from each other.

7. 6. The semiconductor memory device of claim 5, wherein each MOS transistor layer has a plurality of memory cells arranged in a row with a pair of source and bit lines sandwiched between them, and two adjacent memory cells have two different storage gates, and the memory cell structure has a columnar insulating film between the two storage gates as the axis of inversion symmetry, and the memory gates are arranged at both ends of the pair of memory cells, and another pair of memory cells are arranged further back, and a columnar insulating film is sandwiched between the adjacent memory gates, so that they are insulated from each other.

8. The semiconductor memory device of claim 5, wherein the ratio of the width of the silicon channel layer sandwiched between the memory gate and the storage gate to the width between the pillar-shaped insulating film different from the gate insulating film of claim 7 and the memory gate is between 1.8:1 and 2.2:1, and the respective widths of the former are in the range of 18 to 55 nanometers and the latter are in the range of 8 to 31 nanometers.

9. 5. The semiconductor memory device of claim 4, wherein when the source and drain diffusion layers are N-type silicon, "0" data is simultaneously written to all memory cells connected to a certain storage gate, and during the "0" data write operation, holes are removed from the silicon channel layer by applying a certain positive voltage to the storage gate connected to the selected memory cell, a certain positive voltage lower than the storage gate to the memory gate, and an even lower voltage than the storage gate to the bit line and source line, and when the source and drain diffusion layers are P-type silicon, electrons are removed from the silicon channel layer by applying a voltage with the opposite polarity to the voltage in the N-type case to the bit line, memory gate, and storage gate.

10. 5. The semiconductor memory device of claim 4, wherein when the source and drain diffusion layers are N-type silicon, "0" data is simultaneously written to all memory cells connected to a certain storage gate, and during the "0" data write operation, a voltage between 0.5V and 1.5V is applied to the storage gate connected to the selected memory cell, a voltage between 0.2V and 0.8V is applied to the memory gate, and 0V is applied to the bit line and source line, thereby removing holes from the silicon channel layer, and when the source and drain diffusion layers are P-type silicon, a voltage with the opposite polarity to that of the N-type is applied to the bit line, memory gate, and storage gate, thereby removing electrons from the silicon channel layer.

11. 5. A semiconductor memory device according to claim 4, wherein when the source and drain diffusion layers are N-type silicon, "1" data is written to a memory cell connected to a certain memory gate, and during the "1" data write operation, a certain positive voltage is applied to the selected memory gate, a certain negative voltage to the storage gate, a certain positive voltage to the bit line connected to the memory cell to which "1" data is written, 0V to the bit line connected to the memory cell to which "1" data is not written, and 0V to the source line, thereby accumulating holes in the silicon channel layer only in the "1" write cell, and when the source and drain diffusion layers are P-type silicon, electrons are accumulated in the silicon channel layer by applying a voltage with the opposite polarity to that of the N-type voltage to the bit line, memory gate, and storage gate.

12. 5. The semiconductor memory device of claim 4, wherein when the source and drain diffusion layers are N-type silicon, "1" data is written to a memory cell connected to a certain memory gate, and during the operation of writing "1" data, a voltage between 0.8V and 1.5V is applied to the selected memory gate, a voltage between -0.5V and -1.5V is applied to the storage gate, a voltage between 0.8V and 1.5V is applied to the bit line connected to the memory cell into which "1" data is written, 0V is applied to the bit line connected to the memory cell into which "1" data is not written, and 0V is applied to the source line, thereby accumulating holes in the silicon channel layer only in the cell into which "1" is written, and when the source and drain diffusion layers are P-type silicon, a voltage with the polarity reversed for the N-type case is applied to the bit line, memory gate, and storage gate, thereby accumulating electrons in the silicon channel layer.

13. When the source and drain diffusion layers are made of N-type silicon, when reading data from a memory cell connected to a certain memory gate, a certain positive voltage is applied to the memory gate, a certain negative voltage is applied to the storage gate paired with the memory gate, a certain positive voltage is applied to the bit line connected to the memory cell from which data is to be read, 0V is applied to the bit line connected to the memory cell from which data is not to be read, and 0V is applied to the source line, and the current flowing from the source line of the memory cell from which data is to be read to the bit line is detected. In the "1" state, the threshold is lower than in the "0" state, so more current flows, and the current difference is detected by the bit line connected to the 5. The semiconductor memory device according to claim 4, wherein the "0" and "1" data are read by detecting the "0" and "1" data with a sense amplifier circuit in a column decoder connected to the bit line, and when the source and drain diffusion layers are P-type silicon, a voltage with the polarity reversed for the N-type voltage is applied to the bit line, memory gate, and storage gate to detect the current flowing from the source line to the bit line. In the "1" state, the threshold is higher than in the "0" state, so more current flows, and the "0" and "1" data are read by detecting the current difference with a sense amplifier circuit in the column decoder to which the bit line is connected.

14. When the source and drain diffusion layers are made of N-type silicon, when reading data from a memory cell connected to a certain memory gate, a voltage between 0.6V and 1.3V is applied to the memory gate, a voltage between -0.5V and -1.5V is applied to the storage gate paired with the memory gate, a voltage between 0.2V and 0.6V is applied to the bit line connected to the memory cell from which data is to be read, 0V is applied to the bit line connected to the memory cell from which data is not to be read, and 0V is applied to the source line, and the current flowing from the source line of the memory cell from which data is to be read to the bit line is detected, but in the "1" state, the threshold is lower than in the "0" state, so more current flows. The semiconductor memory device of claim 4, wherein the "0" and "1" data are read by detecting the current difference with a sense amplifier circuit in a column decoder to which the bit line is connected, and when the source and drain diffusion layers are P-type silicon, a voltage with the polarity reversed from that of the N-type voltage is applied to the bit line, memory gate, and storage gate to detect the current flowing from the source line to the bit line, and since the threshold value is higher in the "1" state than in the "0" state, more current flows, and the "0" and "1" data are read by detecting the current difference with a sense amplifier circuit in a column decoder to which the bit line is connected.

15. A semiconductor memory device as described in claim 11, characterized in that when rewriting data in a certain memory cell, first "0" is written to all memory cells connected to the storage gate connected to that memory cell, and then "1" data is selectively written to memory cells connected to that memory cell.

16. 16. The semiconductor memory device of claim 15, wherein when the source and drain diffusion layers are N-type silicon, when writing or reading the "0" or "1" data to or from a memory cell connected to a certain memory gate, 0 V is applied to the memory gate connected to a group of unselected memory cells to which data is not written or read, and a certain negative voltage is applied to the storage gate; and when the source and drain diffusion layers are P-type silicon, a voltage with the opposite polarity to that of the N-type is applied to the bit line, memory gate, and storage gate.

17. 16. The semiconductor memory device of claim 15, wherein when the source and drain diffusion layers are N-type silicon, when writing or reading the "0" or "1" data to or from a memory cell connected to a certain memory gate, 0V is applied to the memory gate connected to a group of non-selected memory cells to which data is not written or read, and a voltage between -0.5V and -1.5V is applied to the storage gate; and when the source and drain diffusion layers are P-type silicon, a voltage with the opposite polarity to that of the N-type is applied to the bit line, memory gate, and storage gate.

18. 16. A semiconductor memory device as described in claim 15, wherein, when the source and drain diffusion layers are N-type silicon, a certain negative voltage is applied to the storage gate and 0V is applied to the memory gate, bit line, and source line during a standby period when data is not written or read, and when the source and drain diffusion layers are P-type silicon, a voltage with the opposite polarity to that of the N-type is applied to the bit line, memory gate, and storage gate.

19. A semiconductor memory device as described in claim 15, characterized in that if the device is left for a long time after data is written, the amount of charge stored in the silicon channel of the memory cell will change, so the data in the memory cell is read out within a certain period of time and the data is rewritten.

20. A silicon germanium compound layer is deposited on a silicon substrate, and then an intrinsic silicon semiconductor layer containing no N-type or P-type impurities is deposited. This process is then repeated several times, and then an insulating film is deposited on the stacked silicon germanium compound layer and silicon layer. Next, a mask material that is etch-resistant to the insulating film, silicon layer, and silicon germanium compound layer is deposited. Next, the mask material and the underlying stacked film are patterned into a plurality of strip shapes, and the silicon substrate is exposed where the mask material and stacked film are etched. Next, a buffer film is deposited, and then the surface of the mask material on top of the stacked film is exposed by surface polishing, thereby forming a strip-shaped stacked film and a buffer layer embedded in the spaces therebetween. Next, the buffer layer embedded in the spaces between each strip-shaped stacked film is 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein every other one of the stacked strips is removed, the silicon germanium compound layer is selectively removed from the spaces between the stacked strips from which the embedded buffer film has been removed, an insulating film is then filled into the gaps created by removing the silicon germanium compound layer from the spaces between the stacked strips, and any insulating film deposited in areas other than the gaps of the stacked strips is removed by reactive ion etching, and the remaining buffer layer is then removed, thereby forming a stacked film of multiple strip-shaped insulating films and silicon films on the silicon substrate, and then sequentially forming the source and drain diffusion layers, gate insulating film, memory gate, storage gate, source line, bit line, word line and storage gate line in this stacked film to manufacture a memory cell array.

21. A silicon germanium compound layer is deposited on a silicon substrate, and then an intrinsic silicon semiconductor layer containing no N-type or P-type impurities is deposited. This process is then repeated several times, and an insulating film is deposited on the stacked silicon germanium compound layer and silicon layer. Next, a mask material that is etch-resistant to the insulating film, silicon layer, and silicon germanium compound layer is deposited. Next, the mask material and the underlying stacked film are patterned into a plurality of strips, and the silicon substrate is exposed where the mask material and stacked film are etched. Next, a buffer film is deposited, and then the surface of the mask material on top of the stacked film is exposed by surface polishing, thereby forming a strip-shaped stacked film and a buffer layer embedded in the space between them. Next, the mask material and the underlying stacked film are patterned into a plurality of strips at the center of each strip-shaped stacked film sandwiched between buffer layers on both sides.

2. A method for manufacturing a semiconductor memory device according to claim 1, wherein a memory cell array is manufactured by patterning the silicon substrate at locations where the mask material and the laminated film have been etched, selectively removing the silicon germanium compound layer from the etched portions, filling gaps created by removing the silicon germanium compound layer from the spaces between the laminated strips with an insulating film, removing any insulating film deposited in areas other than the gaps between the laminated strips by reactive ion etching, and then removing the remaining buffer layer, thereby forming a plurality of rectangular-shaped laminated films of insulating films and silicon films on the silicon substrate, and then sequentially forming the source and drain diffusion layers, gate insulating films, memory gates, storage gates, source lines, bit lines, word lines, and storage gate lines in this laminated film.

22. 22. The method for manufacturing a semiconductor memory device according to claim 20, wherein a plurality of the insulating film layers and the silicon layers are sequentially stacked on a substrate, and an insulating film is deposited on the uppermost layer to form a laminated film patterned into the shape of a strip arranged side by side, and a silicon layer containing an acceptor or donor impurity for a source and drain diffusion layer is formed at an end of each silicon layer from a space in the short side direction between adjacent strips, and then patterning is performed from the top surface of the laminated film to form the gate insulating film and the gate conductor layer in a vertical columnar shape in the laminated film, and at least the silicon film layer at the bottom is removed in the etched portion of the laminated film, and then the gate insulating film is first deposited on the side and bottom of the etched portion of the laminated film, and then the gate conductor layer is deposited, and then the gate conductor layer and the gate insulating film are sequentially plane-polished to expose the surface of the insulating film at the top of the laminated film, and then the gate conductor layer is patterned from the top surface to form a memory gate and a storage gate, and then an insulating film is filled in the etched portion of the gate conductor layer to individually insulate each of the memory gates and the storage gates.

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