Display device

Abstract

To provide a display device suitable to high-gradation display.SOLUTION: There is provided a display device that has two drive transistors, a light-emitting device, and pixels, and the two drive transistors and light-emitting device are connected in series. One transistor is a p-channel type and the other transistor is an n-channel type, which are alternately driven. With this constitution, a gate-source voltage can be suppressed from fluctuating during high-gradation display. Further, a transistor which has metal oxide in a channel formation region is used as the n-channel type transistor to enhance display characteristics of low-gradation display.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, memory devices, imaging devices, and operation methods thereof or manufacturing methods thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device. [Background technology]

[0004] Techniques for constructing transistors using metal oxides formed on a substrate have been attracting attention. For example, Patent Documents 1 and 2 disclose techniques for using transistors using zinc oxide or In-Ga-Zn oxide as switching elements for pixels of display devices. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] In a display device using a light-emitting device such as an organic EL element, a drive transistor is connected to one electrode of the light-emitting device, and the luminance of the light-emitting device is controlled by the current passed by the drive transistor.

[0007] When an n-channel transistor is used as the drive transistor, the source of the drive transistor is connected to the anode of the light-emitting device. Here, the cathode potential (common potential) of the light-emitting device may fluctuate or exhibit position dependency due to influences such as electrode resistance in high-gradation display (high-brightness display). Fluctuations in the cathode potential change the Vgs (gate-source voltage) of the n-channel transistor. This can result in a discrepancy between the input image data and the brightness of the light-emitting device.

[0008] On the other hand, when a p-channel transistor is used as the driver transistor, the above problems can be avoided. However, transistors using general silicon for the channel formation region have a high off-state current and insufficient low-level potential (low gradation) transfer characteristics. Furthermore, they have a problem of low layout freedom, such as the need to increase the channel length in consideration of current magnitude control and saturation characteristics.

[0009] Therefore, an object of one embodiment of the present invention is to provide a display device suitable for wide-gray scale display, or to provide a display device with excellent display characteristics.

[0010] Another object is to provide a display device with low power consumption. Another object is to provide a display device with high reliability. Another object is to provide a novel display device or the like. Another object is to provide a method for operating the display device. Another object is to provide a novel semiconductor device or the like.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention relates to a display device suitable for wide gray scale display.

[0013] One embodiment of the present invention is a display device having a pixel including a first transistor, a second transistor, and a light-emitting device, in which one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, the other of the source or the drain of the second transistor is electrically connected to an anode of the light-emitting device, and the first transistor is a p-channel type and the second transistor is an n-channel type.

[0014] Preferably, the first transistor has silicon in a channel formation region, and the second transistor has a metal oxide in a channel formation region, the metal oxide including In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0015] The pixel may further include a third transistor, a fourth transistor, and a fifth transistor, wherein one of the source or the drain of the third transistor is electrically connected to the gate of the first transistor, one of the source or the drain of the fourth transistor is electrically connected to the gate of the second transistor, and one of the source or the drain of the fifth transistor is electrically connected to the other of the source or the drain of the second transistor.

[0016] The third transistor, the fourth transistor, and the fifth transistor each preferably have a metal oxide in a channel formation region, and the metal oxide preferably contains In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0017] The display device further includes a first circuit having a function of outputting a first data potential and a second data potential, one of the first data potential and the second data potential being equal to an input potential to the first circuit, the other of the first data potential and the second data potential being a potential obtained by binarizing the input potential, and one of the first data potential and the second data potential being input to a gate of the first transistor via a third transistor, and the other of the first data potential and the second data potential being input to a gate of the second transistor via a fourth transistor.

[0018] The first circuit has a CMOS inverter circuit having a p-channel transistor having silicon in a channel formation region and an n-channel transistor having a metal oxide in a channel formation region, and the metal oxide can include In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf). [Effects of the Invention]

[0019] By using one embodiment of the present invention, a display device suitable for wide gray scale display or a display device with excellent display characteristics can be provided.

[0020] Alternatively, a display device with low power consumption can be provided. Alternatively, a display device with high reliability can be provided. Alternatively, a novel display device or the like can be provided. Alternatively, a method for operating the display device can be provided. Alternatively, a novel semiconductor device or the like can be provided. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a diagram illustrating a pixel circuit. [Figure 2] 2A and 2B are diagrams illustrating a conventional pixel circuit. [Figure 3] Fig. 3A is a diagram illustrating a signal generating circuit, and Fig. 3B is a diagram illustrating a buffer circuit. [Figure 4] 4A and 4B are diagrams illustrating the output potential of a source driver and a buffer circuit, respectively. [Figure 5] FIG. 5 is a diagram illustrating the operation of the signal generating circuit and the pixel circuit. [Figure 6] FIG. 6 is a diagram illustrating the operation of the signal generating circuit and the pixel circuit. [Figure 7] FIG. 7 is a diagram illustrating a display device. [Figure 8] 8A to 8C are diagrams illustrating a display device. [Figure 9] 9A and 9B are diagrams illustrating a touch panel. [Figure 10] FIG. 10 is a diagram illustrating a display device. [Figure 11] 11A to 11C are diagrams illustrating transistors. [Figure 12] 12A to 12C are diagrams illustrating transistors. [Figure 13] 13A and 13B are diagrams illustrating a transistor. [Figure 14] 14A to 14F are diagrams illustrating an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be designated by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate in different drawings.

[0023] Furthermore, even if a circuit diagram shows a single element, that element may be configured as multiple elements as long as there is no functional problem. For example, multiple transistors operating as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0024] Furthermore, a single conductor may have multiple functions, such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Also, even when elements are shown as being directly connected to each other on a circuit diagram, in reality, the elements may be connected via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0025] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0026] One embodiment of the present invention is a display device including two transistors each functioning as a driving transistor and one light-emitting device (also referred to as a light-emitting element) in a pixel. The two transistors and the light-emitting device are connected in series. When one of the transistors operates as a driving transistor, the other transistor operates as a switch.

[0027] The two transistors are a combination of a p-channel transistor and an n-channel transistor. The p-channel transistor functions as a drive transistor when displaying high gradations (high brightness). At this time, the n-channel transistor is in a low-resistance, conductive state. The n-channel transistor also functions as a drive transistor when displaying low gradations (low brightness). At this time, the p-channel transistor is in a low-resistance, conductive state. This configuration makes it possible to suppress fluctuations in the gate-source voltage (Vgs) when displaying high gradations.

[0028] Furthermore, by using a transistor having a metal oxide in a channel formation region (hereinafter referred to as an OS transistor) as an n-channel transistor, the display characteristics of low gray scale display can be improved. OS transistors have the characteristic of extremely low off-state current.

[0029] The driving transistors can be switched according to a binary signal potential input to the pixel. The binary signal potential is generated by a signal generation circuit provided between the source driver and the pixel. The signal generation circuit outputs two signal potentials to the pixel: a data potential input from the source driver and a potential obtained by binarizing the data potential. The binary signal potential can be used as a gate potential to turn on a transistor operating as a switch with low resistance.

[0030] 1 is a circuit diagram of a pixel included in a display device of one embodiment of the present invention. A pixel 10 includes a transistor 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a capacitor 106, a capacitor 107, and a light-emitting device 108. Note that the transistor 105 may not be provided.

[0031] One of the source or drain of transistor 101 is electrically connected to one electrode of capacitor 106 and the gate of transistor 103. One of the source or drain of transistor 102 is electrically connected to one electrode of capacitor 107 and the gate of transistor 104. One of the source or drain of transistor 103 is electrically connected to one of the source or drain of transistor 104. The other of the source or drain of transistor 103 is electrically connected to the other electrode of capacitor 106. The other electrode of transistor 104 is electrically connected to the anode of light-emitting device 108, the other electrode of capacitor 107, and one of the source or drain of transistor 105.

[0032] The other of the source and the drain of the transistor 101 is electrically connected to a wiring 121. The other of the source and the drain of the transistor 102 is electrically connected to a wiring 122. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 123. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 124. The cathode of the light-emitting device 108 is electrically connected to a wiring 129. The gates of the transistors 101 and 102 are electrically connected to a wiring 125. The gate of the transistor 105 is electrically connected to a wiring 126.

[0033] The wirings 121 and 122 are source lines that connect the pixel 10 to a signal generating circuit 40 and a source driver 20, which will be described later. The wirings 123 and 129 are power supply lines, and the wiring 123 can be a high-potential power supply line, and the wiring 129 can be a low-potential power supply line. The wiring 124 is a wiring that supplies a reset potential (e.g., a low potential). The wirings 125 and 126 are gate lines that control the operation of the transistors connected to them.

[0034] Here, transistors 101, 102, and 105 function as switches. Transistors 103 and 104 function as drive transistors or switches for light-emitting device 108. Transistor 103 is a p-channel transistor, and transistor 104 is an n-channel transistor. Capacitors 106 and 107 function as storage capacitors. Note that although FIG. 1 illustrates transistors 101, 102, and 105 as n-channel transistors, they may also be p-channel transistors.

[0035] FIG. 2A is an example of a conventional pixel circuit, which includes three n-channel transistors (transistors 302, 304, and 305), a capacitor 307, and a light-emitting device 308.

[0036] The transistor 304 is a drive transistor, and a data potential is supplied to the gate of the transistor 304 via the transistor 302. At this time, a reset potential is supplied to the source of the transistor 304 via the transistor 305. In other words, since the gate potential can be supplied in a state where the source potential of the transistor 304 is stable, Vgs becomes an ideal value.

[0037] On the other hand, a display device has multiple light-emitting devices, whose cathodes are connected to a common electrode COM. If the common electrode COM is made of a transparent conductive film (such as indium tin oxide) that has a higher resistance than metal, a voltage drop may occur in the common electrode COM when a large current flows during high-gradation (high-brightness) display. Because the light-emitting device also functions as a constant-voltage element when emitting light, a change in the potential of the common electrode COM (the potential of the cathode) also changes the potential of the anode.

[0038] Ideally, Vgs is maintained by the capacitor 307, which is a storage capacitor, but due to the influence of the parasitic capacitance Cp added to the gate of the transistor 304, the amount of change in the gate potential of the transistor 304 is smaller than the amount of change in the source potential (anode potential). In other words, since Vgs becomes smaller, there is a problem that the desired brightness cannot be obtained.

[0039] FIG. 2B is another example of a conventional pixel circuit, which includes two p-channel transistors (transistor 301 and transistor 303), a capacitor 306, and a light-emitting device 309.

[0040] The transistor 303 is a drive transistor, and a data potential is supplied to the gate of the transistor 303 via the transistor 301. Here, the source of the transistor 303 is electrically connected to a power supply line 323, which can be a low-resistance metal wiring or the like, so that the source potential is always stable and Vgs is an ideal value.

[0041] However, p-channel transistors are generally formed of transistors that have silicon in the channel formation region (hereinafter referred to as Si transistors).Si transistors have a relatively high off-state current, which makes it difficult to transmit low-level potentials.As a result, there is a problem in that they cannot produce sufficient gradation when displaying low gradations (low brightness).

[0042] Furthermore, when Si transistors are used in pixel circuits, the channel length must be increased in consideration of current magnitude control, saturation characteristics, etc., resulting in a problem of low flexibility in layout.

[0043] One aspect of the present invention is a display device suitable for wide gray scale display, which can overcome the drawbacks of the conventional circuits and Si transistors described above.

[0044] In the display device of one embodiment of the present invention, the transistor 103 (a p-channel Si transistor) is used as a driving transistor for high gradation display. The transistor 104 (an n-channel OS transistor) is used as a driving transistor for low gradation (low luminance) display. The transistors 101, 102, and 105 may be Si transistors or OS transistors.

[0045] With this configuration, it is possible to suppress the change in Vgs that occurs in high gradation display when n-channel transistors are used as drive transistors, and it is possible to improve the display quality of high gradation.

[0046] Furthermore, because high-gradation display requires a relatively large current for control, it is not necessary to increase the channel length and suppress the current. In other words, transistors with short channel lengths can be used, which increases the degree of freedom in layout. Furthermore, even if Si transistors with a relatively high off-state current are used, the display is not affected.

[0047] The channel formation region of a Si transistor can be made of amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. Note that when a transistor is provided on an insulating surface such as a glass substrate and the transistor is a p-channel type, polycrystalline silicon is preferably used.

[0048] High-quality polycrystalline silicon can be easily obtained by using a laser crystallization process or the like, and high-mobility transistors can be formed even in p-channel transistors. High-quality polycrystalline silicon can also be obtained by a solid-phase epitaxy method in which a metal catalyst such as nickel or palladium is added to amorphous silicon and then heated. Polycrystalline silicon formed by a solid-phase epitaxy using a metal catalyst may be irradiated with a laser to further enhance its crystallinity. Because the metal catalyst remains in the polycrystalline silicon and deteriorates the electrical characteristics of the transistor, it is preferable to provide a region to which phosphorus or a rare gas is added outside the channel formation region and capture the metal catalyst in that region.

[0049] In low-gradation display, an n-channel transistor is used as the driving transistor. In displays with many low-gradation areas, the current flowing through the entire pixel of the display device is relatively small, so voltage drop in the common electrode connected to the cathode of the light-emitting device is unlikely to occur. In other words, the effect of the change in Vgs described above can be ignored. In addition, it is preferable to use an OS transistor as the n-channel transistor.

[0050] Because OS transistors have a large energy gap in their semiconductor layers, they can exhibit extremely low off-current characteristics of several yA / μm (current value per 1 μm of channel width). This improves the low-level potential transmission characteristics compared to when Si transistors are used as drive transistors, thereby improving the display quality of low gradations.

[0051] It is also preferable to use OS transistors for the transistors 101 and 102. The low off-state current of OS transistors allows the gate potential of the driving transistors (the transistors 103 and 104) to be held for a long time. Therefore, an image can be held even if the frame frequency is lowered. For example, the power consumption of the display device can be reduced by using a first frame frequency (e.g., 60 Hz or higher) for displaying moving images and switching to a second frame frequency (e.g., about 1 to 10 Hz) lower than the first frame frequency for displaying still images.

[0052] To obtain the effect of one embodiment of the present invention, the above structure is not limitative, and all the transistors included in a pixel may be formed using Si transistors or OS transistors.

[0053] The semiconductor material used for an OS transistor can be a metal oxide with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. A typical example is an oxide semiconductor containing indium, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors that prioritize reliability. Furthermore, CAC-OS exhibits high mobility, making it suitable for transistors that operate at high speed.

[0054] OS transistors have characteristics different from Si transistors, such as being free from impact ionization, avalanche breakdown, and short-channel effects, and can form highly reliable circuits. OS transistors also have fewer variations in electrical characteristics due to non-uniformity of crystallinity, which is a problem with Si transistors.

[0055] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn oxide containing indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn oxide can typically be formed by a sputtering method. Alternatively, it may be formed by an atomic layer deposition (ALD) method.

[0056] The atomic ratio of the metal elements in a sputtering target used to form an In-M-Zn-based oxide by sputtering preferably satisfies In≧M and Zn≧M. Preferred atomic ratios of the metal elements in such sputtering targets are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratios of the semiconductor layer to be formed each have a variation of ±40% of the atomic ratio of the metal elements contained in the sputtering target.

[0057] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 or less, more preferably 1 × 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 or less, more preferably 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 An oxide semiconductor having a carrier density above or equal to this can be used. Such an oxide semiconductor is called a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and stable characteristics.

[0058] Note that the present invention is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0059] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase, resulting in n-type conductivity. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0060] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, it may generate carriers, which may increase the off-state current of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0061] Furthermore, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons acting as carriers are generated, increasing the carrier density and making the semiconductor layer more likely to be n-type. As a result, transistors using oxide semiconductors that contain nitrogen tend to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0062] Furthermore, if hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it may react with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors and generate electrons that serve as carriers. Furthermore, some of the hydrogen may bond with oxygen that is bonded to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0063] Defects in which hydrogen has entered oxygen vacancies can function as donors in oxide semiconductors. However, it is difficult to quantitatively evaluate such defects. Therefore, in oxide semiconductors, defects are sometimes evaluated by carrier concentration rather than donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0064] Therefore, it is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0065] The semiconductor layer may also have a non-single-crystal structure. Examples of the non-single-crystal structure include a c-axis aligned crystalline oxide semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. Among non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0066] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain any crystalline components, or an amorphous oxide film has, for example, a completely amorphous structure and does not contain any crystalline parts.

[0067] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single-crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0068] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single-crystal semiconductor layer.

[0069] CAC-OS is a material in which, for example, elements constituting an oxide semiconductor are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0070] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0071] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into mosaics, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter also referred to as a cloud-like structure).

[0072] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0073] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0074] The crystalline compounds have a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals are connected together with their c-axis orientation and no orientation in the ab plane.

[0075] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. CAC-OS is a material structure containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, the crystal structure is a secondary element in CAC-OS.

[0076] Note that CAC-OS does not include a stacked structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0077] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary between the region where the main component is the chromatic aberration and the region where the chromatic aberration is the main component may not be observed.

[0078] When one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are contained instead of gallium, the CAC-OS has a structure in which some regions observed to be nanoparticles containing the metal element as the main component and some regions observed to be nanoparticles containing In as the main component are randomly dispersed in a mosaic pattern.

[0079] The CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When the CAC-OS is formed by a sputtering method, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the better. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0080] CAC-OS has the characteristic that no clear peaks are observed when measured using the θ / 2θ scan by the out-of-plane X-ray diffraction (XRD) method, which indicates that the ab-plane and c-axis orientations of the measured region are not observed.

[0081] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nanobeam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern indicates that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0082] For example, in the case of CAC-OS made of In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 It can be seen that the region where the main component is the crystalline silicon is unevenly distributed and mixed.

[0083] CAC-OS has a different structure from IGZO compounds, in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The structure is such that the regions are separated into a mosaic of regions each containing one of the elements as the main component and a region each containing one of the elements as the main component.

[0084] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is exhibited. X2 Zn Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud-like shape in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0085] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InOX1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing the above as a main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0086] Therefore, when CAC-OS is used in semiconductor devices, GaO X3 Insulation due to X2 Zn Y2 O Z2 , or InO X1 The conductivity due to the gate insulating layer and the gate insulating layer work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ) can be achieved.

[0087] Furthermore, semiconductor devices using CAC-OS have high reliability, making them suitable as a constituent material for various semiconductor devices.

[0088] When the transistor 103 is used as a driving transistor in high gradation display, the transistor 104 acts as a resistor. Therefore, a gate potential is supplied to the transistor 104 to bring the transistor 104 into a low-resistance conducting state (switch-on state). When the transistor 104 is used as a driving transistor in low gradation display, the transistor 103 acts as a resistor. Therefore, a gate potential is supplied to the transistor 103 to bring the transistor 103 into a low-resistance conducting state (switch-on state).

[0089] In this way, a data potential for display and a potential for switching are supplied to the pixel 10. In one embodiment of the present invention, a signal generation circuit can be used to generate a potential for switching based on a data potential supplied from a source driver.

[0090] 3A is a diagram illustrating a signal generation circuit 40 electrically connected between the source driver 20 and the pixel 10. The signal generation circuit 40 includes a circuit 40a and a circuit 40b.

[0091] The circuit 40a outputs the generated signal potential to the wiring 121. That is, the circuit 40a is a circuit for generating a signal potential to control the transistor 103. The circuit 40b outputs the generated signal potential to the wiring 122. That is, the circuit 40b is a circuit for generating a signal potential to control the transistor 104.

[0092] The circuit 40a includes a buffer circuit 41a and a selection circuit 45a. The buffer circuit 41a may have a configuration in which an even number of CMOS inverter circuits 42 are connected in series, as shown in FIG. 3B. The CMOS inverter circuit 42 may have a configuration in which a p-channel transistor 43p and an n-channel transistor 43n are connected in series. While FIG. 3B shows a configuration in which two CMOS inverter circuits 42 are connected in series, an even number of four or more stages may also be used.

[0093] The selection circuit 45a includes an inverter circuit 46a, a transistor 47a, and a transistor 48a. The output terminal of the source driver 20 is electrically connected to one of the source and drain of the transistor 47a and the input terminal of the buffer circuit 41a. The output terminal of the buffer circuit 41a is electrically connected to the gate of the transistor 47a, one of the source and drain of the transistor 48a, and the input terminal of the inverter circuit 46a. The output terminal of the inverter circuit 46b is electrically connected to the gate of the transistor 48a. The other of the source and drain of the transistor 47a and the other of the source and drain of the transistor 48a are electrically connected to the wiring 121.

[0094] The circuit 40b includes a buffer circuit 41b and a selection circuit 45b. The buffer circuit 41b can have the same configuration as the buffer circuit 41a.

[0095] The selection circuit 45b includes an inverter circuit 46b, a transistor 47b, and a transistor 48b. The output terminal of the source driver 20 is electrically connected to one of the source and drain of the transistor 48b and an input terminal of a buffer circuit 41b. The output terminal of the buffer circuit 41b is electrically connected to the gate of the transistor 47b, one of the source and drain of the transistor 47b, and an input terminal of the inverter circuit 46b. The output terminal of the inverter circuit 46b is electrically connected to the gate of the transistor 48b. The other of the source and drain of the transistor 47b and the other of the source and drain of the transistor 48b are electrically connected to a wiring 122.

[0096] The signal generation circuit 40 can be formed using Si transistors. Alternatively, the p-channel transistors in the signal generation circuit 40 may be formed using Si transistors, and the n-channel transistors may be formed using OS transistors. When the transistor 104 used in the pixel 10 is an OS transistor, using an OS transistor as the n-channel transistor in the signal generation circuit 40 eliminates the need for a step of forming an n-channel transistor using Si transistors, thereby reducing manufacturing costs.

[0097] The potential input to the signal generation circuit 40 is the data potential output by the source driver 20, and the buffer circuits 41a and 41b have the function of binarizing the data potential. Therefore, the data potential and a potential obtained by binarizing the data potential are input to the selection circuits 45a and 45b. At this time, the signal potentials output by the signal generation circuit 40 (selection circuits 45a and 45b) are shown in Table 1.

[0098] [Table 1]

[0099] If the output potential of the selection circuit 45a and the output potential of the selection circuit 45b relative to the input potential of the signal generation circuit 40 are the same as those in Table 1, a circuit other than that shown in FIG. 3A may be used as the signal generation circuit 40.

[0100] Here, "DataH" and "DataL" are data potentials (image data). FIG. 4A is a diagram showing the relationship between the display gradation and the output potential of the source driver 20. The output potential on the low gradation side is "DataL" and the output potential on the high gradation side is "DataH". Note that in FIG. 4A, the boundary between the two is set to a gradation near the center, but the boundary between the two may also be set to a gradation lower or higher than the gradation.

[0101] "DataL" is a data potential input to the gate of the transistor 104, which is an n-channel transistor. Therefore, the gray scale and the output potential are proportional to each other, and the higher the gray scale, the larger the output potential. "DataH" is a data potential input to the gate of the transistor 103, which is a p-channel transistor. Therefore, the gray scale and the output potential are inversely proportional to each other, and the higher the gray scale, the smaller the output potential.

[0102] The “DataH” output from the selection circuit 45 a and the “DataL” output from the selection circuit 45 b are at a potential equivalent to the output potential of the source driver 20 .

[0103] Furthermore, "H" is a binarized high-level potential, and "L" is a binarized low-level potential. FIG. 4B is a diagram showing the output characteristics of the buffer circuit 41a or the buffer circuit 41b. The input data is a data potential output by the source driver 20, and when the above-mentioned "DataL" is input, a binarized potential "L" is output by the operation of the two-stage inverter. When "DataH" is input, a binarized potential "H" is output by the operation of the two-stage inverter.

[0104] The potential "L" output from the selection circuit 45a and the potential "H" output from the selection circuit 45b are potentials obtained by binarizing the data potential output by the source driver 20 in the buffer circuit 41a or the buffer circuit 41b. The magnitude relationship between "DataH", "DataL", "H", and "L" is "L"≦"DataL"<"DataH"≦"H".

[0105] 5 is a diagram showing the operation of the signal generation circuit 40 and the pixel 10 when the data potential output by the source driver 20 is “DataH” (high gradation). As shown in Table 1, when the data potential “DataH” is input from the source driver 20 to the signal generation circuit 40, the signal generation circuit 40 outputs the data potential “DataH” to the wiring 121 and outputs a potential “H” to the wiring 122.

[0106] The data potential "DataH" is input to the gate of the transistor 103 via the transistor 101, and the transistor 103 passes a current corresponding to the data potential "DataH." The potential "H" is input to the gate of the transistor 104 via the transistor 102. At this time, the transistor 104 is an n-channel transistor and is therefore in a conducting state with low resistance.

[0107] That is, the transistor 103 acts as a driving transistor for the light-emitting device 108, and the transistor 104 acts as a switch.

[0108] Here, since the transistor 104 does not function as a drive transistor, even if the potential of the anode of the light-emitting device 108 changes during high gradation display and Vgs changes, the display is not affected. Therefore, the display quality during high gradation display can be improved.

[0109] 6 is a diagram showing the operation of the signal generation circuit 40 and the pixel 10 when the data potential output by the source driver 20 is “DataL” (low gradation). As shown in Table 1, when the data potential “DataL” is input from the source driver 20 to the signal generation circuit 40, the signal generation circuit 40 outputs a potential “L” to the wiring 121 and outputs the data potential “DataL” to the wiring 122.

[0110] The potential "L" is input to the gate of the transistor 103 via the transistor 101. At this time, the transistor 103 is a p-channel transistor and is therefore in a low-resistance conducting state. The data potential "DataL" is input to the gate of the transistor 104 via the transistor 102, and the transistor 104 passes a current according to the data potential "DataL."

[0111] That is, the transistor 103 acts as a switch, and the transistor 104 acts as a driving transistor for the light-emitting device 108 .

[0112] Here, by using an OS transistor with low off-state current as the transistor 104, the gradation performance in low gradation display can be improved. That is, in the display device of one embodiment of the present invention, the display quality can be improved from low gradation to high gradation.

[0113] 7 is a diagram illustrating a display device according to one embodiment of the present invention. The display device includes a pixel array 11, a source driver 20, a gate driver 30, and a signal generation circuit 40. The pixel array 11 includes pixels 10 arranged in the column and row directions. Each pixel 10 includes two driving transistors described in this embodiment. Note that the wiring is illustrated simply, and wiring is provided to connect to the elements included in the pixel 10 according to one embodiment of the present invention.

[0114] The source driver 20 and the gate driver 30 may be implemented using sequential circuits such as shift registers.

[0115] The source driver 20 and the gate driver 30 may be formed by externally attaching IC chips using a COF (chip on film) method, a COG (chip on glass) method, a TCP (tape carrier package) method, etc. Alternatively, the source driver 20 and the gate driver 30 may be fabricated on the same substrate as the pixel array 11 using transistors fabricated using the same process as the pixel array 11.

[0116] Although an example in which the gate driver 30 is arranged on one side of the pixel array 11 is shown, two gate drivers 30 may be arranged facing each other across the pixel array 11 to divide the driving rows.

[0117] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes.

[0118] (Embodiment 2) In this embodiment, a configuration example of a display device using a light-emitting device will be described. Note that in this embodiment, the description of the elements, operations, and functions of the display device described in the first embodiment will be omitted.

[0119] The display device described in this embodiment can be applied to the pixels 10 and signal generation circuit 40 described in Embodiment 1. Note that the scanning line driving circuit described below corresponds to a gate driver, and the signal line driving circuit corresponds to a source driver.

[0120] 8A to 8C show the structure of a display device to which one embodiment of the present invention can be applied.

[0121] In FIG. 8A, a sealant 4005 is provided so as to surround a display portion 215 provided over a first substrate 4001 , and the display portion 215 is sealed by the sealant 4005 and a second substrate 4006 .

[0122] 8A, the scan line driver circuit 221a, the signal line driver circuit 231a, the signal line driver circuit 232a, and the common line driver circuit 241a each include a plurality of integrated circuits 4042 provided on a printed board 4041. The integrated circuits 4042 are formed using a single crystal semiconductor or a polycrystalline semiconductor. The common line driver circuit 241a has a function of supplying a specified potential to the wirings 123, 124, and 129 described in Embodiment 1.

[0123] Various signals and potentials are supplied to the scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal line driving circuit 232a via an FPC (Flexible printed circuit) 4018.

[0124] The integrated circuits 4042 included in the scan line driver circuit 221a and the common line driver circuit 241a have a function of supplying selection signals to the display portion 215. The integrated circuits 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a have a function of supplying image data to the display portion 215. The integrated circuits 4042 are mounted in a region on the first substrate 4001 that is different from a region surrounded by the sealant 4005.

[0125] The method for connecting the integrated circuit 4042 is not particularly limited, and wire bonding, COF, COG, TCP, etc. may be used.

[0126] 8B shows an example in which the integrated circuit 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a is mounted by the COG method. In addition, a part or the whole of the driver circuit can be integrally formed on the same substrate as the display unit 215 to form a system-on-panel.

[0127] 8B shows an example in which the scanning line driving circuit 221a and the common line driving circuit 241a are formed on the same substrate as the display unit 215. By forming the driving circuits simultaneously with the pixel circuits in the display unit 215, the number of components can be reduced, thereby improving productivity.

[0128] 8B, a sealant 4005 is provided to surround the display portion 215, the scanning line driver circuit 221a, and the common line driver circuit 241a, which are provided on a first substrate 4001. A second substrate 4006 is provided on the display portion 215, the scanning line driver circuit 221a, and the common line driver circuit 241a. Therefore, the display portion 215, the scanning line driver circuit 221a, and the common line driver circuit 241a are sealed together with the display device by the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0129] 8B shows an example in which the signal line driver circuit 231a and the signal line driver circuit 232a are formed separately and mounted on the first substrate 4001, but this configuration is not limiting. The scanning line driver circuit may be formed separately and mounted, or a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Furthermore, as shown in FIG. 8C, the signal line driver circuit 231a and the signal line driver circuit 232a may be formed on the same substrate as the display unit 215.

[0130] Furthermore, a display device may include a panel in which a display device is sealed, and a module in which an IC including a controller and the like are mounted on the panel.

[0131] The display portion and the scan line driver circuit provided over the first substrate include a plurality of transistors, and the Si transistor or the OS transistor described in Embodiment 1 can be used as the transistors.

[0132] The transistors included in the peripheral driver circuit and the transistors included in the pixel circuits of the display area may have the same structure or different structures. The transistors included in the peripheral driver circuit may all have the same structure, or may have two or more types of transistors. Similarly, the transistors included in the pixel circuits may all have the same structure, or may have two or more types of transistors.

[0133] An input device 4200 can be provided over the second substrate 4006. The display device illustrated in FIGS. 8A to 8C provided with the input device 4200 can function as a touch panel.

[0134] There is no limitation on the sensing device (also referred to as a sensor element) included in the touch panel of one embodiment of the present invention. Various sensors that can detect the proximity or contact of a sensed object such as a finger or a stylus can be used as the sensing device.

[0135] As the sensor type, various types can be used, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure sensitive type.

[0136] In this embodiment, a touch panel having a capacitance type detection device will be described as an example.

[0137] The capacitance type includes a surface capacitance type, a projected capacitance type, etc. The projected capacitance type includes a self-capacitance type, a mutual capacitance type, etc. The mutual capacitance type is preferable because it enables simultaneous multi-point detection.

[0138] The touch panel of one embodiment of the present invention can have various configurations, such as a configuration in which a display device and a detection device that are separately manufactured are attached to each other, or a configuration in which electrodes that constitute a detection device are provided on one or both of a substrate that supports a display device and an opposing substrate.

[0139] 9A and 9B show an example of a touch panel. Fig. 9A is a perspective view of a touch panel 4210. Fig. 9B is a perspective schematic view of an input device 4200. For clarity, only representative components are shown.

[0140] The touch panel 4210 has a configuration in which a display device and a detection device that are separately manufactured are bonded together.

[0141] The touch panel 4210 has an input device 4200 and a display device, which are provided one on top of the other.

[0142] The input device 4200 has a substrate 4263, an electrode 4227, an electrode 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. Furthermore, the electrode 4228 can be electrically connected to the wiring 4239. The FPC 4272b is electrically connected to each of the plurality of wirings 4237 and the plurality of wirings 4238. The FPC 4272b can be provided with an IC 4273b.

[0143] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is provided between the first substrate 4001 and the second substrate 4006, an optical touch sensor using a photoelectric conversion element may be used in addition to a capacitive touch sensor.

[0144] Fig. 10 is a cross-sectional view of the portion indicated by the chain line N1-N2 in Fig. 8B. Fig. 10 shows an example of a display device using a light-emitting device as a display device. The display device has an electrode 4015, which is electrically connected to a terminal of an FPC 4018 via an anisotropic conductive layer 4019. In Fig. 10, the electrode 4015 is electrically connected to a wiring 4014 through openings formed in insulating layers 4112, 4111, and 4110.

[0145] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030 , and the wiring 4014 is formed from the same conductive layer as the source and drain electrodes of the transistor 4010 and the transistor 4011 .

[0146] The display portion 215 and the scanning line driver circuit 221a provided over the first substrate 4001 each include a plurality of transistors, and a transistor 4010 included in the display portion 215 and a transistor 4011 included in the scanning line driver circuit 221a are shown as examples. Note that although bottom-gate transistors are shown as examples of the transistors 4010 and 4011 in FIG. 10, they may also be top-gate transistors.

[0147] An insulating layer 4112 is provided over the transistor 4010 and the transistor 4011. A partition wall 4510 is formed over the insulating layer 4112.

[0148] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to form an opening over the first electrode layer 4030 using a photosensitive resin material so that the side surface of the opening becomes an inclined surface having a continuous curvature.

[0149] The transistors 4010 and 4011 are provided over an insulating layer 4102. The transistors 4010 and 4011 each include an electrode 4017 formed over an insulating layer 4111. The electrode 4017 can function as a backgate electrode.

[0150] The display device also includes a capacitor 4020. In this example, the capacitor 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, an insulating layer 4103, and electrodes formed in the same process as the source electrode and the drain electrode of the transistor 4010. The structure of the capacitor 4020 is not limited thereto, and the capacitor 4020 may be formed using other conductive layers and insulating layers.

[0151] The display device also includes an insulating layer 4111 and an insulating layer 4104. Insulating layers that are less permeable to impurity elements are used as the insulating layer 4111 and the insulating layer 4104. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, it is possible to prevent impurities from entering from the outside.

[0152] The transistor 4010 provided in the display portion 215 is electrically connected to a display device. A light-emitting device can be used as the display device. For example, an EL device that uses electroluminescence can be used as the light-emitting device. The EL device has a layer containing a light-emitting compound between a pair of electrodes (also referred to as an "EL layer"). When a potential difference greater than the threshold voltage of the EL device is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting compound contained in the EL layer emits light.

[0153] The EL device may be, for example, an organic EL device or an inorganic EL device. Note that an LED (including a micro LED) that uses a compound semiconductor as a light-emitting material is also an EL element, and an LED may also be used.

[0154] In addition to the light-emitting compound, the EL layer may contain a substance with high hole-injection properties, a substance with high hole-transport properties, a hole-blocking material, a substance with high electron-transport properties, a substance with high electron-injection properties, or a bipolar substance (a substance with high electron-transport properties and high hole-transport properties).

[0155] The EL layer can be formed by a method such as a vapor deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0156] Inorganic EL devices are classified into dispersion-type inorganic EL devices and thin-film inorganic EL devices based on their element structure. Dispersion-type inorganic EL devices have an emitting layer in which particles of emitting material are dispersed in a binder, and their emission mechanism is donor-acceptor recombination emission, which utilizes donor and acceptor levels. Thin-film inorganic EL devices have a structure in which an emitting layer is sandwiched between dielectric layers, which are in turn sandwiched between electrodes, and their emission mechanism is localized emission, which utilizes inner-shell electron transitions of metal ions. Note that here we will use an organic EL device as the light-emitting device to explain.

[0157] A light-emitting device only needs to have at least one of a pair of electrodes transparent to extract light. A transistor and a light-emitting device are formed on a substrate, and light-emitting devices can be of a top-emission structure in which light is extracted from the surface opposite the substrate, a bottom-emission structure in which light is extracted from the surface facing the substrate, or a dual-emission structure in which light is extracted from both surfaces. Any of these emission structures can be used.

[0158] If necessary, optical members (optical substrates) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing member, a phase difference member, and an anti-reflection member may be provided as appropriate.

[0159] Materials that can be used for the light-shielding layer include carbon black, titanium black, metals, metal oxides, and composite oxides containing solid solutions of multiple metal oxides. The light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. The light-shielding layer may also be a laminated film of films containing the material of the colored layer. For example, a laminated structure may be used in which a film containing the material used for a colored layer that transmits light of one color and a film containing the material used for a colored layer that transmits light of another color. Using a common material for the colored layer and the light-shielding layer is preferred because it allows for the use of common equipment and simplifies the process.

[0160] Materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, etc. The light-shielding layer and the colored layer can be formed, for example, by using an inkjet method or the like.

[0161] A light-emitting device 4513, which is a display device, is electrically connected to a transistor 4010 provided in the display portion 215. Note that the light-emitting device 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, but is not limited to this structure. The structure of the light-emitting device 4513 can be changed as appropriate depending on the direction of light extracted from the light-emitting device 4513, etc.

[0162] The light-emitting layer 4511 may be configured as either a single layer or a stack of multiple layers.

[0163] The color of light emitted from the light-emitting device 4513 can be white, red, green, blue, cyan, magenta, yellow, or the like, depending on the material that makes up the light-emitting layer 4511 .

[0164] There are two methods for achieving color display: combining a light-emitting device 4513 that emits white light with a colored layer, and providing a light-emitting device 4513 that emits a different color for each pixel. The former method is more productive than the latter. On the other hand, the latter method requires a different light-emitting layer 4511 to be produced for each pixel, making it less productive than the former method. However, the latter method can produce an emitted color with higher color purity than the former method. In addition to the latter method, the color purity can be further improved by providing a microcavity structure to the light-emitting device 4513.

[0165] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. For example, quantum dots can be used in the light-emitting layer to function as a light-emitting material.

[0166] A protective layer may be formed over the second electrode layer 4031 and the partition wall 4510 to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting device 4513. Silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed as the protective layer. A filler 4514 is provided in the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 to seal the space. In this way, it is preferable to package (enclose) the light-emitting device 4513 with a protective film (such as a lamination film or an ultraviolet-curable resin film) or a cover material that is highly airtight and has little degassing properties to prevent exposure to the outside air.

[0167] In addition to an inert gas such as nitrogen or argon, ultraviolet curing resin or thermosetting resin can be used as filler 4514, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), EVA (ethylene vinyl acetate), etc. can be used. Also, filler 4514 may contain a desiccant.

[0168] The sealing material 4005 may be a glass material such as glass frit, a curable resin that cures at room temperature such as a two-component mixed resin, a photocurable resin, a thermosetting resin, or other resin material. The sealing material 4005 may also contain a desiccant.

[0169] If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be provided on the light-emitting surface of the light-emitting device. An anti-reflection film may also be provided on the polarizing plate or circular polarizing plate. For example, an anti-glare treatment can be applied to the surface, which diffuses reflected light by using unevenness to reduce glare.

[0170] Furthermore, by using a microcavity structure for the light-emitting device, it is possible to extract light with high color purity. Furthermore, by combining the microcavity structure with a color filter, it is possible to reduce glare and improve the visibility of the displayed image.

[0171] The translucency and reflectivity of the first and second electrode layers (also called pixel electrode layers, common electrode layers, counter electrode layers, etc.) that apply voltage to the display device can be selected depending on the direction of the light to be extracted, the location where the electrode layers are provided, and the pattern structure of the electrode layers.

[0172] For the first electrode layer 4030 and the second electrode layer 4031, a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

[0173] In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or alloys thereof, or metal nitrides thereof.

[0174] The first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer. As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples of the conductive polymer include polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, and a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof.

[0175] In addition, since the transistor is easily damaged by static electricity, etc., it is preferable to provide a protection circuit for protecting the driver circuit, and the protection circuit is preferably configured using a nonlinear element.

[0176] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes.

[0177] (Embodiment 3) In this embodiment, examples of transistors that can be used in place of the transistors described in the above embodiment modes will be described with reference to the drawings.

[0178] The display device of one embodiment of the present invention can be manufactured using various types of transistors such as bottom-gate transistors and top-gate transistors, and therefore, the materials of the semiconductor layers and the transistor structures used can be easily replaced to suit existing manufacturing lines.

[0179] [Bottom-gate transistor] 11A is a cross-sectional view in the channel length direction of a channel protective transistor 810, which is a type of bottom-gate transistor. In FIG. 11A, the transistor 810 is formed over a substrate 771. The transistor 810 has an electrode 746 over the substrate 771 with an insulating layer 772 interposed therebetween. The transistor 810 also has a semiconductor layer 742 over the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer.

[0180] The semiconductor device also has an insulating layer 741 over a channel formation region of the semiconductor layer 742. An electrode 744a and an electrode 744b are formed over the insulating layer 741 and in contact with part of the semiconductor layer 742. The electrode 744a can function as either a source electrode or a drain electrode. The electrode 744b can function as the other of the source electrode and the drain electrode. Part of the electrode 744a and part of the electrode 744b are formed over the insulating layer 741.

[0181] The insulating layer 741 can function as a channel protective layer. Providing the insulating layer 741 over the channel formation region can prevent the semiconductor layer 742 from being exposed when the electrodes 744a and 744b are formed. Therefore, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrodes 744a and 744b are formed.

[0182] The transistor 810 further includes an insulating layer 728 over the electrode 744 a, the electrode 744 b, and the insulating layer 741 , and an insulating layer 729 over the insulating layer 728 .

[0183] When an oxide semiconductor is used for the semiconductor layer 742, it is preferable to use a material that can remove oxygen from a part of the semiconductor layer 742 and generate oxygen vacancies in at least portions of the electrode 744a and the electrode 744b that are in contact with the semiconductor layer 742. The carrier concentration in the region where oxygen vacancies occur in the semiconductor layer 742 increases, and the region becomes n-type, forming an n-type region (n + Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, examples of a material that can remove oxygen from the semiconductor layer 742 and cause oxygen vacancies include tungsten and titanium.

[0184] The formation of the source and drain regions in the semiconductor layer 742 can reduce contact resistance between the semiconductor layer 742 and the electrodes 744a and 744b, and can improve the electrical characteristics of the transistor, such as field-effect mobility and threshold voltage.

[0185] When a semiconductor such as silicon is used for the semiconductor layer 742, a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.

[0186] The insulating layer 729 is preferably formed using a material that has a function of preventing or reducing diffusion of impurities into the transistor from the outside. Note that the insulating layer 729 can be omitted as necessary.

[0187] An electrode 723 that can function as a back gate electrode is provided over the insulating layer 729. The electrode 723 can be formed using a material and a method similar to those of the electrode 746. Note that a structure in which the electrode 723 is not provided is also possible.

[0188] Generally, a back gate electrode is formed of a conductive layer and is arranged so that the gate electrode and the back gate electrode sandwich the channel formation region of the semiconductor layer. Therefore, the back gate electrode can function in the same way as a gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or may be the ground potential (GND potential), or any other potential. In addition, the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently of the gate electrode.

[0189] The electrode 746 and the electrode 723 can both function as gate electrodes. Thus, the insulating layers 726, 728, and 729 can each function as a gate insulating layer. Note that the electrode 723 may be provided between the insulating layers 728 and 729.

[0190] Note that when one of the electrode 746 and the electrode 723 is referred to as a "gate electrode," the other is referred to as a "back gate electrode." For example, when the electrode 723 of the transistor 810 is referred to as a "gate electrode," the electrode 746 is referred to as a "back gate electrode." When the electrode 723 is used as a "gate electrode," the transistor 810 can be considered as a type of top-gate transistor. Furthermore, one of the electrode 746 and the electrode 723 may be referred to as a "first gate electrode," and the other may be referred to as a "second gate electrode."

[0191] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 therebetween and further by setting the electrode 746 and the electrode 723 to the same potential, the region through which carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction, thereby increasing the amount of carrier movement. As a result, the on-state current and the field-effect mobility of the transistor 810 become larger.

[0192] Therefore, the transistor 810 has a large on-state current relative to its area. That is, the area occupied by the transistor 810 can be made small relative to the required on-state current.

[0193] In addition, since the gate electrode and the back gate electrode are formed of conductive layers, they have the function of preventing an electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly, an electric field shielding function against static electricity, etc.) Note that the electric field shielding function can be enhanced by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.

[0194] Furthermore, by forming the back gate electrode using a conductive film having a light-shielding property, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side, thereby preventing light degradation of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor.

[0195] 11B is a cross-sectional view in the channel length direction of a channel-protective transistor 820 having a different configuration from that shown in FIG. 11A. The transistor 820 has a structure similar to that of the transistor 810, except that an insulating layer 741 covers an edge of a semiconductor layer 742. The semiconductor layer 742 and an electrode 744a are electrically connected to each other through an opening formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 742. The semiconductor layer 742 and an electrode 744b are electrically connected to each other through another opening formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 742. The region of the insulating layer 741 that overlaps with the channel formation region can function as a channel protection layer.

[0196] The insulating layer 741 can prevent the semiconductor layer 742 from being exposed when the electrodes 744a and 744b are formed. Therefore, the semiconductor layer 742 can be prevented from being thinned when the electrodes 744a and 744b are formed.

[0197] Furthermore, in the transistor 820, the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are longer than in the transistor 810. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Furthermore, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced.

[0198] 11C is a cross-sectional view in the channel length direction of a channel-etched transistor 825, which is a bottom-gate transistor. In the transistor 825, the electrodes 744a and 744b are formed without using the insulating layer 741. Therefore, part of the semiconductor layer 742 that is exposed during the formation of the electrodes 744a and 744b may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be improved.

[0199] [Top-gate transistor] 12A is a top-gate transistor. The electrodes 744a and 744b are electrically connected to the semiconductor layer 742 in openings formed in the insulating layers 728 and 729.

[0200] Furthermore, by removing a portion of the insulating layer 726 that does not overlap with the electrode 746 and introducing impurities into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask, an impurity region can be formed in a self-aligned manner in the semiconductor layer 742. The transistor 842 has a region in which the insulating layer 726 extends beyond the edge of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 into which the impurities are introduced via the insulating layer 726 is lower than the impurity concentration in the region into which the impurities are introduced without passing through the insulating layer 726. Therefore, an LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 that overlaps with the insulating layer 726 but does not overlap with the electrode 746.

[0201] The transistor 842 further includes an electrode 723 formed over a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with an insulating layer 772 interposed therebetween. The electrode 723 can function as a backgate electrode. Note that the electrode 723 does not necessarily have to be provided.

[0202] 12B, the insulating layer 726 may be entirely removed from a region that does not overlap with the electrode 746. Alternatively, the insulating layer 726 may be left as in a transistor 846 shown in FIG.

[0203] FIG. 13A shows a cross-sectional view of a transistor 810 in the channel width direction, and FIG. 13B shows a cross-sectional view of a transistor 842 in the channel width direction.

[0204] 13A and 13B, the gate electrode and the back gate electrode are connected to each other, and the gate electrode and the back gate electrode have the same potential. Also, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0205] The length in the channel width direction of each of the gate electrode and the back gate electrode is longer than the length in the channel width direction of the semiconductor layer 742, and the entire channel width direction of the semiconductor layer 742 is covered by the gate electrode or the back gate electrode with each insulating layer sandwiched between them.

[0206] With this structure, the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric fields of the gate electrode and the back gate electrode.

[0207] A device structure of a transistor in which the electric fields of the gate electrode and back gate electrode electrically surround the semiconductor layer 742 in which the channel formation region is formed can be called a surrounded channel (S-channel) structure.

[0208] The S-channel structure allows an electric field for inducing a channel to be effectively applied to the semiconductor layer 742 by one or both of the gate electrode and the back gate electrode, thereby improving the current driving capability of the transistor and enabling high on-state current characteristics. Furthermore, since the on-state current can be increased, the transistor can be miniaturized. Furthermore, the S-channel structure allows the mechanical strength of the transistor to be increased.

[0209] Note that the gate electrode and the back gate electrode may not be connected to each other and different potentials may be supplied to them. For example, the threshold voltage of the transistor can be controlled by supplying a constant potential to the back gate electrode.

[0210] This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes and examples.

[0211] (Fourth embodiment) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game consoles including portable devices, portable data terminals, e-book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio player, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIGS.

[0212] 14A shows a digital camera including a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display portion 965, operation keys 966, a zoom lever 968, a lens 969, and the like. The display device of one embodiment of the present invention can be used for the display portion 965.

[0213] 14B shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, operation buttons 914, a camera 919, and the like. Data can be input and output using a touch panel function of the display portion 912. The display device of one embodiment of the present invention can be used for the display portion 912.

[0214] 14C shows a mobile phone including a housing 951, a display portion 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, and the like. The mobile phone includes a touch sensor in the display portion 952. Any operation, such as making a call or inputting text, can be performed by touching the display portion 952 with a finger or a stylus. The housing 951 and the display portion 952 are flexible and can be folded as shown in the figure. The display device of one embodiment of the present invention can be used for the display portion 952.

[0215] 14D shows a drive recorder, which includes a housing 931, a display portion 932, operation buttons 933, a microphone 934, a lens 935, an attachment portion 936, and the like. By attaching the drive recorder to a windshield or the like of a vehicle via the attachment portion 936, a view ahead while the vehicle is traveling can be recorded. The display portion 932 can display a recorded image. The display device of one embodiment of the present invention can be applied to the display portion 932.

[0216] 14E illustrates a television including a housing 971, a display portion 973, operation buttons 974, a speaker 975, a communication connection terminal 976, an optical sensor 977, and the like. A touch sensor is provided in the display portion 973, and an input operation can be performed. The display device of one embodiment of the present invention can be used for the display portion 973.

[0217] 14F illustrates a digital signage having a large display portion 922. In the digital signage, for example, the large display portion 922 is attached to the side surface of a pillar 921. The display device of one embodiment of the present invention can be used for the display portion 922.

[0218] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes. [Explanation of symbols]

[0219] 10: pixel, 11: pixel array, 20: source driver, 30: gate driver, 40: signal generation circuit, 40a: circuit, 40b: circuit, 41a: buffer circuit, 41b: buffer circuit, 42: CMOS inverter circuit, 43n: n-channel transistor, 43p: p-channel transistor, 45a: selection circuit, 45b: selection circuit, 46a: inverter circuit, 46b: inverter circuit, 47a: transistor, 47b: transistor, 48a: transistor, 48b: transistor, 101: transistor, 102: transistor, 103: transistor transistor, 104: transistor, 105: transistor, 106: capacitor, 107: capacitor, 108: light-emitting device, 121: wiring, 122: wiring, 123: wiring, 124: wiring, 125: wiring, 126: wiring, 129: wiring, 215: display unit, 221a: scanning line driving circuit, 231a: signal line driving circuit, 232a: signal line driving circuit, 241a: common line driving circuit, 301: transistor, 302: transistor, 303: transistor, 304: transistor, 305: transistor, 306: capacitor, 307: capacitor, 308: light-emitting device device, 309: light-emitting device, 323: power line, 723: electrode, 726: insulating layer, 728: insulating layer, 729: insulating layer, 741: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode, 771: substrate, 772: insulating layer, 810: transistor, 820: transistor, 825: transistor, 842: transistor, 844: transistor, 846: transistor, 911: housing, 912: display unit, 913: speaker, 914: operation button, 919: camera, 921: pillar, 922: display unit, 931: housing, 932: display unit, 9 33: operation button, 934: microphone, 935: lens, 936: parts, 951: housing, 952: display unit, 953: operation button, 954: external connection port, 955: speaker, 956: microphone, 957: camera, 961: housing, 962: shutter button, 963: microphone, 965: display unit, 966: operation key, 967: speaker, 968: zoom lever, 969: lens, 971: housing, 973: display unit, 974: operation button, 975: speaker, 976: communication connection terminal, 977: optical sensor, 4001: substrate, 4005: sealing material, 4006: substrate,4010: transistor, 4011: transistor, 4014: wiring, 4015: electrode, 4017: electrode, 4018: FPC, 4019: anisotropic conductive layer, 4020: capacitor, 4021: electrode, 4030: electrode layer, 4031: electrode layer, 4041: printed circuit board, 4042: integrated circuit, 4102: insulating layer, 4103: insulating layer, 4104: insulating layer , 4110: insulating layer, 4111: insulating layer, 4112: insulating layer, 4200: input device, 4210: touch panel, 4227: electrode, 4228: electrode, 4237: wiring, 4238: wiring, 4239: wiring, 4263: substrate, 4272b: FPC, 4273b: IC, 4510: partition, 4511: light-emitting layer, 4513: light-emitting device, 4514: filling material,

Claims

[Claim 1] A display device including a pixel including a first transistor, a second transistor, and a light-emitting device, one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the anode of the light-emitting device; the first transistor is a p-channel transistor, The display device, wherein the second transistor is an n-channel transistor.

Images