Display device and method for controlling display device

Abstract

To provide a display device and a method for controlling a display device, capable of reducing change in luminance even when an image signal input cycle transits from a short cycle to a long cycle.SOLUTION: A display device comprises a pixel electrode, a drive circuit that charges the pixel electrode based on an image signal, and a control unit that controls timing at which the drive circuit charges the pixel electrode. When a cycle in which the image signal is input from a host changes from T1 to T2, which is longer than T1, the control unit increases the length of a charging time C2 in a period P2 in which the image signal is input at a cycle T2 compared to the length of a charging time C1 in a period P1 in which the image signal is input at a cycle T1.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a display device and a method for controlling the display device. [Background technology]

[0002] Patent Document 1 describes a display device that performs pause driving, which pauses writing to pixels and displays a still image. This display device performs high-speed scanning and gradation value emphasis driving when transitioning from a pause period during which pause driving is performed to a drive period during which scanning signal lines are scanned and image signal voltages are written to pixels. High-speed scanning involves writing image signal voltages of the same polarity to pixels at a second speed that is faster than a first speed at which image signal voltages calculated based on image signals are written to pixels. Gradation value emphasis driving is an operation that corrects the gradation values of image data for a first frame immediately after the start of the drive period and image data for a second frame immediately after the first frame. This prevents visible flicker when transitioning from a pause period to a drive period. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 130860 Summary of the Invention [Problem to be solved by the invention]

[0004] Here, a display device may transition from a state in which image signal voltages are applied to pixels (image writing) at a short cycle (e.g., 120 Hz) to a state in which images are written at a long cycle (e.g., 1 Hz). In this case, the number of times the pixel is charged decreases from 120 times per second to once per second. Because the pixel TFT has off-leakage, the potential of the pixel (pixel electrode) drops, causing a change (e.g., a decrease) in brightness. That is, conventional display devices have a problem in that brightness changes when transitioning from a period in which an image signal is input at a short cycle to a period in which an image signal is input at a long cycle.

[0005] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a display device and a control method for a display device that can reduce changes in luminance even when the image signal input cycle transitions from a state in which the image signal input cycle is short to a state in which the image signal input cycle is long. [Means for solving the problem]

[0006] In order to solve the above problem, a display device according to a first aspect of the present disclosure comprises a pixel electrode, a drive circuit that charges the pixel electrode based on an image signal, and a control unit that controls the timing at which the drive circuit charges the pixel electrode, wherein when the period in which the image signal is input from the host changes from a first period to a second period that is longer than the first period, the control unit increases the length of the charging time in the second period in which the image signal is input at the second period compared to the length of the charging time in the first period in which the image signal is input at the first period.

[0007] In addition, a control method for a display device according to a second aspect of the present disclosure is a control method for a display device including a pixel electrode and a drive circuit that charges the pixel electrode based on an image signal, which acquires the image signal, and when the period in which the image signal is input from a host changes from a first period to a second period longer than the first period, makes the length of time for which the drive circuit charges the pixel electrode during the second period in which the image signal is input at the second period longer than the length of time for which the drive circuit charges the pixel electrode during the first period in which the image signal is input at the first period. [Effects of the Invention]

[0008] According to the above configuration, even when the period for inputting the image signal transitions from a short state to a long state, the pixel electrode is charged for a long period after the transition, thereby preventing the potential of the pixel electrode from decreasing and reducing changes in brightness. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a display device 100 according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing a part of the configuration of the liquid crystal display 11. As shown in FIG. [Figure 3] FIG. 3 is a diagram for explaining the timing of the gate start pulse signal GSP, the output signal Do, and the display image Di. [Figure 4] FIG. 4 is a diagram for explaining the relationship between the output period of the gate clock signal GCL and the waveform of the source signal So. [Figure 5] FIG. 5 is a block diagram of a display device 200 according to the second embodiment. [Figure 6] FIG. 6 is a block diagram showing the configuration of a source driving circuit 213 according to the second embodiment. [Figure 7] FIG. 7 is a diagram for explaining the relationship between the output period of the gate clock signal GCL in the period P2 and the waveform of the source signal So according to the second embodiment. [Figure 8] FIG. 8 is a block diagram of a display device 300 according to the third embodiment. [Figure 9] FIG. 9 is a diagram for explaining the input / output timing of the input signal Ci, the output signal Do, and the display image Di, and the operation timing of the frame memory 21 according to the third embodiment. [Figure 10] FIG. 10 is a block diagram of a display device 400 according to the fourth embodiment. [Figure 11] FIG. 11 is a diagram for explaining the input / output timing of the input signal Ci, the output signal Do, and the display image Di, and the operation timing of the frame memory 21 according to the fourth embodiment. [Figure 12] FIG. 12 is a block diagram of a display device 500 according to the fifth embodiment. [Figure 13] FIG. 13 is a diagram for explaining the timing of the gate start pulse signal GSP, the output signal Do, and the display image Di according to the fifth embodiment. [Figure 14] FIG. 14 shows the measurement results of the luminance of the display device according to the comparative example. [Figure 15] FIG. 15 shows the results of measuring the luminance of an example of the display device 100 of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments, and appropriate design modifications can be made within the scope of the configuration of the present disclosure. In the following description, the same reference numerals are used in common between different drawings for identical parts or parts having similar functions, and repeated description thereof will be omitted. The configurations described in the embodiments and modifications may be combined or modified as appropriate within the scope of the gist of the present disclosure. To facilitate understanding of the description, the drawings referred to below show simplified or schematic configurations, and some components may be omitted.

[0011] [First embodiment] (Overall configuration of the display device) FIG. 1 is a block diagram showing a schematic configuration of a display device 100 according to a first embodiment. FIG. 2 is a circuit diagram showing a part of the configuration of a liquid crystal display 11. The display device 100 is a device that displays an image (video) based on image signals (R, G, B) supplied from a host controller (hereinafter referred to as "host") not shown. The display device 100 is, for example, a personal computer, a tablet terminal, a smartphone, a smartwatch, or a television device. The display device 100 includes a display panel 10 and a control circuit 20.

[0012] As shown in FIG. 1, a display panel 10 includes a liquid crystal display 11, a gate drive circuit 12, and a source drive circuit 13. As shown in FIG. 2, the liquid crystal display 11 is provided with gate lines 12a connected to the gate drive circuit 12, source lines 13a connected to the source drive circuit 13, TFTs (Thin Film Transistors) 14, pixel electrodes 15, and a common electrode 16. The gate lines 12a are connected to gate electrodes of the TFTs 14. The source lines 13a are connected to source electrodes of the TFTs 14. The pixel electrodes 15 are connected to drain electrodes of the TFTs 14. The TFTs 14 and the pixel electrodes 15 are arranged in regions (pixels) defined by the intersections of multiple gate lines 12a and multiple source lines 13a. The common electrode 16 is an opposing electrode arranged opposite the pixel electrodes 15. The common electrode 16 is provided in common to multiple pixel electrodes 15. The pixel electrode 15 generates an electric field between itself and the common electrode 16, and the electric field drives the liquid crystal, thereby controlling the amount of light that passes through the liquid crystal.

[0013] FIG. 3 is a diagram illustrating the timing of the gate start pulse signal GSP, the output signal Do, and the display image Di. The gate drive circuit 12 sequentially supplies gate signals to the TFTs 14 in each row via the gate lines 12a in response to control signals (such as the gate start pulse signal GSP synchronized with the vertical synchronization signal and the gate clock signal GCL) supplied from the control circuit 20. As shown in FIG. 3, the gate start pulse signal GSP is a signal that is output once at the beginning of one frame and serves as a trigger for the gate drive circuit 12 to start scanning one frame. In this disclosure, the term "frame" refers to an image (one frame) displayed on the screen to compose a video. The time interval (one frame period) at which the gate start pulse signal GSP is output corresponds to the period at which the image signal is input from the host.

[0014] As shown in FIG. 3, the control circuit 20 supplies control signals (such as an output signal Do, a clock signal, and a horizontal synchronization signal) to the source drive circuit 13. The memory controller 22 of the control circuit 20 generates an output signal Do based on the image signal stored in the frame memory 21. The output signal Do includes information on a voltage value (pixel value) corresponding to the image signal. The source drive circuit 13 generates a source signal So (voltage) based on the output signal Do and the horizontal synchronization signal. The source drive circuit 13 then supplies the source signal So (voltage) to the pixel electrode 15 via the source line 13a and the TFT 14, thereby charging the pixel electrode 15. That is, the gate drive circuit 12 and the source drive circuit 13 write an image to be displayed on the liquid crystal display 11 in accordance with the input image signal. As a result, the display image Di displayed on the liquid crystal display 11 is switched, as shown in FIG. 3. Furthermore, during a blank period Vb in which no control signal (clock signal) is supplied to the gate drive circuit 12 and the source drive circuit 13 and no charging is performed on the pixel electrodes 15, the display image Di written immediately before is maintained. Note that in the present disclosure, the concept of "writing" not only includes rewriting the display image Di with a different display image Di, but also includes writing the same display image Di as the display image Di back onto the pixel electrodes 15.

[0015] 1, the control circuit 20 includes a frame memory 21, a memory controller 22, an input detection circuit 23, and a timing generation circuit 24. The control circuit 20 is configured, for example, by an integrated circuit. Although the control circuit 20 is illustrated as a functional block in FIG. 1, each function within the control circuit 20 may be configured as separate hardware (circuits). Alternatively, the control circuit 20 may include a processor that executes a program to provide the functions of the memory controller 22, the input detection circuit 23, and the timing generation circuit 24.

[0016] The frame memory 21 is a memory that stores image signals (pixel values (grayscales) of each of R, G, and B) for at least one entire frame of each pixel. The memory controller 22 writes and reads image signals to and from the frame memory 21. In detail, the memory controller 22 receives image signals from the host and stores the image signals in the frame memory 21. Then, in response to a command from the timing generation circuit 24, the memory controller 22 reads the image signals from the frame memory 21 and supplies the output signal Do to the source driving circuit 13.

[0017] When a predetermined condition is satisfied, the host switches from a state in which an image signal is input to the control circuit 20 at 120 Hz (frame frequency of 120 Hz) to a state in which an image signal is input to the control circuit 20 at 1 Hz (frame frequency of 1 Hz). The "predetermined condition" may be, for example, a case in which no input operation is performed on an operation unit (not shown, such as an operation button, keyboard, or mouse) for a predetermined continuous period. In this case, the host changes the cycle in which the image signal is input to the control circuit 20 from T1 to T2. In this embodiment, the state in which an image signal is input to the control circuit 20 at 120 Hz is referred to as the "high-frequency mode," and the state in which an image signal is input to the control circuit 20 at 1 Hz is referred to as the "low-frequency mode." While "120 Hz" is used as an example of the frequency of the high-frequency mode, other frequencies such as "30 Hz," "60 Hz," and "90 Hz" may also be used. The low-frequency mode may also be a frequency lower than the frequency of the high-frequency mode, other than "1 Hz," or may be a state in which input from the host is completely stopped.

[0018] The input detection circuit 23 detects the presence or absence of an image signal input from the host to the control circuit 20. The input detection circuit 23 detects that the cycle at which the image signal is input from the host has changed from T1 to T2. For example, in the first embodiment, when the input detection circuit 23 detects that the input of the image signal is not performed for a predetermined period (the input has stopped), it determines that the cycle at which the image signal is input from the host has changed from T1 to T2 (the host control mode has changed from the high-frequency mode to the low-frequency mode). Furthermore, without being limited to this example, the input detection circuit 23 may be configured to detect a mode transition (that the host control mode has changed from the high-frequency mode to the low-frequency mode) by receiving a mode change command (command signal) from the host. That is, the display device 100 may be configured so that the output of the image signal from the host is completely stopped and the display device 100 generates its own timing to drive the source drive circuit 13 (PSR drive: Panel Self Refresh drive).

[0019] The timing generation circuit 24 receives an image signal from the host. Based on the image signal, the timing generation circuit 24 generates control signals (such as a gate start pulse signal GSP synchronized with a vertical synchronization signal, a gate clock signal GCL, and a horizontal synchronization signal) to be supplied to each of the gate drive circuit 12 and the source drive circuit 13. The timing generation circuit 24 then transmits control signals including the gate start pulse signal GSP to the gate drive circuit 12 and transmits control signals to the source drive circuit 13. For example, if the cycle at which an image signal is input is T1, the timing generation circuit 24 causes the gate drive circuit 12 and the source drive circuit 13 to charge the pixel electrodes 15 (write an image) at the cycle of T1. At this time, the memory controller 22 reads the image signal from the frame memory 21 and supplies an output signal Do based on the image signal to the source drive circuit 13. As shown in FIG. 3, the timing generation circuit 24 controls the gate drive circuit 12 and the source drive circuit 13 to change the length of the frame period T based on the cycle detected by the input detection circuit 23.

[0020] In this embodiment, as shown in FIG. 3, when the period in which the image signal is input from the host changes from period T1 to period T2, the timing generation circuit 24 increases the length C2 of the charging time during the period P1 in which the image signal changes with period T2 to be longer than the length C1 of the charging time per charge during period P1 in which the image signal changes with period T1. In the first embodiment, the length C2 of the charging time is five times the length C1, but this is not limited to five times the length C1 in the present disclosure. The "charging time" refers to the time during which the gate clock signal GCL is at a high level and the voltage value of the source signal So is equal to or greater than a predetermined voltage value Sot, as shown in FIG. 4. Therefore, for ease of explanation, FIG. 3 illustrates the charging periods C1 and C2 as coinciding with the period in which the output signal Do is output (the period in which the gate clock signal GCL is at a high level), but this is not limited thereto.

[0021] FIG. 4 illustrates the relationship between the output period of the gate clock signal GCL and the waveform of the source signal So. The timing generation circuit 24 increases the cycle of outputting the horizontal synchronization signal (e.g., by five times) and lengthens the period (output period) for outputting the gate clock signal GCL to the gate drive circuit 12 (e.g., by five times), thereby changing the length of the charging time from C1 to C2. As shown in FIG. 4, for example, the output period Q2 of the gate clock signal GCL in period P2 is longer (e.g., five times) than the output period Q1 of the gate clock signal GCL in period P1. As a result, the length of the period Q2a within the output period Q2 during which the source signal So is equal to or greater than the predetermined voltage value Sot is longer (e.g., five times) than the period Q1a within the output period Q1 during which the source signal So is equal to or greater than the predetermined voltage value Sot. Furthermore, in period P1, the source driving circuit 13 outputs a voltage that causes the voltage value of the pixel electrode 15 to reach the voltage value Sot in time Q1b from the start of charging to the pixel electrode 15 (the start of the output period), and in period P2, it outputs a voltage that causes the voltage value of the pixel electrode 15 to reach the voltage value Sot in time Q2b from the start of charging to the pixel electrode 15. In the first embodiment, the time Q2b is the same length as the time Q1b. Note that the "predetermined voltage value Sot" has a different value depending on the gradation to be written to the pixel electrode 15. For example, when the gradation to be written is high, the voltage value Sot is high, and when the gradation to be written is low, the voltage value Sot is low.

[0022] According to the configuration of the first embodiment, even when the cycle of inputting an image signal transitions from a short cycle to a long cycle, the pixel electrode 15 is charged for a long time after the transition. This allows the potential of the pixel electrode 15 to be maintained compared to when the charging time is short, thereby reducing changes (for example, decreases) in brightness.

[0023] It is possible to configure the device so that, when the image signal input cycle changes from a short state to a long state, the charging time per charge is not changed and multiple charging times are performed within one cycle. However, this configuration increases the number of times the gate drive circuit and source drive circuit are driven, resulting in increased power consumption. In contrast, in the first embodiment, the number of times the gate drive circuit and source drive circuit are driven is not increased, so it is possible to reduce changes in brightness while preventing an increase in power consumption.

[0024] [Second embodiment] Next, the configuration of a display device 200 according to a second embodiment will be described with reference to Figures 3 to 7. In the second embodiment, the time Q12b (see Figure 7) from the start of charging the pixel electrode 15 until the voltage value of the pixel electrode 15 reaches the voltage value Sot during the period P2 is longer than the time Q1b (see Figure 4) during the period P1. Note that the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and their description will be omitted.

[0025] FIG. 5 is a block diagram of a display device 200 according to a second embodiment. FIG. 6 is a block diagram showing the configuration of a source driving circuit 213 according to the second embodiment. FIG. 7 is a diagram for explaining the relationship between the output period of a gate clock signal GCL in period P2 and the waveform of a source signal So according to the second embodiment. As shown in FIG. 5, the display device 200 includes a display panel 210 and a control circuit 220. The display panel 210 includes a source driving circuit 213. The control circuit 220 includes a memory controller 222 and a timing generation circuit 224. The memory controller 222 reads an image signal from the frame memory 21 and supplies an output signal Do based on the image signal to the source driving circuit 213.

[0026] When the period in which the image signal is input from the host changes from period T1 to period T2 as shown in FIG. 3, the timing generation circuit 224 increases the length of the charging time during the period in which the image signal changes at period T2 to C12 (see FIG. 7) compared to the length of the charging time per charge during period P1 in which the image signal changes at period T1. Furthermore, in the second embodiment, when the period in which the image signal is input from the host changes from period T1 to period T2, the timing generation circuit 224 outputs a setting change signal R to the source drive circuit 213 as shown in FIG. 6. The setting change signal R is a command signal for lowering the amplification capability setting of the source drive circuit 213. Upon receiving the setting change signal R, the source drive circuit 213 lengthens the time Q12b required for the source signal So to rise compared to the time Q1b before receiving the setting change signal R, as shown in FIG. 7.

[0027] 6, the source driving circuit 213 includes a digital-to-analog conversion circuit 213a (DA conversion circuit), a gradation voltage generation circuit 213b, and an amplifier circuit 213c. The digital-to-analog conversion circuit 213a converts a digital output signal D0 supplied from the memory controller 222 of the control circuit 220 into an analog signal and supplies the converted signal to the amplifier circuit 213c. The gradation voltage generation circuit 213b is a voltage source for the digital-to-analog conversion circuit 213a and applies a predetermined voltage to the digital-to-analog conversion circuit 213a.

[0028] The amplifier circuit 213c is, for example, a buffer circuit that prevents attenuation of the signal output from the digital-analog conversion circuit 213a. The amplifier circuit 213c is, for example, a voltage follower circuit. Upon receiving the setting change signal R output from the control circuit 20, the amplifier circuit 213c lengthens the time Q12b required for the source signal So to rise compared to the time Q1b required before the setting change signal R is received. Note that the function of the amplifier circuit 213c to change the time required for the source signal So to rise can be realized by a known source driver circuit. As a result, as shown in FIG. 7, the time Q12b required for the source signal So to rise is lengthened compared to the time Q1b required before the setting change signal R is received. Furthermore, the time Q12b is longer than the time Q2b in the first embodiment (see FIG. 4). That is, in period Q1, the source drive circuit 213 outputs a voltage that causes the voltage value of the pixel electrode 15 to reach the voltage value Sot in time Q1b from the start of charging of the pixel electrode 15, and in period Q2, outputs a voltage that causes the voltage value of the pixel electrode 15 to reach the voltage value Sot in time Q12b, which is longer than time Q1b from the start of charging of the pixel electrode 15. According to the second embodiment, the power output from the source drive circuit 213 in period Q2 can be reduced, thereby reducing power consumption. Other configurations and effects of the second embodiment are similar to those of the first embodiment.

[0029] [Third embodiment] Next, the configuration of a display device 300 according to a third embodiment will be described with reference to Figures 8 and 9. In the third embodiment, in a period P32 in which the charging time is long (C2), if a new image signal D33 is input to the control circuit 320 while the pixel electrode 15 is being charged based on the image signal D32, charging of the pixel electrode 15 based on the image signal D32 is not performed, and charging of the pixel electrode 15 based on the image signal D32 is continued. Note that the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof will be omitted.

[0030] 8 is a block diagram of a display device 300 according to the third embodiment. The display device 300 includes a control circuit 320. The control circuit 320 includes a memory controller 322.

[0031] 9 is a diagram illustrating the input / output timing of the input signal Ci, the output signal Do, and the display image Di, and the operation timing of the frame memory 21 according to the third embodiment. The input signal Ci is a signal output from the host, and includes an image signal. Upon receiving the input signal Ci from the host, the memory controller 322 supplies the image signal to the frame memory 21 and writes the image signal to the frame memory 21. The memory controller 322 then reads the image signal stored in the frame memory 21 and outputs the read image signal as an output signal Do to the display panel 10. In the display panel 10, the pixel electrodes 15 are charged based on the image signal.

[0032] As shown in FIG. 9, during a period P32 during which the charging time is C2 longer than C1 (see FIG. 3), the image signal D32 is read from the frame memory 21, and the memory controller 322 outputs an output signal Do based on the image signal D32. As a result, in the display panel 10, the pixel electrodes 15 are charged based on the image signal D32, and the display image Di is displayed. In the third embodiment, when a new image signal D33 is input to the control circuit 320 during the period P32, the display device 300 does not charge the pixel electrodes 15 based on the image signal D33, but continues charging the pixel electrodes 15 based on the image signal D32. That is, the memory controller 322 does not write the new image signal D33 input during the period P32 to the frame memory 21. Specifically, when a new image signal D33 is input between time t1 and time t2, which is before time t3 at which the period P32 ends, the memory controller 322 does not write the image signal D33 to the frame memory 21. This prevents the image signal D32 from being overwritten by the image signal D33 in the frame memory 21 before time t3 when the readout of the image signal D32 is completed, and as a result, it is possible to prevent the display image Di from becoming an image in which the image signals D33 and D32 are mixed together.

[0033] Furthermore, even if a new image signal (D34) begins to be input at time t2 during period P32, if the image signal D34 is input over time t4, which is after the end time t3 of period P32 (when there is no possibility of the image signal D32 being overwritten), as shown in FIG. 9 , the memory controller 322 writes the new image signal D34 to the frame memory 21 from time t2 to time t4. As a result, after the end of period P32, an output signal Do based on the image signal D34 is output to the display panel 10, and a display image Di based on the image signal D34 is displayed on the display panel 10. According to the third embodiment, even if a new image signal is input to the control circuit 320 while the pixel electrode 15 is being charged, charging of the pixel electrode 15 based on the new image signal is not performed, thereby preventing tearing (image distortion) caused by collision (overlap) of multiple image signals. Note that other configurations and effects of the third embodiment are similar to those of the first embodiment.

[0034] [Fourth embodiment] Next, the configuration of a display device 400 according to a fourth embodiment will be described with reference to Figures 10 and 11. In the fourth embodiment, when a new image signal D43 is input to the control circuit 420 during charging of the pixel electrodes 15 based on the image signal D42 during a period P42 in which the charging time is long (C2), charging based on the image signal D42 is terminated and charging based on the image signal D43 is started. Note that the same components as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and their description will be omitted.

[0035] 10 is a block diagram of a display device 400 according to the fourth embodiment. The display device 400 includes a control circuit 420. The control circuit 420 includes a memory controller 422.

[0036] 11 is a diagram illustrating the input / output timing of the input signal Ci, the output signal Do, and the display image Di according to the fourth embodiment, and the operation timing of the frame memory 21. When the memory controller 422 receives the input signal Ci from the host, it supplies an image signal to the frame memory 21 and writes the image signal to the frame memory 21. The memory controller 422 then reads out the image signal stored in the frame memory 21 and outputs the read image signal as an output signal Do to the display panel 10. In the display panel 10, the pixel electrodes 15 are charged based on the image signal.

[0037] As shown in FIG. 11, during a period P42 during which the charging time is C2 longer than C1 (see FIG. 3), the image signal D42 is read from the frame memory 21, and the memory controller 422 outputs an output signal Do based on the image signal D42. As a result, in the display panel 10, the pixel electrodes 15 are charged based on the image signal D42, and the display image Di is displayed. In the fourth embodiment, the display device 400 terminates charging based on the image signal D42 when a new image signal D43 is input to the control circuit 420 as the input signal Ci during the period P42. For example, the memory controller 422 increases the speed at which the image signal D42 is read from the frame memory 21 compared to the speed before time t11 when the new image signal D43 was input. As a result, the memory controller 422 can quickly read out the image signal D42 and terminate charging of the pixel electrodes 15 early.

[0038] Furthermore, the memory controller 422 writes the image signal D43 to the frame memory 21 from time t11 when the image signal D43 is input. Then, the memory controller 422 starts reading the image signal D43 from time t12 when the reading of the image signal D42 is completed, and outputs an output signal Do based on the image signal D43 from time t12. As a result, a display image Di based on the image signal D43 is displayed on the display panel 10. Thereafter, during a period P41 during which the charging time is C1, the memory controller 422 outputs an output signal Do based on the input image signal D44. Thus, in the fourth embodiment, even if a new image signal D43 is input to the control circuit 420 while the pixel electrode 15 is being charged, charging of the pixel electrode 15 based on the image signal D43 begins after charging of the pixel electrode 15 based on the image signal D42 is completed. As a result, tearing (image distortion) caused by collision (overlap) between the image signals D42 and D43 can be prevented. That is, it is possible to prevent the display image Di from becoming an image in which the image signal D43 and the image signal D42 are mixed together. Note that the other configurations and effects of the fourth embodiment are the same as those of the first embodiment.

[0039] [Fifth embodiment] Next, the configuration of a display device 500 according to a fifth embodiment will be described with reference to Figures 12 and 13. In the fifth embodiment, when the cycle in which an image signal is input from the host changes from cycle T51 to cycle T52, which is longer than T51, the display device 500 charges the pixel electrodes 15 based on the same image signal multiple times within period P52 of cycle T52. Note that the same components as in the first embodiment are denoted by the same reference numerals as in the first embodiment, and description thereof will be omitted.

[0040] 12 is a block diagram of a display device 500 according to a fifth embodiment. The display device 500 includes a control circuit 520. The control circuit 520 includes a memory controller 522 and a timing generation circuit 524.

[0041] FIG. 13 is a diagram illustrating the timing of the gate start pulse signal GSP, the output signal Do, and the display image Di according to the fifth embodiment. When the input detection circuit 23 detects a change from the period T51 to the period T52, which is longer than T51, the timing generation circuit 524 changes the period for outputting the gate start pulse signal GSP from T51 to T52. The timing generation circuit 524 then increases the length of the charging time C52 during the period P52, during which the image signal changes with the period T52, to be longer than the length of the charging time C51 per charging during the period P51, during which the image signal changes with the period T51. For example, C52 is twice as long as C51. In addition, in the fifth embodiment, the memory controller 522 outputs the output signal Do to the display panel 10 multiple times (three times in the example of FIG. 13) during the period P52, and the pixel electrodes 15 in the display panel 10 are charged multiple times (three times in the example of FIG. 13) based on the same image signal D53.

[0042] According to the fifth embodiment, even when the period T51 transitions from a short state to a long state (T52), the pixel electrode 15 is charged multiple times within one period based on the same image signal, so the period during which the pixel electrode 15 is charged is longer than when charging is performed only once. This makes it possible to reduce changes in the luminance of the display device 500. Note that the other configurations and effects of the fifth embodiment are the same as those of the first embodiment.

[0043] [Measurement results of brightness in examples and comparative examples according to the first embodiment] Next, the measurement results of the luminance of the example and comparative example of the first embodiment will be described with reference to FIGS.

[0044] 14 shows the results of measuring the luminance of a display device according to a comparative example, and is a diagram showing the ratio of luminance after the period has changed from 8.3 ms to 1 s (frequency of 1 Hz), assuming that the luminance when the period of an image signal input from the host is 8.3 ms (frequency of 120 Hz) is "1." The display device according to the comparative example has a charging time of C1 (see FIG. 3) both during the period when the period is 8.3 ms (before time t21) and during the period when the period is 1 s (after time t21). Note that the display device according to the comparative example was prepared for comparison with the examples of the first embodiment, and does not represent prior art.

[0045] FIG. 15 shows the results of measuring the luminance of an example of the display device 100 of the first embodiment. In this example, the period T1 is set to 8.3 ms (frequency of 120 Hz), the period T2 is set to 1 s, and C2 is set to five times the length of C1 in the display device 100 of the first embodiment. FIG. 15 is a diagram showing the ratio of luminance after the period changes from T1 (8.3 ms) to T2 (1 s) when the luminance of the display device 100 at period T1 is set to "1." Note that the period before time t31 in FIG. 15 is the period (P1) during which pixel signals are input at period T1, and the period after time t31 is the period (P2) during which image signals are input at period T2.

[0046] As shown in FIG. 14, in the display device according to the comparative example, after time t21, the luminance ratio was in the range of 0.990 to 0.993. Therefore, it was found that in the display device according to the comparative example, the luminance decreased by a ratio of 0.007 to 0.010. In contrast, as shown in FIG. 15, in the display device according to the example, even after time t31, the luminance ratio was in the range of 0.997 to 1.002. Therefore, it was found that in the display device according to the example, even after time t31, the change in the luminance ratio was 0.003 or less. As a result, it was found that the change in luminance was reduced in the display device according to the example compared to the display device according to the comparative example.

[0047] [Variations] Although the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the invention. Therefore, the present invention is not limited to the above-described embodiments, and can be modified as appropriate within the scope of the spirit of the invention. Modifications of the above-described embodiments will be described below.

[0048] (1) In the first to fifth embodiments, the host controller switches between the low-frequency mode and the high-frequency mode, but the present disclosure is not limited to this. A control circuit of the display device may also perform control to switch between the low-frequency mode and the high-frequency mode.

[0049] (2) In the first to fifth embodiments, an example was shown in which a liquid crystal display was provided in the display panel, but the present disclosure is not limited to this. For example, an organic EL display may be provided in the display panel.

[0050] (3) In the first to fourth embodiments, the length C2 or C12 of the charging time in period P2 is five times the length C1 of the charging time in period P1, and in the fifth embodiment, the length C52 of the charging time in period P52 is twice the length C51 of the charging time in period P51. However, the present disclosure is not limited to this. For example, C2 (or C12) or C52 may be a value less than twice but greater than 1 time C1 or C51, a value greater than 2 times but less than 5 times C1 or C51, or a value greater than 5 times C1 or C51.

[0051] (4) In the fifth embodiment, multiple write operations are performed in the first half of one cycle, but the present disclosure is not limited to this. For example, multiple write operations may be performed in the second half of one cycle, or multiple write operations may be performed in a distributed manner within one cycle.

[0052] (5) In the first to sixth embodiments, an example was shown in which an input detection circuit for detecting the period of change in an image signal is provided within the display device, but the present disclosure is not limited to this. For example, the function of the input detection circuit may be provided outside the display device (e.g., in the host). In this case, the host may be configured to transmit to the display device a signal indicating the length of a frame period (frame rate) or a signal indicating that the length of the frame period has been changed. Then, the display device may be configured to determine the change in the period by receiving the signal.

[0053] The above-described configuration can also be explained as follows.

[0054] A display device according to a first configuration comprises a pixel electrode, a drive circuit that charges the pixel electrode based on an image signal, and a control unit that controls the timing at which the drive circuit charges the pixel electrode, and when the period at which the image signal is input from the host changes from a first period to a second period that is longer than the first period, the control unit increases the length of the charging time in the second period in which the image signal changes in the second period compared to the length of the charging time in the first period in which the image signal changes in the first period (first configuration).

[0055] According to the first configuration, even when the cycle of inputting the image signal changes from a short cycle to a long cycle, the pixel electrodes are charged for a long time after the change, which allows the potential of the pixel electrodes to be maintained compared to when the charging time is short, thereby reducing changes in brightness.

[0056] In the first configuration, the control unit may be configured to set the length of the charging time in the second period to be at least twice the length of the charging time in the first period (second configuration). In the second configuration, the control unit may be configured to set the length of the charging time in the second period to be at least five times the length of the charging time in the first period (third configuration).

[0057] According to the second or third configuration, the charging time can be made sufficiently long, so that the change in brightness can be reduced.

[0058] In any one of the first to third configurations, the drive circuit may be configured to output, in the first period, a voltage that causes the voltage value of the pixel electrode to reach a predetermined voltage value in a first time from the start of charging of the pixel electrode, and to output, in the second period, a voltage that causes the voltage value of the pixel electrode to reach the predetermined voltage value in a second time that is longer than the first time from the start of charging of the pixel electrode (fourth configuration).

[0059] According to the fourth configuration, the power output from the drive circuit in the second period can be reduced, thereby reducing power consumption.

[0060] In any one of the first to fourth configurations, the control unit may be configured, in the second period, when a new second image signal is input to the control unit while the pixel electrode is being charged by the drive circuit based on a first image signal, to continue charging the pixel electrode by the drive circuit based on the first image signal without charging the pixel electrode based on the second image signal (fifth configuration).

[0061] According to the fifth configuration, even if a new second image signal is input to the control unit while the pixel electrode is being charged, charging of the pixel electrode based on the second image signal is not performed, thereby preventing tearing (image distortion) caused by the first image signal and the second image signal colliding (overlapping).

[0062] In any one of the first to fourth configurations, when a new second image signal is input to the control unit during the second period while the pixel electrode is being charged by the drive circuit based on a first image signal, the control unit may be configured to terminate charging of the pixel electrode by the drive circuit based on the first image signal, and after charging of the pixel electrode by the drive circuit based on the first image signal is terminated, start charging of the pixel electrode by the drive circuit based on the second image signal (sixth configuration).

[0063] According to the sixth configuration, even if a new second image signal is input to the control unit while the pixel electrode is being charged, charging of the pixel electrode based on the second image signal begins after charging of the pixel electrode based on the first image signal has finished, thereby preventing tearing (image distortion) caused by the first image signal and the second image signal colliding (overlapping).

[0064] In any one of the first to sixth configurations, the control unit may be configured to, when the period in which the image signal is input from the host changes from the first period to the second period, charge the pixel electrode using the drive circuit based on the same image signal multiple times within one period in which the image signal is input (seventh configuration).

[0065] According to the seventh configuration, even when the cycle of inputting the image signal changes from a short cycle to a long cycle, the pixel electrodes are charged multiple times in one cycle based on the same image signal, so the period during which the pixel electrodes are charged is longer than when the pixel electrodes are charged only once, thereby reducing the change in brightness.

[0066] A control method for a display device according to an eighth configuration is a control method for a display device comprising a pixel electrode and a drive circuit that charges the pixel electrode based on an image signal, and when the period in which the image signal is input from a host changes from a first period to a second period that is longer than the first period, the length of time for which the drive circuit charges the pixel electrode during the second period in which the image signal changes during the second period is made longer than the length of time for which the drive circuit charges the pixel electrode during the first period in which the image signal changes during the first period (eighth configuration).

[0067] According to the eighth configuration, even when the cycle of inputting the image signal changes from a short cycle to a long cycle, the pixel electrodes are charged for a long time after the change, which allows the potential of the pixel electrodes to be maintained compared to when the charging time is short, thereby reducing changes in brightness. [Explanation of symbols]

[0068] 10: display panel, 11: liquid crystal display, 12: gate drive circuit, 12a: gate line, 13: source drive circuit, 13a: source line, 15: pixel electrode, 16: common electrode, 20: control circuit, 21: frame memory, 22: memory controller, 23: input detection circuit, 24: timing generation circuit, 100: display device, 200: display device, 210: display panel, 213: source drive circuit, 213a: digital-to-analog conversion circuit, 213b: gradation voltage generation circuit, 213c: amplifier circuit, 220: control circuit, 222: memory controller, 224: timing generation circuit, 300: display device, 320: control circuit, 322: memory controller, 400: display device, 420: control circuit, 422: memory controller, 500: display device, 520: control circuit, 522: memory controller, 524: timing generation circuit

Claims

1. A pixel electrode; a driving circuit for charging the pixel electrodes based on an image signal; a control unit that controls a timing at which the pixel electrodes are charged by the drive circuit; When the period in which the image signal is input from the host changes from a first period to a second period longer than the first period, the control unit increases the length of the charging time in the second period in which the image signal is input at the second period to be longer than the length of the charging time in the first period in which the image signal is input at the first period.

2. The display device according to claim 1 , wherein the control unit sets the length of the charging time in the second period to at least twice the length of the charging time in the first period.

3. The display device according to claim 2 , wherein the control unit sets the length of the charging time in the second period to be at least five times the length of the charging time in the first period.

4. The drive circuit In the first period, a voltage is outputted such that a voltage value of the pixel electrode reaches a predetermined voltage value within a first time from the start of charging of the pixel electrode; A display device according to any one of claims 1 to 3, wherein during the second period, a voltage is output that causes the voltage value of the pixel electrode to reach the predetermined voltage value in a second time that is longer than the first time from the start of charging of the pixel electrode.

5. A display device described in any one of claims 1 to 3, wherein, during the second period, when a new second image signal is input to the control unit while the pixel electrode is being charged by the drive circuit based on a first image signal, the control unit does not charge the pixel electrode based on the second image signal, but continues charging the pixel electrode by the drive circuit based on the first image signal.

6. The control unit during the second period, when a new second image signal is input to the control unit while the pixel electrodes are being charged by the drive circuit based on a first image signal, the control unit terminates charging of the pixel electrodes by the drive circuit based on the first image signal; The display device according to any one of claims 1 to 3, wherein after charging of the pixel electrode by the driving circuit based on the first image signal is completed, charging of the pixel electrode by the driving circuit based on the second image signal is started.

7. A display device described in any one of claims 1 to 3, wherein when the period in which the image signal is input from the host changes from the first period to the second period, the control unit charges the pixel electrode using the drive circuit based on the same image signal multiple times within one period in which the image signal is input.

8. A method for controlling a display device including pixel electrodes and a drive circuit that charges the pixel electrodes based on an image signal, comprising: Acquire an image signal, A method for controlling a display device, wherein, when the period during which the image signal is input from the host changes from a first period to a second period longer than the first period, the length of time during which the driving circuit charges the pixel electrode during a second period during which the image signal is input at the second period is made longer than the length of time during which the driving circuit charges the pixel electrode during a first period during which the image signal is input at the first period.

Images