Non-volatile storage and integrated circuit device

Abstract

To provide a non-volatile storage that can reduce the possibility that a memory cell is deteriorated earlier.SOLUTION: A non-volatile storage comprises: a memory cell array that has a plurality of memory cells; and a read-out circuit that reads out data from the memory cell array. The read-out circuit, in a first mode, compares a first detection current flowing in a first memory cell electrically connected to a first node with a second detection current flowing in a second memory cell electrically connected to a second node to read out complementary data, and in a second mode, compares a current obtained by adding or subtracting a first reference current to or from the first detection current with the second current to read out the complementary data, or compares the first detection current with a current obtained by adding or subtracting a second reference current to or from the second detection current to read out the complementary data.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a nonvolatile memory device and an integrated circuit device. [Background technology]

[0002] Patent Document 1 describes a nonvolatile memory device in which a first memory cell and a second memory cell provided in a memory cell array have a single mode in which they store separate data and a dual mode in which they store complementary data that are complementary to each other. According to the nonvolatile memory device described in Patent Document 1, the single mode and dual mode can be arbitrarily switched for each memory cell provided in the memory cell array, and therefore it can be used for general purposes depending on the application. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-192329 Summary of the Invention [Problem to be solved by the invention]

[0004] In the nonvolatile memory device described in Patent Document 1, when complementary data is stored in a first memory cell and a second memory cell in dual mode, the data written in the first memory cell and the second memory cell is read in single mode during verification after the complementary data is written. Then, it is determined whether the condition is met: the detection current flowing through the memory cell in which data "1" is written is greater than the reference current, and the detection current flowing through the memory cell in which data "0" is written is smaller than the reference current. Data is repeatedly written to each memory cell until this condition is met. As a result, excessive stress is applied to each memory cell, which may accelerate degradation. [Means for solving the problem]

[0005] One aspect of the nonvolatile memory device according to the present invention is a memory cell array having a plurality of non-volatile memory cells including a first memory cell and a second memory cell; a read circuit that reads data from the memory cell array via a first node and a second node; The readout circuit includes: In a first mode, a first detection current flowing through the first memory cell electrically connected to the first node is compared with a second detection current flowing through the second memory cell electrically connected to the second node, thereby reading complementary data stored in the first memory cell and the second memory cell; In the second mode, the complementary data is read by comparing the current obtained by adding or subtracting a first reference current to the first detection current with the second detection current, or by comparing the first detection current with the current obtained by adding or subtracting a second reference current to the second detection current.

[0006] One aspect of the integrated circuit device according to the present invention is The nonvolatile memory device includes one aspect of the nonvolatile memory device. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile memory device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing a detailed configuration example of a memory cell array, a switch circuit, and a read circuit in the first embodiment. [Figure 3] FIG. 4 is a diagram showing the state of the readout circuit when set to the first mode in the first embodiment. [Figure 4] FIG. 4 is a diagram showing the state of the readout circuit when set to a second mode in the first embodiment. [Figure 5]FIG. 10 is a diagram showing another state of the readout circuit when the second mode is set in the first embodiment. [Figure 6] FIG. 10 is a diagram showing an example of data read in the second mode when the difference between the first detected current and the second detected current is small in the first embodiment. [Figure 7] FIG. 10 is a diagram showing an example of data read in the second mode when the difference between the first detected current and the second detected current is large in the first embodiment. [Figure 8] FIG. 6 is an explanatory diagram of a margin for the difference between a first detected current and a second detected current. [Figure 9] FIG. 4 is a flowchart showing an example of a procedure for reading data in a first mode in the first embodiment. [Figure 10] FIG. 10 is a flowchart showing an example of a procedure for reading data in a second mode in the first embodiment. [Figure 11] FIG. 11 is a diagram showing an example of data read in the first mode and the second mode when the difference between the first detected current and the second detected current is small in the second embodiment. [Figure 12] FIG. 11 is a diagram showing an example of data read in the first mode and the second mode when the difference between the first detected current and the second detected current is large in the second embodiment. [Figure 13] FIG. 11 is a flowchart showing an example of a procedure for writing data and verifying data by reading data in a second mode according to the second embodiment. [Figure 14] FIG. 10 is a flowchart showing an example of a procedure for reading data in the first mode and the second mode in the second embodiment. [Figure 15] FIG. 11 is a diagram showing the state of the readout circuit when set to a third mode in the third embodiment. [Figure 16] FIG. 11 is a diagram showing another state of the readout circuit when the third mode is set in the third embodiment. [Figure 17] FIG. 11 is a flowchart showing an example of a procedure for reading data stored in a first memory cell in a third mode in the third embodiment. [Figure 18]FIG. 11 is a flowchart showing an example of a procedure for reading data stored in a second memory cell in a third mode in the third embodiment. [Figure 19] FIG. 10 is a diagram showing a detailed configuration example of a memory cell array, a switch circuit, and a read circuit according to a fourth embodiment. [Figure 20] FIG. 13 is a diagram showing the state of the readout circuit when set to the first mode in the fourth embodiment. [Figure 21] FIG. 13 is a diagram showing the state of the readout circuit when set to the second mode in the fourth embodiment. [Figure 22] FIG. 13 is a diagram showing another state of the readout circuit when the second mode is set in the fourth embodiment. [Figure 23] FIG. 13 is a diagram showing an example of data read in the second mode when the difference between the first detected current and the second detected current is small in the fourth embodiment. [Figure 24] FIG. 13 is a diagram showing an example of data read in the second mode when the difference between the first detected current and the second detected current is large in the fourth embodiment. [Figure 25] FIG. 13 is a flowchart showing an example of a procedure for reading data in a second mode in the fourth embodiment. [Figure 26] FIG. 1 is a functional block diagram showing an example of the configuration of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Non-volatile storage devices 1-1. First embodiment Fig. 1 is a block diagram showing a schematic configuration of a nonvolatile memory device 1 according to this embodiment. As shown in Fig. 1, the nonvolatile memory device 1 includes a memory cell array 10, a power supply circuit 20, a word line boost circuit 30, a word line drive circuit 40, a source line drive circuit 50, a switch circuit 60, a read circuit 70, a memory control circuit 80, and a register 90. Fig. 2 is a diagram showing a detailed configuration example of the memory cell array 10, the switch circuit 60, and the read circuit 70. The configuration of the nonvolatile memory device 1 will be described below with reference to Figs. 1 and 2.

[0010] The memory control circuit 80 controls the power supply circuit 20, the word line boost circuit 30, the word line drive circuit 40, the source line drive circuit 50, the switch circuit 60 and the read circuit 70 so as to cause the multiple memory cells MC included in the memory cell array 10 to perform erase, write or read operations.

[0011] The memory cell array 10 has a plurality of nonvolatile memory cells MC arranged in a matrix of m rows and 2n columns, where m and n are each integers equal to or greater than 2. For example, if m=2048 and n=1024, the memory cell array 10 may include 2048×2048 memory cells arranged in a matrix of 2048 rows and 2048 columns. Various types of memory cells MC may be considered, such as MONOS type, floating gate type, ferroelectric type, phase-change type, and magnetoresistive type. MONOS is an abbreviation for Metal-Oxide-Nitride-Oxide-Silicon.

[0012] The memory cell array 10 includes m word lines WL1, WL2,...,WLm, m source lines SL1, SL2,...,SLm, n bit lines BLA1, BLA2,...,BLAn, and n bit lines BLB1, BLB2,...,BLBn. Each of the word lines WL1 to WLm is connected to 2n memory cells MC arranged in a respective row. Each of the source lines SL1 to SLm is connected to 2n memory cells MC arranged in a respective row. Each of the bit lines BLA1 to BLAn is connected to n memory cells MC out of the 2n memory cells MC arranged in a respective column. Each of the bit lines BLB1 to BLBn is connected to the remaining n memory cells MC out of the 2n memory cells MC arranged in a respective column.

[0013] In FIG. 2, the memory cell MC connected to the word line WLi and the bit line BLAj is “MC1 ij ", and the memory cell MC connected to the word line WLi and the bit line BLBj is represented as "MC2 ij As shown in FIG. 2, the memory cell array 10 includes m×n memory cells MC1 11 ~MC1 mn and m×n memory cells MC2 11 ~MC21 mn Includes n memory cells MC1 i1 ~MC1 in and n memory cells MC2 i1 ~MC2 in Each gate of the n memory cells MC1 is connected to a word line WLi. i1 ~MC1 in and n memory cells MC2 i1 ~MC2 in Each source of the memory cells MC1 is connected to a source line SLi. i is an integer between 1 and m. 1j ~MC1 mj The drains of the m memory cells MC2 are connected to the bit lines BLAj. 1j ~MC2 mjEach drain of the memory cell MC1 is connected to a bit line BLBj, where j is an integer between 1 and n. ij and memory cell MC2 ij are complementary cells, one storing data "0" and the other storing data "1".

[0014] 1, for example, a reference power supply potential VSS, a high power supply potential VPP for erasing and writing data, and a logic power supply potential VDD for a logic circuit are externally supplied to the power supply circuit 20. Alternatively, the power supply circuit 20 may generate another power supply potential by boosting or lowering one of a plurality of power supply potentials supplied from the outside.

[0015] The reference power supply potential VSS is a reference potential that serves as a reference relative to other potentials, and the following description will be given assuming that the reference power supply potential VSS is the ground potential. The high power supply potential VPP is a predetermined potential higher than the reference power supply potential VSS, for example, about 5V to 10V. The logic power supply potential VDD is a potential higher than the reference power supply potential VSS and lower than the high power supply potential VPP, for example, about 1.2V to 1.8V.

[0016] The power supply circuit 20 supplies a logic power supply potential VDD to the memory control circuit 80, and is controlled by the memory control circuit 80 to supply, as necessary, a high power supply potential VPP and a logic power supply potential VDD to each part of the nonvolatile memory device 1. In Fig. 1, the power supply potential supplied from the power supply circuit 20 to the word line boost circuit 30 is shown as a word line power supply potential VWL, and the power supply potential supplied from the power supply circuit 20 to the source line drive circuit 50 is shown as a source line power supply potential VSL.

[0017] In an erase mode in which data in a memory cell is erased and a write mode in which data is written to a memory cell, the power supply circuit 20 supplies a high power supply potential VPP as a word line power supply potential VWL and a source line power supply potential VSL to the word line boost circuit 30 and the source line drive circuit 50. The word line boost circuit 30 supplies the high power supply potential VPP to the word line drive circuit 40 as a word line power supply potential INT_VWL.

[0018] In a read mode for reading data from a memory cell, the power supply circuit 20 supplies the logic power supply potential VDD as the word line power supply potential VWL and the source line power supply potential VSL to the word line boost circuit 30 and the source line drive circuit 50. The word line boost circuit 30 generates a drive potential higher than the logic power supply potential VDD, which is the high-potential power supply potential supplied to the read circuit 70, and supplies the drive potential to the word line drive circuit 40 as the word line power supply potential INT_VWL.

[0019] The word line driving circuit 40 drives the word line connected to the memory cell MC selected by the memory control circuit 80 from among the m word lines WL1 to WLm. The source line driving circuit 50 drives the source line connected to the memory cell MC selected by the memory control circuit 80 from among the m source lines SL1 to SLm.

[0020] In the read mode, the switch circuit 60 connects the bit line BLAk, which is connected to a memory cell MC selected by the memory control circuit 80 among the n bit lines BLA1 to BLAn, to the bit line BLA, and connects the bit line BLBk, which is connected to a memory cell MC selected by the memory control circuit 80 among the n bit lines BLB1 to BLBn, to the bit line BLB, where k is an integer between 1 and n.

[0021] 2, the switch circuit 60 includes n N-channel MOS transistors 61A-1 to 61A-n, n N-channel MOS transistors 61B-1 to 61B-n, an N-channel MOS transistor 62A, and an N-channel MOS transistor 62B. In FIG. 2, switch control signals SS1 to SSn, SSA, and SSB are signals supplied from the memory control circuit 80.

[0022] A switch control signal SSj is input to each gate of MOS transistors 61A-j, 61B-j, and switch control signals SS1 to SSn are mutually exclusively high level, where j is an arbitrary integer between 1 and n. When the switch control signal SSj is low level, MOS transistors 61A-j, 61B-j are both in an off state where their sources and drains are non-conductive, and when the switch control signal SSj is high level, MOS transistors 61A-j, 61B-j are both in an on state where their sources and drains are conductive.

[0023] A switch control signal SSA is input to the gate of the MOS transistor 62 A. When the switch control signal SSA is at a low level, the MOS transistor 62 A is in an off state where the source and drain are not conductive, and when the switch control signal SSA is at a high level, the MOS transistor 62 A is in an on state where the source and drain are conductive.

[0024] A switch control signal SSB is input to the gate of the MOS transistor 62 B. When the switch control signal SSB is at a low level, the MOS transistor 62 B is in an off state where the source and drain are not conductive, and when the switch control signal SSB is at a high level, the MOS transistor 62 B is in an on state where the source and drain are conductive.

[0025] For example, when the switch control signal SSj and the switch control signal SSA are both at a high level, the MOS transistors 61A-j and 62A are both turned on, and the m memory cells MC1 1j~MC1 mj At this time, if the word line WLi and the source line SLi are selected, the drains of the memory cells MC1 ij The drain-source of the bit line BLA is electrically connected, and a current flows from the bit line BLA to the source line SLi.

[0026] Similarly, when the switch control signal SSj and the switch control signal SSB are both at a high level, the MOS transistors 61B-j and 62B are both turned on, and the m memory cells MC2 1j ~MC2 mj At this time, if the word line WLi and the source line SLi are selected, the drains of the memory cells MC2 ij The drain-source of the bit line BLB is electrically connected to the source line SLi, and a current flows from the bit line BLB to the source line SLi.

[0027] Hereinafter, the memory cell MC1 electrically connected to the bit line BLA will be described. ij is referred to as the "first memory cell", and memory cell MC1 ij The current flowing through the memory cell MC2 electrically connected to the bit line BLB is referred to as the "first detection current." ij is referred to as the "second memory cell", and memory cell MC2 ij The current flowing through the resistor R1 is referred to as the "second detection current."

[0028] As shown in Fig. 1, in read mode, the read circuit 70 outputs a data signal DQ in response to the voltages of the bit lines BLA and BLB. Specifically, as shown in Fig. 2, the read circuit 70 includes P-channel MOS transistors 71A, 71B, 73A, and 73B, N-channel MOS transistors 74A and 74B, current sources 72A and 72B, and an output circuit 75. In Fig. 2, enable signals ENA and ENB are signals supplied from the memory control circuit 80.

[0029] The MOS transistor 71A has a gate and a drain connected to a first node N1, and a source connected to a VDD node, which is a power supply node to which a logic power supply potential VDD is supplied. The first node N1 is connected to the bit line BLA. The MOS transistor 71B has a gate connected to the gate of the MOS transistor 71A and the first node N1, a drain connected to a second node N2, and a source connected to the VDD node. The second node N2 is connected to the bit line BLB.

[0030] For example, when the switch control signals SSj, SSA, and SSB are all at a high level and the word line WLi and the source line SLi are selected, the first memory cell MC1 ij is electrically connected to the bit line BLA, and the second memory cell MC2 ij is electrically connected to the bit line BLB. At this time, the MOS transistor 71A and the memory cell MC1 ij A current flows to the VSS node, which is a reference node to which the reference power supply potential VSS is supplied, via the memory cell MC1. ij A first detection current ID1 flows from the VDD node to the MOS transistor 71B and the memory cell MC2. ij A current flows to the VSS node via memory cell MC2. ij A second detection current ID2 flows through the resistor .

[0031] The current source 72A has one end connected to the first node N1 and the other end connected to the VSS node. The current source 72A operates when the enable signal ENA is at a high level, and flows a first reference current IR1 from the first node N1 to the VSS node. The current source 72B has one end connected to the second node N2 and the other end connected to the VSS node. The current source 72B operates when the enable signal ENB is at a high level, and flows a second reference current IR2 from the second node N2 to the VSS node. It is preferable that the first reference current IR1 and the second reference current IR2 are equal. Here, "equal" is a concept that also includes cases where slight differences occur due to manufacturing errors, etc.

[0032] The MOS transistor 73A has a gate connected to the bit line BLA, a source connected to the VDD node, and a drain connected to the third node N3. The MOS transistor 74A has a gate connected to the gate of the MOS transistor 74B and the fourth node N4, a source connected to the VSS node, and a drain connected to the third node N3.

[0033] The MOS transistor 73B has a gate connected to the bit line BLB, a source connected to the VDD node, and a drain connected to the fourth node N4. The MOS transistor 74B has a gate and a drain connected to the gate of the MOS transistor 74A and the fourth node N4, and a source connected to the VSS node.

[0034] The output circuit 75 selects either the third node N3 or the fourth node N4 as the output node and outputs a low-level or high-level data signal DQ. The following description will be given taking the third node N3 as the output node as an example. In this embodiment, when the voltage V1 of the first node N1 connected to the bit line BLA is lower than the voltage V2 of the second node N2 connected to the bit line BLB, the voltage V3 of the third node N3 becomes higher than the voltage V4 of the fourth node N4, and the output circuit 75 outputs a high-level data signal DQ. Also, when the voltage V1 of the first node N1 is higher than the voltage V2 of the second node N2, the voltage V3 of the third node N3 becomes lower than the voltage V4 of the fourth node N4, and the output circuit 75 outputs a low-level data signal DQ. A high-level data signal DQ corresponds to data "1," and a low-level data signal DQ corresponds to data "0." In this manner, the read circuit 70 reads data from the memory cell array 10 via the first node N1 and the second node N2.

[0035] The memory control circuit 80 is configured with, for example, a logic circuit or an analog circuit, and receives a chip selection signal CS, a mode selection signal MS, a clock signal CK, and an address signal ADR from outside the nonvolatile memory device 1. In addition, the memory control circuit 80 receives a read mode selection signal RMS from a register 90.

[0036] When the nonvolatile memory device 1 is selected by the chip selection signal CS, the memory control circuit 80 sets the nonvolatile memory device 1 to an erase mode, a write mode or a read mode in accordance with the mode selection signal MS.

[0037] In the erase mode, the memory control circuit 80 synchronizes with the clock signal CK and controls each part of the nonvolatile memory device 1 to erase data in multiple memory cells MC specified by the address signal ADR. For example, erasing the data sets the data in the memory cells MC to "1." If the m×n memory cells MC included in the memory cell array 10 are divided into multiple sectors, in the erase mode the memory control circuit 80 may simultaneously erase the data in all memory cells MC included in the sector specified by the address signal ADR.

[0038] In the write mode, the memory control circuit 80 receives write data WDT from the outside and controls each unit of the nonvolatile memory device 1 so as to write each bit of the write data WDT to a plurality of memory cells MC designated by the address signal ADR. For example, each bit of data in the plurality of memory cells MC to be written is set to "1" in advance by data erasure or the like, and data "0" is written to the necessary memory cells MC.

[0039] In the read mode, the memory control circuit 80 controls each unit of the nonvolatile memory device 1 so as to sequentially read out data from a plurality of memory cells MC designated by the address signal ADR as a data signal DQ. The memory control circuit 80 then reads out the data from the plurality of memory cells MC designated by the address signal ADR and outputs the data to the outside as read data RDT.

[0040] In this embodiment, the read mode includes a first mode and a second mode. In the first mode, the read circuit 70 compares the first detection current ID1 with the second detection current ID2 to determine the current density of the first memory cell MC1. ij The first data stored in the second memory cell MC2 ijIn the second mode, the read circuit 70 compares a current obtained by adding a first reference current IR1 to the first detection current ID1 with the second detection current ID2 to read complementary data, or compares the first detection current ID1 with a current obtained by adding a second reference current IR2 to the second detection current ID2 to read complementary data.

[0041] The register 90 outputs a read mode selection signal RMS to the memory control circuit 80. The register 90 is accessible from outside the nonvolatile memory device 1, and the read mode can be set externally to either the first mode or the second mode. In other words, the register 90 is a register that can be externally set to operate the read circuit 70 in either the first mode or the second mode.

[0042] In the first mode, both enable signals ENA and ENB are at low level. Figure 3 shows the state of the read circuit 70 when the read mode is set to the first mode. As shown in Figure 3, in the first mode, the enable signal ENA is at low level and the current source 72A stops operating, so the first reference current IR1 does not flow. Also, the enable signal ENB is at low level and the current source 72B stops operating, so the second reference current IR2 does not flow.

[0043] In the example of FIG. 3, the first memory cell MC1 ij is connected, the first memory cell MC1 ij A first detection current ID1 flows through the bit line BLB. ij is connected, the second memory cell MC2 ij A second detection current ID2 flows through the bit line BLA. The voltage V1 at the first node N1 connected to the bit line BLA is determined in accordance with the first detection current ID1, and the voltage V2 at the second node N2 connected to the bit line BLB is determined in accordance with the second detection current ID2.

[0044] First memory cell MC1 ij and the second memory cell MC2 ij is a complementary cell, and the first memory cell MC1 ij and the second memory cell MC2 ij The first memory cell MC1 stores complementary data, one of which is data "1" and the other is data "0." ij stores data "1", and the second memory cell MC2 ij When the first memory cell MC1 stores data "0", the first detection current ID1 is greater than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. ij stores data "0", and the second memory cell MC2 ij When the data "1" is stored in the first node N1, the first detection current ID1 is smaller than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ.

[0045] In this way, in the first mode, the read circuit 70 reads the first memory cell MC1 electrically connected to the first node N1. ij a first detection current ID1 flowing through the second memory cell MC2 electrically connected to the second node N2; ij By comparing the detected current ID2 flowing through the first memory cell MC1 with the detected current ID2 flowing through the first memory cell MC1, ij and the second memory cell MC2 ij The complementary data stored in the buffer is read out as a data signal DQ.

[0046] In the second mode, one of the enable signals ENA and ENB is at a low level and the other is at a high level. Figures 4 and 5 show the state of the read circuit 70 when the read mode is set to the second mode. In the example of Figures 4 and 5, as in Figure 3, the first memory cell MC1 is connected to the VDD node via the first node N1. ijA first detection current ID1 flows from the VDD node to the second memory cell MC2 via the second node N2. ij 4 and 5, in the second mode, one of the current sources 72A and 72B operates, and the other does not operate.

[0047] 4, the enable signal ENA is at a high level, causing the current source 72A to operate, resulting in a first reference current IR1 flowing. Therefore, a current ID1+IR1, which is the sum of the first detection current ID1 and the first reference current IR1, flows through the MOS transistor 71A. Meanwhile, the enable signal ENB is at a low level, causing the current source 72B to stop operating, preventing the second reference current IR2 from flowing, and instead causing the second detection current ID2 to flow through the MOS transistor 71B. The voltage V1 at the first node N1 is determined in accordance with the current ID1+IR1 flowing through the MOS transistor 71A, and the voltage V2 at the second node N2 is determined in accordance with the second detection current ID2 flowing through the MOS transistor 71B.

[0048] First memory cell MC1 ij stores data "1", and the second memory cell MC2 ij When the first memory cell MC1 stores data "0", the first detection current ID1 is larger than the second detection current ID2. Therefore, the current ID1+IR1 is larger than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. On the other hand, when the first memory cell MC1 stores data "0", the first detection current ID1 is larger than the second detection current ID2. Therefore, the current ID1+IR1 is larger than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. ij stores data "0", and the second memory cell MC2 ijWhen the first node N1 stores data "1," the first detection current ID1 is smaller than the second detection current ID2. At this time, if the difference between the first detection current ID1 and the second detection current ID2 is larger than the first reference current IR1, the current ID1+IR1 is smaller than the second detection current ID2. As a result, the voltage V1 at the first node N1 is higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ. On the other hand, if the difference between the first detection current ID1 and the second detection current ID2 is smaller than the first reference current IR1, the current ID1+IR1 is larger than the second detection current ID2. As a result, the voltage V1 at the first node N1 is lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ.

[0049] 5, the enable signal ENA is at a low level, causing the current source 72A to stop operating, preventing the first reference current IR1 from flowing, and instead causing the first detection current ID1 to flow through the MOS transistor 71A. Meanwhile, the enable signal ENB is at a high level, causing the current source 72B to operate, causing the second reference current IR2 to flow. Therefore, a current ID2+IR2, which is the sum of the second detection current ID2 and the second reference current IR2, flows through the MOS transistor 71B. The voltage V1 at the first node N1 is determined in accordance with the first detection current ID1 flowing through the MOS transistor 71A, and the voltage V2 at the second node N2 is determined in accordance with the current ID2+IR2 flowing through the MOS transistor 71B.

[0050] First memory cell MC1 ij stores data "1", and the second memory cell MC2 ijWhen the first memory cell MC1 stores data "0," the first detection current ID1 becomes larger than the second detection current ID2. At this time, if the difference between the first detection current ID1 and the second detection current ID2 is larger than the second reference current IR2, the first detection current ID1 becomes larger than the current ID2+IR2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. On the other hand, if the difference between the first detection current ID1 and the second detection current ID2 is smaller than the second reference current IR2, the first detection current ID1 becomes smaller than the current ID2+IR2. As a result, the voltage V1 at the first node N1 becomes higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ. On the other hand, when the first memory cell MC1 stores data "0," the first detection current ID1 becomes larger than the current ID2+IR2. ij stores data "0", and the second memory cell MC2 ij When the data "1" is stored in the first node N1, the first detection current ID1 is smaller than the second detection current ID2. Therefore, the first detection current ID1 is smaller than the current ID2+IR2. As a result, the voltage V1 at the first node N1 becomes higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ.

[0051] In this way, in the second mode, the read circuit 70 reads the first memory cell MC1 electrically connected to the first node N1. ij a current ID1+IR1 obtained by adding a first reference current IR1 to a first detection current ID1 flowing through the second memory cell MC2 electrically connected to the second node N2; ij By comparing the detected current ID2 flowing through the first memory cell MC1 with the detected current ID2 flowing through the first memory cell MC1, ij and the second memory cell MC2 ij Alternatively, in the second mode, the read circuit 70 reads out the complementary data stored in the first memory cell MC1 electrically connected to the first node N1 as the data signal DQ. ij a first detection current ID1 flowing through the second memory cell MC2 electrically connected to the second node N2; ijThe second detection current ID2 flowing through the first memory cell MC1 is added to the second reference current IR2 to obtain a current ID2+IR2. ij and the second memory cell MC2 ij The complementary data stored in the buffer is read out as a data signal DQ.

[0052] In this second mode, data is read from, for example, the first memory cell MC1 ij and the second memory cell MC2 ij and verifying the complementary data written to the first memory cell MC1 in the initial state. ij and the second memory cell MC2 ij When the data stored in is regarded as complementary data, it can be used to check whether the initial value of the complementary data is "1", "0", or indefinite.

[0053] Specifically, the read circuit 70 first reads complementary data by adding the first reference current IR1 to the first detection current ID1, and then reads complementary data by adding the second reference current IR2 to the second detection current ID2. If the two read complementary data do not match, this indicates that there is insufficient margin for the threshold for determining whether data is "1" or "0." For example, as shown in FIG. 6, if the difference between the first detection current ID1 and the second detection current ID2 is small, the data read by adding the first reference current IR1 to the first detection current ID1 is "1," while the data read by adding the second reference current IR2 to the second detection current ID2 is "0." Therefore, the two data do not match. For example, if the two complementary data do not match during verification after writing the complementary data, the data is written again. Furthermore, when checking the initial values of the complementary data, the data is determined to be indefinite.

[0054] On the other hand, if the two read complementary data match, it means that there is a sufficient margin for the threshold for determining whether data is "1" or "0." For example, as shown in FIG. 7, if the difference between the first detection current ID1 and the second detection current ID2 is large, the data read by adding the first reference current IR1 to the first detection current ID1 is "1," while the data read by adding the second reference current IR2 to the second detection current ID2 is "1," so the two match. For example, if the two complementary data match when verified after being written, there is no need to write them again. Furthermore, when checking the initial value of the complementary data, it is determined to be data "1" or data "0."

[0055] Here, assuming that the first reference current IR1 and the second reference current IR2 are equal, the first memory cell MC1, which is a complementary cell, ij and the second memory cell MC2 ij Let us consider a case where data "1" is written to one of the paired first memory cells MC1 and data "0" is written to the other. In this case, if the difference between the first detection current ID1 and the second detection current ID2 is larger than the first reference current IR1 (=second reference current IR2), erroneous reading of complementary data will not occur. ij and the second memory cell MC2 ijTherefore, as shown in FIG. 8, it is acceptable for the difference between the first detection current ID1 and the second detection current ID2 to be greater than the first reference current IR1 (=second reference current IR2). Therefore, as compared to conventional writing, in which the distribution of the detection current flowing through each memory storing data "1" and the distribution of the detection current flowing through each memory storing data "0" are distributed so that they do not overlap above or below the reference current, this embodiment does not require an excessive margin for the difference between the first detection current ID1 and the second detection current ID2, thereby reducing the write time. Therefore, it is not necessary to apply excessive stress to each memory cell MC, and deterioration of each memory cell MC is reduced.

[0056] 9 is a flowchart showing an example of a procedure for reading data in the first mode. In the example of FIG. 9, first, in step S1, an external device of the nonvolatile memory device 1 sets the first mode in the register 90. Next, if a data read request is received from the external device in step S2, the read circuit 70 compares the first detection current ID1 with the second detection current ID2 and reads complementary data in step S3. Then, the external device obtains read data RDT including the complementary data output from the nonvolatile memory device 1.

[0057] FIG. 10 is a flowchart illustrating an example of a procedure for reading data in the second mode. In the example of FIG. 10, first, in step S11, an external device of the nonvolatile memory device 1 sets the register 90 to the second mode. Next, if a data read request is received from the external device in step S12, the read circuit 70 compares a current ID1+IR1, which is obtained by adding a first reference current IR1 to a first detection current ID1, with a second detection current ID2 in step S13 to read complementary data. Then, the external device acquires read data RDT, which is output from the nonvolatile memory device 1 and includes the complementary data. Furthermore, in step S14, the read circuit 70 compares a current ID2+IR2, which is obtained by adding a second reference current IR2 to a first detection current ID1, with the first detection current ID1 to read the complementary data. Then, the external device acquires read data RDT, which is output from the nonvolatile memory device 1 and includes the complementary data. If the two complementary data contained in the two acquired read data RDT match, the external device can determine that the difference between the first detection current ID1 and the second detection current ID2 is sufficient, and if the two complementary data do not match, the external device can determine that the difference between the first detection current ID1 and the second detection current ID2 is insufficient.

[0058] In the nonvolatile memory device 1 according to the first embodiment described above, the read circuit 70 compares the current ID1+IR1 obtained by adding the first reference current IR1 to the first detection current ID1 with the second detection current ID2 in the second mode. ij and the second memory cell MC2 ij The complementary data can be read by reading out the complementary data stored in the first detection current ID1 and comparing it with a current ID2+IR2 obtained by adding a second reference current IR2 to the second detection current ID2.

[0059] For example, the external device may ij and the second memory cell MC2 ijIn a verify operation after writing complementary data to the first memory cell MC1, it is determined whether the two complementary data read in the second mode match, and the writing of complementary data is repeated until they match, and the writing can be completed when the difference between the first detection current ID1 and the second detection current ID2 becomes larger than the first reference current IR1 and the second reference current IR2. Therefore, according to the nonvolatile memory device 1 of the first embodiment, it is not necessary to make the difference between the first detection current ID1 and the second detection current ID2 larger than necessary, and the writing time can be shortened, and stress due to application of a high voltage during writing is reduced, ij and the second memory cell MC2 ij This can reduce the risk of accelerated deterioration of the

[0060] Furthermore, for example, in the initial state of the nonvolatile memory device 1, the external device reads the first memory cell MC1 ij and the second memory cell MC2 ij It is possible to determine whether the initial value of the data stored in is "0", "1", or indefinite.

[0061] Furthermore, according to the nonvolatile memory device 1 of the first embodiment, an external device can arbitrarily select whether to read complementary data in the first mode or the second mode, thereby improving versatility.

[0062] 1-2. Second embodiment Hereinafter, for the nonvolatile memory device 1 of the second embodiment, the same symbols will be used for configurations similar to those of the first embodiment, and explanations similar to those of the first embodiment will be omitted or simplified, with the main focus being on the differences from the first embodiment.

[0063] A block diagram showing the schematic configuration of the nonvolatile memory device 1 of the second embodiment is the same as Fig. 1, and therefore its illustration and description will be omitted. In addition, the detailed configurations of the memory cell array 10, switch circuit 60, and read circuit 70 in the second embodiment are the same as Fig. 2, and therefore their illustration and description will be omitted.

[0064] In the second embodiment, the register 90 can set the read mode to the first mode. Data reading in the first mode is the same as in the first embodiment.

[0065] In the second embodiment, the register 90 can set the read mode to the second mode. When the register 90 is set to the second mode, the read circuit 70 reads data only once in the second mode based on the write data in the verify operation after the data is written. Specifically, the read circuit 70 reads data from the first memory cell MC1 ij and the second memory cell MC2 ij Based on the complementary data written to the first memory cell MC1, it is determined whether to add the first reference current IR1 to the first detection current ID1 or the second reference current IR2 to the second detection current ID2, and the complementary data is read in the second mode. ij The first data "0" is stored in the second memory cell MC2. ij When the second data "1" is written to the first memory cell MC1, the read circuit 70 compares the current ID1+IR1 obtained by adding the first reference current IR1 to the first detection current ID1 with the second detection current ID2 in the second mode. ij and the second memory cell MC2 ij The complementary data stored in the first memory cell MC1 is read out as a data signal DQ. ij The first data "1" is stored in the second memory cell MC2. ij When the second data "0" is written to the first memory cell MC1, the read circuit 70 compares the first detection current ID1 with the current ID2+IR2 obtained by adding the second reference current IR2 to the second detection current ID2 in the second mode. ij and the second memory cell MC2 ij The complementary data stored in the complementary data register 10 is read out as a data signal DQ. If the written complementary data does not match the read complementary data in the verification after the complementary data has been written, the complementary data is written again.

[0066] In the second embodiment, the register 90 can set the read mode to both the first mode and the second mode. When the register 90 is set to both the first mode and the second mode, the read circuit 70 first reads data in the first mode, and then reads data only once in the second mode based on the read complementary data. Specifically, the read circuit 70 reads data from the first memory cell MC1 in the first mode. ij and the second memory cell MC2 ij and determines whether to add a first reference current IR1 to the first detection current ID1 or a second reference current IR2 to the second detection current ID2 based on the complementary data read in the first mode, and reads the complementary data in the second mode. For example, when data "0" is read in the first mode, the read circuit 70 compares the current ID1+IR1 obtained by adding the first reference current IR1 to the first detection current ID1 with the second detection current ID2 in the second mode. ij and the second memory cell MC2 ij When the read circuit 70 reads out the data "1" in the first mode, the read circuit 70 compares the first detection current ID1 with the current ID2+IR2 obtained by adding the second reference current IR2 to the second detection current ID2, thereby detecting the complementary data stored in the first memory cell MC1. ij and the second memory cell MC2 ij The complementary data stored in the buffer is read out as a data signal DQ.

[0067] In the first and second modes, data is read from the first memory cell MC1 in the initial state, for example. ij and the second memory cell MC2 ij When the data stored in is regarded as complementary data, it can be used to check whether the initial value of the complementary data is "1", "0", or indefinite.

[0068] Specifically, if the complementary data read in the first mode and the complementary data read in the second mode do not match, this means that there is an insufficient margin for the threshold for determining whether data is "1" or "0." For example, as shown in the upper part of FIG. 11, when the difference between the first detection current ID1 and the second detection current ID2 is small, the data read in the first mode is "1," whereas the data read in the second mode by adding the second reference current IR2 to the second detection current ID2 is "0," so the two do not match. Also, as shown in the lower part of FIG. 11, when the difference between the second detection current ID2 and the first detection current ID1 is small, the data read in the first mode is "0," whereas the data read in the second mode by adding the first reference current IR1 to the first detection current ID1 is "1," so the two do not match. Therefore, in these cases, the data is determined to be indefinite.

[0069] On the other hand, if the complementary data read in the first mode and the complementary data read in the second mode match, this means that there is a sufficient margin for the decision threshold between data "1" and data "0." For example, as shown in the upper part of FIG. 12, when the difference between the first detection current ID1 and the second detection current ID2 is large, the data read in the first mode is "1," whereas the data read in the second mode by adding the second reference current IR2 to the second detection current ID2 is "1," so the two match. Therefore, in this case, the data is determined to be "1." Also, as shown in the lower part of FIG. 12, when the difference between the second detection current ID2 and the first detection current ID1 is large, the data read in the first mode is "0," whereas the data read in the second mode by adding the first reference current IR1 to the first detection current ID1 is "0," so the two match. Therefore, in this case, the data is determined to be "0."

[0070] Fig. 13 is a flowchart showing an example of a procedure for writing data and verifying data by reading it in the second mode. In the example of Fig. 13, first, in step S21, an external device of the nonvolatile memory device 1 sets the second mode in the register 90. Next, if a data write request is received from the external device in step S22, complementary data is written in step S23.

[0071] Next, in step S24, if the complementary data written in step S23 is "0," then in step S25, the read circuit 70 compares the current ID1+IR1, obtained by adding the first reference current IR1 to the first detection current ID1, with the second detection current ID2 in the second mode to read the complementary data. The external device then obtains read data RDT, including the complementary data, output from the nonvolatile memory device 1. On the other hand, if the complementary data written in step S23 is "1" in step S24, then in step S26, the read circuit 70 compares the first detection current ID1 with the current ID2+IR2, obtained by adding the second detection current ID2 and the second reference current IR2, to read the complementary data. The external device then obtains read data RDT, including the complementary data, output from the nonvolatile memory device 1. If the complementary data contained in the write data WDT matches the complementary data contained in the acquired read data RDT, the external device determines that the difference between the first detection current ID1 and the second detection current ID2 is sufficient; if the two complementary data do not match, the external device determines that the difference between the first detection current ID1 and the second detection current ID2 is insufficient, and can write data again.

[0072] 14 is a flowchart showing an example of a procedure for reading data in the first mode and the second mode. In the example of FIG. 14, first, in step S31, an external device of the nonvolatile memory device 1 sets the first mode and the second mode in the register 90. Next, if a data read request is received from the external device in step S32, the read circuit 70 compares the first detection current ID1 and the second detection current ID2 in the first mode and reads complementary data in step S33. Then, the external device obtains read data RDT including the complementary data output from the nonvolatile memory device 1.

[0073] Next, in step S34, if the complementary data read in step S33 is "0," then in step S35, the read circuit 70 compares the current ID1+IR1, obtained by adding the first reference current IR1 to the first detection current ID1, with the second detection current ID2 in the second mode to read the complementary data. The external device then obtains read data RDT, including the complementary data, output from the nonvolatile memory device 1. On the other hand, if the complementary data read in step S33 is "1" in step S34, then in step S36, the read circuit 70 compares the first detection current ID1 with the current ID2+IR2, obtained by adding the second detection current ID2 and the second reference current IR2, to read the complementary data. The external device then obtains read data RDT, including the complementary data, output from the nonvolatile memory device 1. If the two complementary data contained in the two acquired read data RDT match, the external device can determine that the difference between the first detection current ID1 and the second detection current ID2 is sufficient, and if the two complementary data do not match, the external device can determine that the difference between the first detection current ID1 and the second detection current ID2 is insufficient.

[0074] Other configurations and functions of the nonvolatile memory device 1 of the second embodiment are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0075] According to the nonvolatile memory device 1 of the second embodiment described above, the same effects as those of the nonvolatile memory device 1 of the first embodiment can be obtained.

[0076] Furthermore, according to the nonvolatile memory device 1 of the second embodiment, the read circuit 70 sequentially reads complementary data in the first mode and then in the second mode in response to an instruction from an external device, thereby reducing the processing load on the external device compared to when the external device instructs the read of complementary data in the first mode and then instructs the read of complementary data in the second mode.

[0077] Furthermore, according to the nonvolatile memory device 1 of the second embodiment, the read circuit 70 only needs to read once in the second mode for verifying the complementary data after it has been written, thereby reducing the time required for verifying. Furthermore, according to the nonvolatile memory device 1 of the second embodiment, the read circuit 70 reads data for verifying the data after it has been written in response to a write instruction from an external device, thereby reducing the processing load on the external device compared to when the external device instructs writing and then instructs reading data for verifying the data after it has been written.

[0078] 1-3. Third embodiment Hereinafter, for the nonvolatile memory device 1 of the third embodiment, the same symbols will be used for configurations similar to those of the first or second embodiment, and explanations similar to those of the first or second embodiment will be omitted or simplified, with the focus being on the differences from the first and second embodiments.

[0079] A block diagram showing the schematic configuration of the nonvolatile memory device 1 of the third embodiment is the same as that of Fig. 1, and therefore illustration and description thereof will be omitted. In addition, detailed configurations of the memory cell array 10, switch circuit 60, and read circuit 70 in the third embodiment are the same as those of Fig. 2, and therefore illustration and description thereof will be omitted.

[0080] In the third embodiment, the register 90 can set the read mode to the first mode. Data reading in the first mode is similar to that in the first embodiment. Also, in the third embodiment, the register 90 can set the read mode to the second mode. Data reading in the second mode is similar to that in the first or second embodiment. Also, in the third embodiment, the register 90 may be able to set the read mode to either the first mode or the second mode. Data reading in the first mode and the second mode is similar to that in the second embodiment.

[0081] Furthermore, in the third embodiment, the register 90 can set the read mode to a third mode.

[0082] In the third mode, the read circuit 70 compares the first detection current ID1 with the second reference current IR2 to determine whether the first memory cell MC1 ij or by comparing the second detection current ID2 with the first reference current IR1, ij The data stored in

[0083] In the third mode, the switch control signal SSA and the enable signal ENB are at a high level, and the switch control signal SSB and the enable signal ENA are at a low level, so that the first memory cell MC1 ij Alternatively, the switch control signal SSB and the enable signal ENA are set to a high level, and the switch control signal SSA and the enable signal ENB are set to a low level, so that the data stored in the second memory cell MC2 is read out. ij In the third mode, the data stored in the first memory cell MC1 is read out. ij When the data stored in the second memory cell MC2 is read, the third node N3 is selected as the output node by the output circuit 75, and the second memory cell MC2 ijWhen data stored in is read, the fourth node N4 is selected as the output node by the output circuit 75. Figures 15 and 16 show the state of the read circuit 70 when the read mode is set to the third mode.

[0084] In the example of FIG. 15, the first memory cell MC1 ij The first detection current ID1 flows through the second memory cell MC2 ij The second detection current ID2 does not flow through the MOS transistor 71A. Furthermore, because the enable signal ENA is at a low level and the current source 72A is stopped from operating, the first reference current IR1 does not flow, and the first detection current ID1 flows through the MOS transistor 71A. On the other hand, because the enable signal ENB is at a high level and the current source 72B is operating, the second reference current IR2 flows through the MOS transistor 71B. The voltage V1 at the first node N1 is determined according to the first detection current ID1 flowing through the MOS transistor 71A, and the voltage V2 at the second node N2 is determined according to the second reference current IR2 flowing through the MOS transistor 71B.

[0085] First memory cell MC1 ij When the first memory cell MC1 stores data "1", the first detection current ID1 becomes larger than the second reference current IR2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. ij stores data "0," the first detection current ID1 is smaller than the second reference current IR2. As a result, the voltage V1 at the first node N1 becomes higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ.

[0086] In the example of FIG. 16, the second memory cell MC2 ij A second detection current ID2 flows through the first memory cell MC1 ijThe first detection current ID1 does not flow through the MOS transistor 71B. Furthermore, because the enable signal ENB is at a low level and the current source 72B is stopped from operating, the second reference current IR2 does not flow, and the second detection current ID2 flows through the MOS transistor 71B. On the other hand, because the enable signal ENA is at a high level and the current source 72A is operating, the first reference current IR1 flows through the MOS transistor 71A. The voltage V2 at the second node N2 is determined according to the second detection current ID2 flowing through the MOS transistor 71B, and the voltage V1 at the first node N1 is determined according to the first reference current IR1 flowing through the MOS transistor 71A.

[0087] Second memory cell MC2 ij When the second memory cell MC2 stores data "1", the second detection current ID2 becomes larger than the first reference current IR1. As a result, the voltage V2 at the second node N2 becomes lower than the voltage V1 at the first node N1, and the output circuit 75 outputs a high-level data signal DQ. ij stores data "0," the second detection current ID2 is smaller than the first reference current IR1. As a result, the voltage V2 at the second node N2 becomes higher than the voltage V1 at the first node N1, and the output circuit 75 outputs a low-level data signal DQ.

[0088] In this way, in the third embodiment, the register 90 can set the read mode to the third mode. That is, in the third embodiment, the register 90 is a register that can externally set whether the read circuit 70 operates in the first mode, the second mode, or the third mode.

[0089] In this embodiment, the first memory cell MC1 ij and the second memory cell MC2 ij The first memory cell MC1 may store complementary data in pairs, or may store data individually. ij and the second memory cell MC2 ijThe complementary data stored in the first memory cell MC1 is read in the first mode, and in the latter case, ij and the second memory cell MC2 ij The data stored individually in each of the memory cells is read out in the third mode.

[0090] The memory cells MC included in the memory cell array 10 may be divided into multiple groups, and the register 90 may be configured to set whether data is to be read in the first mode or the third mode for each group. For example, each memory cell MC included in the first group may store complementary data in pairs, and each memory cell MC included in the second group may store data individually. In this case, the read circuit 70 may read complementary data from each pair of memory cells MC in the first group in the first mode, and read data from each memory cell MC in the second group in the third mode. The memory cells MC included in the memory cell array 10 may be divided into groups for each sector.

[0091] 17 and 18 are flowcharts showing an example of a procedure for reading data in the third mode.

[0092] FIG. 17 shows the first memory cell MC1 ij 17 is a diagram showing a procedure for reading data stored in the nonvolatile memory device 1. In the example of FIG. 17, first, in step S41, an external device of the nonvolatile memory device 1 sets the third mode in the register 90. Next, if there is a data read request from the external device in step S42, the read circuit 70 compares the first detection current ID1 with the second reference current IR2 and reads the data in step S43. Then, the external device obtains read data RDT including the data output from the nonvolatile memory device 1.

[0093] FIG. 18 shows the second memory cell MC2 ij18 is a diagram showing a procedure for reading data stored in the nonvolatile memory device 1. In the example of FIG. 18, first, in step S51, an external device of the nonvolatile memory device 1 sets the third mode in the register 90. Next, if there is a data read request from the external device in step S52, the read circuit 70 compares the second detection current ID2 with the first reference current IR1 and reads the data in step S53. Then, the external device obtains read data RDT including the data output from the nonvolatile memory device 1.

[0094] Other configurations and functions of the nonvolatile memory device 1 of the third embodiment are the same as those of the first or second embodiment, and therefore description thereof will be omitted.

[0095] According to the nonvolatile memory device 1 of the third embodiment described above, the same effects as those of the nonvolatile memory device 1 of the first or second embodiment can be obtained. Furthermore, according to the nonvolatile memory device 1 of the third embodiment, an external device can ij and the second memory cell MC2 ij In other words, according to the nonvolatile memory device 1 of the third embodiment, it is possible to select whether to store complementary data or individual data in each memory cell MC, and to read out the two individual data in the third mode. That is, according to the nonvolatile memory device 1 of the third embodiment, it is possible to select whether to store complementary data or individual data in each memory cell MC, and therefore an external device can use the memory cell array 10 for general purposes depending on the application. For example, when storing multiple data of different types in the memory cell array 10, the utilization efficiency of the memory cell array 10 can be improved by appropriately selecting whether to store complementary data or individual data depending on the characteristics of each data.

[0096] Furthermore, according to the nonvolatile memory device 1 of the third embodiment, an external device can arbitrarily select whether to read data in the first mode, the second mode, or the third mode, thereby improving versatility.

[0097] 1-4. Fourth embodiment Hereinafter, for the nonvolatile memory device 1 of the fourth embodiment, the same symbols will be used for configurations similar to those of the first to third embodiments, and explanations similar to those of the first to third embodiments will be omitted or simplified, with the main focus being on the differences from the first to third embodiments.

[0098] A block diagram showing the schematic configuration of the nonvolatile memory device 1 of the fourth embodiment is the same as that of Fig. 1, and therefore its illustration and description will be omitted. Fig. 19 is a diagram showing a detailed configuration example of the memory cell array 10, switch circuit 60, and read circuit 70 in the fourth embodiment. The configurations of the memory cell array 10 and switch circuit 60 are the same as those of Fig. 2, and therefore their description will be omitted.

[0099] As shown in FIG. 19, the readout circuit 70 in the fourth embodiment differs from the readout circuit 70 in the first to third embodiments shown in FIG. 2 in that current sources 76A and 76B are added.

[0100] The current source 76A has one end connected to the VDD node and the other end connected to a first node N1. The current source 76A operates when an enable signal ENA2 is at a high level, and flows a first reference current IR1 from the VDD node to the first node N1. The current source 76B has one end connected to the VDD node and the other end connected to a second node N2. The current source 76B operates when an enable signal ENB2 is at a high level, and flows a second reference current IR2 from the VDD node to the second node N2. The enable signals ENA2 and ENB2 are signals supplied from the memory control circuit 80. It is preferable that the first reference current IR1 and the second reference current IR2 are equal. Here, "equal" is a concept that also includes cases where slight differences occur due to manufacturing errors, etc.

[0101] In the first mode, the enable signals ENA, ENB, ENA2, and ENB2 are all low. Figure 20 shows the state of the read circuit 70 when the read mode is set to the first mode. As shown in Figure 20, in the first mode, the enable signal ENA is low and the current source 72A stops operating, so the first reference current IR1 does not flow. Also, the enable signal ENB is low and the current source 72B stops operating, so the second reference current IR2 does not flow.

[0102] In the example of FIG. 20, the first memory cell MC1 ij is connected, the first memory cell MC1 ij A first detection current ID1 flows through the bit line BLB. ij is connected, the second memory cell MC2 ij A second detection current ID2 flows through the first node N1. The voltage V1 at the first node N1 is determined in accordance with the first detection current ID1, and the voltage V2 at the second node N2 is determined in accordance with the second detection current ID2.

[0103] First memory cell MC1 ij and the second memory cell MC2 ij is a complementary cell, and the first memory cell MC1 ij and the second memory cell MC2 ij The first memory cell MC1 stores complementary data, one of which is data "1" and the other is data "0." ij stores data "1", and the second memory cell MC2 ij When the first memory cell MC1 stores data "0", the first detection current ID1 is greater than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. ij stores data "0", and the second memory cell MC2 ijWhen the data "1" is stored in the first node N1, the first detection current ID1 is smaller than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ.

[0104] In this way, in the first mode, the read circuit 70 reads the first memory cell MC1 electrically connected to the first node N1. ij a first detection current ID1 flowing through the second memory cell MC2 electrically connected to the second node N2; ij By comparing the detected current ID2 flowing through the first memory cell MC1 with the detected current ID2 flowing through the first memory cell MC1, ij and the second memory cell MC2 ij The complementary data stored in the buffer is read out as a data signal DQ.

[0105] In the second mode, both the enable signals ENA and ENB are at a low level. Also, one of the enable signals ENA2 and ENB2 is at a low level, and the other is at a high level. FIGS. 21 and 22 show the state of the read circuit 70 when the read mode is set to the second mode. In the examples of FIGS. 21 and 22, as in FIG. 20, the first memory cell MC1 is connected to the VDD node via the first node N1. ij A first detection current ID1 flows from the VDD node to the second memory cell MC2 via the second node N2. ij 21 and 22, in the second mode, the current sources 72A and 72B stop operating, one of the current sources 76A and 76B operates, and the other stops operating.

[0106] 21, the enable signal ENA2 is at a high level, causing the current source 76A to operate, resulting in a first reference current IR1 flowing. Therefore, a current ID1-IR1, which is the first detection current ID1 minus the first reference current IR1, flows through the MOS transistor 71A. Meanwhile, the enable signal ENB2 is at a low level, causing the current source 76B to stop operating, preventing the second reference current IR2 from flowing, and instead causing the second detection current ID2 to flow through the MOS transistor 71B. The voltage V1 at the first node N1 is determined in accordance with the current ID1-IR1 flowing through the MOS transistor 71A, and the voltage V2 at the second node N2 is determined in accordance with the second detection current ID2 flowing through the MOS transistor 71B.

[0107] First memory cell MC1 ij stores data "1", and the second memory cell MC2 ij When the first memory cell MC1 stores data "0," the first detection current ID1 becomes larger than the second detection current ID2. At this time, if the difference between the first detection current ID1 and the second detection current ID2 is larger than the first reference current IR1, the current ID1-IR1 becomes larger than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. On the other hand, if the difference between the first detection current ID1 and the second detection current ID2 is smaller than the first reference current IR1, the current ID1-IR1 becomes smaller than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ. On the other hand, when the first memory cell MC1 stores data "0," the first detection current ID1 becomes larger than the voltage V2 at the second node N2. ij stores data "0", and the second memory cell MC2 ij When the data "1" is stored in the first node N1, the first detection current ID1 is smaller than the second detection current ID2. Therefore, the current ID1-IR1 is smaller than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ.

[0108] 22, the enable signal ENA2 is at a low level, causing the current source 76A to stop operating, preventing the first reference current IR1 from flowing, and instead causing the first detection current ID1 to flow through the MOS transistor 71A. Meanwhile, the enable signal ENB2 is at a high level, causing the current source 76B to operate, causing the second reference current IR2 to flow. Therefore, a current ID2-IR2, which is the second detection current ID2 minus the second reference current IR2, flows through the MOS transistor 71B. The voltage V1 at the first node N1 is determined in accordance with the first detection current ID1 flowing through the MOS transistor 71A, and the voltage V2 at the second node N2 is determined in accordance with the current ID2-IR2 flowing through the MOS transistor 71B.

[0109] First memory cell MC1 ij stores data "1", and the second memory cell MC2 ij When the first memory cell MC1 stores data "0", the first detection current ID1 is larger than the second detection current ID2. Therefore, the first detection current ID1 is larger than the current ID2-IR2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. On the other hand, when the first memory cell MC1 stores data "0", the first detection current ID1 is larger than the second detection current ID2. Therefore, the first detection current ID1 is larger than the current ID2-IR2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. ij stores data "0", and the second memory cell MC2 ij When the first node N1 stores data "1," the first detection current ID1 is smaller than the second detection current ID2. At this time, if the difference between the first detection current ID1 and the second detection current ID2 is larger than the second reference current IR2, the first detection current ID1 is smaller than the current ID2-IR2. As a result, the voltage V1 at the first node N1 is higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ. On the other hand, if the difference between the first detection current ID1 and the second detection current ID2 is smaller than the second reference current IR2, the first detection current ID1 is larger than the current ID2-IR2. As a result, the voltage V1 at the first node N1 is lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ.

[0110] In this way, in the second mode, the read circuit 70 in the fourth embodiment reads the first memory cell MC1 electrically connected to the first node N1. ij a current ID1-IR1 obtained by subtracting a first reference current IR1 from a first detection current ID1 flowing through the second memory cell MC2 electrically connected to the second node N2; ij By comparing the detected current ID2 flowing through the first memory cell MC1 with the detected current ID2 flowing through the first memory cell MC1, ij and the second memory cell MC2 ij Alternatively, in the second mode, the read circuit 70 reads out the complementary data stored in the first memory cell MC1 electrically connected to the first node N1 as the data signal DQ. ij a first detection current ID1 flowing through the second memory cell MC2 electrically connected to the second node N2; ij The second detection current ID2 flowing through the first memory cell MC1 is compared with the current ID2-IR2 obtained by subtracting the second reference current IR2 from the second detection current ID2 flowing through the first memory cell MC1. ij and the second memory cell MC2 ij The complementary data stored in the buffer is read out as a data signal DQ.

[0111] In this second mode, data is read from, for example, the first memory cell MC1 ij and the second memory cell MC2 ij and verifying the complementary data written to the first memory cell MC1 in the initial state. ij and the second memory cell MC2 ij When the data stored in is regarded as complementary data, it can be used to check whether the initial value of the complementary data is "1", "0", or indefinite.

[0112] Specifically, the read circuit 70 first subtracts the first reference current IR1 from the first detection current ID1 to read complementary data, and then subtracts the second reference current IR2 from the second detection current ID2 to read complementary data. If the two read complementary data do not match, this indicates that there is insufficient margin for the threshold for determining whether data is "1" or "0." For example, as shown in FIG. 23, if the difference between the first detection current ID1 and the second detection current ID2 is small, the data read by subtracting the first reference current IR1 from the first detection current ID1 is "0," while the data read by subtracting the second reference current IR2 from the second detection current ID2 is "1," indicating that the two complementary data do not match. For example, if the two complementary data do not match during verification after being written, the complementary data is written again. Furthermore, when checking the initial values of the complementary data, the data is determined to be indefinite.

[0113] On the other hand, if the two read complementary data match, it means that there is a sufficient margin for the decision threshold between data "1" and data "0." For example, as shown in FIG. 24, when the difference between the first detection current ID1 and the second detection current ID2 is large, the data read by subtracting the first reference current IR1 from the first detection current ID1 is "1," while the data read by subtracting the second reference current IR2 from the second detection current ID2 is "1," so the two match. For example, if the two complementary data match in verification after writing the complementary data, there is no need to write them again. Furthermore, when checking the initial value of the complementary data, it is determined to be data "1" or data "0."

[0114] Here, assuming that the first reference current IR1 and the second reference current IR2 are equal, the first memory cell MC1, which is a complementary cell, ij and the second memory cell MC2 ijAssume that data "1" is written to one of the sensed currents ID1 and ID2, and data "0" is written to the other. In this case, if the difference between the first sensed current ID1 and the second sensed current ID2 is larger than the first reference current IR1 (=second reference current IR2), erroneous reading of the complementary data will not occur. Therefore, there is no need to assume an excessive margin for the difference between the first sensed current ID1 and the second sensed current ID2, and the write time can be shortened.

[0115] FIG. 25 is a flowchart illustrating an example of a procedure for reading data in the second mode according to the fourth embodiment. In the example of FIG. 25, first, in step S61, an external device of the nonvolatile memory device 1 sets the register 90 to the second mode. Next, if a data read request is received from the external device in step S62, the read circuit 70 compares a current ID1-IR1, obtained by subtracting a first reference current IR1 from a first detection current ID1, with a second detection current ID2 in step S63 to read complementary data. The external device then acquires read data RDT, including the complementary data, output from the nonvolatile memory device 1. Furthermore, in step S64, the read circuit 70 compares the first detection current ID1 with a current ID2-IR2, obtained by subtracting a second reference current IR2 from a second detection current ID2, to read the complementary data. The external device then acquires read data RDT, including the complementary data, output from the nonvolatile memory device 1. If the two complementary data contained in the two acquired read data RDT match, the external device can determine that the difference between the first detection current ID1 and the second detection current ID2 is sufficient, and if the two complementary data do not match, the external device can determine that the difference between the first detection current ID1 and the second detection current ID2 is insufficient.

[0116] In addition, the read circuit 70 in the fourth embodiment has the same structure as the second embodiment, in which the first memory cell MC1 ij and the second memory cell MC2 ijBased on the complementary data written in the register, it may be determined whether to subtract the first reference current IR1 from the first detection current ID1 or the second reference current IR2 from the second detection current ID2, and the complementary data may be read out in the second mode.

[0117] Further, the read circuit 70 in the fourth embodiment, like the second embodiment, reads the first memory cell MC1 in the first mode. ij and the second memory cell MC2 ij and based on the complementary data read in the first mode, determine whether to subtract the first reference current IR1 from the first detection current ID1 or the second reference current IR2 from the second detection current ID2, and read the complementary data in the second mode.

[0118] Further, the read circuit 70 in the fourth embodiment, like the third embodiment, reads the first memory cell MC1 in the third mode. ij or second memory cell MC2 ij Alternatively, a single piece of data may be read from the read circuit 70. In the third mode, both enable signals ENA2 and ENB2 are at a low level. Also, one of the enable signals ENA and ENB is at a low level and the other is at a high level. That is, in the third mode, both current sources 76A and 76B stop operating, one of current sources 72A and 72B operates, and the other stops operating. However, like the first embodiment, the read circuit 70 in the fourth embodiment does not necessarily have the third mode as an operating mode, and in this case, the current sources 72A and 72B may not be provided.

[0119] Other configurations and functions of the nonvolatile memory device 1 of the fourth embodiment are the same as those of the first, second or third embodiment, and therefore description thereof will be omitted.

[0120] In the nonvolatile memory device 1 according to the fourth embodiment described above, the read circuit 70 compares the current ID1-IR1 obtained by subtracting the first reference current IR1 from the first detection current ID1 with the second detection current ID2 in the second mode, thereby determining the current ID1-IR1 of the first memory cell MC1. ij and the second memory cell MC2 ij The complementary data can be read by reading out the complementary data stored in the first detection current ID1 and comparing it with a current ID2-IR2 obtained by subtracting the second reference current IR2 from the second detection current ID2.

[0121] For example, the external device may ij and the second memory cell MC2 ij In a verify operation after writing complementary data to the first memory cell MC1, it is determined whether the two complementary data read in the second mode match, and the writing of complementary data is repeated until they match, and the writing can be completed when the difference between the first detection current ID1 and the second detection current ID2 becomes larger than the first reference current IR1 and the second reference current IR2. Therefore, according to the nonvolatile memory device 1 of the fourth embodiment, it is not necessary to make the difference between the first detection current ID1 and the second detection current ID2 larger than necessary, and the writing time can be shortened, and stress due to application of a high voltage during writing is reduced, ij and the second memory cell MC2 ij This can reduce the risk of accelerated deterioration of the

[0122] Furthermore, for example, in the initial state of the nonvolatile memory device 1, the external device reads the first memory cell MC1 ij and the second memory cell MC2 ij It is possible to determine whether the initial value of the data stored in is "0", "1", or indefinite.

[0123] Furthermore, in addition to the above-mentioned effects, the nonvolatile memory device 1 of the fourth embodiment can also provide the same effects as the nonvolatile memory device 1 of the first, second or third embodiment.

[0124] 1-5. Variations The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0125] For example, in each of the above embodiments, in the first mode, the read circuit 70 outputs a high-level data signal DQ corresponding to data "1" when the first detection current ID1 is greater than the second detection current ID2, and outputs a low-level data signal DQ corresponding to data "0" when the first detection current ID1 is smaller than the second detection current ID2. However, in the former case, the read circuit 70 may output a low-level data signal DQ corresponding to data "0", and in the latter case, the read circuit 70 may output a high-level data signal DQ corresponding to data "1".

[0126] Furthermore, for example, in the first to third embodiments, the readout circuit 70 can add a reference current to both the first detection current ID1 and the second detection current ID2 in the second mode, and in the fourth embodiment, the readout circuit 70 can subtract a reference current from both the first detection current ID1 and the second detection current ID2 in the second mode. However, the readout circuit 70 may also be capable of adding or subtracting a reference current from only one of the first detection current ID1 and the second detection current ID2. For example, in the second mode, the readout circuit 70 may compare a current ID1+IR1 obtained by adding a first reference current IR1 to the first detection current ID1 with the second detection current ID2 to read complementary data, and may further compare a current ID1-IR1 obtained by subtracting the first reference current IR1 from the first detection current ID1 with the second detection current ID2 to read complementary data. Alternatively, in the second mode, the read circuit 70 may compare the first detection current ID1 with a current ID2+IR2 obtained by adding the second reference current IR2 to the second detection current ID2 to read complementary data, and may further compare the first detection current ID1 with a current ID2-IR2 obtained by subtracting the second reference current IR2 from the second detection current ID2 to read complementary data.

[0127] 2. Integrated circuit devices and electronic equipment FIG. 26 is a functional block diagram showing a configuration example of an electronic device using an integrated circuit device having the nonvolatile memory device 1 of any of the above embodiments.

[0128] The electronic device 100 shown in FIG. 26 includes an integrated circuit device 110, an operation unit 120, a communication unit 130, a display unit 140, and a sound output unit 150.

[0129] The integrated circuit device 110 incorporates a nonvolatile memory device 1, a CPU 111 which is a processor, a ROM 112, and a RAM 113. CPU is an abbreviation for Central Processing Unit. ROM is an abbreviation for Read Only Memory, and RAM is an abbreviation for Random Access Memory. Note that the integrated circuit device 110 and the electronic device 100 may omit or modify some of the components shown in FIG. 26, or other components may be added to the components shown in FIG. 26.

[0130] The CPU 111 performs processes such as reading data from the nonvolatile storage device 1 and various arithmetic and control processes using data supplied from the nonvolatile storage device 1, etc., in accordance with a program stored in the nonvolatile storage device 1 or the ROM 112. That is, the CPU 111 functions as the external device described above. For example, the CPU 111 performs various data processes in response to operation signals supplied from the operation unit 120, controls the communication unit 130 to perform data communication with the outside, generates image signals for displaying various images on the display unit 140, and generates sound signals for outputting various sounds from the sound output unit 150.

[0131] The nonvolatile storage device 1 and the ROM 112 store programs, data, etc. for the CPU 111 to perform various arithmetic processing and control processing. The RAM 113 is used as a working area for the CPU 111, and temporarily stores programs and data read from the nonvolatile storage device 1 or the ROM 112, data input using the operation unit 120, or the results of calculations executed by the CPU 111 according to the programs.

[0132] The operation unit 120 is an input device including, for example, operation keys and button switches, and outputs operation signals to the CPU 111 in response to user operations. The communication unit 130 is composed of, for example, analog and digital circuits, and performs data communication between the CPU 111 and external devices. The display unit 140 includes, for example, a display driver circuit and a liquid crystal display device, and displays various information based on display signals supplied from the CPU 111. The sound output unit 150 includes, for example, a sound generation circuit and a speaker, and outputs voice and various sounds based on sound signals supplied from the CPU 111.

[0133] Examples of such electronic devices 100 include smart cards, calculators, electronic dictionaries, electronic game devices, mobile terminals such as mobile phones, digital still cameras, digital movie cameras, televisions, videophones, security television monitors, head-mounted displays, personal computers, printers, network devices, car navigation devices, measuring devices, medical devices, etc. Among these, examples of medical devices include electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic devices, electronic endoscopes, etc.

[0134] According to this embodiment, an integrated circuit device 110 or an electronic device 100 that maintains high reliability for a longer period of time can be provided by using a nonvolatile memory device 1 that can reduce the risk of accelerated deterioration of memory cells.

[0135] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0136] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0137] The following can be derived from the above-described embodiment and modifications.

[0138] One aspect of the nonvolatile memory device is a memory cell array having a plurality of non-volatile memory cells including a first memory cell and a second memory cell; a read circuit that reads data from the memory cell array via a first node and a second node; The readout circuit includes: In a first mode, a first detection current flowing through the first memory cell electrically connected to the first node is compared with a second detection current flowing through the second memory cell electrically connected to the second node, thereby reading complementary data stored in the first memory cell and the second memory cell; In the second mode, the complementary data is read by comparing the current obtained by adding or subtracting a first reference current to the first detection current with the second detection current, or by comparing the first detection current with the current obtained by adding or subtracting a second reference current to the second detection current.

[0139] In this nonvolatile memory device, the read circuit reads complementary data stored in the first memory cell and the second memory cell in the second mode by comparing the current obtained by adding or subtracting the first reference current to the first detection current with the second detection current, and further reads the complementary data by comparing the first detection current with the current obtained by adding or subtracting the second reference current to the second detection current.

[0140] For example, in a verify operation after writing complementary data to the first memory cell and the second memory cell, the external device determines whether the two complementary data read in the second mode match, repeats writing of the complementary data until they match, and ends writing when the difference between the first detection current and the second detection current becomes larger than the first reference current and the second reference current. Therefore, with this nonvolatile memory device, it is not necessary to make the difference between the first detection current and the second detection current larger than necessary, and it is possible to shorten the write time and reduce stress caused by application of a high voltage during writing, thereby reducing the risk of accelerated deterioration of the first memory cell and the second memory cell.

[0141] Furthermore, for example, in the initial state of the nonvolatile memory device 1, the external device can determine whether the initial value of the data stored in the first memory cell and the second memory cell is "0", "1", or indefinite based on the two complementary data read in the second mode.

[0142] One aspect of the nonvolatile storage device is The read circuit may include a register that can be externally set to operate in either the first mode or the second mode.

[0143] According to this nonvolatile memory device, an external device can arbitrarily select whether to read data in the first mode or the second mode, thereby improving versatility.

[0144] In one embodiment of the nonvolatile storage device, The readout circuit includes: In a third mode, the first detection current may be compared with the second reference current to read data stored in the first memory cell, or the second detection current may be compared with the first reference current to read data stored in the second memory cell.

[0145] According to this nonvolatile memory device, an external device can write independent individual data, rather than complementary data, to the first memory cell and the second memory cell, and read these two individual data in the third mode. That is, according to this nonvolatile memory device, it is possible to select whether to store complementary data or individual data in each memory cell, so that the external device can use the memory cell array for general purposes depending on the application. For example, when storing multiple different types of data in the memory cell array, the utilization efficiency of the memory cell array can be improved by appropriately selecting whether to store complementary data or individual data depending on the characteristics of each data.

[0146] One aspect of the nonvolatile storage device is The read circuit may include a register that can be externally set to operate in any one of the first mode, the second mode, and the third mode.

[0147] According to this nonvolatile memory device, an external device can arbitrarily select whether to read data in the first mode, the second mode, or the third mode, thereby improving versatility.

[0148] In one embodiment of the nonvolatile storage device, The readout circuit includes: reading the complementary data in the first mode; Based on the complementary data read in the first mode, it may be determined whether to add or subtract the first reference current to the first detection current or add or subtract the second reference current to the second detection current, and the complementary data may be read in the second mode.

[0149] According to this nonvolatile memory device, the read circuit sequentially reads complementary data in the first mode and then in the second mode in response to an instruction from an external device, thereby reducing the processing load on the external device compared to when the external device instructs the read of complementary data in the first mode and then instructs the read of complementary data in the second mode.

[0150] In one embodiment of the nonvolatile storage device, The readout circuit includes: Based on the complementary data written to the first memory cell and the second memory cell, it may be determined whether to add or subtract the first reference current to the first detection current or add or subtract the second reference current to the second detection current, and the complementary data may be read in the second mode.

[0151] According to this nonvolatile memory device, the read circuit only needs to read once in the second mode for verifying the complementary data after it has been written, thereby reducing the time required for verifying. Also, according to this nonvolatile memory device, the read circuit reads data for verifying the complementary data after it has been written in response to a write instruction from an external device, thereby reducing the processing load on the external device compared to when the external device instructs writing and then instructs reading data for verifying the data after it has been written.

[0152] One aspect of the integrated circuit device is The nonvolatile memory device includes one aspect of the nonvolatile memory device.

[0153] This integrated circuit device is equipped with a nonvolatile memory device that can reduce the risk of accelerated deterioration of the first memory cell and the second memory cell that store complementary data, thereby enabling high reliability to be maintained for a longer period of time. [Explanation of symbols]

[0154] 1...nonvolatile memory device, 10...memory cell array, 20...power supply circuit, 30...word line boost circuit, 40...word line drive circuit, 50...source line drive circuit, 60...switch circuit, 61A-1 to 61A-n...MOS transistor, 61B-1 to 61B-n...MOS transistor, 62A, 62B...MOS transistor, 70...readout circuit, 71A, 71B...MOS transistor, 72A, 72B...current source, 73A, 73B...MOS transistor, 74A, 74B...MOS transistor, 75...output circuit, 76A, 76B...current source, 80...memory control circuit, 90...register, 100...electronic device, 110...integrated circuit device, 111...CPU, 112...ROM, 113...RAM, 120...operation unit, 130...communication unit, 140...display unit, 150...sound output unit

Claims

1. a memory cell array having a plurality of non-volatile memory cells including a first memory cell and a second memory cell; a read circuit for reading data from the memory cell array via a first node and a second node; The readout circuit includes: In a first mode, a first detection current flowing through the first memory cell electrically connected to the first node is compared with a second detection current flowing through the second memory cell electrically connected to the second node, thereby reading out complementary data stored in the first memory cell and the second memory cell; In the second mode, the complementary data is read by comparing the current obtained by adding or subtracting a first reference current to the first detection current with the second detection current, or by comparing the first detection current with the current obtained by adding or subtracting a second reference current to the second detection current.

2. In claim 1, A nonvolatile memory device comprising a register capable of externally setting whether the read circuit operates in the first mode or the second mode.

3. In claim 1, The readout circuit includes: In a third mode, the nonvolatile memory device reads data stored in the first memory cell by comparing the first detection current with the second reference current, or reads data stored in the second memory cell by comparing the second detection current with the first reference current.

4. In claim 3, A nonvolatile memory device comprising a register capable of externally setting whether the read circuit is to operate in the first mode, the second mode, or the third mode.

5. In claim 1, The readout circuit includes: reading the complementary data in the first mode; A nonvolatile memory device that determines whether to add or subtract the first reference current to the first detection current or add or subtract the second reference current to the second detection current based on the complementary data read in the first mode, and reads the complementary data in the second mode.

6. In claim 1, The readout circuit includes: A nonvolatile memory device that determines whether to add or subtract the first reference current to the first detection current or add or subtract the second reference current to the second detection current based on the complementary data written in the first memory cell and the second memory cell, and reads the complementary data in the second mode.

7. An integrated circuit device comprising the nonvolatile memory device according to claim 1 .

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