Non-volatile storage and integrated circuit device

Abstract

To provide a non-volatile storage that can increase the reliability of data stored in a memory cell.SOLUTION: A non-volatile storage comprises: a memory cell array that has a plurality of non-volatile memory cells including a first memory cell; a read-out circuit that compares a detection current flowing in the first memory cell with a reference current to read out data stored in the first memory cell, and outputs a logic level data signal according to the data; and a counter that counts the number of times the logic level of the data signal makes a transition from a first level to a second level.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to non-volatile memory devices and integrated circuit devices. [Background technology]

[0002] Patent Document 1 describes a nonvolatile memory device in which a first memory cell and a second memory cell provided in a memory cell array have a single mode in which they store separate data and a dual mode in which they store complementary data that are complementary to each other. According to the nonvolatile memory device described in Patent Document 1, the single mode and dual mode can be arbitrarily switched for each memory cell provided in the memory cell array, and therefore it can be used for general purposes depending on the application. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-192329 Summary of the Invention [Problem to be solved by the invention]

[0004] In the nonvolatile memory device described in Patent Document 1, when data is written to a first memory cell and a second memory cell in single mode or dual mode, the data written to the first memory cell or the second memory cell is read in single mode during verification after the data is written. Then, a detection current flowing through the first memory cell or the second memory cell is compared with a reference current to determine whether the written data is read correctly. If the difference between the detection current and the reference current is small, the read data may repeatedly be inverted due to noise, fluctuations in the power supply potential, etc., but the correct data may be read depending on the read timing. In other words, there is a risk that verification will pass even if the difference between the detection current and the reference current is insufficient, and therefore it is desirable to improve the reliability of the data stored in the memory cells. [Means for solving the problem]

[0005] One aspect of the nonvolatile memory device according to the present invention is a memory cell array having a plurality of non-volatile memory cells including a first memory cell; a read circuit that reads data stored in the first memory cell by comparing a detection current flowing through the first memory cell with a reference current, and outputs a data signal of a logic level corresponding to the data; a counter that counts the number of times the logic level of the data signal transitions from a first level to a second level.

[0006] Another aspect of the nonvolatile memory device according to the present invention is a memory cell array having a plurality of non-volatile memory cells including a first memory cell and a second memory cell; a read circuit that compares a first detection current flowing through the first memory cell with a second detection current flowing through the second memory cell to read complementary data stored in the first memory cell and the second memory cell, and outputs a data signal of a logic level corresponding to the complementary data; a counter that counts the number of times the logic level of the data signal transitions from a first level to a second level.

[0007] One aspect of the integrated circuit device according to the present invention is The nonvolatile memory device includes one aspect of the nonvolatile memory device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile memory device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing a detailed configuration example of a memory cell array, a switch circuit, and a read circuit in this embodiment. [Figure 3] FIG. 4 is a diagram showing the state of the readout circuit when set to the first mode in the first embodiment. [Figure 4] FIG. 4 is a diagram showing the state of the readout circuit when set to a second mode in the first embodiment. [Figure 5] FIG. 10 is a diagram showing another state of the readout circuit when the second mode is set in the first embodiment. [Figure 6] FIG. 4 is a timing chart showing an example of waveforms of various signals in a test mode. [Figure 7] FIG. 10 is a timing chart showing another example of waveforms of various signals in the test mode. [Figure 8] FIG. 10 is a flowchart showing an example of a procedure for processing in a read mode and a test mode when the first mode is set. [Figure 9] FIG. 10 is a flowchart showing an example of a procedure for processing the first memory cell in the read mode and test mode when the second mode is set. [Figure 10] FIG. 10 is a flowchart showing an example of a procedure for processing the read mode and test mode for the second memory cell when the second mode is set. [Figure 11] FIG. 11 is a flowchart showing an example of a procedure for data writing and verifying when the first mode is set in the second embodiment. [Figure 12] FIG. 11 is a flowchart showing an example of a procedure for writing data to a first memory cell and verifying the data when the second mode is set in the second embodiment. [Figure 13] FIG. 11 is a flowchart showing an example of a procedure for writing data to a second memory cell and verifying the data when the second mode is set in the second embodiment. [Figure 14] FIG. 1 is a functional block diagram showing an example of the configuration of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. Non-volatile storage devices 1-1. First embodiment Fig. 1 is a block diagram showing a schematic configuration of a nonvolatile memory device 1 of this embodiment. As shown in Fig. 1, the nonvolatile memory device 1 includes a memory cell array 10, a power supply circuit 20, a word line boost circuit 30, a word line drive circuit 40, a source line drive circuit 50, a switch circuit 60, a read circuit 70, a memory control circuit 80, a register 90, a counter 91, a determination circuit 92, and a selector 93. Fig. 2 is a diagram showing a detailed configuration example of the memory cell array 10, the switch circuit 60, and the read circuit 70. The configuration of the nonvolatile memory device 1 will be described below with reference to Figs. 1 and 2.

[0011] The memory control circuit 80 controls the power supply circuit 20, the word line boost circuit 30, the word line drive circuit 40, the source line drive circuit 50, the switch circuit 60 and the read circuit 70 so as to cause the multiple memory cells MC included in the memory cell array 10 to perform erase, write or read operations.

[0012] The memory cell array 10 has a plurality of nonvolatile memory cells MC arranged in a matrix of m rows and 2n columns, where m and n are each integers equal to or greater than 2. For example, if m=2048 and n=1024, the memory cell array 10 may include 2048×2048 memory cells arranged in a matrix of 2048 rows and 2048 columns. Various types of memory cells MC may be considered, such as MONOS type, floating gate type, ferroelectric type, phase-change type, and magnetoresistive type. MONOS is an abbreviation for Metal-Oxide-Nitride-Oxide-Silicon.

[0013] The memory cell array 10 includes m word lines WL1, WL2,...,WLm, m source lines SL1, SL2,...,SLm, n bit lines BLA1, BLA2,...,BLAn, and n bit lines BLB1, BLB2,...,BLBn. Each of the word lines WL1 to WLm is connected to 2n memory cells MC arranged in a respective row. Each of the source lines SL1 to SLm is connected to 2n memory cells MC arranged in a respective row. Each of the bit lines BLA1 to BLAn is connected to n memory cells MC out of the 2n memory cells MC arranged in a respective column. Each of the bit lines BLB1 to BLBn is connected to the remaining n memory cells MC out of the 2n memory cells MC arranged in a respective column.

[0014] In FIG. 2, the memory cell MC connected to the word line WLi and the bit line BLAj is “MC1 ij ", and the memory cell MC connected to the word line WLi and the bit line BLBj is represented as "MC2 ij As shown in FIG. 2, the memory cell array 10 includes m×n memory cells MC1 11 ~MC1 mn and m×n memory cells MC2 11 ~MC21 mn Includes n memory cells MC1 i1 ~MC1 inand n memory cells MC2 i1 ~MC2 in Each gate of the n memory cells MC1 is connected to a word line WLi. i1 ~MC1 in and n memory cells MC2 i1 ~MC2 in Each source of the memory cells MC1 is connected to a source line SLi. i is an integer between 1 and m. 1j ~MC1 mj The drains of the m memory cells MC2 are connected to the bit lines BLAj. 1j ~MC2 mj Each drain of each of the transistors is connected to a bit line BLBj, where j is an integer between 1 and n.

[0015] 1, for example, a reference power supply potential VSS, a high power supply potential VPP for erasing and writing data, and a logic power supply potential VDD for a logic circuit are externally supplied to the power supply circuit 20. Alternatively, the power supply circuit 20 may generate another power supply potential by boosting or lowering one of a plurality of power supply potentials supplied from the outside.

[0016] The reference power supply potential VSS is a reference potential that serves as a reference relative to other potentials, and the following description will be given assuming that the reference power supply potential VSS is the ground potential. The high power supply potential VPP is a predetermined potential higher than the reference power supply potential VSS, for example, about 5V to 10V. The logic power supply potential VDD is a potential higher than the reference power supply potential VSS and lower than the high power supply potential VPP, for example, about 1.2V to 1.8V.

[0017] The power supply circuit 20 supplies a logic power supply potential VDD to the memory control circuit 80, and is controlled by the memory control circuit 80 to supply, as necessary, a high power supply potential VPP and a logic power supply potential VDD to each part of the nonvolatile memory device 1. In Fig. 1, the power supply potential supplied from the power supply circuit 20 to the word line boost circuit 30 is shown as a word line power supply potential VWL, and the power supply potential supplied from the power supply circuit 20 to the source line drive circuit 50 is shown as a source line power supply potential VSL.

[0018] In an erase mode in which data in a memory cell is erased and a write mode in which data is written to a memory cell, the power supply circuit 20 supplies a high power supply potential VPP as a word line power supply potential VWL and a source line power supply potential VSL to the word line boost circuit 30 and the source line drive circuit 50. The word line boost circuit 30 supplies the high power supply potential VPP to the word line drive circuit 40 as a word line power supply potential INT_VWL.

[0019] In a read mode for reading data from a memory cell, the power supply circuit 20 supplies the logic power supply potential VDD as the word line power supply potential VWL and the source line power supply potential VSL to the word line boost circuit 30 and the source line drive circuit 50. The word line boost circuit 30 generates a drive potential higher than the logic power supply potential VDD, which is the high-potential power supply potential supplied to the read circuit 70, and supplies the drive potential to the word line drive circuit 40 as the word line power supply potential INT_VWL.

[0020] The word line driving circuit 40 drives the word line connected to the memory cell MC selected by the memory control circuit 80 from among the m word lines WL1 to WLm. The source line driving circuit 50 drives the source line connected to the memory cell MC selected by the memory control circuit 80 from among the m source lines SL1 to SLm.

[0021] In the read mode, the switch circuit 60 connects the bit line BLAk, which is connected to a memory cell MC selected by the memory control circuit 80 among the n bit lines BLA1 to BLAn, to the bit line BLA, and connects the bit line BLBk, which is connected to a memory cell MC selected by the memory control circuit 80 among the n bit lines BLB1 to BLBn, to the bit line BLB, where k is an integer between 1 and n.

[0022] 2, the switch circuit 60 includes n N-channel MOS transistors 61A-1 to 61A-n, n N-channel MOS transistors 61B-1 to 61B-n, an N-channel MOS transistor 62A, and an N-channel MOS transistor 62B. In FIG. 2, switch control signals SS1 to SSn, SSA, and SSB are signals supplied from the memory control circuit 80.

[0023] A switch control signal SSj is input to each gate of MOS transistors 61A-j, 61B-j, and switch control signals SS1 to SSn are mutually exclusively high level, where j is an arbitrary integer between 1 and n. When the switch control signal SSj is low level, MOS transistors 61A-j, 61B-j are both in an off state where their sources and drains are non-conductive, and when the switch control signal SSj is high level, MOS transistors 61A-j, 61B-j are both in an on state where their sources and drains are conductive.

[0024] A switch control signal SSA is input to the gate of the MOS transistor 62 A. When the switch control signal SSA is at a low level, the MOS transistor 62 A is in an off state where the source and drain are not conductive, and when the switch control signal SSA is at a high level, the MOS transistor 62 A is in an on state where the source and drain are conductive.

[0025] A switch control signal SSB is input to the gate of the MOS transistor 62 B. When the switch control signal SSB is at a low level, the MOS transistor 62 B is in an off state where the source and drain are not conductive, and when the switch control signal SSB is at a high level, the MOS transistor 62 B is in an on state where the source and drain are conductive.

[0026] For example, when the switch control signal SSj and the switch control signal SSA are both at a high level, the MOS transistors 61A-j and 62A are both turned on, and the m memory cells MC1 1j ~MC1 mj At this time, if the word line WLi and the source line SLi are selected, the drains of the memory cells MC1 ij The drain-source of the bit line BLA is electrically connected, and a current flows from the bit line BLA to the source line SLi.

[0027] Similarly, when the switch control signal SSj and the switch control signal SSB are both at a high level, the MOS transistors 61B-j and 62B are both turned on, and the m memory cells MC2 1j ~MC2 mj At this time, if the word line WLi and the source line SLi are selected, the drains of the memory cells MC2 ij The drain-source of the bit line BLB is electrically connected to the source line SLi, and a current flows from the bit line BLB to the source line SLi.

[0028] Hereinafter, the memory cell MC1 electrically connected to the bit line BLA will be described. ij is referred to as the "first memory cell", and memory cell MC1 ij The current flowing through the memory cell MC2 electrically connected to the bit line BLB is referred to as the "first detection current." ij is referred to as the "second memory cell", and memory cell MC2 ij The current flowing through the resistor R1 is referred to as the "second detection current."

[0029] As shown in Fig. 1, in read mode, the read circuit 70 outputs a data signal DQ in response to the voltages of the bit lines BLA and BLB. Specifically, as shown in Fig. 2, the read circuit 70 includes P-channel MOS transistors 71A, 71B, 73A, and 73B, N-channel MOS transistors 74A and 74B, current sources 72A and 72B, and an output circuit 75. In Fig. 2, enable signals ENA and ENB are signals supplied from the memory control circuit 80.

[0030] The MOS transistor 71A has a gate and a drain connected to a first node N1, and a source connected to a VDD node, which is a power supply node to which a logic power supply potential VDD is supplied. The first node N1 is connected to the bit line BLA. The MOS transistor 71B has a gate connected to the gate of the MOS transistor 71A and the first node N1, a drain connected to a second node N2, and a source connected to the VDD node. The second node N2 is connected to the bit line BLB.

[0031] For example, when the switch control signals SSj and SSA are both at a high level and the word line WLi and the source line SLi are selected, the first memory cell MC1 ij is electrically connected to the bit line BLA. At this time, the MOS transistor 71A and the memory cell MC1 ij A current flows to the VSS node, which is a reference node to which the reference power supply potential VSS is supplied, via the memory cell MC1. ij A first detection current ID1 flows through the resistor .

[0032] Also, for example, when the switch control signals SSj and SSB are both at a high level and the word line WLi and the source line SLi are selected, the second memory cell MC2 ij is electrically connected to the bit line BLB. At this time, the MOS transistor 71B and the memory cell MC2 ij A current flows to the VSS node via memory cell MC2. ijA second detection current ID2 flows through the resistor .

[0033] The current source 72A has one end connected to the first node N1 and the other end connected to the VSS node. The current source 72A operates when the enable signal ENA is at a high level, and flows a first reference current IR1 from the first node N1 to the VSS node. The current source 72B has one end connected to the second node N2 and the other end connected to the VSS node. The current source 72B operates when the enable signal ENB is at a high level, and flows a second reference current IR2 from the second node N2 to the VSS node. It is preferable that the first reference current IR1 and the second reference current IR2 are equal. Here, "equal" is a concept that also includes cases where slight differences occur due to manufacturing errors, etc.

[0034] The MOS transistor 73A has a gate connected to the bit line BLA, a source connected to the VDD node, and a drain connected to the third node N3. The MOS transistor 74A has a gate connected to the gate of the MOS transistor 74B and the fourth node N4, a source connected to the VSS node, and a drain connected to the third node N3.

[0035] The MOS transistor 73B has a gate connected to the bit line BLB, a source connected to the VDD node, and a drain connected to the fourth node N4. The MOS transistor 74B has a gate and a drain connected to the gate of the MOS transistor 74A and the fourth node N4, and a source connected to the VSS node.

[0036] The output circuit 75 selects either the third node N3 or the fourth node N4 as the output node and outputs a low-level or high-level data signal DQ. The following description will be given taking the third node N3 as the output node as an example. In this embodiment, when the voltage V1 of the first node N1 connected to the bit line BLA is lower than the voltage V2 of the second node N2 connected to the bit line BLB, the voltage V3 of the third node N3 becomes higher than the voltage V4 of the fourth node N4, and the output circuit 75 outputs a high-level data signal DQ. Also, when the voltage V1 of the first node N1 is higher than the voltage V2 of the second node N2, the voltage V3 of the third node N3 becomes lower than the voltage V4 of the fourth node N4, and the output circuit 75 outputs a low-level data signal DQ. A high-level data signal DQ corresponds to data "1," and a low-level data signal DQ corresponds to data "0." In this manner, the read circuit 70 reads data from the memory cell array 10 via the first node N1 and the second node N2.

[0037] The memory control circuit 80 is configured with, for example, a logic circuit or an analog circuit, and receives a chip selection signal CS, a mode selection signal MS, a clock signal CK, and an address signal ADR from outside the nonvolatile memory device 1. In addition, the memory control circuit 80 receives a read mode selection signal RMS from a register 90.

[0038] When the nonvolatile memory device 1 is selected by the chip selection signal CS, the memory control circuit 80 sets the nonvolatile memory device 1 to an erase mode, a write mode, a read mode or a test mode in accordance with the mode selection signal MS.

[0039] In the erase mode, the memory control circuit 80 synchronizes with the clock signal CK and controls each part of the nonvolatile memory device 1 to erase data in multiple memory cells MC specified by the address signal ADR. For example, erasing the data sets the data in the memory cells MC to "1." If the m×n memory cells MC included in the memory cell array 10 are divided into multiple sectors, in the erase mode the memory control circuit 80 may simultaneously erase the data in all memory cells MC included in the sector specified by the address signal ADR.

[0040] In the write mode, the memory control circuit 80 receives write data WDT from the outside and controls each unit of the nonvolatile memory device 1 so as to write each bit of the write data WDT to a plurality of memory cells MC designated by the address signal ADR. For example, each bit of data in the plurality of memory cells MC to be written is set to "1" in advance by data erasure or the like, and data "0" is written to the necessary memory cells MC.

[0041] In the read mode, the memory control circuit 80 controls each unit of the nonvolatile memory device 1 so as to sequentially read out data from a plurality of memory cells MC designated by the address signal ADR as a data signal DQ. The memory control circuit 80 then reads out the data from the plurality of memory cells MC designated by the address signal ADR and outputs the data to the outside as read data RDT.

[0042] In this embodiment, the read mode and the test mode (to be described later) include a first mode and a second mode. In the first mode, the read circuit 70 compares the first detection current ID1 with the second detection current ID2 to determine whether the first memory cell MC1 ij The first data stored in the second memory cell MC2 ijIn the second mode, the read circuit 70 reads complementary data to the second data stored in the first memory cell MC1 and outputs a data signal DQ having a logic level corresponding to the data. ij or by comparing the second detection current ID2 with the first reference current IR1, ij and outputs a data signal DQ of a logic level corresponding to the data.

[0043] The register 90 outputs a read mode selection signal RMS to the memory control circuit 80. The register 90 is accessible from outside the nonvolatile memory device 1, and the read mode can be set externally to either the first mode or the second mode. In other words, the register 90 is a register that can be externally set to operate the read circuit 70 in either the first mode or the second mode.

[0044] In the first mode, both enable signals ENA and ENB are low. Figure 3 shows the state of the readout circuit 70 when set to the first mode. As shown in Figure 3, in the first mode, the enable signal ENA is low and the current source 72A stops operating, so the first reference current IR1 does not flow. Also, the enable signal ENB is low and the current source 72B stops operating, so the second reference current IR2 does not flow.

[0045] In the example of FIG. 3, the first memory cell MC1 ij is connected, the first memory cell MC1 ij A first detection current ID1 flows through the bit line BLB. ij is connected, the second memory cell MC2 ijA second detection current ID2 flows through the bit line BLA. The voltage V1 at the first node N1 connected to the bit line BLA is determined in accordance with the first detection current ID1, and the voltage V2 at the second node N2 connected to the bit line BLB is determined in accordance with the second detection current ID2.

[0046] First memory cell MC1 ij and the second memory cell MC2 ij is a complementary cell, and the first memory cell MC1 ij and the second memory cell MC2 ij The first memory cell MC1 stores complementary data, one of which is data "1" and the other is data "0." ij stores data "1", and the second memory cell MC2 ij When the first memory cell MC1 stores data "0", the first detection current ID1 is greater than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. ij stores data "0", and the second memory cell MC2 ij When the data "1" is stored in the first node N1, the first detection current ID1 is smaller than the second detection current ID2. As a result, the voltage V1 at the first node N1 becomes higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ.

[0047] In this way, in the first mode, the read circuit 70 reads the first memory cell MC1 electrically connected to the first node N1. ij a first detection current ID1 flowing through the second memory cell MC2 electrically connected to the second node N2; ij By comparing the detected current ID2 flowing through the first memory cell MC1 with the detected current ID2 flowing through the first memory cell MC1, ij and the second memory cell MC2 ij The complementary data stored in the buffer is read out as a data signal DQ.

[0048] In the second mode, the switch control signal SSA and the enable signal ENB are at a high level, and the switch control signal SSB and the enable signal ENA are at a low level, so that the first memory cell MC1 ij Alternatively, the switch control signal SSB and the enable signal ENA are set to a high level, and the switch control signal SSA and the enable signal ENB are set to a low level, so that the data stored in the second memory cell MC2 is read out. ij In the second mode, the data stored in the first memory cell MC1 is read out. ij When the data stored in the second memory cell MC2 is read, the third node N3 is selected as the output node by the output circuit 75, and the second memory cell MC2 ij When data stored in is read out, the fourth node N4 is selected as the output node by the output circuit 75. Figures 4 and 5 show the state of the read circuit 70 when set in the second mode.

[0049] In the example of FIG. 4, the first memory cell MC1 ij The first detection current ID1 flows through the second memory cell MC2 ij The second detection current ID2 does not flow through the MOS transistor 71A. Furthermore, because the enable signal ENA is at a low level and the current source 72A is stopped from operating, the first reference current IR1 does not flow, and the first detection current ID1 flows through the MOS transistor 71A. On the other hand, because the enable signal ENB is at a high level and the current source 72B is operating, the second reference current IR2 flows through the MOS transistor 71B. The voltage V1 at the first node N1 is determined according to the first detection current ID1 flowing through the MOS transistor 71A, and the voltage V2 at the second node N2 is determined according to the second reference current IR2 flowing through the MOS transistor 71B.

[0050] First memory cell MC1 ijWhen the first memory cell MC1 stores data "1", the first detection current ID1 becomes larger than the second reference current IR2. As a result, the voltage V1 at the first node N1 becomes lower than the voltage V2 at the second node N2, and the output circuit 75 outputs a high-level data signal DQ. ij stores data "0," the first detection current ID1 is smaller than the second reference current IR2. As a result, the voltage V1 at the first node N1 becomes higher than the voltage V2 at the second node N2, and the output circuit 75 outputs a low-level data signal DQ.

[0051] In the example of FIG. 5, the second memory cell MC2 ij A second detection current ID2 flows through the first memory cell MC1 ij The first detection current ID1 does not flow through the MOS transistor 71B. Furthermore, because the enable signal ENB is at a low level and the current source 72B is stopped from operating, the second reference current IR2 does not flow, and the second detection current ID2 flows through the MOS transistor 71B. On the other hand, because the enable signal ENA is at a high level and the current source 72A is operating, the first reference current IR1 flows through the MOS transistor 71A. The voltage V2 at the second node N2 is determined according to the second detection current ID2 flowing through the MOS transistor 71B, and the voltage V1 at the first node N1 is determined according to the first reference current IR1 flowing through the MOS transistor 71A.

[0052] Second memory cell MC2 ij When the second memory cell MC2 stores data "1", the second detection current ID2 becomes larger than the first reference current IR1. As a result, the voltage V2 at the second node N2 becomes lower than the voltage V1 at the first node N1, and the output circuit 75 outputs a high-level data signal DQ. ij stores data "0," the second detection current ID2 is smaller than the first reference current IR1. As a result, the voltage V2 at the second node N2 becomes higher than the voltage V1 at the first node N1, and the output circuit 75 outputs a low-level data signal DQ.

[0053] In this embodiment, the first memory cell MC1 ij and the second memory cell MC2 ij The first memory cell MC1 may store complementary data in pairs, or may store data individually. ij and the second memory cell MC2 ij The complementary data stored in the first memory cell MC1 is read in the first mode, and in the latter case, ij and the second memory cell MC2 ij The data stored individually in each of the memory cells is read out in the second mode.

[0054] The memory cells MC included in the memory cell array 10 may be divided into multiple groups, and the register 90 may be set to select whether data is read in the first mode or the second mode for each group. For example, the memory cells MC included in the first group may store complementary data in pairs, and each memory cell MC included in the second group may store data individually. In this case, the read circuit 70 may read complementary data from each pair of memory cells MC in the first group in the first mode, and read data from each memory cell MC in the second group in the second mode. The memory cells MC included in the memory cell array 10 may be divided into groups for each sector.

[0055] First memory cell MC1 ij and the second memory cell MC2 ij When complementary data is stored in the first memory cell MC1, in the first mode of data reading, ij The first detection current ID1 flowing through the second memory cell MC2 ij If the difference between the voltage V1 at the first node N1 and the voltage V2 at the second node N2 is not sufficient, the difference between the voltage V1 at the first node N1 and the voltage V2 at the second node N2 will be small. ij When data is stored in the first memory cell MC1 alone, when data is read in the second mode, ijIf the difference between the first detection current ID1 and the second reference current IR2 flowing through the second memory cell MC2 is not sufficient, the difference between the voltage V1 at the first node N1 and the voltage V2 at the second node N2 will be small. ij When data is stored in the second memory cell MC2 alone, when reading data in the second mode, ij If the difference between the second detection current ID2 flowing through the first node N1 and the first reference current IR1 is not sufficient, the difference between the voltage V1 at the first node N1 and the voltage V2 at the second node N2 will be small. If the difference between the voltage V1 at the first node N1 and the voltage V2 at the second node N2 is not sufficient, the data signal DQ output from the read circuit 70 will transition between low and high levels multiple times due to the effects of noise, fluctuations in the power supply potential, etc., and the read data RDT will differ depending on the timing at which the memory control circuit 80 captures the data signal DQ.

[0056] Therefore, in this embodiment, the mode selection signal MS can be used to set a test mode for determining whether the difference between the voltage V1 at the first node N1 and the voltage V2 at the second node N2 is sufficient based on the number of transitions in the logic level of the data signal DQ during data read. The memory control circuit 80 outputs a high-level test signal TST in the test mode and a low-level test signal TST in modes other than the test mode.

[0057] The counter 91 counts the number of times the logic level of the data signal DQ output from the read circuit 70 transitions from a first level to a second level. For example, the first level may be a low level and the second level may be a high level. Alternatively, the first level may be a high level and the second level may be a low level. The counter 91 operates when the test mode is set, i.e., when the test signal TST is at a high level, and stops operating when the test mode is not set, i.e., when the test signal TST is at a low level.

[0058] The determination circuit 92 determines whether the count value CNT of the counter 91 is equal to or greater than a threshold value TH, and outputs a determination signal CQ of a logic level corresponding to the determination result. For example, the determination circuit 92 outputs a high-level determination signal CQ when the count value CNT is equal to or greater than the threshold value TH, and outputs a low-level determination signal CQ when the count value CNT is less than the threshold value TH. The threshold value TH may be set to an appropriate value, for example, by evaluating the actual nonvolatile memory device 1, taking into account the occurrence of noise, fluctuations in power supply potential, etc.

[0059] When the test mode is set, i.e., when the test signal TST is at a high level, the selector 93 selects the decision signal CQ output from the decision circuit 92 and outputs it as the data signal DQX, and when the test mode is not set, i.e., when the test signal TST is at a low level, the selector 93 selects the data signal DQ output from the read circuit 70 and outputs it as the data signal DQX.

[0060] In the test mode, the memory control circuit 80 controls each component of the nonvolatile memory device 1 so that data from multiple memory cells MC designated by the address signal ADR is read out in sequence as a data signal DQ. Furthermore, the memory control circuit 80 controls the counter 91 and the selector 93 so that a determination signal CQ corresponding to the data from each memory cell MC read out in sequence is output as a data signal DQX. The memory control circuit 80 then generates read data RDT including the logical value of the determination signal CQ corresponding to the data from the multiple memory cells MC designated by the address signal ADR, and outputs the data to the outside.

[0061] This test mode is, for example, ij and the second memory cell MC2 ij and verifying the complementary data written to the first memory cell MC1 in the initial state. ij and the second memory cell MC2 ijWhen the data stored in the first memory cell MC1 is regarded as complementary data, this test mode can be used to check whether the initial value of the complementary data is "1", "0", or indefinite. ij or second memory cell MC2 ij Verifying data written to the first memory cell MC1 alone, and initializing the ij or second memory cell MC2 ij This can be used to check whether the initial value of the data stored in is "1", "0", or indefinite.

[0062] In the read mode, the memory control circuit 80 controls the selector 93 so that the data read from each memory cell MC in turn is output as a data signal DQX. The memory control circuit 80 then generates read data RDT including the logical values of the data signal DQ for the data in the memory cells MC specified by the address signal ADR, and outputs the read data RDT to the outside.

[0063] 6 and 7 are timing charts showing examples of waveforms of various signals in the test mode, in which the test mode is set to the first mode.

[0064] In the examples of FIGS. 6 and 7, at time t1, the word line WLi and the bit lines BLAj and BLBj are selected, and the first memory cell MC1 ij A first detection current ID1 flows through the second memory cell MC2 ij A second detection current ID2 flows through the first memory cell MC1. ij The data "1" is stored in the second memory cell MC2 ij6 and 7, the threshold value TH is set to 3. In the example shown in FIG. 6, the threshold value TH is set to 3. The data signal DQ is initialized to 0 in advance, and the count value CNT is held at 0 at the timing when the data signal DQ first transitions from low to high. In the examples shown in FIG. 6 and FIG. 7, the threshold value TH is set to 3. In the example shown in FIG. 6, the threshold value TH is set to 3. In the example shown in FIG. 6, the threshold value TH is set to 3. In the example shown in FIG. 6, the threshold value TH is set to 3. In the example shown in FIG. 6, the threshold value TH is set to 3. In the example shown in FIG. 7 ...

[0065] 6, the difference between the first detection current ID1 and the second detection current ID2 is sufficiently large, and the voltage V1 at the first node N1 is always maintained smaller than the voltage V2 at the second node N2. Therefore, the voltage V3 at the third node N3 is maintained larger than the voltage V4 at the fourth node N4, and the data signal DQ is maintained at a high level, so the count value CNT remains unchanged at 0. Furthermore, because the count value CNT is less than the threshold value TH, the determination signal CQ is maintained at a low level, and the data signal DQX is also maintained at a low level.

[0066] 7, there is almost no difference between the first detection current ID1 and the second detection current ID2, and the magnitude relationship between the voltage V1 at the first node N1 and the voltage V2 at the second node N2 repeatedly changes due to noise, fluctuations in the power supply potential, and the like. As a result, the magnitude relationship between the voltage V3 at the third node N3 and the voltage V4 at the fourth node N4 also repeatedly changes, causing the data signal DQ to repeatedly transition between low and high levels. After the data signal DQ first transitions from low to high, the count value CNT increases by one each time it transitions from low to high. Then, at time t5, the data signal DQ transitions from low to high, and at time t6, the count value CNT becomes 3. As a result, the count value CNT becomes equal to or greater than the threshold value TH, the determination signal CQ transitions from low to high, and the data signal DQX also transitions from low to high.

[0067] Although Figures 6 and 7 show an example in which the test mode is set to the first mode, even when the test mode is set to the second mode, the waveforms of various signals will be similar to those in Figure 6 or 7 depending on the difference between the first detection current ID1 and the second reference current IR2, or the difference between the second detection current ID2 and the first reference current IR1.

[0068] FIG. 8 is a flowchart illustrating an example of the processing procedure for the read mode and test mode when the first mode is set. In the example of FIG. 8, first, in step S1, an external device of the nonvolatile memory device 1 sets the first mode in the register 90. Next, if the external device requests data reading in the read mode or test mode in step S2, the read circuit 70 compares the first detection current ID1 with the second detection current ID2 to read complementary data and generate a data signal DQ in step S3. Next, if the request is for data reading in the test mode in step S4, the counter 91 counts the number of low-to-high transitions of the data signal DQ in step S5. In step S6, the decision circuit 92 compares the count value CNT with a threshold value TH to generate a decision signal CQ. Furthermore, in step S7, the selector 93 selects the decision signal CQ as the data signal DQX, thereby terminating the test mode processing. On the other hand, if the request in step S4 is for reading data in read mode, the selector 93 selects the data signal DQ as the data signal DQX in step S8, and the read mode processing ends. Then, the external device obtains read data RDT including the logical value of the data signal DQX output from the nonvolatile memory device 1. Based on the read data RDT in test mode, the external device can determine whether the difference between the first detection current ID1 and the second detection current ID2 is sufficient.

[0069] 9 and 10 are flow charts showing an example of the procedure of the read mode and test mode processes when the second mode is set.

[0070] FIG. 9 shows the first memory cell MC1 ij9 is a diagram showing a procedure for a process of reading data stored in the register 90. In the example of FIG. 9, first, in step S11, an external device of the nonvolatile memory device 1 sets the second mode in the register 90. Next, if the external device requests data reading in the read mode or test mode in step S12, the read circuit 70 compares the first detection current ID1 with the second reference current IR2 to read the data and generate a data signal DQ in step S13. Next, if the request is for data reading in the test mode in step S14, the counter 91, the determination circuit 92, and the selector 93 perform the same processes as in steps S5, S6, and S7 of FIG. 8, respectively, to terminate the test mode process. On the other hand, if the request is for data reading in the read mode in step S14, the selector 93 performs the same process as in step S8 of FIG. 8 to terminate the read mode process in step S18. Then, the external device acquires read data RDT, which includes the logical value of the data signal DQX, output from the nonvolatile memory device 1. The external device can determine whether the difference between the first detection current ID1 and the second reference current IR2 is sufficient based on the read data RDT in the test mode.

[0071] FIG. 10 shows the second memory cell MC2 ij10 shows a procedure for reading data stored in the register 90. In the example of FIG. 10, first, in step S21, an external device of the nonvolatile memory device 1 sets the second mode in the register 90. Next, if the external device requests data reading in the read mode or test mode in step S22, the read circuit 70 compares the second detection current ID2 with the first reference current IR1 to read the data and generate a data signal DQ in step S23. Next, if the request is for data reading in the test mode in step S24, the counter 91, the determination circuit 92, and the selector 93 perform the same processes as steps S5, S6, and S7 of FIG. 8, respectively, in steps S25, S26, and S27, thereby ending the test mode process. On the other hand, if the request is for data reading in the read mode in step S24, the selector 93 performs the same process as step S8 of FIG. 8 in step S28, thereby ending the read mode process. Then, the external device acquires read data RDT, which includes the logical value of the data signal DQX, output from the nonvolatile memory device 1. The external device can determine whether the difference between the second detection current ID2 and the first reference current IR1 is sufficient based on the read data RDT in the test mode.

[0072] In the nonvolatile memory device 1 according to the first embodiment described above, when the test mode is set, the read circuit 70 compares the first detection current ID1 and the second detection current ID2 in the first mode to determine whether the first memory cell MC1 ij and the second memory cell MC2 ijand outputs a data signal DQ, and a counter 91 counts the number of times the logic level of the data signal DQ transitions from the first level to the second level. When the difference between the first detection current ID1 and the second detection current ID2 is small, the read data repeatedly switches between "0" and "1" due to noise, fluctuations in the power supply potential, etc., and the logic level of the data signal DQ repeatedly switches, so that the count value CNT of the counter 91 increases. In the second mode, the read circuit 70 compares the first detection current ID1 with the second reference current IR2, or the second detection current ID2 with the first reference current IR1, thereby detecting the first memory cell MC1. ij or second memory cell MC2 ij and outputs a data signal DQ, and a counter 91 counts the number of times the logic level of the data signal DQ transitions from the first level to the second level. If the difference between the first detection current ID1 and the second reference current IR2, or the difference between the second detection current ID2 and the first reference current IR1, is small, the read data repeatedly switches between "0" and "1" due to noise, fluctuations in the power supply potential, etc., and the logic level of the data signal DQ repeatedly switches, so that the count value CNT of the counter 91 increases.

[0073] For example, the external device may ij and the second memory cell MC2 ij In the verify operation after writing the complementary data to the first memory cell MC1, it is determined whether or not the difference between the first detection current ID1 and the second detection current ID2 is sufficient based on the count value CNT, and the first memory cell MC1 is continuously supplied with the first detection current ID1 until the difference becomes sufficiently large. ij and the second memory cell MC2 ij Alternatively, the external device can repeatedly write the complementary data to the first memory cell MC1. ij or second memory cell MC2 ijIn a verify operation after writing data to the first memory cell MC1, it is determined whether or not the difference between the first detection current ID1 and the second reference current IR2, or the difference between the second detection current ID2 and the first reference current IR1, is sufficient based on the count value CNT, and the first memory cell MC1 is continuously supplied with the first detection current ID1 until the difference becomes sufficiently large. ij or second memory cell MC2 ij Therefore, according to the nonvolatile memory device 1 of the first embodiment, the first memory cell MC1 ij or second memory cell MC2 ij This can improve the reliability of the complementary data stored in the memory.

[0074] Also, for example, the external device may ij and the second memory cell MC2 ij In a verify operation after writing complementary data to the first memory cell MC1, it is determined whether the two complementary data read in the first mode match, and the writing of complementary data is repeated until they match, and the writing can be completed when the difference between the first detection current ID1 and the second detection current ID2 becomes larger than the first reference current IR1 and the second reference current IR2. Therefore, according to the nonvolatile memory device 1 of the first embodiment, it is not necessary to make the difference between the first detection current ID1 and the second detection current ID2 larger than necessary, and the writing time can be shortened, and stress due to application of a high voltage during writing is reduced, ij and the second memory cell MC2 ij This can reduce the risk of accelerated deterioration of the

[0075] Further, for example, in the initial state of the nonvolatile memory device 1, the external device reads the first memory cell MC1 ij and the second memory cell MC2 ij Similarly, in the initial state of the nonvolatile memory device 1, the external device can determine whether the initial value of the data stored in the first memory cell MC1 is "0", "1", or indefinite based on the data read in the second mode.ij or second memory cell MC2 ij It is possible to determine whether the initial value of the data stored in is "0", "1", or indefinite.

[0076] Furthermore, according to the nonvolatile memory device 1 of the first embodiment, the determination circuit 92 can determine whether the difference between the first detection current ID1 and the second reference current IR2, or the difference between the second detection current ID2 and the first reference current IR1, based on the count value CNT, or whether the difference between the first detection current ID1 and the second detection current ID2 is sufficient, thereby reducing the processing load of an external device. Furthermore, since the selector 93 selects and outputs either the data signal DQ or the determination signal CQ, the memory control circuit 80 can easily read out the data signal DQ and the determination signal CQ using a common signal line.

[0077] Furthermore, according to the nonvolatile memory device 1 of the first embodiment, the external device ij and the second memory cell MC2 ij and the complementary data can be written to the first memory cell MC1 and read out in the second mode. ij and the second memory cell MC2 ij It is also possible to write independent individual data, rather than complementary data, into each memory cell MC, and read out the two individual data in the second mode. That is, according to the nonvolatile memory device 1 of the first embodiment, it is possible to select whether to store complementary data or individual data in each memory cell MC, so that an external device can use the memory cell array 10 for general purposes depending on the application. For example, when storing multiple different types of data in the memory cell array 10, the utilization efficiency of the memory cell array 10 can be improved by appropriately selecting whether to store complementary data or individual data depending on the characteristics of each data.

[0078] Furthermore, according to the nonvolatile memory device 1 of the first embodiment, an external device can arbitrarily select whether to read complementary data in the first mode or the second mode, thereby improving versatility.

[0079] 1-2. Second embodiment Hereinafter, for the nonvolatile memory device 1 of the second embodiment, the same symbols will be used for configurations similar to those of the first embodiment, and explanations similar to those of the first embodiment will be omitted or simplified, with the main focus being on the differences from the first embodiment.

[0080] A block diagram showing the schematic configuration of the nonvolatile memory device 1 of the second embodiment is the same as Fig. 1, and therefore its illustration and description will be omitted. In addition, the detailed configurations of the memory cell array 10, switch circuit 60, and read circuit 70 in the second embodiment are the same as Fig. 2, and therefore their illustration and description will be omitted.

[0081] In the second embodiment, when a data write request is received from an external device, data is automatically read in a test mode in the verification after the data write. ij and the second memory cell MC2 ij When the complementary data is written to the first memory cell MC1, the nonvolatile memory device 1 is automatically set to the test mode, and the read circuit 70 ij and the second memory cell MC2 ij The counter 91 counts the number of times the logic level of the data signal DQ transitions from the first level to the second level, the decision circuit 92 determines whether the count value CNT of the counter 91 is equal to or greater than the threshold value TH and outputs a decision signal CQ, and the selector 93 selects the decision signal CQ and outputs the data signal DQX. When the decision signal CQ is at a high level, the first memory cell MC1 ij and the second memory cell MC2 ij The data is written to again.

[0082] Also, the first memory cell MC1 ij When data is written to the first memory cell MC1 alone, the nonvolatile memory device 1 is automatically set to a test mode, and the read circuit 70 reads the first memory cell MC1 ij The counter 91 counts the number of times the logic level of the data signal DQ transitions from the first level to the second level, the decision circuit 92 determines whether the count value CNT of the counter 91 is equal to or greater than the threshold value TH and outputs a decision signal CQ, and the selector 93 selects the decision signal CQ and outputs the data signal DQX. When the decision signal CQ is at a high level, the first memory cell MC1 ij The data is written to again.

[0083] Similarly, the second memory cell MC2 ij When data is written to the second memory cell MC2 alone, the nonvolatile memory device 1 is automatically set to a test mode, and the read circuit 70 reads the second memory cell MC2 ij The second memory cell MC2 reads out the data stored therein and outputs a data signal DQ having a logic level corresponding to the data. Then, a counter 91 counts the number of times the logic level of the data signal DQ transitions from the first level to the second level. A decision circuit 92 determines whether the count value CNT of the counter 91 is equal to or greater than a threshold value TH and outputs a decision signal CQ. A selector 93 selects the decision signal CQ and outputs a data signal DQX. When the decision signal CQ is at a high level, the second memory cell MC2 ij The data is written to again.

[0084] 11 is a flowchart showing an example of the procedure for data write and verify processing when the first mode is set. In the example of FIG. 11, first, in step S41, an external device of the nonvolatile memory device 1 sets the first mode in the register 90. Next, in step S42, if there is a request for data write from the external device, in step S43, the first memory cell MC1 ij and the second memory cell MC2 ijThe complementary data is written to the nonvolatile memory device 1. Next, in step S44, the nonvolatile memory device 1 is automatically set to test mode. In step S45, the read circuit 70 compares the first detection current ID1 and the second detection current ID2 to read the complementary data and generate a data signal DQ. Next, in step S46, the counter 91 counts the number of low-to-high transitions of the data signal DQ. In step S47, the decision circuit 92 compares the count value CNT with a threshold value TH to generate a decision signal CQ. Furthermore, in step S48, the selector 93 selects the decision signal CQ as the data signal DQX, thereby ending the test mode process. Then, the external device obtains read data RDT, which includes the logical value of the data signal DQX, output from the nonvolatile memory device 1. Based on the read data RDT, the external device determines whether the difference between the first detection current ID1 and the second detection current ID2 is sufficient. If the external device determines that the difference is insufficient, it can write data again.

[0085] 12 and 13 are flow charts showing an example of the procedure of data writing and verifying processes when the second mode is set.

[0086] FIG. 12 shows the first memory cell MC1 ij 12 is a diagram showing a procedure for writing and verifying data to the first memory cell MC1. In the example of FIG. 12, first, in step S51, an external device of the nonvolatile memory device 1 sets the register 90 to the second mode. Next, in step S52, if there is a request for writing data from the external device, in step S53, ij11 , and data is written to the nonvolatile memory device 1. Next, in step S54, the nonvolatile memory device 1 is automatically set to test mode. In step S55, the read circuit 70 compares the first detection current ID1 with the second reference current IR2 to read data and generate a data signal DQ. Next, in steps S56, S57, and S58, the counter 91, the determination circuit 92, and the selector 93 perform the same processes as steps S46, S47, and S48 of FIG. 11 , respectively, to terminate the test mode process. Then, the external device obtains read data RDT output from the nonvolatile memory device 1, which includes the logical value of the data signal DQX. Based on the read data RDT, the external device determines whether the difference between the first detection current ID1 and the second reference current IR2 is sufficient. If the external device determines that the difference is insufficient, it can write data again.

[0087] FIG. 13 shows the second memory cell MC2 ij 13 is a diagram showing a procedure for writing and verifying data to the second memory cell MC2. In the example of FIG. 13, first, in step S61, an external device of the nonvolatile memory device 1 sets the second mode in the register 90. Next, in step S62, if there is a request for writing data from the external device, in step S63, ij 11 , and data is written to the nonvolatile memory device 1. Next, in step S64, the nonvolatile memory device 1 is automatically set to test mode. In step S65, the read circuit 70 compares the second detection current ID2 with the first reference current IR1 to read the data and generate a data signal DQ. Next, in steps S56, S57, and S58, the counter 91, the determination circuit 92, and the selector 93 perform the same processes as steps S46, S47, and S48 of FIG. 11 , respectively, to terminate the test mode process. Then, the external device obtains read data RDT output from the nonvolatile memory device 1, which includes the logical value of the data signal DQX. Based on the read data RDT, the external device determines whether the difference between the second detection current ID2 and the first reference current IR1 is sufficient. If the external device determines that the difference is insufficient, it can write data again.

[0088] Other configurations and functions of the nonvolatile memory device 1 of the second embodiment are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0089] According to the nonvolatile memory device 1 of the second embodiment described above, the same effects as those of the nonvolatile memory device 1 of the first embodiment can be obtained.

[0090] Furthermore, according to the nonvolatile memory device 1 of the second embodiment, the read circuit 70 automatically reads data for verifying after writing in response to a write instruction from an external device, thereby reducing the processing load on the external device compared to when the external device instructs writing and then instructs reading data for verifying after writing.

[0091] 1-3. Variations The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0092] For example, in each of the above embodiments, in the first mode, the read circuit 70 outputs a high-level data signal DQ corresponding to data "1" when the first detection current ID1 is greater than the second detection current ID2, and outputs a low-level data signal DQ corresponding to data "0" when the first detection current ID1 is smaller than the second detection current ID2. However, in the former case, the read circuit 70 may output a low-level data signal DQ corresponding to data "0", and in the latter case, the read circuit 70 may output a high-level data signal DQ corresponding to data "1".

[0093] Also, for example, in each of the above embodiments, the read mode and the test mode have a first mode and a second mode, but it is also possible to have one of the first mode and the second mode and not the other.

[0094] Also, for example, in each of the above embodiments, the nonvolatile memory device 1 includes the determination circuit 92, but may not include the determination circuit 92. In this case, the nonvolatile memory device 1 outputs the count value CNT in the test mode, and an external device determines whether the count value CNT is equal to or greater than the threshold value TH.

[0095] 2. Integrated circuit devices and electronic equipment FIG. 14 is a functional block diagram showing an example of the configuration of an electronic device using an integrated circuit device having the nonvolatile memory device 1 of any of the above embodiments.

[0096] The electronic device 100 shown in FIG. 14 includes an integrated circuit device 110, an operation unit 120, a communication unit 130, a display unit 140, and a sound output unit 150.

[0097] The integrated circuit device 110 incorporates a nonvolatile memory device 1, a CPU 111 which is a processor, a ROM 112, and a RAM 113. CPU is an abbreviation for Central Processing Unit. ROM is an abbreviation for Read Only Memory, and RAM is an abbreviation for Random Access Memory. Note that the integrated circuit device 110 and the electronic device 100 may omit or modify some of the components shown in FIG. 14, or other components may be added to the components shown in FIG. 14.

[0098] The CPU 111 performs processes such as reading data from the nonvolatile storage device 1 and various arithmetic and control processes using data supplied from the nonvolatile storage device 1, etc., in accordance with a program stored in the nonvolatile storage device 1 or the ROM 112. That is, the CPU 111 functions as the external device described above. For example, the CPU 111 performs various data processes in response to operation signals supplied from the operation unit 120, controls the communication unit 130 to perform data communication with the outside, generates image signals for displaying various images on the display unit 140, and generates sound signals for outputting various sounds from the sound output unit 150.

[0099] The nonvolatile storage device 1 and the ROM 112 store programs, data, etc. for the CPU 111 to perform various arithmetic processing and control processing. The RAM 113 is used as a working area for the CPU 111, and temporarily stores programs and data read from the nonvolatile storage device 1 or the ROM 112, data input using the operation unit 120, or the results of calculations executed by the CPU 111 according to the programs.

[0100] The operation unit 120 is an input device including, for example, operation keys and button switches, and outputs operation signals to the CPU 111 in response to user operations. The communication unit 130 is composed of, for example, analog and digital circuits, and performs data communication between the CPU 111 and external devices. The display unit 140 includes, for example, a display driver circuit and a liquid crystal display device, and displays various information based on display signals supplied from the CPU 111. The sound output unit 150 includes, for example, a sound generation circuit and a speaker, and outputs voice and various sounds based on sound signals supplied from the CPU 111.

[0101] Examples of such electronic devices 100 include smart cards, calculators, electronic dictionaries, electronic game devices, mobile terminals such as mobile phones, digital still cameras, digital movie cameras, televisions, videophones, security television monitors, head-mounted displays, personal computers, printers, network devices, car navigation devices, measuring devices, medical devices, etc. Among these, examples of medical devices include electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic devices, electronic endoscopes, etc.

[0102] According to this embodiment, it is possible to provide an integrated circuit device 110 or an electronic device 100 that maintains high reliability by using a nonvolatile memory device 1 that can improve the reliability of data stored in memory cells.

[0103] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0104] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0105] The following can be derived from the above-described embodiment and modifications.

[0106] One aspect of the nonvolatile memory device is a memory cell array having a plurality of non-volatile memory cells including a first memory cell; a read circuit that reads data stored in the first memory cell by comparing a detection current flowing through the first memory cell with a reference current, and outputs a data signal of a logic level corresponding to the data; a counter that counts the number of times the logic level of the data signal transitions from a first level to a second level.

[0107] In this nonvolatile memory device, a read circuit compares the detection current with a reference current to read out the data stored in the first memory cell and output a data signal, and a counter counts the number of times the logic level of the data signal transitions from a first level to a second level. When the difference between the detection current and the reference current is small, noise, fluctuations in the power supply potential, etc. cause the read data to repeatedly flip between "0" and "1," and the logic level of the data signal repeatedly flips, causing the count value of the counter to increase.

[0108] For example, in a verify operation after writing data to the first memory cell, the external device can determine whether the difference between the detected current and the reference current is sufficient based on the count value of the counter, and repeat writing data to the first memory cell until the difference becomes sufficiently large. Therefore, this nonvolatile memory device can improve the reliability of the data stored in the first memory cell.

[0109] Furthermore, for example, in the initial state of the nonvolatile memory device 1, the external device can determine whether the initial value of the data stored in the first memory cell is "0", "1", or indefinite based on the logic level of the data signal and the count value of the counter.

[0110] Another aspect of the nonvolatile memory device is a memory cell array having a plurality of non-volatile memory cells including a first memory cell and a second memory cell; a read circuit that compares a first detection current flowing through the first memory cell with a second detection current flowing through the second memory cell to read complementary data stored in the first memory cell and the second memory cell, and outputs a data signal of a logic level corresponding to the complementary data; a counter that counts the number of times the logic level of the data signal transitions from a first level to a second level.

[0111] In this nonvolatile memory device, a read circuit compares the first detection current with the second detection current to read complementary data stored in the first memory cell and the second memory cell, outputting a data signal, and a counter counts the number of times the logic level of the data signal transitions from the first level to the second level. When the difference between the first detection current and the second detection current is small, the read data repeatedly flips between "0" and "1" due to noise, fluctuations in power supply potential, etc., and the logic level of the data signal repeatedly flips, causing the count value of the counter to increase.

[0112] For example, in a verify operation after writing the complementary data to the first memory cell and the second memory cell, the external device can determine whether the difference between the first detected current and the second detected current is sufficient based on the count value of the counter, and repeat writing the complementary data to the first memory cell and the second memory cell until the difference becomes sufficiently large. Therefore, this nonvolatile memory device can improve the reliability of the complementary data stored in the first memory cell and the second memory cell.

[0113] Furthermore, according to this nonvolatile memory device, since the first detection current and the second detection current are compared rather than compared with a reference current, there is no need to make the difference between the first detection current and the second detection current larger than necessary, and the write time can be shortened. Therefore, stress caused by application of a high voltage during writing can be reduced, and the risk of accelerated deterioration of the first memory cell and the second memory cell can be reduced.

[0114] Furthermore, for example, in the initial state of the nonvolatile memory device 1, the external device can determine whether the initial value of the data stored in the first memory cell and the second memory cell is "0", "1", or indefinite based on the logic level of the data signal and the count value of the counter.

[0115] In one aspect of the nonvolatile storage device, When data is written to the first memory cell, the read circuit reads data stored in the first memory cell and outputs the data signal at a logic level corresponding to the data; The counter may count the number of times the logic level of the data signal transitions from the first level to the second level.

[0116] According to this non-volatile memory device, in response to a write instruction from an external device, the read circuit automatically reads data for verification after the data has been written, thereby reducing the processing load on the external device compared to when the external device instructs writing and then instructs reading data for verification after the writing.

[0117] In one aspect of the nonvolatile storage device, When the complementary data is written to the first memory cell and the second memory cell, the read circuit reads data stored in the first memory cell and the second memory cell, and outputs the data signal at a logic level corresponding to the data; The counter may count the number of times the logic level of the data signal transitions from the first level to the second level.

[0118] According to this non-volatile memory device, in response to a write instruction from an external device, the read circuit automatically reads data for verification after writing complementary data, thereby reducing the processing load on the external device compared to when the external device instructs writing and then instructs reading data for verification after writing.

[0119] In one aspect of the nonvolatile storage device, The counter may operate when the test mode is set, and may stop operating when the test mode is not set.

[0120] One aspect of the nonvolatile storage device is a determination circuit that determines whether the count value of the counter is equal to or greater than a threshold value and outputs a determination signal of a logic level corresponding to the determination result; The device may further include a selector that selects and outputs the determination signal when the test mode is set, and selects and outputs the data signal when the test mode is not set.

[0121] According to this nonvolatile memory device, the determination circuit can determine whether the difference between the detected current and the reference current is sufficient or whether the difference between the first detected current and the second detected current is sufficient based on the count value of the counter, thereby reducing the processing load on the external device. Also, according to this nonvolatile memory device, the selector selects and outputs either the data signal or the determination signal, so the data signal and the determination signal can be easily read out using a common signal line.

[0122] One aspect of the integrated circuit device is The nonvolatile memory device includes one aspect of the nonvolatile memory device.

[0123] This integrated circuit device is provided with a nonvolatile memory device that can increase the reliability of data stored in the memory cells, and therefore can maintain high reliability. [Explanation of symbols]

[0124] 1...nonvolatile memory device, 10...memory cell array, 20...power supply circuit, 30...word line boost circuit, 40...word line drive circuit, 50...source line drive circuit, 60...switch circuit, 61A-1 to 61A-n...MOS transistor, 61B-1 to 61B-n...MOS transistor, 62A, 62B...MOS transistor, 70...readout circuit, 71A, 71B...MOS transistor, 72A, 72B...current source, 73A, 73B...MOS transistor, 74A, 74B...MOS transistor, 75...output circuit, 80...memory control circuit, 90...register, 91...counter, 92...determination circuit, 93...selector, 100...electronic device, 110...integrated circuit device, 111...CPU, 112...ROM, 113...RAM, 120...operation unit, 130...communication unit, 140...display unit, 150...sound output unit

Claims

1. a memory cell array having a plurality of non-volatile memory cells including a first memory cell; a read circuit that reads data stored in the first memory cell by comparing a detection current flowing through the first memory cell with a reference current, and outputs a data signal of a logic level corresponding to the data; a counter that counts the number of times the logic level of the data signal transitions from a first level to a second level.

2. a memory cell array having a plurality of non-volatile memory cells including a first memory cell and a second memory cell; a read circuit that compares a first detection current flowing through the first memory cell with a second detection current flowing through the second memory cell to read complementary data stored in the first memory cell and the second memory cell, and outputs a data signal of a logic level corresponding to the complementary data; a counter that counts the number of times the logic level of the data signal transitions from a first level to a second level.

3. In claim 1, When data is written to the first memory cell, the read circuit reads data stored in the first memory cell and outputs the data signal at a logic level corresponding to the data; The counter counts the number of times the logic level of the data signal transitions from the first level to the second level.

4. In claim 2, When the complementary data is written to the first memory cell and the second memory cell, the read circuit reads data stored in the first memory cell and the second memory cell, and outputs the data signal at a logic level corresponding to the data; The counter counts the number of times the logic level of the data signal transitions from the first level to the second level.

5. In claim 1 or 2, The nonvolatile storage device, wherein the counter operates when the device is set to a test mode and stops operating when the device is not set to the test mode.

6. In claim 1 or 2, a determination circuit that determines whether the count value of the counter is equal to or greater than a threshold value and outputs a determination signal of a logic level corresponding to the determination result; a selector that selects and outputs the determination signal when the test mode is set, and selects and outputs the data signal when the test mode is not set.

7. 3. An integrated circuit device comprising the nonvolatile memory device according to claim 1.

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