Semiconductor memory device

Abstract

To provide a semiconductor memory device to realize power saving when writing data.SOLUTION: A semiconductor memory device 1 includes: a memory transistor 10; a control circuit 20 that applies a write voltage to the memory transistor 10 when writing data to the memory transistor 10; and a current suppression circuit 30 that suppresses a channel current Ic flowing to the memory transistor 10 when a write voltage is applied to the memory transistor 10.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor memory device. [Background technology]

[0002] Semiconductor memory devices such as OTPROMs (one-time programmable read-only memories) and MTPROMs (multi-time PROMs) are used for various purposes.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-103158

[0005] [overview] In conventional semiconductor memory devices, there is room for further study on power saving during data writing.

[0006] For example, a semiconductor memory device according to the present disclosure includes a memory transistor, a control circuit configured to apply a write voltage to the memory transistor when writing data to the memory transistor, and a current suppression circuit configured to suppress a channel current flowing through the memory transistor when the write voltage is applied to the memory transistor. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a write operation of a semiconductor memory device according to a first comparative example. [Figure 2] FIG. 2 is a diagram showing the writing principle of the semiconductor memory device according to the first comparative example. [Figure 3]FIG. 3 is a diagram showing the relationship between the presence or absence of data writing and the on-threshold voltage. [Figure 4] FIG. 4 is a diagram showing a read operation of the semiconductor memory device according to the first comparative example. [Figure 5] FIG. 5 is a diagram showing the reading principle of the semiconductor memory device according to the first comparative example. [Figure 6] FIG. 6 is a diagram showing a write operation of the semiconductor memory device according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing the writing principle of the semiconductor memory device according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing a write operation of the semiconductor memory device according to the modification of the first embodiment. [Figure 9] FIG. 9 is a diagram showing the writing principle of a semiconductor memory device according to a modification of the first embodiment. [Figure 10] FIG. 10 is a diagram showing a write operation of the semiconductor memory device according to the second comparative example. [Figure 11] FIG. 11 is a diagram showing a read operation of the semiconductor memory device according to the second comparative example. [Figure 12] FIG. 12 is a diagram showing a write operation of the semiconductor memory device according to the second embodiment. [Figure 13] FIG. 13 is a diagram showing a read operation of the semiconductor memory device according to the second embodiment. [Figure 14] FIG. 14 is a diagram showing a semiconductor memory device according to a third comparative example. [Figure 15] FIG. 15 is a diagram showing a write operation of the semiconductor memory device according to the third comparative example. [Figure 16] FIG. 16 is a diagram showing a semiconductor memory device according to the third embodiment. [Figure 17] FIG. 17 is a diagram showing a write operation of the semiconductor memory device according to the third embodiment. [Figure 18] FIG. 18 is a diagram showing a write operation of the semiconductor memory device according to the first modification of the third embodiment. [Figure 19] FIG. 19 is a diagram showing a write operation of the semiconductor memory device according to the second modification of the third embodiment.

[0008] [Detailed explanation] <Semiconductor Memory Device (First Comparative Example)> 1 is a diagram showing a write operation of a semiconductor memory device according to a first comparative example (a configuration example to be compared with the first embodiment described later). The semiconductor memory device 1 according to the first comparative example includes a memory transistor 10 and a control circuit 20.

[0009] The memory transistor 10 is a storage element for storing one bit of data ("0" or "1"). For example, an NMOSFET (N-channel type metal oxide semiconductor field effect transistor) may be used as the memory transistor 10.

[0010] In this specification, a MOSFET refers to a transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOSFET is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0011] The source S, drain D, gate G and back gate B of the memory transistor 10 are all connected to a control circuit 20.

[0012] The control circuit 20 controls the voltages applied to the source S, drain D, gate G, and back gate B of the memory transistor 10. For example, when writing data (e.g., "1") to the memory transistor 10, the control circuit 20 applies write voltages to the source S, drain D, gate G, and back gate B of the memory transistor 10, respectively.

[0013] Referring to this diagram, the control circuit 20 applies a power supply voltage VDD1 to the source S and gate G of the memory transistor 10 as one of the write voltages. The control circuit 20 also applies a reference voltage VSS to the drain D and back gate B of the memory transistor 10 as one of the write voltages. The reference voltage VSS may be, for example, a ground voltage GND. At this time, a channel current Ic (= a write current for writing data to the memory transistor 10) flows through the drain D of the memory transistor 10.

[0014] 2 is a diagram (= longitudinal cross-sectional view of a memory transistor 10) showing the writing principle of the semiconductor memory device 1 according to the first comparative example. The memory transistor 10 includes, for example, a low-concentration p-type semiconductor substrate 100, a high-concentration n-type semiconductor region 101, a high-concentration n-type semiconductor region 102, a high-concentration p-type semiconductor region 103, a gate insulating layer 104, a gate electrode 105, and sidewalls 106.

[0015] The heavily doped n-type semiconductor regions 101 and 102 and the heavily doped p-type semiconductor region 103 are formed in the surface layer of the lightly doped p-type semiconductor substrate 100. The heavily doped n-type semiconductor region 101 corresponds to the drain D of the memory transistor 10. The heavily doped n-type semiconductor region 102 corresponds to the source S of the memory transistor 10. The heavily doped p-type semiconductor region 103 corresponds to the back gate B of the memory transistor 10.

[0016] The gate insulating layer 104 and the gate electrode 105 are stacked on a channel region formed between the high-concentration n-type semiconductor region 101 and the high-concentration n-type semiconductor region 102. The sidewall 106 is formed to surround the gate electrode 105.

[0017] As described above, when writing data (for example, "1") to the memory transistor 10, the control circuit 20 applies write voltages to the source S, drain D, gate G, and back gate B of the memory transistor 10, respectively.

[0018] Referring to this figure, the control circuit 20 applies a power supply voltage VDD1 as one of the write voltages to the heavily doped n-type semiconductor region 102 and the gate electrode 105. The control circuit 20 also applies a reference voltage VSS as one of the write voltages to the heavily doped n-type semiconductor region 101 and the heavily doped p-type semiconductor region 103.

[0019] Application of such a write voltage forms an inversion layer 107 between the heavily doped n-type semiconductor region 101 and the heavily doped n-type semiconductor region 102. However, at a pinch-off point 108 in the figure, the inversion layer 107 cannot be maintained. As a result, a depletion layer 109 is formed around the heavily doped n-type semiconductor region 102 (= the source S of the memory transistor 10). Note that the memory transistor 10 may be an NMOSFET that does not have an electric field relaxation diffusion region, such as an LDD (lightly doped drain), so that the high electric field depletion layer 109 is formed.

[0020] When high-speed carriers enter the high-electric field depletion layer 9, hot carriers (hot electrons) having high energy are generated. The hot carriers cross the gate insulating layer 104 and are trapped in the sidewall 106.

[0021] As described above, in a write operation of the memory transistor 10, the gate G and source S (= the side into which hot carriers are injected) of the memory transistor 10 are short-circuited and connected to a high potential node. Also, the back gate B and drain D (= the side from which carriers that become hot carriers are discharged) of the memory transistor 10 are short-circuited and connected to a low potential node.

[0022] 3 is a diagram showing the relationship between whether data "1" is written and the on-threshold voltage Vth of the memory transistor 10. The horizontal axis represents the gate-source voltage Vgs of the memory transistor 10. The vertical axis represents the drain current Id of the memory transistor 10.

[0023] The hot carriers trapped in the sidewall 106 by the above-described writing operation (Figs. 1 and 2) inhibit the formation of the inversion layer 107 when the gate-source voltage Vgs is applied. As a result, the on-threshold voltage Vth of the memory transistor 10 increases.

[0024] Referring to this figure, when data "1" is not written in the memory transistor 10, the on-threshold voltage Vth becomes the voltage value Vth0. Therefore, the drain current Id easily flows. Note that, conversely, this state can be understood as a state in which data "0" is written in the memory transistor 10. On the other hand, when data "1" is written in the memory transistor 10, the on-threshold voltage Vth becomes the voltage value Vth1 (> Vth0). Therefore, the drain current Id becomes difficult to flow.

[0025] As described above, in the semiconductor memory device 1, data is written in the memory transistor 10 by utilizing the so-called HCI [hot carrier injection] phenomenon.

[0026] In the read operation of the memory transistor 10, it may be determined whether or not a predetermined read current ID (= drain current) flows in a state where a predetermined gate voltage VG (where Vth0 < VG < Vth1) is applied to the memory transistor 10.

[0027] FIG. 4 is a diagram showing the read operation of the semiconductor memory device 1 according to the first comparative example. When the control circuit 20 reads whether or not data "1" is written in the memory transistor 10, read voltages are applied to the source S, gate G, and back gate B of the memory transistor 10, respectively, and a predetermined read current ID is caused to flow through the drain D of the memory transistor 10.

[0028] Referring to this figure, the control circuit 20 applies a reference voltage VSS to the source S and back gate B of the memory transistor 10 as one of the read voltages. The control circuit 20 also applies a gate voltage VG to the gate G of the memory transistor 10 as one of the read voltages. The gate voltage VG is preferably set to a voltage value higher than the voltage value Vth0 and lower than the voltage value Vth1. The control circuit 20 also drives a current source A connected between the application terminal of a power supply voltage VDD2 (e.g., VDD2≦VDD1) and the drain D of the memory transistor 10, causing a predetermined read current ID to flow through the drain D of the memory transistor 10.

[0029] 5 is a diagram (= longitudinal cross-sectional view of memory transistor 10) showing the read principle of the semiconductor memory device 1 according to the first comparative example. This diagram shows a state in which hot carriers are trapped in the sidewall 106 of the memory transistor 10, i.e., a state in which data "1" has been written. Note that the same reference numerals as in FIG. 2 are used for the components already mentioned, and redundant explanations will be omitted.

[0030] As mentioned above, when the control circuit 20 reads whether data "1" is written in the memory transistor 10, it applies a read voltage to the source S, gate G, and back gate B of the memory transistor 10, and also passes a predetermined read current ID through the drain D of the memory transistor 10.

[0031] Referring to this figure, the control circuit 20 applies a reference voltage VSS as one of the read voltages to the heavily doped n-type semiconductor region 102 and the heavily doped p-type semiconductor region 103. The control circuit 20 also applies a gate voltage VG as one of the read voltages to the gate electrode 105. The control circuit 20 also drives the current source A to pass a predetermined read current ID through the heavily doped n-type semiconductor region 101.

[0032] If the read current ID flows, it is determined that data "1" has not been written, or conversely, that data "0" has been written. On the other hand, if the read current ID does not flow, it is determined that data "1" has been written.

[0033] <Considerations regarding power saving> In the semiconductor memory device 1 according to the first comparative example, no limit is imposed on the channel current Ic that flows through the memory transistor 10 during data writing. Therefore, the channel current Ic can become excessively large (for example, on the order of mA). As a result, the voltage drop in the path through which the channel current Ic flows (such as wiring resistance and transistor on-resistance) cannot be ignored.

[0034] If a large voltage drop occurs in the path through which the channel current Ic flows during data writing, the potential difference between the back gate B and the source S (= the side into which hot carriers are injected) of the memory transistor 10 decreases, which can degrade the data writing efficiency.

[0035] In view of these considerations, a first embodiment that can achieve power saving during data writing will be proposed below.

[0036] <Semiconductor Memory Device (First Embodiment)> 6 is a diagram showing a write operation of the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 according to the first embodiment is based on the first comparative example (FIG. 1) described above, and further includes a current suppression circuit 30.

[0037] When writing data (for example, "1") to the memory transistor 10, the control circuit 20 applies write voltages to the source S, gate G, and back gate B of the memory transistor 10, respectively.

[0038] Referring to this figure, the control circuit 20 applies a power supply voltage VDD1 as one of the write voltages to the source S and gate G of the memory transistor 10. The control circuit 20 also applies a reference voltage VSS as one of the write voltages to the back gate B of the memory transistor 10.

[0039] The current suppression circuit 30 suppresses the channel current Ic that flows between the drain D of the memory transistor 10 and the application terminal of the reference voltage VSS when the above-mentioned write voltage is applied to the memory transistor 10. The current suppression circuit 30 may include, for example, a current source (described in detail later) that performs constant current control of the channel current Ic that flows during data writing.

[0040] 7 shows the writing principle of the semiconductor memory device 1 according to the first embodiment (a longitudinal cross-sectional view of the memory transistor 10). Note that the same reference numerals as in FIG. 2 are used for the components already mentioned, and redundant explanations will be omitted.

[0041] As described above, when writing data (for example, "1") to the memory transistor 10, the control circuit 20 applies write voltages to the source S, gate G, and back gate B of the memory transistor 10, respectively.

[0042] For example, the control circuit 20 applies a power supply voltage VDD1 as one of the write voltages to the heavily doped n-type semiconductor region 102 and the gate electrode 105. The control circuit 20 also applies a reference voltage VSS as one of the write voltages to the heavily doped p-type semiconductor region 103. Application of such a write voltage traps hot carriers in the sidewall 106.

[0043] The current suppression circuit 30 also suppresses the channel current Ic that flows between the heavily doped n-type semiconductor region 101 (=drain D) and the application terminal of the reference voltage VSS. For example, the current suppression circuit 30 performs constant current control so that the channel current Ic that flows during data writing becomes a desired value.

[0044] Note that the depletion layer 109 in the high electric field is formed by the potential difference between the high-concentration n-type semiconductor region 102 (= source S) and the high-concentration p-type semiconductor region 103 (= back gate B). Therefore, even if the amount of carriers entering the depletion layer 109 decreases with the suppression of the channel current Ic flowing through the high-concentration n-type semiconductor region 101 (= drain D), hot carriers can be trapped in the sidewall 106.

[0045] As described above, in the semiconductor memory device 1 according to the first embodiment, the channel current Ic flowing through the memory transistor 10 is suppressed during data writing. Therefore, power saving during data writing can be realized. Also, the voltage drop in the path where the channel current Ic flows during data writing is reduced. Therefore, the potential difference between the back gate B and the source S (= the side where hot carriers are injected) of the memory transistor 10 is ensured, so that the data writing efficiency can be improved. Further, the suppression of the voltage drop described above also leads to a reduction in the variation of the on-threshold voltage Vth (= voltage value Vth1) after data writing.

[0046] Note that the read operation of the semiconductor memory device 1 according to the first embodiment is the same as that of the previous first comparative example (FIGS. 4 and 5). Therefore, duplicate explanations are omitted.

[0047] FIG. 8 is a diagram showing the write operation of the semiconductor memory device 1 according to a modification of the first embodiment. The semiconductor memory device 1 according to this modification is based on the previous first embodiment (FIG. 6), but the write voltage of the memory transistor 10 is changed.

[0048] Referring to this figure, the control circuit 20 applies an arbitrary voltage VDD1′ different from the power supply voltage VDD1 (for example, VSS < VDD1′ < VDD1) to the gate of the memory transistor 10. Thus, the gate G and the source S of the memory transistor 10 do not necessarily have to be shorted.

[0049] 9 shows the writing principle of the semiconductor memory device 1 according to a modification of the first embodiment (a longitudinal cross-sectional view of the memory transistor 10). Note that the same reference numerals as in FIG. 7 are used for the components already mentioned, and redundant explanations will be omitted.

[0050] As shown in the figure, the control circuit 20 applies an arbitrary voltage VDD1′ as one of the write voltages to the gate electrode 105. According to this modification, the voltage VDD1′ can be arbitrarily selected to most efficiently trap hot carriers in the sidewall 106.

[0051] <Semiconductor Memory Device (Second Comparative Example)> 10 is a diagram showing a write operation of the semiconductor memory device 1 according to the second comparative example. Like the first comparative example (FIG. 1), the semiconductor memory device 1 according to the second comparative example includes a memory transistor 10 and a control circuit 20. In particular, this diagram clearly shows, as components of the control circuit 20, transistors P1 to P4 (e.g., PMOSFETs [P-channel type MOSFETs]), transistors N1 and N2 (e.g., NMOSFETs), and a current source CS1.

[0052] The sources and back gates of the transistors P1 to P4 are all connected to the wiring L1. The gates of the transistors P2 and P3 are connected to the drain of the transistor P2. The drains of the transistors P1 and P2 are connected to a first terminal of a current source CS1. A second terminal of the current source CS1 is connected to the wiring L2. The drains of the transistors P3 and N2 are connected to the drain D of the memory transistor 10. The drains of the transistors P4 and N1 are connected to the source S of the memory transistor 10. The sources and back gates of the transistors N1 and N2 and the back gate B of the memory transistor 10 are connected to the wiring L2. The drain D of the memory transistor 10 is connected to an application terminal of the output signal OUT.

[0053] The transistors P2 and P3 form a current mirror CM1, which mirrors the drain current of the transistor P2 (=constant current I1 generated by the current source CS1) as the drain current of the transistor P3 (=read current ID).

[0054] As described above, the semiconductor memory device 1 according to the second comparative example is a single-bit type having one memory transistor 10.

[0055] Next, the voltage application state during data writing will be described. A power supply voltage VDD1 is applied to the wiring L1. If the semiconductor memory device 1 is manufactured using a submicron rule (0.5 μm<wiring width≦1 μm), the power supply voltage VDD1 may be, for example, 3 to 7 V. A reference voltage VSS is applied to the wiring L2.

[0056] The reference voltage VSS is applied to the gate of transistor P1. At this time, transistor P1 is turned on. Therefore, the current mirror CM1 is disabled. On the other hand, the power supply voltage VDD1 is applied to the gate of transistor N2. At this time, transistor N2 is turned on. Therefore, the reference voltage VSS is applied to the drain D of memory transistor 10.

[0057] A reference voltage VSS is applied to the gates of transistors P4 and N1. At this time, transistor P4 is turned on and transistor N1 is turned off. As a result, a power supply voltage VDD1 is applied to the source S of memory transistor 10. A power supply voltage VDD1 is applied to the gate G of memory transistor 10. A reference voltage VSS is applied to the back gate B of memory transistor 10.

[0058] In this way, when writing data (for example, "1") to the memory transistor 10, the control circuit 20 applies write voltages to the source S, drain D, gate G, and back gate B of the memory transistor 10, respectively.

[0059] Referring to this figure, the control circuit 20 applies a power supply voltage VDD1 to the source S and gate G of the memory transistor 10 as one of the write voltages. The control circuit 20 also applies a reference voltage VSS to the drain D and back gate B of the memory transistor 10 as one of the write voltages. At this time, a channel current Ic flows through the drain D of the memory transistor 10 via the path indicated by the dashed arrow in the figure, and hot carriers are trapped in the sidewall 106.

[0060] 11 is a diagram showing a read operation of the semiconductor memory device 1 according to the second comparative example. This diagram shows a state in which hot carriers are trapped in the sidewall 106 of the memory transistor 10, i.e., a state in which data "1" has been written. Note that the same reference numerals as in FIG. 10 are used for the components already mentioned, and redundant explanations will be omitted.

[0061] The voltage application state during data read will be described below: A power supply voltage VDD2 is applied to the line L1, and a reference voltage VSS is applied to the line L2.

[0062] A power supply voltage VDD2 is applied to the gate of transistor P1. At this time, transistor P1 is in the off state. Therefore, current mirror CM1 is in the enabled state. On the other hand, reference voltage VSS is applied to the gate of transistor N2. At this time, transistor N2 is in the off state. Therefore, a constant current I1 generated by current source CS1 can flow through drain D of memory transistor 10 as read current ID.

[0063] A power supply voltage VDD2 is applied to the gates of transistors P4 and N1. At this time, transistor P4 is turned off and transistor N1 is turned on. As a result, a reference voltage VSS is applied to the source S of memory transistor 10. The reference voltage VSS is also applied to the back gate B of memory transistor 10. A gate voltage VG is applied to the gate G of memory transistor 10.

[0064] In this way, when the control circuit 20 reads whether data "1" is written in the memory transistor 10, it applies a read voltage to the source S, gate G, and back gate B of the memory transistor 10, and passes a predetermined read current ID through the drain D of the memory transistor 10.

[0065] Referring to this figure, the control circuit 20 applies a reference voltage VSS to the source S and back gate B of the memory transistor 10 as one of the read voltages. The control circuit 20 also applies a gate voltage VG to the gate G of the memory transistor 10 as one of the read voltages. The control circuit 20 also passes a predetermined read current ID (=constant current I1) through the drain D of the memory transistor 10 via the path indicated by the dashed arrow in the figure.

[0066] If the read current ID flows, it is determined that data "1" has not been written, or conversely, that data "0" has been written. In this case, OUT ≒ VSS. On the other hand, if the read current ID does not flow, it is determined that data "1" has been written. In this case, OUT ≒ VDD2.

[0067] <Considerations regarding power saving> Incidentally, in the semiconductor memory device 1 according to the second comparative example, as in the first comparative example (FIG. 1), no limit is imposed on the channel current Ic that flows through the memory transistor 10 during data writing. As a result, a large voltage drop occurs in the path through which an excessively large channel current Ic (for example, on the order of mA) flows, which can deteriorate the efficiency of writing data.

[0068] One way to suppress the voltage drop is to reduce the on-resistance of each of the transistors P4 and N2 (e.g., Ron<100Ω). However, this approach increases the device size of each of the transistors P4 and N2.

[0069] In view of these considerations, a second embodiment is proposed below that can achieve power saving during data writing without increasing the element size.

[0070] <Semiconductor Memory Device (Second Embodiment)> FIG. 12 is a diagram showing a write operation of the semiconductor memory device 1 according to the second embodiment. The semiconductor memory device 1 according to the second embodiment is based on the second comparative example (FIGS. 10 and 11) and further includes a current suppression circuit 30. In particular, this diagram clearly shows transistors N3 and N4 (e.g., NMOSFETs) and a current source CS2 as components of the current suppression circuit 30. Note that the same reference numerals as in FIG. 10 are used for the components already mentioned, and redundant explanations will be omitted.

[0071] A first terminal of the current source CS2 is connected to the line L1. A second terminal of the current source CS2 is connected to the drains of the transistors N3 and N4. The gates of the transistors N2 and N3 are both connected to the drain of the transistor N3. The drain of the transistor N2 is connected to the drain D of the memory transistor 10. The sources and back gates of the transistors N2 to N4 are connected to the line L2.

[0072] Transistors N2 and N3 form a current mirror CM2. The current mirror CM2 mirrors the drain current of transistor N3 (constant current I2 generated by current source CS2) as the drain current of transistor N2 (channel current Ic). Note that the constant current I2 may be, for example, on the order of μA or less.

[0073] The voltage application state during data writing is basically the same as that of the previous second comparative example (FIG. 10). That is, the power supply voltage VDD1 is applied to the wiring L1. The reference voltage VSS is applied to the wiring L2. The reference voltage VSS is applied to the gate of the transistor P1. The reference voltage VSS is applied to the gates of the transistors P4 and N1, respectively. The power supply voltage VDD1 (or an arbitrary voltage VDD1') is applied to the gate G of the memory transistor 10. The reference voltage VSS is applied to the back gate B of the memory transistor 10.

[0074] Also, the reference voltage VSS is applied to the gate of the transistor N4. At this time, the transistor N4 is turned off. Therefore, the current mirror CM2 is in an active state. Therefore, the constant current I2 generated by the current source CS2 flows as the channel current Ic to the drain D of the memory transistor 10.

[0075] Thus, in the semiconductor memory device 1 according to the second embodiment, the current source CS2 that generates a constant current I2 of the order of μA or less is used as the supply source of the carrier (= channel current Ic) that becomes the hot carrier. Therefore, since the channel current Ic is suppressed, power saving during data writing can be realized.

[0076] Also, the voltage drop in the path where the channel current Ic flows during data writing is reduced. Therefore, the potential difference between the back gate B and the source S (= the side where hot carriers are injected) of the memory transistor 10 is ensured, so that the data writing efficiency can be improved. In addition, the suppression of the above voltage drop also leads to a reduction in the variation of the on-threshold voltage Vth (= voltage value Vth1) after data writing.

[0077] Furthermore, in the semiconductor memory device 1 according to the second embodiment, the on-resistances of the transistors P4 and N2 are increased (for example, 100Ω < Ron < 10kΩ) as compared with the previous second comparative example (FIG. 10). That is, the element sizes of the transistors P4 and N2 are reduced. Therefore, miniaturization of the semiconductor memory device 1 (= reduction of the substrate area) becomes possible.

[0078] 13 is a diagram showing a read operation of the semiconductor memory device 1 according to the second embodiment. This diagram shows a state in which hot carriers are trapped in the sidewall 106 of the memory transistor 10, i.e., a state in which data "1" has been written. Note that the same reference numerals as in FIG. 12 are used for the components already mentioned, and redundant explanations will be omitted.

[0079] The voltage application state during data read is basically the same as in the second comparative example (FIG. 11) described above. That is, a power supply voltage VDD2 is applied to the line L1. A reference voltage VSS is applied to the line L2. A power supply voltage VDD2 is applied to the gate of the transistor P1. A power supply voltage VDD2 is applied to the gates of the transistors P4 and N1. A gate voltage VG is applied to the gate G of the memory transistor 10. A reference voltage VSS is applied to the back gate B of the memory transistor 10.

[0080] Furthermore, the power supply voltage VDD2 is applied to the gate of the transistor N4. At this time, the transistor N4 is turned on. Therefore, the current mirror CM2 is disabled. Therefore, the current suppression circuit 30 does not interfere with the read operation of the memory transistor 10. Note that, during data read, the current source CS2 and the line L1 or the current source CS2 and the drain of the transistor N3 may be open.

[0081] <Semiconductor Memory Device (Third Comparative Example)> 14 is a diagram showing a semiconductor memory device 1 according to a third comparative example. The semiconductor memory device 1 includes memory transistors 11a, 11b, and 11c (e.g., NMOSFETs), memory transistors 12a, 12b, and 12c (e.g., NMOSFETs), memory transistors 13a, 13b, and 13c (e.g., NMOSFETs), and a control circuit 20.

[0082] In particular, this figure clearly shows, as components of the control circuit 20, transistors P1 and P2 (e.g., PMOSFETs), transistors P3a, P3b, and P3c (e.g., PMOSFETs), transistors P4a, P4b, and P4c (e.g., PMOSFETs), transistors N1a, N1b, and N1c (e.g., NMOSFETs), transistors N2a, N2b, and N2c (e.g., NMOSFETs), and current source CS1.

[0083] The control circuit 20 also includes bit lines BLa, BLb, and BLc, source lines SLa, SLb, and SLc, and word lines WL1, WL2, and WL3.

[0084] The sources and back gates of the transistors P1, P2, P3a to P3c, and P4a to P4c are connected to the wiring L1. The gates of the transistors P2 and P3a to P3c are connected to the drain of the transistor P2. The drains of the transistors P1 and P2 are connected to a first terminal of a current source CS1. The second terminal of the current source CS1 is connected to the wiring L2.

[0085] The drains of transistors P3a and N2a and memory transistors 11a, 12a, and 13a are connected to bit line BLa. The drains of transistors P3b and N2b and memory transistors 11b, 12b, and 13b are connected to bit line BLb. The drains of transistors P3c and N2c and memory transistors 11c, 12c, and 13c are connected to bit line BLc.

[0086] The drains of transistors P4a and N1a and the sources of memory transistors 11a, 12a, and 13a are connected to source line SLa. The drains of transistors P4b and N1b and the sources of memory transistors 11b, 12b, and 13b are connected to source line SLb. The drains of transistors P4c and N1c and the sources of memory transistors 11c, 12c, and 13c are connected to source line SLc.

[0087] The sources and back gates of the transistors N1a to N1c and N2a to N2c are connected to the wiring L2, and the back gates of the memory transistors 11a to 11c, 12a to 12c and 13a to 13c are connected to the wiring L2.

[0088] The gates of memory transistors 11a, 11b, and 11c are connected to word line WL1, the gates of memory transistors 12a, 12b, and 12c are connected to word line WL2, and the gates of memory transistors 13a, 13b, and 13c are connected to word line WL3.

[0089] The transistors P2 and P3a to P3c form a current mirror CM1. The current mirror CM1 mirrors the drain current of the transistor P2 (=constant current I1 generated by the current source CS1) as the drain current (=read current ID) of each of the transistors P3a to P3c.

[0090] As described above, the semiconductor memory device 1 according to the third comparative example is an array bit type having a plurality of memory transistors 11a, 11b, 11c, 12a, 12b, 12c, 13a, 13b, and 13c arranged in an array (two-dimensional matrix).

[0091] Next, the voltage application state of each part will be described. A power supply voltage VDD is applied to the line L1. When writing data, a power supply voltage VDD1 is applied as the power supply voltage VDD. When reading data, a power supply voltage VDD2 is applied as the power supply voltage VDD. A reference voltage VSS is applied to the line L2.

[0092] A voltage V0 is applied to the gate of the transistor P1. During data writing, a reference voltage VSS is applied as the voltage V0. During data reading, a power supply voltage VDD2 is applied as the voltage V0.

[0093] Voltages V1a, V1b, and V1c are applied to the gates of the transistors N1a, N1b, and N1c, respectively. During data writing, a reference voltage VSS is applied as the voltages V1a to V1c. During data reading, a power supply voltage VDD2 is applied as the voltages V1a to V1c.

[0094] Voltages V2a, V2b, and V2c are applied to the gates of the transistors N2a, N2b, and N2c, respectively. During data writing, when the bit lines BLa to BLc are selected, a power supply voltage VDD1 is applied as the voltages V2a to V2c. During data writing, when the bit lines BLa to BLc are not selected, a reference voltage VSS is applied as the voltages V2a to V2c. During data writing, the power supply voltage VDD1 may be applied as the voltages V2a to V2c regardless of whether the bit lines BLa to BLc are selected or not. During data reading, a reference voltage VSS is applied as the voltages V2a to V2c.

[0095] Voltages V3a, V3b, and V3c are applied to the gates of the transistors P4a, P4b, and p4c, respectively. During data writing, when the source lines SLa to SLc are selected, a reference voltage VSS is applied as the voltages V3a to V3c. During data writing, when the source lines SLa to SLc are not selected, a power supply voltage VDD1 is applied as the voltages V3a to V3c. During data writing, the reference voltage VSS may be applied as the voltages V3a to V3c regardless of whether the source lines SLa to SLc are selected or not. During data reading, a power supply voltage VDD2 is applied as the voltages V3a to V3c.

[0096] During data writing, the word line to be selected among the word lines WL1 to WL3 is applied with the power supply voltage VDD1, while the word lines not to be selected among the word lines WL1 to WL3 are applied with the reference voltage VSS.

[0097] During data read, a gate voltage VG is applied to a selected word line among the word lines WL1 to WL3, while a reference voltage VSS is applied to a non-selected word line among the word lines WL1 to WL3.

[0098] 15 is a diagram showing the write operation of the semiconductor memory device 1 according to the third comparative example. For ease of explanation, this diagram shows only memory transistors 11a and 11b and memory transistors 12a and 12b as the multiple memory transistors arranged in an array. This diagram also illustrates the case where memory transistor 11a is selected as the target for writing data "1."

[0099] In this case, the power supply voltage VDD1 is applied to the word line WL1 connected to the gate G of the memory transistor 11a, while the reference voltage VSS is applied to the word line WL2 not connected to the gate G of the memory transistor 11a.

[0100] Furthermore, the power supply voltage VDD1 is applied to the source lines SLa and SLb, respectively. In reference to FIG. 14, this can be understood as a state in which the transistors P4a and P4b are turned on and the transistors N1a and N1b are turned off.

[0101] Furthermore, the reference voltage VSS is applied to the bit line BL1a to which the drain D of the memory transistor 11a is connected. In reference to FIG. 14, this can be understood as a state in which the current mirror CM1 is disabled and the transistor N2a is turned on. Meanwhile, the bit line BL1b, to which the drain D of the memory transistor 11a is not connected, is set to an open state. In reference to FIG. 14, this can be understood as a state in which the current mirror CM1 is disabled and the transistor N2b is turned off.

[0102] In this way, when writing data (for example, "1") to the memory transistor 11a to be written, the control circuit 20 applies write voltages to the source S, drain D, gate G, and back gate B of the memory transistor 11a.

[0103] Referring to this diagram, the control circuit 20 applies a power supply voltage VDD1 to the source S and gate G of the memory transistor 11a as one of the write voltages. The control circuit 20 also applies a reference voltage VSS to the drain D and back gate B of the memory transistor 11a as one of the write voltages. At this time, a channel current Ic flows through the drain D of the memory transistor 11a via the path indicated by the dashed arrow in the diagram, trapping hot carriers. Meanwhile, no channel current Ic flows through the unselected memory transistors 11b, 12a, and 12b.

[0104] <Considerations regarding power saving> Incidentally, in the semiconductor memory device 1 according to the third comparative example, as in the first comparative example (FIG. 1) and the second comparative example (FIG. 10), no limitation is imposed on the channel current Ic flowing through the memory transistor 11a to which data is to be written. Therefore, a large voltage drop occurs in the path through which an excessively large channel current Ic (for example, on the order of mA) flows, which may result in a deterioration in data writing efficiency.

[0105] Furthermore, as mentioned above, if an attempt is made to suppress the above voltage drop by reducing the on-resistance of each of the transistors P4a and N2a (for example, Ron<100Ω), the element size of each of the transistors P4a and N2a will increase.

[0106] Furthermore, in the array bit type semiconductor memory device 1, the number of memory transistors to which data can be simultaneously written is limited depending on the current capacity of a power supply circuit (not shown) connected to the wiring L1.

[0107] The above-listed problems are the same regardless of whether the memory transistors 11a to 11c or 12a to 12c are the target of writing.

[0108] In view of these considerations, a third embodiment that can solve the above problems is proposed below.

[0109] <Semiconductor Memory Device (Third Embodiment)> FIG. 16 is a diagram showing a semiconductor memory device 1 according to a third embodiment. The semiconductor memory device 1 according to the third embodiment is based on the third comparative example (FIG. 14) described above, and further includes a current suppression circuit 30. In particular, this diagram clearly shows transistors N3 and N4 (e.g., NMOSFETs) and a current source CS2 as components of the current suppression circuit 30. Note that the same reference numerals as in FIG. 14 are used for the components already described, and redundant explanations will be omitted.

[0110] A first terminal of the current source CS2 is connected to the wiring L1. A second terminal of the current source CS2 is connected to the drains of the transistors N3 and N4. The gates (=node nd) of the transistors N2a to N2c and N3 are all connected to the drain of the transistor N3. The drains of the transistors N2a to N2c are connected to the bit lines BLa to BLc. The sources and back gates of the transistors N2a to N2c, N3 and N4 are connected to the wiring L2.

[0111] Transistors N2a to N2c and N3 form a current mirror CM2. The current mirror CM2 mirrors the drain current of transistor N3 (=constant current I2 generated by current source CS2) as the drain current (=channel current Ic) of each of transistors N2a to N2c. Note that the constant current I2 may be, for example, on the order of μA or less.

[0112] The voltage application state of each part is the same as that of the third comparative example (FIG. 14) described above, so duplicated explanations will be omitted. A voltage V0 is applied to the gate of transistor N4. As described above, during data writing, the reference voltage VSS is applied as voltage V0. Meanwhile, during data reading, the power supply voltage VDD2 is applied as voltage V0.

[0113] 17 is a diagram showing a write operation of the semiconductor memory device 1 according to the third embodiment. For ease of explanation, only memory transistors 11a and 11b and memory transistors 12a and 12b are shown as a plurality of memory transistors arranged in an array. This diagram also illustrates a case where memory transistor 11a is selected as the target for writing data "1."

[0114] In this case, the power supply voltage VDD1 is applied to the word line WL1 connected to the gate G of the memory transistor 11a, while the reference voltage VSS is applied to the word line WL2 not connected to the gate G of the memory transistor 11a.

[0115] Furthermore, a power supply voltage VDD1 is applied to a source line SLa to which the source S of the memory transistor 11a is connected. In terms of FIG. 16, this can be understood as a state in which the transistor P4a is turned on and the transistor N1a is turned off.

[0116] On the other hand, the source line SLb to which the source S of the memory transistor 11a is not connected is set to an open state, which can be understood as a state in which both the transistors P4b and N1b are turned off, in accordance with the above-mentioned FIG.

[0117] During data write, the current mirror CM2 of the current suppression circuit 30 is enabled. At this time, a constant current I2 generated by the current source CS2 flows as a channel current Ic through the current path from the source line SLa to the wiring L2 via the memory transistor 11a, the bit line BLa, and the transistor N2a. The voltage applied to the bit line BLa is a voltage (=VDD1-Vx) lower than the power supply voltage VDD1 by the gate-drain voltage Vx of the memory transistor 11a. Meanwhile, no write target that passes the channel current Ic is connected to the bit line BLb. Therefore, the voltage applied to the bit line BLb is pulled down to the reference voltage VSS via the transistor N2b.

[0118] As described above, in the semiconductor memory device 1 according to the third embodiment, as in the second embodiment (FIG. 12), a current source CS2 that generates a constant current I2 on the order of μA or less is used as a supply source of carriers (=channel current Ic) that become hot carriers. Therefore, the channel current Ic is suppressed, and power saving during data writing can be achieved.

[0119] Furthermore, the voltage drop in the path through which the channel current Ic flows during data writing is reduced, which makes it possible to improve the data writing efficiency, reduce the variation in the on-threshold voltage after data writing, and reduce the size of the semiconductor memory device 1.

[0120] Furthermore, in the semiconductor memory device 1 according to the third embodiment, it is possible to increase the number of memory transistors to which data can be simultaneously written without unnecessarily increasing the current capacity of the power supply circuit (not shown) connected to the wiring L1.

[0121] 18 is a diagram showing a write operation of the semiconductor memory device 1 according to the first modification of the third embodiment. The semiconductor memory device 1 according to the first modification is based on the third embodiment (FIG. 17) and further includes a switch SW0 and switches SW1a and SW1b as components of the control circuit 20.

[0122] The switch SW0 is connected between the source of the transistor N3 and the line L2, and is turned on when writing data, and turned off when reading data.

[0123] The switch SW1a is connected between the source of the transistor N2a and the line L2. That is, the switch SW1a conducts / cuts off a current path from the bit line BLa to the line L2 via the transistor N2a that forms the output stage of the current mirror CM2. The switch SW1a is turned on when the bit line BLa is selected during data writing. On the other hand, the switch SW1a is turned off when the bit line BLa is not selected during data writing. The switch SW1a is also turned off during data reading.

[0124] The switch SW1b is connected between the source of the transistor N2b and the line L2. That is, the switch SW1b conducts / cuts off the current path from the bit line BLb to the line L2 via the transistor N2b that forms the output stage of the current mirror CM2. The switch SW1b is turned on when the bit line BLb is selected during data writing. On the other hand, the switch SW1b is turned off when the bit line BLb is not selected during data writing. The switch SW1b is also turned off during data reading.

[0125] 17, the control circuit 20 may open the bit line BLb instead of the source line SLb to which the memory transistor 11a to be written is not connected. In this case, the power supply voltage VDD1 may be applied to the source line SLb.

[0126] 19 is a diagram showing a write operation of the semiconductor memory device 1 according to the second modification of the third embodiment. The semiconductor memory device 1 according to the second modification is based on the third embodiment (FIG. 17) and further includes switches SW2a and SW2b as components of the control circuit 20.

[0127] The switch SW2a is connected between the bit line BLa and the drain of the transistor N2a. That is, the switch SW2a conducts / cuts off the current path from the bit line BLa to the line L2 via the transistor N2a that forms the output stage of the current mirror CM2. The switch SW2a is turned on when the bit line BLa is selected during data writing. On the other hand, the switch SW2a is turned off when the bit line BLa is not selected during data writing. The switch SW2a is also turned off during data reading.

[0128] The switch SW2b is connected between the bit line BLb and the drain of the transistor N2b. That is, the switch SW2b conducts / cuts off the current path from the bit line BLb to the line L2 via the transistor N2b that forms the output stage of the current mirror CM2. The switch SW2b is turned on when the bit line BLb is selected during data writing. On the other hand, the switch SW2b is turned off when the bit line BLb is not selected during data writing. The switch SW2b is also turned off during data reading.

[0129] 17, the control circuit 20 may open the bit line BLb instead of the source line SLb to which the memory transistor 11a to be written is not connected. In this case, the power supply voltage VDD1 may be applied to the source line SLb.

[0130] Furthermore, as can be seen from a comparison between the first modified example (FIG. 18) and the second modified example (FIG. 19), the switches for conducting / cutting off the current path through which the channel current Ic flows may be inserted on the source side or on the drain side of each of the transistors N2a and N2b.

[0131] <Applicable to> The semiconductor memory device 1 according to the present disclosure can be applied to a wide range of devices that require data adjustment and retention during the manufacturing process, such as series regulators, switching regulators, motor control devices, power supply devices, and sensor devices.

[0132] <Additional Notes> The semiconductor memory device according to the present disclosure can achieve power saving during data writing.

[0133] [Appendix 1] A memory transistor (10); a control circuit (20) configured to apply a write voltage to the memory transistor (10) when writing data to the memory transistor (10); a current suppression circuit (30) configured to suppress a channel current (Ic) flowing through the memory transistor (10) when the write voltage is applied to the memory transistor (10); A semiconductor memory device (1) comprising:

[0134] [Appendix 2] The control circuit (20) applies, as the write voltage, a first power supply voltage (VDD1) to the source (S) of the memory transistor (10), a reference voltage (VSS) to the back gate (B) of the memory transistor (10), and applies the first power supply voltage (VDD1) or an arbitrary voltage (VDD1') different from the first power supply voltage (VDD1) to the gate (G) of the memory transistor (10); 2. The semiconductor memory device (1) according to claim 1, wherein the current suppression circuit (30) suppresses the channel current (Ic) flowing through the drain (D) of the memory transistor (10).

[0135] [Appendix 3] The on-threshold voltage (Vth) of the memory transistor (10) is a first voltage value (Vth0) if the data is not written to the memory transistor (10), and is a second voltage value (Vth1) if the data is written to the memory transistor (10); The semiconductor memory device (1) according to Appendix 2, wherein, when reading whether the data has been written to the memory transistor (10), the control circuit (20) applies the reference voltage (VSS) to the source (S) and back gate (B) of the memory transistor (10), applies a gate voltage (VG) higher than the first voltage value (Vth0) and lower than the second voltage value (Vth1) to the gate (G) of the memory transistor (10), and passes a predetermined read current (ID) through the drain (D) of the memory transistor (10).

[0136] [Appendix 4] The semiconductor memory device (1) according to any one of appendices 1 to 3, which is a single-bit type having one memory transistor (10).

[0137] [Appendix 5] The semiconductor memory device (1) described in Appendix 4, wherein the current suppression circuit (30) includes a current source (CS2) configured to generate a predetermined constant current (I2), and a current mirror (CM2) configured to mirror the constant current (I2) and output it to the drain (D) of the memory transistor (10).

[0138] [Appendix 6] The semiconductor memory device (1) according to any one of appendices 1 to 3, which is an array bit type having a plurality of the memory transistors (11a, 11b, 11c, 12a, 12b, 12c, 13a, 13b, 13c).

[0139] [Appendix 7] The semiconductor memory device described in Appendix 6, wherein the current suppression circuit (30) includes a current source (CS2) configured to generate a predetermined constant current (I2), and a current mirror (CM2) configured to mirror the constant current (I2) and output it to the drains (D) of each of the plurality of memory transistors (11a, 11b, 11c, 12a, 12b, 12c, 13a, 13b, 13c).

[0140] [Appendix 8] The semiconductor memory device (1) according to appendix 7, wherein the control circuit (20) sets in an open state a source line (SLb) to which a write target (11a) of the plurality of memory transistors (11a, 11b, 12a, 12b) is not connected.

[0141] [Appendix 9] The semiconductor memory device (1) according to appendix 7, wherein the control circuit (20) sets a bit line (BLb) to which a write target (11a) of the plurality of memory transistors (11a, 11b, 12a, 12b) is not connected to an open state.

[0142] [Appendix 10] The semiconductor memory device (1) described in Appendix 9, wherein the control circuit (20) includes a plurality of switches (SW1a, SW1b, SW2a, SW2b) configured to respectively conduct / cut off a plurality of current paths from a plurality of bit lines (BLa, BLb) via a plurality of transistors (N2a, N2b) forming an output stage of the current mirror (CM2) to an application terminal of a reference voltage (VSS).

[0143] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0144] 1. Semiconductor memory device 10 Memory transistor (NMOSFET) 11a, 11b, 11c Memory transistor (NMOSFET) 12a, 12b, 12c Memory transistor (NMOSFET) 13a, 13b, 13c Memory transistor (NMOSFET) 20 Control circuit 30 Current suppression circuit 100 Low concentration p-type semiconductor substrate 101 Highly doped n-type semiconductor region (drain) 102 Highly doped n-type semiconductor region (source) 103 Highly doped p-type semiconductor region (back gate) 104 Gate insulating layer 105 gate electrode 106 Sidewall 107 Inversion Layer 108 Pinch-off point 109 Depletion Layer A current source B Back Gate BLa, BLb, BLc bit lines CM1, CM2 current mirror CS1, CS2 current source D Drain G Gate L1, L2 wiring N1, N1a, N1b, N1c transistors (NMOSFET) N2, N2a, N2b, N2c transistors (NMSOFET) N3 transistor (NMOSFET) N4 transistor (NMOSFET) P1 transistor (PMOSFET) P2 transistor (PMOSFET) P3, P3a, P3b, P3c transistors (PMOSFET) P4, P4a, P4b, P4c transistors (PMOSFET) S sauce SLa, SLb, SLc source lines SW0 switch SW1a and SW1b switches SW2a and SW2b switches WL1, WL2, WL3 word lines

Claims

1. a memory transistor; a control circuit configured to apply a write voltage to the memory transistor when writing data to the memory transistor; a current suppression circuit configured to suppress a channel current flowing through the memory transistor when the write voltage is applied to the memory transistor; A semiconductor memory device comprising:

2. the control circuit applies, as the write voltage, a first power supply voltage to the source of the memory transistor, a reference voltage to the back gate of the memory transistor, and the first power supply voltage or an arbitrary voltage different from the first power supply voltage to the gate of the memory transistor; 2. The semiconductor memory device according to claim 1, wherein said current suppression circuit suppresses said channel current flowing through the drain of said memory transistor.

3. an on-threshold voltage of the memory transistor is a first voltage value when the data is not written in the memory transistor, and is a second voltage value when the data is written in the memory transistor; 3. The semiconductor memory device according to claim 2, wherein, when reading whether the data is written to the memory transistor, the control circuit applies the reference voltage to the source and back gate of the memory transistor, applies a gate voltage higher than the first voltage value and lower than the second voltage value to the gate of the memory transistor, and passes a predetermined read current through the drain of the memory transistor.

4. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a single-bit type having one memory transistor.

5. 5. The semiconductor memory device according to claim 4, wherein said current suppression circuit includes: a current source configured to generate a predetermined constant current; and a current mirror configured to mirror said constant current and output it to the drain of said memory transistor.

6. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an array bit type having a plurality of said memory transistors.

7. 7. The semiconductor memory device according to claim 6, wherein the current suppression circuit includes a current source configured to generate a predetermined constant current, and a current mirror configured to mirror the constant current and output it to the drains of each of the plurality of memory transistors.

8. 8. The semiconductor memory device according to claim 7, wherein said control circuit sets in an open state source lines of said plurality of memory transistors to which no write target is connected.

9. 8. The semiconductor memory device according to claim 7, wherein said control circuit sets to an open state bit lines among said plurality of memory transistors to which no write target is connected.

10. 10. The semiconductor memory device according to claim 9, wherein said control circuit includes a plurality of switches configured to respectively conduct / cut off a plurality of current paths from a plurality of bit lines through a plurality of transistors forming an output stage of said current mirror to a terminal to which a reference voltage is applied.

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