Characteristic compensation circuit

Abstract

To provide a characteristic compensation circuit that can suppress a fluctuation in an output voltage due to a stress variation.SOLUTION: A first embedded Zener diode ZD 1 is reverse-biased by a current source 10 from a cathode connected to a first node N1 toward an anode connected to a ground node NG. A second embedded Zener diode ZD2 is forward-biased by the current source 10 from an anode connected to a second node N2 to a cathode connected to the ground node. While voltage-dividing resistors R0 and R1 are connected between the first node N1 and the second node N2 in a resistor voltage-dividing circuit 11, a voltage based on the voltage-dividing resistors R0 and R1 is defined as an output voltage Vout. A temperature characteristic of the output voltage is compensated for by weighting-adding a voltage across the Zener diode ZD 1 and a voltage across the Zener diode ZD 2 using the resistor voltage-dividing circuit 11.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a characteristic compensation circuit. [Background technology]

[0002] For example, Patent Documents 1 and 2 propose reference power supply circuits that are capable of compensating for output fluctuations due to temperature characteristics. According to the reference power supply circuits described in Patent Documents 1 and 2, the positive temperature characteristics of a Zener diode are offset by the negative temperature characteristics of a diode or a diode-connected bipolar junction transistor (hereinafter referred to as a BJT). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent No. 3,916,508 [Patent Document 2] US Patent Publication No. 11 / 402863 Summary of the Invention [Problem to be solved by the invention]

[0004] Diodes and diode-connected BJTs are susceptible to stress, and there is a risk that the output voltage will fluctuate due to stress fluctuations caused by package distortion or other factors.

[0005] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a characteristic compensation circuit that can suppress fluctuations in output voltage due to stress fluctuations. [Means for solving the problem]

[0006] The invention of claim 1 includes a bias circuit, a first buried Zener diode biased by the bias circuit in a direction from its cathode connected to a first node to its anode connected to a ground node, a second buried Zener diode biased by the bias circuit in a direction from its anode connected to a second node to its cathode connected to the ground node, and a resistive voltage divider circuit having voltage divider resistors connected between the first node and the second node, and outputs a voltage based on the voltage divider resistors of the resistive voltage divider circuit.

[0007] The voltage applied to the first buried Zener diode and the voltage applied to the second buried Zener diode are weighted and added by a resistive voltage divider circuit to compensate for the temperature characteristics of the voltages of the first buried Zener diode and the second buried Zener diode.

[0008] According to the invention of claim 1, a forward-biased second buried Zener diode is used instead of a normal forward-biased diode or diode-connected BJT, which makes it less susceptible to fluctuations in output voltage due to stress fluctuations. As a result, fluctuations in output voltage due to stress fluctuations can be suppressed. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating the configuration of a characteristic compensation circuit according to a first embodiment. [Figure 2] Specific example of the characteristic compensation circuit in the first embodiment [Figure 3] Layout configuration example of buried Zener diode in the first embodiment [Figure 4] Specific example of characteristic compensation circuit in the second embodiment DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, several embodiments of the characteristic compensation circuit will be described with reference to the drawings. Components that perform the same functions in the various embodiments will be designated by the same reference numerals, and descriptions thereof may be omitted.

[0011] (First embodiment) The first embodiment will be described with reference to Figures 1 to 3. A temperature compensation circuit 1 serving as a characteristic compensation circuit is configured to include a current source 10 serving as a bias circuit, a first buried Zener diode ZD1, a second buried Zener diode ZD2, and a resistive voltage divider circuit 11. Hereinafter, the first buried Zener diode ZD1 will be abbreviated as "Zener diode ZD1" and the second buried Zener diode ZD2 will be abbreviated as "Zener diode ZD2."

[0012] The current source 10 generates a constant current I0 based on the power supply voltage VDD_HIGH and outputs it to a first node N1. The first node N1 is connected to the cathode of the Zener diode ZD1, a first terminal T1 of the resistive voltage divider circuit 11, and the current source 10. The second node N2 is connected to the anode of the Zener diode ZD2 and a third terminal T3 of the resistive voltage divider circuit 11. The second terminal T2 of the resistive voltage divider circuit 11 is connected to a third node N3. The third node N3 serves as a terminal for the output voltage Vout.

[0013] The Zener diode ZD1 has a cathode connected to the first node N1 and an anode connected to the ground node NG. The Zener diode ZD1 is reverse biased in the direction from the cathode to the anode by the current source 10. Only one Zener diode ZD1 is connected.

[0014] The Zener diode ZD2 has an anode connected to the second node N2 and a cathode connected to the ground node NG. The Zener diode ZD2 is forward biased from the anode to the cathode by the current source 10. Although an example is shown in which only one Zener diode ZD2 is connected to the relevant location, multiple Zener diodes ZD2 may be connected in series.

[0015] A resistive voltage-dividing circuit 11 is connected between a first node N1 and a second node N2. The resistive voltage-dividing circuit 11 is configured by combining a plurality of voltage-dividing resistors R0 and R1, and divides the voltage between the first node N1 and the second node N2. As illustrated in FIG. 2, the voltage-dividing resistors R0 and R1 are connected between a first terminal T1 and a third terminal T3 of the resistive voltage-dividing circuit 11.

[0016] 1, the temperature compensation circuit 1 outputs a voltage based on the voltage-dividing resistors R0 and R1 of the resistive voltage-dividing circuit 11. Specifically, as illustrated in FIG. 2, the temperature compensation circuit 1 outputs the voltage of the third node N3 divided by the voltage-dividing resistors R0 and R1 of the resistive voltage-dividing circuit 11.

[0017] The temperature compensation circuit 1 is configured to compensate for the temperature characteristics of the voltages of the Zener diodes ZD1 and ZD2 by weighting and adding the voltages applied to the Zener diodes ZD1 and ZD2 using a resistive voltage divider circuit 11.

[0018] <Layout example of Zener diodes ZD1 and ZD2> The Zener diodes ZD1 and ZD2 have a layout structure in which they have the same planar shape (for example, a rectangular shape) as shown in Fig. 3. Furthermore, the formation areas A1 and A2 of the Zener diodes ZD1 and ZD2 are arranged adjacent to each other.

[0019] Next, the principle of temperature compensation according to the first embodiment will be described. The voltage of the first node N1 to which the reverse-biased Zener diode ZD1 is connected is set to a Zener voltage V Z , the anode-cathode voltage of the forward-biased Zener diode ZD2 is the forward voltage V D When the weighting coefficients are α and β, the general formula of the output voltage Vout obtained by weighting addition using the resistive voltage divider circuit 11 can be written as the following formula (1).

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[0020] Therefore, in the specific example configuration shown in Figure 2, the output voltage Vout is the Zener voltage V Z and forward voltage V D and can be written as the following equation (2), which is weighted by the resistance ratio and added together.

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[0021] Furthermore, by partially differentiating equation (2) with respect to temperature T, the temperature characteristic of the output voltage Vout is obtained as shown in equation (3) below.

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[0022] Generally, the temperature characteristics of a forward-biased Zener diode ZD2 are given by ∂V D / ∂T is negative. Therefore, the reverse-biased Zener diode ZD1 has a temperature characteristic of ∂V Z It is advisable to form it so that / ∂T is positive. Then, by adjusting the voltage dividing resistors R0 and R1 to an appropriate resistance ratio, the temperature characteristics of the output voltage Vout can be made appropriate.

[0023] <Summary of this embodiment> Conventionally, a typical forward diode or a diode-connected BJT has often been used in the location of the Zener diode ZD2 described in this embodiment. However, these methods result in large fluctuations in the output voltage Vout in response to fluctuations in stress. In particular, in vehicle applications, it is necessary to withstand various vibrations, and it is undesirable for the output voltage Vout to fluctuate significantly due to the vibrations.

[0024] Therefore, in this embodiment, a buried Zener diode ZD2 is used to generate the forward bias voltage VD. The buried Zener diodes ZD1 and ZD2 have junctions located deeper than the surface of the semiconductor wafer due to manufacturing reasons. This makes them less susceptible to stress than normal diodes or diode-connected BJTs. This makes them less susceptible to stress than normal diodes or diode-connected BJTs, and minimizes the stress dependence of the output voltage Vout. As a result, a configuration that is less susceptible to stress than conventional configurations can be achieved, making it possible to configure a reference power supply circuit with minimal stress dependence.

[0025] In this embodiment, the voltage V applied to the Zener diode ZD1 Z and the voltage V applied to the Zener diode ZD2 D The temperature characteristics of the output voltage Vout are compensated for by weighting and adding these voltages V by the resistive voltage divider circuit 11. Specifically, the voltage difference between the cathodes of the reverse-biased Zener diode ZD1 has a positive temperature characteristic, and the voltage difference between the cathodes of the forward-biased Zener diode ZD2 has a negative temperature characteristic. Z , V D These are weighted and added by the resistive voltage divider circuit 11 so that their respective temperature characteristics are offset, and are output as the output voltage Vout. As a result, it is possible to configure a reference power supply circuit that can compensate for the temperature characteristics and has low stress dependency as well as low temperature dependency.

[0026] The resistive voltage divider circuit 11 is configured by a circuit consisting of multiple voltage dividing resistors R0 and R1 connected in series, and the divided voltage by the multiple voltage dividing resistors R0 and R1 is used as the output voltage Vout, which allows for a simple configuration.

[0027] (Second embodiment) A second embodiment will be described with reference to FIG. 4. FIG. 4 shows an example of the configuration of a resistive voltage-dividing circuit 211 shown in place of FIG. 2. The resistive voltage-dividing circuit 211 is a circuit including a plurality of voltage-dividing resistors R2 to R5 connected in series, and a plurality of semiconductor switches S1 to S3 whose input terminals are connected in parallel to common connection nodes N4 to N6 of the plurality of voltage-dividing resistors R2 to R5 and whose output terminals are connected in common. A control circuit 20 is configured by control logic and controls the on / off of the semiconductor switches S1 to S3. The resistive voltage-dividing circuit 211 outputs a voltage divided by the plurality of voltage-dividing resistors R2 to R5 as an output voltage Vout through the input terminals and output terminals of the semiconductor switches S1 to S3.

[0028] In this embodiment, the semiconductor switches S1 to S3 are each composed of one or more MOS transistors having one or more control terminals (gates). Each of the semiconductor switches S1 to S3 may be composed of, for example, an N-channel MOS transistor alone or a P-channel MOS transistor alone.

[0029] The semiconductor switches S1 to S3 may also be configured by connecting the input terminals and output terminals (drains / sources) of N-channel MOS transistors and P-channel MOS transistors in common in parallel. The semiconductor switches S1 to S3 can switch between open and short between the input terminals (drains) and output terminals (sources) according to the voltage applied to the control terminals.

[0030] The terminals on one side of the semiconductor switches S1 to S3, which are MOS transistors, are all common, and the control circuit 20 can obtain an output voltage Vout with any resistance ratio by turning on only one of the semiconductor switches (for example, S1). Even with this configuration, the same effects as those of the above-described embodiment can be obtained. Here, the configuration has been described in which the semiconductor switches S1 to S3 are connected to the common connection nodes N4 to N6 of the multiple voltage-dividing resistors R2 to R5, but this is not limiting, and another semiconductor switch may be connected between the first node N1 and the third node N3.

[0031] (Other embodiments) The present disclosure is not limited to the above-described embodiment, and for example, the following modifications or extensions are possible. The bias circuit is not limited to the current source 10. A plurality of second buried Zener diodes ZD2 may be connected in series.

[0032] The present disclosure is not limited to the inventions set forth in the claims, but also includes the following disclosure contents. [1] a bias circuit (10); a first buried Zener diode (ZD1) biased by the bias circuit in a direction from a cathode connected to the first node to an anode connected to the ground node; a second buried Zener diode (ZD2) biased by the bias circuit in a direction from an anode connected to the second node to a cathode connected to the ground node; a resistive voltage dividing circuit (11; 211) in which a voltage dividing resistor is connected between the first node and the second node; a voltage based on the voltage dividing resistor of the resistive voltage dividing circuit is output; a characteristic compensation circuit that compensates for the temperature characteristic of the output voltage by weighting and adding the voltage applied to the first buried Zener diode and the voltage applied to the second buried Zener diode using the resistive voltage divider circuit;

[0033] [2] The resistive voltage dividing circuit (11) is configured by a circuit having a plurality of voltage dividing resistors connected in series, The characteristic compensation circuit of [1], wherein the output voltage is a voltage divided by the plurality of voltage dividing resistors.

[0034] [3] The resistive voltage divider circuit (211) is a circuit comprising a plurality of voltage dividing resistors (R2 to R5) connected in series, and a plurality of semiconductor switches (S1 to S3) whose input terminals are connected in parallel to a common connection node of the plurality of voltage dividing resistors and whose output terminals are connected in common, and is a characteristic compensation circuit of [1] or [2] that outputs a voltage divided by the plurality of voltage dividing resistors through the input terminals and output terminals of the semiconductor switches.

[0035] [4] The characteristic compensation circuit according to any one of [1] to [3], wherein the first buried Zener diode and the second buried Zener diode have the same layout.

[0036] [5] The characteristic compensation circuit according to any one of [1] to [4], wherein the first buried Zener diode is disposed adjacent to the second buried Zener diode.

[0037] [6] The semiconductor switch is composed of one or more MOS transistors with one or more control terminals, and can switch between open and short between the input terminal and the output terminal depending on the voltage applied to the control terminal [3] or a characteristic compensation circuit [4] or [5] that cites [3].

[0038] Although the present disclosure has been described with reference to the embodiments as described above, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0039] In the drawing, 10 denotes a current source (bias circuit), ZD1 denotes a first buried Zener diode, ZD2 denotes a second buried Zener diode, 11 and 211 denote resistive voltage dividing circuits, R0 to R5 denote voltage dividing resistors, and S0 to S3 denote semiconductor switches.

Claims

1. A bias circuit (10); a first buried Zener diode (ZD1) biased by the bias circuit in a direction from a cathode connected to the first node to an anode connected to the ground node; a second buried Zener diode (ZD2) biased by the bias circuit in a direction from an anode connected to the second node to a cathode connected to the ground node; a resistive voltage dividing circuit (11; 211) in which a voltage dividing resistor is connected between the first node and the second node, a voltage based on the voltage dividing resistor of the resistive voltage dividing circuit is output; a characteristic compensation circuit that compensates for the temperature characteristic of the output voltage by weighting and adding the voltage applied to the first buried Zener diode and the voltage applied to the second buried Zener diode using the resistive voltage divider circuit;

2. The resistive voltage dividing circuit (11) is configured by a circuit having a plurality of voltage dividing resistors connected in series, 2. The characteristic compensation circuit according to claim 1, wherein the output voltage is a voltage divided by the plurality of voltage dividing resistors.

3. The resistance voltage divider circuit (211) is a circuit comprising a plurality of voltage dividing resistors (R2 to R5) connected in series, and a plurality of semiconductor switches (S1 to S3) whose input terminals are connected in parallel to a common connection node of the plurality of voltage dividing resistors and whose output terminals are connected in common, and the characteristic compensation circuit according to claim 1 outputs a voltage divided by the plurality of voltage dividing resistors through the input terminals and output terminals of the semiconductor switches.

4. 4. The characteristic compensation circuit according to claim 1, wherein the first buried Zener diode and the second buried Zener diode have the same layout.

5. 4. The characteristic compensation circuit according to claim 1, wherein the first buried Zener diode is disposed adjacent to the second buried Zener diode.

6. 4. The characteristic compensation circuit according to claim 3, wherein the semiconductor switch is configured by one or more MOS transistors having one or more control terminals, and can switch between open and short between the input terminal and the output terminal in accordance with the voltage applied to the control terminal.

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