Power supply device and memory system

Abstract

To provide a power supply device whose convenience can be improved.SOLUTION: A power supply device according to one embodiment of the present invention includes: a power supply terminal to which a first voltage is supplied from the outside; one or more step-down circuits that generate a second voltage supplied to a memory device; first and second connection lines that are arranged in parallel with each other and individually connect between the power supply terminal and the step-down circuit; a first switch element that is placed between the power supply terminal and the step-down circuit on the first connection line; a boost circuit that is placed on the second connection line and boosts the first voltage supplied from the power supply terminal; a first capacitive element that is placed between the boost circuit and the step-down circuit on the second connection line; a second switch element that is placed between the boost circuit and the first capacitive element on the second connection line; and a third switch element that is placed between the first capacitive element and the step-down circuit on the second connection line.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power supply unit that generates a voltage to be supplied to a memory device, and to a memory system that includes such a power supply unit and a memory device. [Background technology]

[0002] BACKGROUND ART Various memory systems have been proposed that include a memory device such as a flash memory and a power supply unit (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6299443 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for improved convenience in such memory systems, etc. It is desirable to provide a power supply device and a memory system that can improve convenience. [Means for solving the problem]

[0005] A power supply device according to one embodiment of the present invention is a device that generates a voltage to be supplied to a memory device, and includes: a power supply terminal to which a first voltage is supplied from outside; one or more step-down circuits that generate a second voltage to be supplied to the memory device; first and second connection lines arranged in parallel with each other and individually connecting between the power supply terminal and the step-down circuits; a first switch element arranged on the first connection line between the power supply terminal and the step-down circuit; a boost circuit arranged on the second connection line that boosts the first voltage supplied from the power supply terminal; a first capacitance element arranged on the second connection line between the step-up circuit and the step-down circuit; a second switch element arranged on the second connection line between the step-up circuit and the first capacitance element; and a third switch element arranged on the second connection line between the first capacitance element and the step-down circuit.

[0006] A memory system according to one embodiment of the present invention includes the power supply apparatus according to the embodiment of the present invention and the memory device. [Effects of the Invention]

[0007] According to the power supply device and memory system according to an embodiment of the present invention, it is possible to improve convenience. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing an example of a schematic configuration of a memory system according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing a schematic configuration of a memory system according to a comparative example. [Figure 3] FIG. 3 is a timing diagram illustrating an example of the operation of the memory system shown in FIG. [Figure 4] FIG. 4 is a circuit diagram showing an example of an operating state during normal operation in FIG. [Figure 5] FIG. 5 is a circuit diagram showing an example of an operating state when the power supply in FIG. 3 is shut off. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The description will be made in the following order: 1. Embodiment (Application to a memory system including a flash memory and a power supply unit) 2. Variations

[0010] <1. Embodiment> [composition] 1 is a circuit diagram showing an example of the schematic configuration of a memory system (memory system 4) according to an embodiment of the present invention. This memory system 4 is a system (flash memory system) that is applied to a memory device (flash memory device) such as a flash memory 21 described below. As shown in FIG. 1, the memory system 4 includes a power supply device 1, a flash memory 21, a memory controller 22, and a host I / F (interface) 3.

[0011] (Flash Memory 21, etc.) The flash memory 21 is a nonvolatile memory that stores (memorizes) data supplied from the outside (host) via a host I / F 3 (described later), as indicated by the arrow in Fig. 1. The memory controller 22 is a controller that writes data supplied from the host via the host I / F 3 to the flash memory 21 (write operation) and reads data stored in the flash memory 21 (read operation), as indicated by the arrow in Fig. 1.

[0012] The signal FBSY transmitted from the flash memory 21 to the memory controller 22 indicates whether the flash memory 21 is capable of accepting commands from the memory controller 22. Specifically, when FBSY="H (High)", the flash memory 21 is capable of accepting commands from the memory controller 22 (the flash memory 21 is accessible from the memory controller 22). On the other hand, when FBSY="L (Low)", the flash memory 21 is not capable of accepting commands from the memory controller 22 (the flash memory 21 is not accessible from the memory controller 22: Busy state). In such a Busy state, data received from the memory controller 22 is being written to cells in the flash memory 21 (write period). If the power is interrupted at this time (when the externally supplied voltage V1, described below, drops below a predetermined threshold), the data in the flash memory 21 is likely to be destroyed.

[0013] Here, the above-mentioned flash memory 21 and memory controller 22 each correspond to a specific example of a "memory device" in the present invention.

[0014] The host I / F 3 is an interface for data transfer between the memory system 4 (flash memory 21 and memory controller 22) and the host. In the case of an SSD (Solid State Drive) standard, examples of such a host I / F 3 include SATA (Serial Advanced Technology Attachment), PATA (Parallel Advanced Technology Attachment), and PCIe (Peripheral Component Interconnect-Express).

[0015] (Power supply 1) The power supply device 1 is a device that generates voltages (voltages V2a to V2c, which will be described later) to be supplied to the above-mentioned memory devices (flash memory 21 and memory controller 22). As shown in Fig. 1, the power supply device 1 includes a power supply terminal Tin, connection lines L1 and L2, a voltage boost circuit 11, multiple (three) voltage drop circuits 12a to 12c, a NOT (logical negation) circuit 131, an AND (logical product) circuit 132, voltage detection circuits 14a and 14b, switch elements SW1 to SW3, capacitors C1 and C2, and dummy resistors Ra to Re.

[0016] Here, the connection line L1 corresponds to a specific example of a "first connection line" in the present invention, and the connection line L2 corresponds to a specific example of a "second connection line" in the present invention. The voltage detection circuit 14a corresponds to a specific example of a "voltage detection circuit" in the present invention. The switch element SW1 corresponds to a specific example of a "first switch element" in the present invention, the switch element SW2 corresponds to a specific example of a "second switch element" in the present invention, and the switch element SW3 corresponds to a specific example of a "third switch element" in the present invention. The capacitor C1 corresponds to a specific example of a "first capacitance element" in the present invention, and the capacitor C2 corresponds to a specific example of a "second capacitance element" in the present invention.

[0017] 1, the power supply terminal Tin is a terminal to which a voltage V1 (host supply voltage) is supplied from the outside (host) of the memory system 4. Note that this voltage V1 is, for example, 3.3V.

[0018] The connection lines L1 and L2 are arranged in parallel with each other and individually connect the power supply terminal Tin to the step-down circuits 12a to 12c (described later). Specifically, as shown in Fig. 1, the connection line L1 is connected from the power supply terminal Tin to the step-down circuits 12a to 12c via the connection point P1, the switch element SW1, and the connection point P3, respectively, in that order. On the other hand, the connection line L2 is connected from the power supply terminal Tin to the step-down circuits 12a to 12c via the connection point P1, the boost circuit 11, the switch element SW2, the connection point P2, the switch element SW3, and the connection point P3, respectively, in that order.

[0019] The boost circuit 11 is disposed on the connection line L2 as described above, and is a circuit that boosts the voltage V1 (e.g., 3.3 V) supplied from the power supply terminal Tin and outputs the boosted voltage V2 (boosted voltage: e.g., 5 V). This voltage V2 is a voltage for power supply backup when the power supply is shut off (when the voltage V1 drops below a predetermined threshold), which will be described later, and is stored as an electric charge in a capacitor C1, which will be described later.

[0020] As shown in FIG. 1, the step-down circuits 12a to 12c are circuits that step down the voltage VL supplied from the connection line L1 or the connection line L2 via the connection point P3, thereby generating voltages V2a to V2c (step-down voltages) that are supplied to the flash memory 21 and the memory controller 22. Specifically, the step-down circuit 12a steps down the voltage VL to generate voltage V2a, and supplies this voltage to the flash memory 21 and the memory controller 22, respectively. The step-down circuit 12b steps down the voltage VL to generate voltage V2b, and supplies this voltage to the memory controller 22, respectively. The step-down circuit 12c steps down the voltage VL to generate voltage V2c, and supplies this voltage to the flash memory 21 and the memory controller 22, respectively. In the example of FIG. 1, the values of the voltages V2a to V2c satisfy the magnitude relationship V2a≧V2b≧V2c. In this manner, in this embodiment, the voltages V2a to V2c output from the plurality of step-down circuits 12a to 12c have different voltage values that are suited to the memory devices (flash memory 21 and memory controller 22).

[0021] Here, the above voltage V1 corresponds to a specific example of a "first voltage" in the present invention, and the voltages V2a to V2c each correspond to a specific example of a "second voltage" in the present invention.

[0022] As shown in FIG. 1, the voltage detection circuit 14a detects the voltage V1 supplied from the power supply terminal Tin via the connection point P1. Furthermore, as will be described in detail later, the voltage detection circuit 14a outputs a signal V1_EN (="L" or "H") according to the magnitude of the detected voltage V1 (according to the magnitude relationship between the voltage V1 and a predetermined threshold voltage Vth). When the signal V1_EN="L", the switch elements SW1 and SW2 (described later) are each set to the OFF state (disconnected state), the switch element SW3 (described later) is set to the ON state (connected state), and the boost circuit 11 is set to the stopped state. On the other hand, when the signal V1_EN="H", the switch elements SW1 and SW2 are each set to the ON state, the switch element SW3 is set to the OFF state, and the boost circuit 11 is set to the operating state. By setting the ON / OFF states of the switch elements SW1 to SW3 in this manner, the power supply path (power supply routes Rp1 and Rp2 (described later)) within the power supply device 1 is controlled.

[0023] 1, the voltage detection circuit 14b is a circuit that detects the voltage V2a output from the step-down circuit 12a. Furthermore, this voltage detection circuit 14b outputs a signal FWP (="L" or "H") depending on the magnitude of the detected voltage V2a. When this signal FWP="L", a data write operation to the flash memory 21 is prohibited, and when the signal FWP="H", a data write operation to the flash memory 21 is permitted (write prohibition is lifted).

[0024] The NOT circuit 131 is a circuit that outputs a signal (inverted signal) V2_EN (="H" or "L") that is the logical inversion of the signal V1_EN (="L" or "H") output from the voltage detection circuit 14a. That is, when the signal V1_EN="L", the signal V2_EN="H", and when the signal V1_EN="H", the signal V2_EN="L". The signal V2_EN generated in this manner is supplied to the switch element SW3 (see FIG. 1).

[0025] 1, the AND circuit 132 is a circuit that outputs a signal POR, which is a logical product (AND) signal of the signal V1_EN output from the voltage detection circuit 14a and the signal FWP output from the voltage detection circuit 14b, to the memory controller 22. When this signal POR="L", the operation of the memory controller 22 is stopped, and when the signal POR="H", the operation of the memory controller 22 is permitted (the operation stop is released).

[0026] As shown in FIG. 1, the switch element SW1 is disposed on the connection line L1 between the power supply terminal Tin and the step-down circuits 12a to 12c (between the connection points P1 and P3). The switch element SW1 is set to an ON or OFF state by a signal V1_EN output from the voltage detection circuit 14a. The switch element SW2 is disposed on the connection line L2 between the step-up circuit 11 and the capacitor C1 (between the step-up circuit 11 and the connection point P2). The switch element SW2 is set to an ON or OFF state by a signal V1_EN output from the voltage detection circuit 14a. The switch element SW3 is disposed on the connection line L2 between the capacitor C1 and the step-down circuits 12a to 12c (between the connection points P2 and P3). The switch element SW3 is set to an ON or OFF state by a signal V2_EN output from the NOT circuit 131.

[0027] Each of these switch elements SW1 to SW3 is configured using a switch element having a backflow prevention function.

[0028] As shown in FIG. 1, capacitor C1 is a capacitive element (large-capacity capacitor) arranged on connection line L2 between voltage step-up circuit 11 and voltage step-down circuits 12a to 12c. Specifically, one end of capacitor C1 is connected to connection point P2, and the other end of capacitor C1 is connected to ground. This capacitor C1 is a backup capacitor for supplying charge to flash memory 21 and memory controller 22 in the event of a power outage (when voltage V1 drops below a predetermined threshold), as will be described in detail later. As will be described in detail later, when such a power outage occurs, charge is supplied from capacitor C1 to voltage step-down circuits 12a to 12c, thereby ensuring power supply when flash memory 21 is in a busy state and preventing corruption of data in flash memory 21.

[0029] 1, the capacitor C2 is a capacitance element (auxiliary capacitor) disposed on the connection line L2 between the switch element SW3 and the step-down circuits 12a to 12c. Specifically, one end of the capacitor C2 is connected to the connection point P3, and the other end of the capacitor C2 is connected to ground. The capacitor C2 is a capacitor that compensates for a predetermined delay time when the above-mentioned power supply interruption occurs (the delay time when the switch elements SW1 and SW3 are switched from the on state to the off state, and when the switch element SW2 is switched from the off state to the on state).

[0030] Each of the dummy resistors Ra to Re is a resistive element for discharging excess charge. As shown in FIG. 1, the dummy resistor Ra is arranged between the output line of the voltage V2a from the step-down circuit 12a and the ground. Similarly, the dummy resistor Rb is arranged between the output line of the voltage V2b from the step-down circuit 12b and the ground, and the dummy resistor Rc is arranged between the output line of the voltage V2c from the step-down circuit 12c and the ground. Furthermore, the dummy resistor Rd is arranged between the input line (connection point P3) of each of the step-down circuits 12a to 12c and the ground, and the dummy resistor Re is arranged in parallel with the capacitor C1 between the connection point P2 and the ground.

[0031] [Operation, Actions and Effects] Next, with reference to FIGS. 2 to 5 in addition to FIG. 1, an example of operation of the present embodiment (an example of operation of the memory system 4 and the power supply device 1) will be described in detail in comparison with a comparative example.

[0032] (A. Comparative example) Fig. 2 is a circuit diagram showing the schematic configuration of a memory system (memory system 104) according to a comparative example. Memory system 104 of this comparative example corresponds to memory system 4 of the present embodiment shown in Fig. 1, except that power supply device 101 is provided instead of power supply device 1. As shown in Fig. 2, power supply device 101 of this comparative example includes a power supply terminal Tin, four step-down circuits 91a to 91d, a voltage detection circuit 92, a discharge circuit 93, a step-up circuit 94, voltage detection circuits 95 and 97, a level shift circuit 96, a switch element SW, a capacitor C, diodes D1 and D2, and dummy resistors Ra to Rd.

[0033] In this power supply device 101, the voltage V1 supplied to the power supply terminal Tin is detected by a voltage detection circuit 95, and the voltage is level-shifted by a level shift circuit 96 before being supplied as a signal POR to the switch element SW, the boost circuit 94, and the memory controller 22. The voltage (V1-Vt) obtained from the power supply terminal Tin via a diode D1 is detected by a voltage detection circuit 92, and a signal EN output from the voltage detection circuit 92 is supplied to a discharge circuit 93 and the step-down circuits 91a-91d. The step-down circuits 91a-91d step down the voltage (V1-Vt) and output the voltages V2a(VC), V2b, V2c, and V2d to the flash memory 21 and the memory controller 22. The voltage detection circuit 97 detects the voltage V2a(VC), and supplies a signal FWP to the flash memory 21. The voltage V2a(VC) is also supplied to the step-up circuit 94 and the level shift circuit 96. The voltage V3 (boosted voltage) output from the boost circuit 94 is supplied to the capacitor C and also to the discharge circuit 93 via the switch element SW and the diode D2. The dummy resistors Ra to Rd are respectively arranged between the output lines of the step-down circuits 91a to 91d and the ground.

[0034] In the power supply device 101 configured as described above, voltage V1 supplied from the outside (host) to power supply terminal Tin is used to generate voltages required by the flash memory 21 and memory controller 22 in each of the step-down circuits 91a to 91d. In addition, voltage V2a (VC) output from step-down circuit 91a is boosted by step-up circuit 94, and the boosted voltage V3 is used to charge capacitor C.

[0035] In this power supply device 101, when a drop in voltage V1 (the occurrence of a power cutoff) is detected by the voltage detection circuit 95, a signal POR output from the level shift circuit 96 stops the operation of the memory controller 22. Furthermore, this signal POR switches the switch element SW from an off state to an on state, and the charge stored in the capacitor C (large-capacity capacitor) is supplied to each of the step-down circuits 91a-91d via the switch element SW and diode D2, thereby ensuring the power supply voltage (voltage VL). In this way, the power supply voltage (voltage VL) of each of the step-down circuits 91a-91d is ensured during the busy state of the flash memory 21 (the period during which data is written to the cells), and therefore the data written during the busy state is guaranteed even when the power is cut off.

[0036] However, in the power supply device 101 (memory system 104) of this comparative example, as shown in Figure 2, the voltage V1 supplied from the host drops by the forward voltage Vt of the backflow prevention diode D1 (dropping from V1 to (V1-Vt)). Therefore, for example, if the voltage V1 is a relatively low voltage (low voltage system), the voltage margin becomes small (it becomes difficult to ensure the voltage margin), making it difficult to use the voltage V1 of such a low voltage system and potentially reducing convenience.

[0037] (B. Operation Example of This Embodiment) In contrast to this, in the memory system 4 of this embodiment, the circuit configuration shown in FIG. 1 is configured to perform, for example, the following operations.

[0038] FIG. 3 is a timing diagram illustrating an example of operation of the memory system 4 shown in FIG. 1 (operation examples during normal operation, "Power_Down," and "Power_UP," which will be described later). Specifically, FIG. 3(A) shows the voltage VA indicating the detection state of voltage V1 by the voltage detection circuit 14a, and FIGS. 3(B) to 3(D) show the on / off states of the switch elements SW1 to SW3, respectively. FIG. 3(E) collectively illustrates the aforementioned voltages V1, V2, V2a to V2c, and VL. FIGS. 3(F), 3(G), and 3(I) show the aforementioned signals FWP, POR, and FBSY, respectively, and FIG. 3(H) shows the data (DATA) supplied to the flash memory 21. The horizontal axis in FIG. 3 represents time t, and timings t1 to t6 along this time t are shown in FIG. 3.

[0039] FIG. 4 is a circuit diagram showing an example of the operating state during normal operation in FIG. 3 (when voltage V1≧threshold voltage Vth (the period from timing t2 to t5 in FIG. 3)). Meanwhile, FIG. 5 is a circuit diagram showing an example of the operating state during power-off in FIG. 3 (when voltage V1<threshold voltage Vth (the period from timing t5 onward in FIG. 3)). The period up to timing t2 shown in FIG. 3 corresponds to the above-mentioned "Power_UP" state (voltage V1<threshold voltage Vth). In addition, in FIGS. 4 and 5, the power supply routes Rp1 and Rp2, which will be described below, are indicated by arrows.

[0040] (B-1. During normal operation) First, during the normal operation shown in FIG. 3, the memory system 4 of this embodiment operates as shown in FIG. 4, for example.

[0041] That is, during this normal operation, the voltage V1 supplied to the power supply terminal Tin is equal to or higher than a predetermined threshold voltage Vth (e.g., 2.7 V) (V1≧Vth: see FIGS. 3A and 3E), so the signal V1_EN="H" and the signal V2_EN="L". Therefore, the voltage detection circuit 14a sets the switch elements SW1 and SW2 to the ON state and sets the switch element SW3 to the OFF state (see FIGS. 3B to 3D). Also, during this normal operation, the boost circuit 11 is set to an operating state. Then, as shown in FIG. 4, the power supply device 1 is provided with the following two power supply routes Rp1 and Rp2.

[0042] In the power supply route Rp1, based on the voltage V1 (VL) supplied from the power supply terminal Tin to the step-down circuits 12a to 12c via the connection line L1, voltages V2a to V2c are supplied from the step-down circuits 12a to 12c to the flash memory 21 and the memory controller 22, respectively (see FIG. 4). That is, during normal operation, the power supply route Rp1 is used to supply the voltages V2a to V2c to the flash memory 21 and the memory controller 22, respectively. Furthermore, during normal operation, the power supply route Rp1 is used to supply the voltage V1 (VL) to the step-down circuits 12a to 12c as well as to the capacitor C2, thereby charging the capacitor C2 (see FIG. 4).

[0043] On the other hand, in the power supply route Rp2, the voltage V1 is supplied from the power supply terminal Tin to the boost circuit 11 via the connection line L2, and the voltage V2 (boosted voltage) output from the boost circuit 11 is supplied to the capacitor C1 via the switch element SW2 (see FIG. 4). That is, during normal operation, the capacitor C1 is charged based on the voltage V2 using the power supply route Rp2. Note that during normal operation, as described above, the switch element SW3 is set to the off state, and therefore power is not supplied to the step-down circuits 12a to 12c using the power supply route Rp2 (see FIG. 4).

[0044] Also, during this normal operation, the voltage V2a is monitored by the voltage detection circuit 14b. When it is confirmed that the voltage is sufficient as the power supply to the flash memory 21, the signal FWP = "H" (see Fig. 3(F)). Then, since the signal V1_EN = "H" as described above, the signal POR output from the AND circuit 132 becomes "H" (see Fig. 3(G)), and the memory controller 22 is set to the operating state. Therefore, for example, as shown in Figs. 3(H) and 3(I), based on the data (DATA: Write Data_A, Write Data_B) supplied to the flash memory 21, data is written into the cells in the flash memory 21 during the period when the signal FBSY = "L".

[0045] Note that the above power supply route Rp1 corresponds to a specific example of the "first power supply route" in the present invention, and the power supply route Rp2 corresponds to a specific example of the "second power supply route" in the present invention.

[0046] (B-2. When power is cut off) Also, when the power is cut off as shown in Fig. 3, in the memory system 4 of the present embodiment, operations are performed as shown in Fig. 5, for example.

[0047] That is, when the power is cut off, since the voltage V1 supplied to the power supply terminal Tin is less than the above-mentioned threshold voltage Vth (V1 < Vth: see Figs. 3(A) and 3(E)), the signals V1_EN = "L" and V2_EN = "H" are obtained. Therefore, the voltage detection circuit 14a sets the switch elements SW1 and SW2 to the off state respectively, and sets the switch element SW3 to the on state (see Figs. 3(B) to 3(D)). Also, when the power is cut off, the operation of the boost circuit 11 is set to the stop state, and since the above-mentioned signal V1_EN = "L", the signal POR output from the AND circuit 132 becomes "L" (see Fig. 3(G)), and the operation of the memory controller 22 is also set to the stop state.

[0048] Then, when the power supply is cut off, the following operation is performed using the power supply route Rp2 described above, as shown in Fig. 5. That is, the power stored in capacitors C1 and C2 is supplied to step-down circuits 12a to 12c, respectively, and voltages V2a to V2c are supplied from step-down circuits 12a to 12c to flash memory 21 and memory controller 22, respectively, based on the stored power (see Fig. 5). That is, when the power supply is cut off, voltages V2a to V2c are supplied to flash memory 21 and memory controller 22, respectively, using this power supply route Rp2. Note that, when the power supply is cut off, as described above, switch elements SW1 and SW2 are each set to the off state, so that the power stored in capacitors C1 and C2 does not escape to the host side via power supply terminal Tin.

[0049] Thus, in this embodiment, even when the power is cut off ("Power_Down"), the following occurs during the busy period of the flash memory 21 (the period during which data is written to the cells): That is, each power supply voltage (the voltages V2a to V2c described above) is maintained for a certain period (see timings t5 to t6 in FIGS. 3(E) and 3(I)). Note that the capacitor C1 (large-capacity capacitor) has a capacity that can maintain a voltage for a period longer than the busy period of the flash memory 21 (the period during which data is written to the cells). Therefore, even if the power is cut off as described above during the period during which data is written to the cells in the flash memory 21, the data is guaranteed.

[0050] In the comparative example described above, for example, the voltage V1 (=5.0 V), the voltage detected by the voltage detection circuit 95 (=4.0 V), and the voltage V2a (=3.3 V) are used. The difference between these voltages is relatively large, resulting in the following: That is, in this comparative example, the Schottky diode (diode D1) suppresses the backflow of charge and compensates for the switching time of the switch element SW. In contrast, in the present embodiment, for example, the voltage V1 (=3.3 V), the voltage detected by the voltage detection circuit 14a (=2.8 V), and the voltage V2a (=3.0 V) are used. The difference between these voltages is relatively small, resulting in the following: That is, the Schottky diodes used in the comparative example are replaced with switch elements (switch elements SW1 to SW3) that do not have a forward voltage loss. Furthermore, the delay in the switching time of each switch element SW1 to SW3 is addressed by providing a capacitor C2 (auxiliary capacitor) as described above.

[0051] As mentioned above, when the power is cut off, the operation of the memory controller 22 (such as internal operations and communication with the flash memory 21) is stopped. At this time, the load on the voltage V1 is suddenly reduced, which may cause the value of the voltage V1 to rise momentarily. In this case, the voltage detection circuit 14a may react to the instantaneous rise in the voltage V1 and switch the signal POR from "L" to "H," which may cause malfunction of the switch elements SW1 to SW3. Therefore, when the voltage detection circuit 14a detects the voltage V1, for example, hysteresis may be provided with respect to the threshold voltage Vth. Specifically, for example, when the voltage V1 rises, the voltage detection circuit 14a switches the signal V1_EN from "L" to "H" if the voltage V1 exceeds the threshold voltage Vth1=2.75V. On the other hand, when the voltage V1 drops, the voltage detection circuit 14a switches the signal V1_EN from "H" to "L" when the voltage V1 falls below the threshold voltage Vth2 of 2.65 V. In this way, when hysteresis is provided for the threshold voltage Vth, it is possible to prevent the above-mentioned malfunction.

[0052] (C. Actions and Effects) In this way, in the present embodiment, the switch elements SW1 to SW3, the boost circuit 11, and the capacitor C1 are respectively arranged on the connection lines L1 and L2 that individually connect the power supply terminal Tin and the step-down circuits 12a to 12c in the above-described configuration. As a result, when power is supplied from the power supply terminal Tin to the step-down circuits 12a to 12c via the connection line L1 or the connection line L2 based on the voltage V1 supplied, the following occurs. That is, in the present embodiment, unlike the case of the comparative example described above, since a decrease in the voltage V1 due to the forward voltage of the reverse current prevention diode does not occur, for example, even when the voltage V1 is relatively low (low voltage system), it becomes easier to secure a voltage margin during power supply. As a result, in the present embodiment, it is possible to improve the convenience of the power supply device 1 and the memory system 4 as compared with such a comparative example.

[0053] Also, in the present embodiment, the two power supply routes Rp1 and Rp2 described above are provided respectively. Then, during normal operation (when V1≥Vth), the power supply route Rp1 is used, and during power-off (when V1<Vth), the power supply route Rp2 is used to supply the voltages V2a to V2c to the flash memory 21 and the memory controller 22. In this way, by switching the power supply route (power supply route Rp1 or power supply route Rp2) used according to the magnitude relationship between the voltage V1 and the threshold voltage Vth, the above-described power margin is effectively secured, and as a result, it is possible to further improve the convenience.

[0054] Furthermore, in the present embodiment, since a capacitor C2 (auxiliary capacitor) is provided between the switch element SW3 and the step-down circuits 12a to 12c on the connection line L2, the following occurs. That is, as described above, this capacitor C2 assists a predetermined delay time when power-off occurs (the delay time when the switch elements SW1 and SW3 are switched from the on state to the off state and the switch element SW2 is switched from the off state to the on state). As a result, in the present embodiment, it is possible to further improve the convenience.

[0055] Additionally, in this embodiment, a plurality of step-down circuits 12a to 12c are provided, and the voltages V2a to V2c output from these step-down circuits 12a to 12c are different from one another and are adapted to the flash memory 21 and the memory controller 22. This facilitates appropriate operation in the flash memory 21 and the memory controller 22, thereby further improving convenience.

[0056] <2. Modifications> Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments and various modifications are possible.

[0057] For example, in the above embodiment, specific circuit configurations of the memory system and power supply device are given and explained, but the present invention is not limited to the examples of the above embodiment, and other circuit configurations may be used, for example.

[0058] Specifically, in the above embodiment, an example in which a plurality of (three) step-down circuits are provided in the power supply device has been described, but this is not limiting. For example, the power supply device may be provided with only one step-down circuit, or with two or four or more step-down circuits.

[0059] In the above embodiment, an example has been described in which two capacitors C1 and C2 (first and second capacitance elements) are provided in the power supply device, but the present invention is not limited to this example. For example, the power supply device may be provided with only capacitor C1 (first capacitance element) and not with capacitor C2 (second capacitance element).

[0060] Furthermore, in the above embodiment, as a specific example of a "memory device" in the present invention, an example in which a flash memory and a memory controller are each provided in a memory system has been described, but the present invention is not limited to this example. For example, the memory system may be provided with only one of the flash memory and the memory controller.

[0061] In the above embodiment, the voltage detection circuit 14a outputs the signal V1_EN (="L" or "H") according to the magnitude of the detected voltage V1 (according to the magnitude relationship between the voltage V1 and a predetermined threshold voltage Vth), and the switch elements SW1 to SW3 are set by this signal V1_EN. However, the present invention is not limited to this example. That is, for example, two voltage detection circuits for detecting the voltage V1 may be provided, and control may be performed such that one voltage detection circuit sets the switch elements SW1 and SW3, and the other voltage detection circuit 14a sets the switch element SW2. Furthermore, for example, the threshold voltages Vth in these two voltage detection circuits may have different values.

[0062] In addition, in the above embodiment, specific examples of operation of the memory system and power supply device are given and described, but the operation examples are not limited to those described in the above embodiment, and other operation examples may also be used.

[0063] Furthermore, in the above embodiment, an example of a memory system (flash memory system) applied to a memory device (flash memory device) such as a flash memory has been described, but the present invention is not limited to this example. That is, for example, the memory system of the present invention may be applied to memory devices other than such flash memory devices.

[0064] Furthermore, the configuration examples described so far may be applied in any combination.

[0065] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0066] The present invention can also be configured as follows. (1) 1. An apparatus for generating a voltage to supply to a memory device, comprising: a power supply terminal to which a first voltage is supplied from an external source; one or more step-down circuits that generate a second voltage supplied to the memory device; first and second connection lines arranged in parallel to each other and individually connecting the power supply terminal and the step-down circuit; a first switch element disposed on the first connection line between the power supply terminal and the step-down circuit; a boost circuit disposed on the second connection line and configured to boost the first voltage supplied from the power supply terminal; a first capacitance element disposed on the second connection line between the voltage step-up circuit and the voltage step-down circuit; a second switch element disposed on the second connection line between the boost circuit and the first capacitance element; a third switch element disposed on the second connection line between the first capacitance element and the step-down circuit; A power supply unit comprising: (2) a first power supply route, in which the second voltage is supplied from the step-down circuit to the memory device based on the first voltage supplied to the step-down circuit via the first connection line; a second power supply route through which the second voltage is supplied from the step-down circuit to the memory device based on power stored in the first capacitance element, the power being supplied to the step-down circuit via the second connection line; Each is provided The power supply device according to (1) above. (3) When the first voltage is equal to or greater than a threshold voltage, the second voltage is supplied to the memory device using the first power supply route, and When the first voltage is less than the threshold voltage, the second voltage is supplied to the memory device using the second power supply route. The power supply device according to (2) above. (4) A second capacitance element is further provided on the second connection line between the third switch element and the step-down circuit. The power supply device according to any one of (1) to (3) above. (5) further comprising a voltage detection circuit that detects the first voltage; The voltage detection circuit when the first voltage is equal to or higher than a threshold voltage, the first and second switch elements are set to an ON state and the third switch element is set to an OFF state, thereby controlling so that the first voltage is supplied to each of the step-down circuit and the second capacitance element, and a boosted voltage output from the step-up circuit is supplied to the first capacitance element; When the first voltage is less than the threshold voltage, the first and second switch elements are set to an OFF state and the third switch element is set to an ON state, thereby controlling so that the power stored in the first and second capacitance elements is supplied to the step-down circuit. The power supply device according to (4) above. (6) A plurality of the step-down circuits are provided, The second voltages output from the plurality of step-down circuits have different voltage values suited to the memory device. The power supply device according to any one of (1) to (5) above. (7) The memory device is at least one of a flash memory and a memory controller. The power supply device according to any one of (1) to (6) above. (8) The power supply device according to any one of (1) to (7) above; the memory device; A memory system comprising: [Explanation of symbols]

[0067] 1...power supply device, 11...boost circuit, 12a to 12c...step-down circuit, 131...NOT circuit, 132...AND circuit, 14a, 14b...voltage detection circuit, 21...flash memory, 22...memory controller, 3...host I / F, 4...memory system, Tin...power supply terminal, SW1 to SW3...switching elements, C1, C2...capacitors, Ra to Re...dummy resistors, P1 to P3...connection points, L1, L2...connection lines, Rp1, Rp2...power supply route, V1, V2, V2a to V2c, VL, VA...voltage, Vth...threshold voltage, V1_EN, V2_EN, FWP, POR, FBSY...signal, t...time, t1 to t6...timing

Claims

1. 1. An apparatus for generating a voltage to supply to a memory device, comprising: a power supply terminal to which a first voltage is supplied from an external source; one or more step-down circuits that generate a second voltage supplied to the memory device; first and second connection lines arranged in parallel to each other and individually connecting the power supply terminal and the step-down circuit; a first switch element disposed on the first connection line between the power supply terminal and the step-down circuit; a boost circuit disposed on the second connection line and configured to boost the first voltage supplied from the power supply terminal; a first capacitance element disposed on the second connection line between the voltage step-up circuit and the voltage step-down circuit; a second switch element disposed on the second connection line between the boost circuit and the first capacitance element; a third switch element disposed on the second connection line between the first capacitance element and the step-down circuit; A power supply unit comprising:

2. a first power supply route, in which the second voltage is supplied from the step-down circuit to the memory device based on the first voltage supplied to the step-down circuit via the first connection line; a second power supply route through which the second voltage is supplied from the step-down circuit to the memory device based on power stored in the first capacitance element, the power being supplied to the step-down circuit via the second connection line; Each is provided The power supply device of claim 1 .

3. When the first voltage is equal to or greater than a threshold voltage, the second voltage is supplied to the memory device using the first power supply route, and When the first voltage is less than the threshold voltage, the second voltage is supplied to the memory device using the second power supply route. The power supply device according to claim 2 .

4. A second capacitance element is further provided on the second connection line between the third switch element and the step-down circuit. The power supply device according to any one of claims 1 to 3.

5. further comprising a voltage detection circuit that detects the first voltage; The voltage detection circuit when the first voltage is equal to or higher than a threshold voltage, the first and second switch elements are set to an ON state and the third switch element is set to an OFF state, thereby controlling so that the first voltage is supplied to each of the step-down circuit and the second capacitance element, and a boosted voltage output from the step-up circuit is supplied to the first capacitance element; When the first voltage is less than the threshold voltage, the first and second switch elements are set to an OFF state and the third switch element is set to an ON state, thereby controlling so that the power stored in the first and second capacitance elements is supplied to the step-down circuit.

5. The power supply device according to claim 4.

6. A plurality of the step-down circuits are provided, The second voltages output from the plurality of step-down circuits have different voltage values suited to the memory device. The power supply device according to any one of claims 1 to 3.

7. The memory device is at least one of a flash memory and a memory controller. The power supply device according to any one of claims 1 to 3.

8. The power supply device according to any one of claims 1 to 3; the memory device; A memory system comprising:

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