Display device

Abstract

To provide a semiconductor device typified by a display device with higher display quality by suppressing parasitic capacitance generated in a connection portion between a semiconductor layer and an electrode and preventing an influence of voltage drop due to wiring resistance and defective signal writing or poor gradation in a pixel.SOLUTION: A semiconductor device can have such a structure that: a wire with low resistance is connected to a thin film transistor including a source electrode including metal with high oxygen affinity, a drain electrode, and an oxide semiconductor layer with suppressed impurity concentration. The thin film transistor including the oxide semiconductor can be sealed by being surrounded by an insulation film.SELECTED DRAWING: Figure 39

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device using a thin film transistor (hereinafter also referred to as a TFT).

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. Thin film transistors (also called TFTs) are Thin-film transistors are used in electronic devices such as ICs and electro-optical devices. It is widely used in devices, and development is particularly being accelerated as a switching element for image display devices. .

[0004] Thin film transistors are mainly made of semiconductors such as amorphous silicon or polycrystalline silicon. Amorphous silicon TFTs are made using conductive materials. Although the cost is low, it can accommodate large-area glass substrates, while polycrystalline silicon is used. Although the TFT has high field effect mobility, it requires a crystallization process such as laser annealing. However, it has the characteristic that it is not necessarily suited to enlarging the area of the glass substrate.

[0005] In contrast, a TFT is fabricated using an oxide semiconductor as the semiconductor material, and the TFT is used as an electronic device. For example, the technology of using niobium as a semiconductor material in semiconductor devices such as silicon dioxide is attracting attention. TFTs were fabricated using lead and In-Ga-Zn-O oxide semiconductors, and used as switches for image display devices. Techniques used for etching elements and the like are disclosed in Patent Documents 1 and 2.

[0006] A TFT in which a channel formation region (also called a channel region) is formed in an oxide semiconductor is The oxide semiconductor film has a higher field-effect mobility than the TFTs using silicon. It is possible to form a film at temperatures below 300°C using methods such as sputtering. The manufacturing process is simpler than that of TFTs using capacitors.

[0007] Using such oxide semiconductors, TFTs are formed on glass substrates, plastic substrates, etc. Liquid crystal display, electroluminescent display (also called EL display) It is also expected to be applied to display devices such as electronic paper.

[0008] In addition, in an active matrix semiconductor device such as a liquid crystal display device, the screen size There is a trend toward larger screen sizes of 60 inches or more, and even larger screen sizes of 120 inches or more. The development is also taking into consideration the screen size. In addition, the screen resolution is also high definition. Image quality (HD, 1366 x 768), Full HD image quality (FHD, 1920 x 1080 ) and the trend is toward higher definition, with resolutions of 3840 x 2048 or 4096 x 2180. The development of so-called 4K digital cinema display devices is also being rushed.

[0009] As display devices become more highly precise, the number of pixels required increases dramatically. The write time per pixel is shortened, and thin film transistors have fast operating characteristics and a large on-state current. On the other hand, due to the recent energy shortage problem, power consumption is being reduced. Therefore, thin film transistors with low off-state current are also required. Therefore, there is a demand for devices that suppress unnecessary leakage current.

[0010] Furthermore, larger screen sizes and higher definitions tend to increase the wiring resistance within the display unit. Increased wiring resistance can cause delays in signal transmission to the end of the signal line and voltage drops in the power line. As a result, display quality deteriorates, resulting in uneven display and poor gradation, and increased power consumption. It ends up like this.

[0011] In order to suppress the increase in wiring resistance, a technology has been developed to form a low-resistance wiring layer using copper (Cu). This has been investigated (see, for example, Patent Documents 3 and 4). [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2004-133422 [Patent Document 4] Japanese Patent Application Laid-Open No. 2004-163901 Summary of the Invention [Problem to be solved by the invention]

[0013] The parasitic capacitance between the source electrode and the semiconductor layer, and between the drain electrode and the semiconductor layer of a thin film transistor Since parasitic resistance reduces the on-current, technologies to reduce parasitic resistance are being investigated. In a thin film transistor having an oxide semiconductor layer, high resistance is generated at the connection interface between the oxide semiconductor and the metal. However, there is a problem in that a harmful oxide film is formed.

[0014] Furthermore, technologies to suppress the off-state current of thin film transistors are being investigated. In a thin film transistor having a layer, carriers remaining in the oxide semiconductor layer are In addition, there is a problem that impurities may be introduced into the thin film transistor from the outside over a long period of use. This can cause problems such as the transistor characteristics changing, such as the threshold voltage.

[0015] In addition, in order to prevent an increase in wiring resistance, a technique for forming a low-resistance wiring layer using copper (Cu) is used. However, Cu is easily diffused in semiconductors and silicon oxide, and This may cause the device to operate unstable and significantly reduce the yield.

[0016] One embodiment of the present invention is to prevent the influence of a voltage drop due to wiring resistance, a signal writing failure to a pixel, and a gradation failure. and to provide a semiconductor device, such as a display device, with better display quality. This is one of the challenges.

[0017] Another object of one embodiment of the present invention is to achieve high-speed operation of a semiconductor device.

[0018] Another object of one embodiment of the present invention is to achieve power saving in a semiconductor device.

[0019] Another embodiment of the present invention is a thin film transistor which operates stably and a semiconductor device including the thin film transistor. One of the goals is to provide a place for

[0020] Another object of one embodiment of the present invention is to realize a semiconductor device with excellent productivity. . [Means for solving the problem]

[0021] In order to solve the above problems, the present invention provides a source electrode and a drain electrode containing a metal with a strong oxygen affinity. a thin film transistor in which an in-electrode is connected to an oxide semiconductor layer in which the impurity concentration is suppressed; A semiconductor device can be constructed by connecting a thin film transistor using an oxide semiconductor. The transistor can be sealed by surrounding it with an insulating film.

[0022] That is, one embodiment of the present invention disclosed in this specification is a method for forming a first insulating layer containing silicon nitride on a substrate. The gate wiring is formed of a first conductive layer having low resistance on the first insulating layer, and the first conductive layer a gate electrode layer made of an insulating layer, and a second insulating layer containing silicon nitride on the gate electrode layer; a third insulating layer containing silicon oxide on the second insulating layer; and an island-shaped oxide layer on the third insulating layer. A semiconductor layer is provided, and the semiconductor layer functions as a source electrode and a drain electrode on the island-shaped oxide semiconductor layer. a second conductive layer, and a fourth insulating layer containing silicon oxide over the second conductive layer and the oxide semiconductor layer; a fifth insulating layer containing silicon nitride on the fourth insulating layer; Through an opening in the layer, a layer that functions as either a source electrode or a drain electrode is a third conductive layer electrically contacting the second conductive layer, and a fifth insulating layer a sixth insulating layer including silicon nitride covering the fourth insulating layer, the fifth insulating layer and the sixth insulating layer; The second electrode, which functions as the other of the source electrode and the drain electrode, is exposed through an opening provided in the layer. a fourth conductive layer electrically contacting the second conductive layer, the second conductive layer being a conductive material having oxygen affinity; The semiconductor device is an electrical layer.

[0023] Furthermore, one embodiment of the present invention disclosed in this specification is a semiconductor device including a conductive layer containing Cu on the first insulating layer. The gate wiring is formed of a conductive layer containing a high-melting point metal that covers the conductive layer, The semiconductor device has the gate electrode layer comprising:

[0024] In one embodiment of the present invention disclosed in this specification, the first conductive layer and the second conductive layer are The semiconductor device has a storage capacitor portion sandwiching the second insulating layer and the third insulating layer.

[0025] Furthermore, one embodiment of the present invention disclosed in this specification is a method for manufacturing a semiconductor device using any one of indium, gallium, and zinc. The semiconductor device includes an oxide semiconductor layer including any one of the above.

[0026] In one embodiment of the present invention disclosed in this specification, the second conductive layer may be formed of any one of W, Ta, Mo, and T. Contains at least one element selected from the group consisting of I, Cr, Al, Zr, and Ca. The semiconductor device includes:

[0027] Another embodiment of the present invention disclosed in this specification is a semiconductor device including a semiconductor substrate having a first insulating layer including silicon nitride formed on the substrate. A gate wiring and a gate electrode layer are formed on the first insulating layer using a low-resistance first conductive layer. forming a second insulating layer containing silicon nitride on the gate electrode layer; and forming an oxide film on the second insulating layer. A third insulating layer containing silicon is formed, and the substrate temperature is heated to 100°C or more and 600°C or less. forming an oxide semiconductor layer on the third insulating layer; and forming a conductive film having oxygen affinity on the oxide semiconductor layer. The second conductive layer is formed using the layer to function as a source electrode and a drain electrode. A fourth insulating layer containing silicon oxide is formed on the insulating layer and the oxide semiconductor layer, and a nitride film is formed on the fourth insulating layer. A fifth insulating layer containing silicon is formed, and an opening is formed in the fourth insulating layer and the fifth insulating layer. A second conductive layer that functions as either a source or drain electrode through an opening. a third conductive layer electrically contacting the fifth insulating layer, and a silicon nitride film covering the third conductive layer and the fifth insulating layer. forming a sixth insulating layer including a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer; and a second conductive layer that functions as the other of the source electrode and the drain electrode through the opening. A fourth conductive layer electrically connected to the first conductive layer is formed in accordance with the present invention.

[0028] In this specification, the term "gate" refers to a gate electrode and a part or all of a gate wiring. The gate wiring is a wiring that connects the gate electrode of at least one transistor with another electrode or This refers to a wiring for electrically connecting to another wiring, and is used, for example, for scanning in a display device. The lines are also included in the gate wiring.

[0029] The source refers to a source region, a source electrode, and part or all of a source wiring. The source region is a region of the semiconductor layer whose resistivity is equal to or less than a certain value. The source wiring is a conductive layer that is connected to the source region. A transistor for electrically connecting the source electrode of one transistor to another electrode or another wiring. For example, when a signal line in a display device is electrically connected to a source electrode, In this case, the source wiring also includes the signal line.

[0030] The drain refers to the drain region, drain electrode, and part or all of the drain wiring. The drain region is a region of the semiconductor layer whose resistivity is equal to or less than a certain value. The drain electrode is the conductive layer connected to the drain region. The drain electrode of at least one transistor is electrically connected to another electrode or another wiring. For example, a signal line in a display device is connected to a drain electrode. When electrically connected, the drain wiring also includes the signal line.

[0031] In addition, in this document (specification, claims, drawings, etc.), The source and drain are interchangeable depending on the transistor structure and operating conditions. It is difficult to determine whether the deviation is the source or the drain. In the specification, claims, drawings, etc., One arbitrarily selected terminal is referred to as either the source or the drain, and the other terminal is referred to as the source or the drain. and the other end of the drain.

[0032] In this specification, the term "light emitting device" refers to an image display device, a light emitting device, or a light It also refers to a light source (including lighting devices) that has a connector, such as an FPC (Flexible Printed Circuit). le printed circuit) or TAB (Tape Automate d Bonding) tape or TCP (Tape Carrier Packaging) e) is attached to the module, and the printed wiring board is attached to the end of the TAB tape or TCP. A module with a COG (Chip On Glass) on a substrate on which a light emitting element is formed. s) All modules in which ICs (integrated circuits) are directly mounted using this method are also included in the light-emitting device. Let's say. [Effects of the Invention]

[0033] To provide a semiconductor device capable of high speed operation and a semiconductor device with low power consumption. In addition, the present invention provides a semiconductor device that operates stably and is highly reliable. [Brief explanation of the drawings]

[0034] [Figure 1] 1A and 1B illustrate a structure of a display device according to an embodiment. [Figure 2] 1A to 1C illustrate an example of the configuration of a pixel of a display device according to an embodiment. [Figure 3] 1A to 1C illustrate an example of the configuration of a pixel of a display device according to an embodiment. [Figure 4] 2A to 2C illustrate a manufacturing process of a pixel portion of a display device according to an embodiment; [Figure 5] 2A to 2C illustrate a manufacturing process of a pixel portion of a display device according to an embodiment; [Figure 6] 1A and 1B are diagrams illustrating a gray-tone mask and a half-tone mask. [Figure 7] 2A to 2C illustrate a manufacturing process of a pixel portion of a display device according to an embodiment; [Figure 8] 1A and 1B are diagrams illustrating an inverter circuit according to an embodiment; [Figure 9] 1A and 1B are diagrams illustrating a protection circuit according to an embodiment; [Figure 10] 1A and 1B are diagrams illustrating a protection circuit according to an embodiment; [Figure 11] 5A and 5B are diagrams illustrating a connection portion according to an embodiment. [Figure 12] 3A to 3C are diagrams illustrating a terminal portion according to an embodiment. [Figure 13] 3A to 3C are diagrams illustrating a terminal portion according to an embodiment. [Figure 14] 1A to 1C illustrate a semiconductor device. [Figure 15] 1A to 1C illustrate a semiconductor device. [Figure 16] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 17] 1A to 1C illustrate a semiconductor device. [Figure 18] FIG. 1 is a block diagram illustrating a display device. [Figure 19] 1A and 1B are a diagram illustrating a configuration of a signal line driver circuit and a timing chart illustrating an operation thereof; [Figure 20] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 21] 1A and 1B are a circuit diagram and a timing chart illustrating the operation of a shift register; [Figure 22] 1A to 1C illustrate a semiconductor device. [Figure 23] 1A to 1C illustrate a semiconductor device. [Figure 24] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 25] FIG. 1 is an external view showing an example of an electronic book. [Figure 26] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 27] FIG. 1 is an external view showing an example of a gaming machine. [Figure 28] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 29] 1A to 1C illustrate a semiconductor device. [Figure 30] 1A to 1C illustrate a semiconductor device. [Figure 31] 1A to 1C illustrate a semiconductor device. [Figure 32] 1A to 1C illustrate a semiconductor device. [Figure 33] 1A to 1C illustrate a semiconductor device. [Figure 34] 1A to 1C illustrate a semiconductor device. [Figure 35] 1A to 1C illustrate a semiconductor device. [Figure 36] 1A to 1C illustrate a semiconductor device. [Figure 37] 1A to 1C illustrate a semiconductor device. [Figure 38] 1A to 1C illustrate an example of the configuration of a pixel of a display device according to an embodiment. [Figure 39] 1A to 1C illustrate an example of the configuration of a pixel of a display device according to an embodiment. [Figure 40] 2A to 2C illustrate a manufacturing process of a pixel portion of a display device according to an embodiment; [Figure 41] A diagram showing the crystal structure of metal and oxygen in IGZO. [Figure 42] 1A and 1B are diagrams showing a structural model of metal atoms and oxygen atoms near the interface between a tungsten film and an oxide semiconductor film. [Figure 43]1A and 1B are diagrams showing a structural model of a metal atom and an oxygen atom near an interface between a molybdenum film and an oxide semiconductor film; [Figure 44] 1A and 1B are diagrams showing a structural model of metal atoms and oxygen atoms near the interface between a titanium film and an oxide semiconductor film. [Figure 45] FIG. 1 is a diagram showing the crystal structure of titanium dioxide having a rutile structure. [Figure 46] Density of states diagram of titanium dioxide with a rutile structure. [Figure 47] Density of states diagram of oxygen-deficient titanium dioxide. [Figure 48] Density of states diagram of titanium monoxide. [Figure 49] FIG. 1 is a band diagram illustrating one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0035] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to denote the same parts or parts having similar functions. A repeated explanation will be omitted.

[0036] (Embodiment 1) In this embodiment, a display device in which a semiconductor element using an oxide semiconductor is formed in a pixel portion and its periphery is used. One embodiment of the display device will be described with reference to FIGS. 1(A) and 1(B).

[0037] The structure of the display device 30 is shown in FIG. 1(A). The display device 30 has a gate terminal portion 7 on a substrate 100. and a source terminal portion 8. The display device 30 also has a gate wiring 20_1 and a gate Gate wiring (20_1 to 20_n (n is a natural number)) including wiring 20_2, and The source wirings (60_1 to 60_m) including the source wiring 60_1 and the source wiring 60_2 (however, In addition, the pixel region 94 of the display device 30 is provided with a pixel 93 are arranged in a matrix. Each pixel 93 is connected to at least one pair of gate wirings and is connected to the source wiring.

[0038] The display device 30 also includes common wiring 44, common wiring 45, common wiring 46, and common wiring 65. In addition, for example, the common wiring 45 is connected to the common wiring 65 via a connection portion 95. The common wirings are electrically connected to each other and are at the same potential.

[0039] The common wiring 44, the common wiring 45, the common wiring 46, and the common wiring 65 are connected to a terminal 71, a terminal The common wiring is connected to the terminal 75, the terminal 81, and the terminal 85, respectively. It has a common connection part 96 that can be electrically connected to the substrate.

[0040] In addition, the gate signal line terminals (70_1 to 70_i (where i is a natural number)) of the gate terminal section 7 are The gate driver circuit 91 (hereinafter also referred to as the scanning line driver circuit) is connected to the gate driver circuit 91 via the protection circuit 97. The terminal 74 is connected to the gate drive circuit 91. This connects the gate wiring ( 20_1 to 20_n (where n is a natural number) are connected to the common wiring 65 via a protection circuit 97. It is being done.

[0041] In addition, the source signal line terminals (80_1 to 80_k (where k is a natural number)) of the source terminal section 8 are The signal line driver circuit 92 is connected to the source driver circuit 92 (hereinafter also referred to as a signal line driver circuit) and is connected to the source driver circuit 92 via a protection circuit 97. The terminal 84 is connected to the common wiring 44. The terminal 84 is connected to the source driving circuit 92. This connects an external power supply (not shown) to the source driver circuit 92. 60_1 to 60_m (where m is a natural number) are connected to the common wiring 45 via a protection circuit 97. It is being done.

[0042] The gate driver circuit and the source driver circuit use the thin film transistor disclosed in this specification, It can be formed simultaneously with the pixel region. Either one or both of them is formed on a separately prepared substrate by forming a single crystal semiconductor film or a polycrystalline semiconductor film. and mounted using COG, wire bonding, or TAB methods. That's fine.

[0043] An example of an equivalent circuit applicable to the pixel 93 is shown in FIG. The circuit is an example in which a liquid crystal element is used as a display element in the pixel 93.

[0044] Next, an example of the pixel configuration of the display device shown in FIG. 1 will be described with reference to FIG. 2. 2(B) and 2(C) are top views showing the planar structure of the pixel. 2(A) and 2(B). The dashed lines correspond to the cross sections A1-A2, B1-B2, and C1-C2 in FIG. 2(B). The chain line D1-D2 in FIG. 2(A) corresponds to the cross section D1-D2 in FIG. 2(C). Correct.

[0045] The cross sections A1-A2 and D1-D2 show the area of the thin film transistor 250 used in the pixel section. The layer structure is shown, and the thin film transistor 250 is an embodiment of a bottom gate structure.

[0046] In the cross sections A1-A2 and D1-D2, an insulating layer 201 provided on a substrate 200 and 2, a gate wiring 202 provided on the insulating layer 201 and a gate electrode 203 provided on the gate wiring 202. a gate wiring 203, an insulating layer 204 provided on the gate wiring 203, and a thin film transistor 206 provided on the insulating layer 204. A semiconductor layer 205 is formed on the semiconductor layer 205, and a pair of electrodes 207a and an electrode 207b, and an insulating layer 207a provided on the electrode 207a, the electrode 207b, and the semiconductor layer 205. 08, and the source wiring 201 which is in contact with the electrode 207a through an opening provided in the insulating layer 208. 9, a source wiring 210 provided on the source wiring 209, and a The insulating layer 211 is formed on the insulating layer 208, and the electrode 211 is formed on the insulating layer 208 through openings formed in the insulating layer 211 and the insulating layer 208. and an electrode 212 in contact with 207b.

[0047] The cross section B1-B2 shows the stacked structure of the storage capacitor (also called Cs capacitor). In B1-B2, an insulating layer 201 is formed on a substrate 200, and a storage capacitor wiring 2 is formed on the insulating layer 201. 13, a storage capacitor wiring 214 on the storage capacitor wiring 213, and an insulating layer 14 on the storage capacitor wiring 214. 204, an electrode 207b on the insulating layer 204, an insulating layer 208 on the electrode 207b, and an insulating layer An insulating layer 211 is provided on the insulating layer 208, and an electrode 212 is provided on the insulating layer 211.

[0048] The cross section C1-C2 shows the stacked structure at the intersection of the gate wiring and the source wiring. In the cross section C1-C2, an insulating layer 201 is formed on a substrate 200, and a gate insulating layer 202 is formed on the insulating layer 201. A gate wiring 202, a gate wiring 203 on the gate wiring 202, and an insulating layer on the gate wiring 203. An insulating layer 208 is formed on the insulating layer 204, and a source wiring 209 is formed on the insulating layer 208. , a source wiring 210 is formed on the source wiring 209, and an insulating layer 211 is formed on the source wiring 210. At the wiring intersection, a semiconductor layer is formed between the insulating layer 204 and the insulating layer 208. The structure may be such that:

[0049] One embodiment of the present invention is not limited to the pixel configuration shown in FIG. The element configuration is illustrated in Fig. 3. The thin film transistor 251 illustrated in Fig. 3 has a bottom gate structure. This is one mode of a thin film transistor and can be called a channel protective type.

[0050] The thin film transistor 251 includes an insulating layer 201 provided on a substrate 200 and a a gate wiring 202 provided on the substrate; and a gate wiring 203 provided on the gate wiring 202. An insulating layer 204 provided on the gate wiring 203 and a semiconductor layer provided on the insulating layer 204 205, a channel protection layer 225 provided on the semiconductor layer 205, and a channel protection layer 22 A pair of electrodes 207a and 207b are provided on the substrate 5. , an insulating layer 208 provided on the semiconductor layer 205, and an opening provided in the insulating layer 208. A source wiring 209 contacting the electrode 207a via a a source wiring 210, an insulating layer 211 provided on the source wiring 210, and an electrode 212 that contacts the electrode 207b through an opening provided in the insulating layer 208; .

[0051] 2B or 3 is shown in FIG. 39. The film transistor 252 is formed by an insulating layer 201 provided on the substrate 200 and a thin film transistor 252 provided on the insulating layer 201. The insulating layer 204 is formed on the gate wiring 203. 204 and a pair of electrodes 20 7a and electrode 207b, and a layer provided on the electrode 207a, the electrode 207b, and the semiconductor layer 205. The insulating layer 208 is connected to the electrode 207a through an opening formed in the insulating layer 208. a source wiring 209, an insulating layer 211 provided on the source wiring 209, and an electrode 212 that contacts the electrode 207b through an opening provided in the insulating layer 208; .

[0052] The wiring material may be selected appropriately depending on the performance required of the display device. Even if only the source wiring 209, which requires higher transmission characteristics than the source wiring, is made of Cu, good.

[0053] A conductive film containing Al as a main component is used for the gate wiring 203 as a wiring material with low electrical resistance. In this case, the gate electrode of the thin film transistor is connected to the gate wiring 203 as shown in FIG. It can be configured as follows.

[0054] The storage capacitor of the pixel exemplified in this embodiment is a storage capacitor wiring formed in the same layer as the gate wiring. The insulating layer 204 is formed between the electrode 212 and the source line 207b. Compared to 10, the electrode 207b is closer to the storage capacitor wiring in the thickness direction, It is suitable for forming

[0055] The gate wiring 202 and the source wiring 210 are formed of a conductive material containing Cu. The increase in resistance can be prevented. A conductive material containing an element having a melting point higher than that of Cu, such as r, is used to form a layer in contact with the gate wiring 202 and By forming the gate wiring 202 so as to cover the entire surface, migration of the gate wiring 202 is suppressed, and the semiconductor device In addition, the reliability of the device can be improved by using the conductive layer containing Cu. The insulating layer is an insulating layer containing silicon nitride, and the gate wiring 202 containing Cu is sandwiched between the insulating layers. Alternatively, wrapping can prevent Cu diffusion.

[0056] Also, the gate wiring 202 overlaps with the semiconductor layer 205 in which the channel of the thin film transistor is formed. The gate wiring 203 is arranged so as not to be folded, and a part of the gate wiring 203 that is in contact with the gate wiring 202 is extended. The gate electrode is formed by overlapping with the semiconductor layer 205. , and further prevents Cu contained in the gate wiring 202 from affecting the thin film transistor. It is possible.

[0057] In addition, at least an insulating layer 204 and an insulating layer 205 are formed between the gate wiring and the source wiring at the wiring intersection. By sandwiching the layer 208, the distance between the wirings in the film thickness direction can be greatly increased. As a result, the parasitic capacitance at the wiring intersection can be reduced.

[0058] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0059] (Embodiment 2) In this embodiment mode, a manufacturing process of a pixel portion of the display device described in Embodiment Mode 1 will be described with reference to FIGS. 4 and 5. Note that the cross sections A1-A2 and B1- The cross section A1-A2, B1-B2, the cross section C1-C2, and the cross section D1-D2 are the same as those in FIG. 10A and 10B are cross-sectional views of the areas indicated by the dashed lines B2, C1-C2, and D1-D2.

[0060] First, an insulating layer 201 containing silicon nitride is formed on a substrate 200 to a thickness of preferably 50 nm to 300 nm. The substrate 200 is preferably a glass substrate, a ceramic substrate, or a glass substrate. In addition to the ceramic substrate, a plastic with heat resistance that can withstand the processing temperature of this manufacturing process is also used. In addition, when the substrate does not need to be transparent, a stainless steel alloy can be used. A substrate made of a metal such as SiO 2 or the like, on the surface of which an insulating film is provided, may also be used. For example, barium borosilicate glass, aluminoborosilicate glass or aluminosilicate glass It is recommended to use a non-alkali glass substrate such as quartz or sapphire. The substrate 200 can be a 3rd generation (550 mm x 650 mm) 3.5th generation (600mm x 720mm or 620mm x 750mm), 4th generation (6 80mm x 880mm, or 730mm x 920mm, 5th generation (1100mm x 1 300mm), 6th generation (1500mm x 1850mm), 7th generation (1870mm x 2 200mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2 800mm, 2450mm x 3050mm, 10th generation (2950mm x 3400mm) In this embodiment, the substrate 200 is made of aluminoboron. Silicate glass is used.

[0061] The insulating layer 201 can be formed by using a silicon nitride film or a silicon nitride oxide film as a single layer or a stacked layer. In this specification, silicon nitride oxide refers to a material having a higher content of nitrogen than oxygen. Preferably, the content of fluorine is high, as measured by RBS and HFS. The composition range is 5 to 30 atomic % of oxygen, 20 to 55 atomic % of nitrogen, and 25 to 35 atomic % of silicon. The insulating layer 201 is formed by sputtering. A ring method, a CVD method, a coating method, a printing method, or the like can be used as appropriate. A silicon nitride film having a thickness of 100 nm is formed as the insulating layer 201. The film contains phosphorus (P). It may be doped with fluorine (B).

[0062] Next, a 1000 volt film is formed on the insulating layer 201 by sputtering, vacuum deposition, or plating. Cu is deposited to a thickness of 00 nm or more and 500 nm or less, preferably 200 nm or more and 300 nm or less. A conductive film containing the compound is formed on the conductive film by a photolithography method, an ink-jet method, or the like. A mask is formed, and the conductive film is etched using the mask to form the gate wiring 202 and the protective film. The capacitance wiring 213 can be formed. In order to improve the adhesion of the gate wiring 202, Between the insulating layer 201 and the gate wiring 202, a metal such as W, Ta, Mo, Ti, or Cr is formed. layer, or an alloy layer combining these, or a nitride or oxide thereof is also good.

[0063] Note that when a resist mask is formed by the inkjet method, a photomask is not used. This reduces manufacturing costs. In addition, conductive nanopaste such as copper can be applied by the inkjet method. By discharging onto a plate and baking, the gate wiring 202 and the storage capacitor wiring 213 are formed inexpensively. It is possible.

[0064] In this embodiment, a Cu film having a thickness of 250 nm is formed on the insulating layer 201. The Cu film is selectively etched using a resist mask formed in the lithography process. A port wiring 202 is formed (see FIG. 4(A)).

[0065] Next, W, Ta, or the like is deposited on the gate wiring 202 by sputtering, vacuum deposition, or the like. Elements with a higher melting point than Cu, such as Mo, Ti, and Cr, or a combination of the above elements The alloy or the like is used as a conductive film, and the thickness is 5 nm to 200 nm, preferably 10 nm to 100 nm. The conductive film is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. In this embodiment, a tungsten single layer structure having a thickness of 200 nm can be used. A conductive film is formed.

[0066] Next, a mask is formed on the conductive film by photolithography, ink jetting, or the like. The conductive film is then etched using the mask to form the gate wiring 203 and the storage capacitor wiring 204. In this embodiment, the second photolithography step can form the The conductive film is selectively etched using a resist mask to form the gate wiring 203 and the storage capacitor. Then, the wiring 214 is formed (see FIG. 4(B)).

[0067] The gate wiring and storage capacitor wiring are made of a conductive material containing elements with a higher melting point than Cu. By applying such a structure, the migration of the layer containing Cu can be prevented. This can suppress the dispersion and improve the reliability of the semiconductor device.

[0068] Next, an insulating layer 204 functioning as a gate insulating layer is formed on the gate wiring 203 to a thickness of 50 nm or more. The thickness is preferably 800 nm or less, and more preferably 100 nm or more and 600 nm or less. In this embodiment, the insulating layer 204 is formed by stacking the insulating layer 204b on the insulating layer 204a. The edge layer 204a is a silicon nitride layer (SiN y (y>0) The insulating layer 204b is a silicon oxide layer (SiO x (x>0) on the insulating layer 204a The gate insulating layer 204 is formed to a thickness of 100 nm.

[0069] The insulating layer 204 also functions as a protective layer. The insulating layer is an insulating layer containing silicon nitride, and a conductive layer containing Cu is sandwiched between the insulating layers, or By wrapping the material, Cu diffusion can be prevented.

[0070] Next, a semiconductor layer 205 is formed on the insulating layer 204. Conductor films are In-Ga-Zn-O, In-Sn-Zn-O, and In-Al-Zn-O , Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In- Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O series, Zn-O The oxide semiconductor film is formed by oxidizing a rare gas (typically, argon) In an atmosphere, an oxygen atmosphere, or a mixture of a rare gas (typically argon) and oxygen The film can be formed by sputtering.

[0071] When using the sputtering method, the silicon dioxide (SiO2) content is 2% by weight or more and 10% by weight or less. The oxide semiconductor film is deposited using a target containing SiO x (X>0 ) can suppress crystallization. This is particularly effective when heat treatment is performed in a later step.

[0072] Here, a target for forming an oxide semiconductor film containing In, Ga, and Zn (composition ratio: In2O3:Ga2O3:ZnO=1:1:1 [mol%], or In:Ga:Zn =1:1:0.5[at.%]), the distance between the substrate and the target was 100 mm, Pressure 0.6 Pa, direct current (DC) power 0.5 kW, oxygen (oxygen flow rate 100%) atmosphere When a pulsed direct current (DC) power supply is used, the powdery material (pulse) generated during film formation is This is preferable because it reduces the amount of particles (also called "tickles" or "dust") and makes the film thickness distribution uniform. In this form, the oxide semiconductor film is formed using an In-Ga-Zn-O-based oxide semiconductor film forming target. An In-Ga-Zn-O based film is formed by sputtering using a nozzle.

[0073] The filling rate of the oxide semiconductor film forming target is 90% or more and 100% or less, preferably 90% or more. The filling rate is 5% or more and 99.9% or less. By using a target for oxide semiconductor film formation with a high filling rate, As a result, the formed oxide semiconductor film becomes a dense film.

[0074] Note that the thickness of the oxide semiconductor film is preferably 5 nm to 30 nm. The appropriate thickness varies depending on the semiconductor material, and the thickness may be selected appropriately depending on the material.

[0075] In this embodiment, the oxide semiconductor film is formed successively over the gate insulating layer 204. The multi-chamber sputtering equipment used in this ) target and a target for an oxide semiconductor film, The deposition chamber in which the target for the thin film is installed has a cryopump as an exhaust means. A turbomolecular pump is used instead of a cryopump, and the intake port of the turbomolecular pump is A cold trap may be provided to adsorb moisture and the like.

[0076] The deposition chamber evacuated using a cryopump contains, for example, hydrogen atoms and hydrogen atoms such as H2O. Compounds containing carbon atoms and compounds containing arsenic are exhausted. The concentration of impurities contained in the semiconductor film can be reduced.

[0077] The oxide semiconductor film is formed while the substrate is heated. The temperature is 00 to 600°C, preferably 200 to 400°C. By forming the oxide semiconductor film from the oxide semiconductor film, the impurity concentration in the formed oxide semiconductor film can be reduced. In addition, the heating temperature can be adjusted to control the composition ratio of the elements that make up the oxide semiconductor. For example, in the case of an oxide semiconductor containing zinc, the vapor pressure of zinc is Therefore, if the film is formed at a high temperature, the ratio of zinc contained in the formed semiconductor layer will decrease. Note that the sputtering conditions should be as gentle as possible so as not to damage the oxide semiconductor film. The conditions are peaceful.

[0078] The sputtering method uses RF sputtering, which uses a high frequency power supply, and DC sputtering. There are DC sputtering methods, and pulsed DC sputtering methods that apply a bias in a pulsed manner. The F sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal conductive films. It is used when forming a film.

[0079] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0080] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0081] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0082] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Reverse sputtering is performed to generate a mask, and dust adhering to the surface of the gate insulating layer 204 is removed. Reverse sputtering is a method of applying an electric current to the substrate side using an RF power source in an argon atmosphere. This method involves applying pressure to form plasma near the substrate to modify the surface. Instead of the atmosphere, nitrogen, helium, oxygen, etc. may be used.

[0083] Next, a mask is formed on the oxide semiconductor film by photolithography, an ink-jet method, or the like. The oxide semiconductor film is selectively etched using the mask to form island-shaped oxide semiconductors. In this embodiment, a resist layer 205 is formed by a third photolithography process. The oxide semiconductor film is selectively etched using a mask to form an island-shaped oxide semiconductor layer 20. 5 is formed (see Figure 4(C)).

[0084] Next, although not shown in FIGS. 2 to 5, the gate wiring 203 and the electrode 20 (to be described later) are connected. An opening (also called a contact hole) for connecting the electrode 7a or the electrode 207b is formed in the insulating layer. The insulating layer 204 is formed by photolithography or ink jet printing. A mask is formed by this, and the insulating layer 204 is selectively etched using the mask to form contacts. Here, a hole is formed in the resist mask formed in the fourth photolithography step. The insulating layer 204 is selectively etched using a mask to form contact holes.

[0085] The contact holes are formed by the fourth photolithography process. This may be performed after the formation of the silicon dioxide film and before the formation of the semiconductor layer 205.

[0086] Next, a conductive film is formed over the oxide semiconductor layer 205. The conductive film may be formed using a material selected from the group consisting of W, Ta, and Mo. , Ti, Cr, Al, or alloys of the above elements can be used. In addition, metal nitrides such as titanium nitride, tantalum nitride, and tungsten nitride are used as conductive films. The conductive film may have a stack of two or more layers.

[0087] When heat treatment is performed at 200 to 600°C, the conductive film must have heat resistance to withstand this heat treatment. For example, an aluminum alloy containing an element to prevent hillocks, It is preferable to use a conductive film laminated with a heat-resistant conductive film.

[0088] The conductive film in contact with the oxide semiconductor layer 205 is preferably made of a material containing a metal with high oxygen affinity.

[0089] Metals with high oxygen affinity include titanium (Ti), aluminum (Al), and manganese (M n), magnesium (Mg), zirconium, beryllium, or thorium It is preferable that the material be selected from a plurality of materials, and in this embodiment, a titanium film is used.

[0090] When an oxide semiconductor layer is formed in contact with a conductive film having high oxygen affinity, the carrier density near the interface The amount of the oxide semiconductor increases, a low-resistance region is formed, and the contact resistance between the oxide semiconductor and the conductive film can be reduced. This is because the conductive film with high oxygen affinity extracts oxygen from the oxide semiconductor layer. At the interface between the oxide semiconductor layer and the conductive film, a layer containing excess metal in the oxide semiconductor layer (also called a composite layer) is formed. This is due to the formation of either a thin film or an oxidized conductive film, or both. For example, in a configuration in which an In-Ga-Zn-O-based oxide semiconductor layer is in contact with a titanium film, A layer containing excess indium and a titanium oxide layer are formed near the interface between the oxide semiconductor layer and the titanium film. In addition, indium may be generated near the interface between the oxide semiconductor layer and the titanium film. In some cases, either an excess In-Ga-Zn-O layer or a titanium oxide layer may form. The layer with excess indium, which is deficient in oxygen from the oxide semiconductor layer of the system, has high electrical conductivity and is oxidized. This can reduce the contact resistance between the compound semiconductor layer and the conductive film.

[0091] Note that a conductive titanium oxide film may be used as the conductive film in contact with the oxide semiconductor layer. In this case, in a configuration in which an In-Ga-Zn-O-based oxide semiconductor layer and a titanium oxide film are in contact with each other, In this case, a layer containing excessive indium is generated near the interface between the oxide semiconductor layer and the titanium oxide film. This may occur.

[0092] The above-mentioned In-Ga-Zn-O oxide semiconductor film is used as the active layer of a thin film transistor. In the thin film transistor with a channel etch structure, the source electrode or the drain electrode In the vicinity of the interface between the metal film used as a gate electrode and the In-Ga-Zn-O-based oxide semiconductor film, The layer with a higher indium concentration than other regions (In-rich layer) and the titanium oxide film (TiO X The phenomenon of the formation of the nuclei 311 will be described in detail in the fourteenth embodiment.

[0093] The conductive film has a thickness of 100 nm to 500 nm, preferably 200 nm to 300 nm. The conductive film is formed by a method such as sputtering or vacuum evaporation (electron beam evaporation). ) or arc discharge ion plating method or spray method. Also, silver, gold, Conductive nanopaste such as copper is used by screen printing or inkjet printing. It may also be formed by extrusion and firing.

[0094] Next, a mask is formed on the conductive film by photolithography, ink jetting, or the like. The conductive film is then etched using the mask to form an electrode 207 that functions as a source electrode. In this embodiment, an electrode 207b serving as a drain electrode can be formed. First, a 200 nm thick Ti film was formed as a conductive film by sputtering, and then a fifth photolithography was performed. Using a resist mask formed in the lithography process, a conductive film is selected by dry etching. Then, electrodes 207a and 207b are formed by selectively etching.

[0095] In the fifth photolithography step, only the conductive film in contact with the oxide semiconductor layer is formed. Only the conductive film in contact with the oxide semiconductor layer is selectively removed. Therefore, an alkaline etchant is used, which is ammonia hydrogen peroxide (composition weight ratio: When hydrogen:ammonia:water=5:2:2) is used, the metal conductive film is selectively removed, and I The oxide semiconductor layer made of the n-Ga-Zn-O based oxide semiconductor can be left.

[0096] In addition, depending on the etching conditions, the oxide semiconductor layer In this case, the exposed areas of the source and drain electrode layers may be etched. The thickness of the oxide semiconductor layer in the sandwiched region (the region sandwiched between 207a and 207b) is The thickness of the oxide semiconductor layer in the region where the source electrode layer overlaps with the wiring 203, or the thickness of the drain electrode layer The thickness of the oxide semiconductor layer in the overlapping region is thinner than that in the overlapping region (see FIG. 4D).

[0097] Next, the insulating layer 208 is formed over the gate insulating layer 204 and the oxide semiconductor layer 205. The layer 208 is made up of water, hydrogen ions, and OH - It does not contain impurities such as The insulating layer 208 is formed using an inorganic insulating film that prevents the insulating layer 208 from being damaged. The source wiring is formed using an inorganic insulating film that suppresses migration of Cu-containing layers. In this embodiment, the insulating layer 208 is formed by stacking the insulating layer 208b on the insulating layer 208a. Complete.

[0098] An oxide insulating film is used for the insulating layer 208a in contact with the oxide semiconductor layer 205. 8a has a thickness of at least 1 nm, and is formed by sputtering or the like to an oxide insulating film. The method can be appropriately used to prevent the incorporation of impurities such as hydrogen. A silicon film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxide nitride film, or the like is used. It may be formed as a single layer or a multilayer.

[0099] The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower, and in this embodiment, it is set to 100° C. The silicon oxide film is formed by sputtering in a rare gas (typically argon) atmosphere. It is carried out under an atmosphere of air, oxygen, or a rare gas (typically argon) and oxygen. Note that the oxide insulating film formed by a sputtering method is particularly dense, and the thickness of the insulating film is It can be used as a single layer as a protective film to suppress the phenomenon of impurities diffusing into the substrate. In addition, phosphorus (P) or boron (B) doped targets are used to deposit phosphorus (P) into the oxide insulating film. ) and boron (B) can also be added.

[0100] In addition, a silicon oxide target or a silicon target can be used as the target, In particular, a silicon target is preferred. The silicon oxide film formed by sputtering has dangling bonds between silicon atoms or oxygen atoms (dangling bonds). It contains a lot of tungsten bonds.

[0101] Since the insulating layer 208a includes many dangling bonds, the impurities contained in the oxide semiconductor layer 205 The oxide semiconductor layer 205 is diffused into the insulating layer 208a through the interface between the oxide semiconductor layer 205 and the insulating layer 208a. Specifically, hydrogen atoms contained in the oxide semiconductor layer 205 and hydrogen atoms such as H2O are easily Compounds containing atoms and compounds containing carbon atoms are easily diffused and transferred to the insulating layer 208a. It is immobilized on the edge layer 208a.

[0102] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0103] At this stage, a region where the oxide semiconductor layer 205 and the oxide insulating layer 208a are in contact with each other is formed. The oxide semiconductor layer overlaps the gate electrode and is sandwiched between the gate insulating layer 204 and the insulating layer 208a. The region of the insulating layer 205 becomes a channel forming region. The insulating layer 208a serves as a channel protection layer. It functions as such.

[0104] The insulating layer 208b formed on the insulating layer 208a is an insulating film containing nitrogen. 08b is at least 1 nm thick, and the insulating film is formed by a method such as sputtering, using water or hydrogen. The film is formed by using a method that does not mix impurities such as silicon nitride and oxynitride. A silicon film, an aluminum nitride film, or the like is used. In this embodiment, RF sputtering is used. This is used to form the insulating layer 208b of a silicon nitride film.

[0105] In this embodiment, a silicon nitride film having a thickness of 400 nm is formed as the insulating layer 208b.

[0106] Next, an opening 216 (contact hole) for connecting the electrode 207a and the source wiring 209 is formed. A metal film (also referred to as a metal film) is formed on the insulating layer 208. A mask is formed by an ink jet method or the like, and the insulating layer 208 is selectively formed using the mask. In this embodiment, the sixth photolithography is performed to form contact holes. The insulating layer 208 is selectively etched using the resist mask formed in the etching process. Form a contact hole.

[0107] Next, in order to form the source wiring 209, a sputtering method, a vacuum deposition method, or the like is used. Conductive films with a higher melting point than Cu, such as W, Ta, Mo, Ti, and Cr, or those containing the above elements The combined alloy is used as a conductive film with a thickness of 5 nm to 200 nm, preferably 10 nm or more. It is formed to a thickness of 100 nm or less. In addition, tantalum nitride (T Titanium nitride (TiN) or titanium nitride (TiN) may be formed.

[0108] Next, a conductive film containing Cu is deposited on the substrate by sputtering, vacuum deposition, or plating. The thickness of the insulating film is 00 nm or more and 500 nm or less, preferably 200 nm or more and 300 nm or less. forming a mask on the conductive film by photolithography, ink-jet printing, or the like; The conductive film containing Cu and the conductive film for forming the source wiring 209 are etched using the mask. By this process, the source wiring 209 and the source wiring 210 can be formed.

[0109] In this embodiment, a conductive film for forming the source wiring 209 is made of titanium nitride having a thickness of 50 nm. A Cu film having a thickness of 250 nm is used as the conductive film for forming the source wiring 210. The conductive film is selectively etched using the resist mask formed in the seventh photolithography step. Then, etching is performed to form a source wiring 209 and a source wiring 210 (see FIG. 5(A)).

[0110] The source wiring is made of a layer containing Cu and a layer containing an element with a higher melting point than Cu. This makes it possible to suppress migration in the Cu-containing layer and improve the reliability of the semiconductor device. Furthermore, a layer containing an element having a melting point higher than that of Cu is also provided on the source wiring 210, and C A layer containing u may be sandwiched between layers containing an element having a melting point higher than that of Cu. Depending on the environment and conditions of use of the device, the source wiring may be formed only from a layer containing Cu. .

[0111] Next, the insulating layer 211 is formed to a thickness of 50 nm to 300 nm, preferably 100 nm to 200 nm. The insulating layer 211 is formed to a thickness of 100 nm or less. The insulating layer 211 is formed in the same manner as the insulating layer 201. In this embodiment, a silicon nitride film having a thickness of 10 nm is formed as the insulating layer 211. The insulating layer 211 also functions as a protective layer. The insulating layer to be placed is an insulating layer containing silicon nitride, and the conductive layer containing Cu is sandwiched between the insulating layers. By wrapping the material, Cu diffusion can be prevented (see FIG. 5(B)).

[0112] Next, a contact for connecting the electrode 207b to the electrode 212 that functions as a pixel electrode is Holes are formed in the insulating layer 211 and the insulating layer 208. Photolithography is performed on the insulating layer 211. A mask is formed by a dye method, an ink jet method, or the like, and the insulating layer 211 and The insulating layer 208 is selectively etched to form contact holes. The insulating layer 211 and the insulating layer 212 are formed using a resist mask formed in the eighth photolithography step. The insulating layer 208 is selectively etched to form a contact hole (opening 217). .

[0113] Next, a transparent conductive film is formed to a thickness of 30 nm by using a sputtering method, a vacuum deposition method, or the like. the conductive film is formed to a thickness of 50 nm or more and 200 nm or less, preferably 50 nm or more and 100 nm or less; A mask is formed on the substrate by photolithography or ink jetting, and the mask is The conductive film is etched using the etchant to form the electrode 212 that functions as a pixel electrode. Cut.

[0114] Examples of the light-transmitting conductive film include indium oxide containing tungsten oxide, tungsten oxide, and Indium zinc oxide containing stainless steel, indium oxide containing titanium oxide, titanium oxide Indium tin oxide (hereinafter referred to as ITO), indium zinc Conductive materials with transparency, such as lead oxide and indium tin oxide with silicon oxide added, are used. It can be used.

[0115] The light-transmitting conductive film may be formed by a conductive film containing a conductive polymer (also called a conductive polymer). The pixel electrode formed using the conductive composition can be formed by the sheet. Resistance is 10,000Ω / □ or less, and light transmittance at a wavelength of 550nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that:

[0116] In this embodiment, ITO is formed to a thickness of 80 nm as a light-transmitting conductive film. A light-transmitting conductive film is selected using a resist mask formed in a photolithography process. The electrode 212 that functions as a pixel electrode is formed by selectively etching the film (see FIG. 5(C)). .

[0117] Note that in this embodiment, the gate insulating layer 204 and the oxide semiconductor layer 205 are successively formed. The formed gate insulating layer 204 is exposed to the air, and then an oxide semiconductor layer 205 is formed. In this case, the gate insulating layer 204 may be formed in an inert gas atmosphere (nitrogen, helium, Neon, argon, etc.) and heat treatment (400°C or higher but below the distortion point of the substrate). By this heat treatment, the gate insulating layer 204 Impurities such as hydrogen and water contained in the gas can be removed.

[0118] The silicon oxide layer, the silicon nitride layer, the silicon oxynitride layer, or the silicon nitride oxide layer may be formed by sputtering. In addition to the above method, the film may be formed by plasma CVD. For example, the film may be formed by using SiH4, A silicon oxynitride layer can be formed by plasma CVD using oxygen and nitrogen. The thickness of the insulating layer 204 is set to 100 nm or more and 500 nm or less. In the case of a laminated layer, the thickness is set to, for example, A first gate insulating layer having a thickness of 50 nm or more and 200 nm or less, and a 5 nm thick insulating film on the first gate insulating layer. The second gate insulating layer is laminated to a thickness of 100 nm or more and 300 nm or less. If the film formed using the above method contains impurities such as hydrogen and water, the above heat treatment is carried out to remove the impurities. It is preferable to form an oxide semiconductor film after removing the insulating film.

[0119] In this embodiment, the gate insulating layer is selectively formed by the fourth photolithography process. A contact hole is formed by etching to reach the gate wiring layer (not shown). This method is not limited to the above. For example, after forming the gate insulating layer 204, A resist mask may be formed, and a contact hole reaching the gate wiring layer may be formed.

[0120] After the oxide semiconductor layer 205 is formed, the oxide semiconductor layer 205 is dehydrated or dehydrogenated. The conversion may be performed.

[0121] The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or higher and less than 750°C. If the temperature is 425°C or higher, the heat treatment time is 1 hour or longer. However, if the temperature is less than 425°C, the heat treatment time should be longer than 1 hour. In the first heat treatment, the substrate is introduced into an electric furnace, which is a type of heat treatment apparatus, and an oxide semiconductor After the layer was heat-treated in a nitrogen atmosphere, the oxide semiconductor was removed without contact with the air. The oxide semiconductor layer is obtained by preventing the re-incorporation of water and hydrogen into the conductor layer. The same furnace is used to heat the material from the heating temperature T for dehydrogenation to a temperature high enough to prevent water from entering again. Specifically, the temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below the heating temperature T. The decomposition may be carried out under a rare gas atmosphere such as helium, neon, or argon, without being limited to a nitrogen atmosphere. Hydration or dehydrogenation is carried out.

[0122] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Use an RTA (Rapid Thermal Anneal) device such as an LRTA devices can be used with halogen lamps, metal halide lamps, and xenon lamps. Arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. This is a device that heats the material to be treated by radiating light (electromagnetic waves) emitted from a lamp. The device uses the heat radiation from the light emitted from the lamp and heats the gas with the light emitted from the lamp. The object to be treated is heated by thermal conduction from the heated gas. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment Active gas is used. In addition, LRTA and GRTA devices use not only lamps but also resistors. The device is equipped with a device that heats the object to be treated by heat conduction or heat radiation from a heat source such as an anti-heat source. It may be possible to do so.

[0123] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0124] Note that depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. For example, if the crystallization rate is 90% or more, Alternatively, the oxide semiconductor layer may be 80% or more microcrystalline. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor containing no crystalline components may be obtained. It may also be a conductive film.

[0125] After the first heat treatment, the oxide semiconductor layer becomes oxygen-deficient and has low resistance. The oxide semiconductor film after the treatment has a higher carrier concentration than the oxide semiconductor film immediately after the deposition, and is therefore preferable. Or 1 x 10 18 / cm 3 The oxide semiconductor layer has a carrier concentration of at least 1000 .mu.m.

[0126] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is then removed and subjected to a third photolithography step.

[0127] After the insulating layer 208 is formed, a second heat treatment (preferably at a temperature of 200° C. or higher and 400° C. or lower, For example, temperatures between 250°C and 350°C are used in an inert gas atmosphere or nitrogen gas atmosphere. It is also possible.

[0128] For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. In this case, part of the oxide semiconductor layer 205 is heated while being in contact with the oxide insulating layer 208a. In addition, the oxide semiconductor layer 205 was heated in a state where the other part of the oxide semiconductor layer 205 was in contact with the electrodes 207a and 207b. will be done.

[0129] The oxide semiconductor layer 205 whose resistance is reduced by the first heat treatment is in contact with the oxide insulating layer 208a. When the second heat treatment is performed in this state, the region in contact with the oxide insulating layer 208a is in an oxygen-excess state. As a result, the oxide semiconductor layer 205 is in contact with the oxide insulating layer 208a. The oxide semiconductor layer 205 is made to have a high resistance (i-type) in the depth direction.

[0130] Specifically, the oxide semiconductor layer 205 is formed on the oxide insulating layer 208a. The oxide semiconductor layer 205 having a high resistance (i-type) region is formed on the layer 204. will be done.

[0131] The thin film transistor manufactured in this embodiment has a high resistance (I-type) in the channel formation region. Since a thick oxide semiconductor layer is formed, the threshold voltage is positive and the enhancement effect is Indicates type behavior.

[0132] The electrodes 207a and 207b are made of a metal conductive film having a high affinity with oxygen, and the oxide semiconductor When the second heat treatment is performed on the region in contact with the conductive layer 205, oxygen tends to move to the metal conductive film side. The oxide semiconductor layer in the region in contact with the metal conductive film, which has a strong affinity for oxygen, becomes N-type. An example of a metal that has a strong affinity for oxygen is Ti.

[0133] The timing for performing the second heat treatment is immediately after the end of the sixth photolithography process. There are no particular limitations on the process, as long as it is a process subsequent to the sixth photolithography process.

[0134] In this embodiment, a photolithography process using a multi-tone mask is applied. Regarding the photolithography process using a multi-tone mask, reference is made to FIGS. This will be used to explain.

[0135] A multi-tone mask is a mask that can perform exposure with multiple levels of light intensity. The light, medium and unexposed areas are exposed at three exposure levels. By the process of forming a resist mask having regions of multiple thicknesses (typically two types), Therefore, by using a multi-tone mask, the number of exposure masks can be reduced. It is possible to reduce it.

[0136] Typical examples of multi-tone masks include a gray-tone mask 801a as shown in FIG. 6(A), There is a halftone mask 801b as shown in FIG. 6(C).

[0137] As shown in FIG. 6(A), the gray-tone mask 801a is made up of a transparent substrate 802 and a The light-shielding portion 803 is formed on the substrate 801 and a diffraction grating 804. On the other hand, the diffraction grating 804 has a light transmittance of 0%. By setting the spacing between the transparent portions to be equal to or less than the resolution limit of the light used for exposure, the light transmittance The diffraction grating 804 can be formed by periodic slits, dots, meshes, etc. Either periodic slits, dots, or meshes can be used.

[0138] The light-transmitting substrate 802 may be a light-transmitting substrate such as quartz. The diffraction grating 804 is formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. This can be done.

[0139] When the gray-tone mask 801a is irradiated with exposure light, as shown in FIG. 6(B), the light-shielding portion In 803, the light transmittance 805 is 0%, and the light blocking portion 803 and the diffraction grating 804 are provided. In the unobstructed area, the light transmittance 805 is 100%. The light transmittance 805 in the selected area can be adjusted within the range of 10 to 70%. The light transmittance in 804 can be adjusted by adjusting the slits, dots, or meshes of the diffraction grating. This is possible by adjusting the spacing and pitch.

[0140] As shown in FIG. 6(C), the halftone mask 801b is formed by a transparent substrate 802 and a The semi-transmitting portion 807 is made of Mo SiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light section 806 can be formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. Cut.

[0141] When the halftone mask 801b is irradiated with exposure light, as shown in FIG. 6(D), the light-shielding portion In 806, the light transmittance 808 is 0%, and the light-shielding portion 806 and the semi-transmitting portion 807 are provided. In the unshaded area, the light transmittance 808 is 100%. The light transmittance 808 in the selected area can be adjusted within the range of 10 to 70%. The light transmittance of the semi-transparent portion 807 can be adjusted by adjusting the material of the semi-transparent portion 807. .

[0142] Next, referring to FIG. 7, the third photolithography step and the fifth photolithography step will be described. An example of replacing the lithography process with a single multi-tone mask is shown below. I will explain.

[0143] In the third photolithography process of the present embodiment, a semiconductor layer is formed on the insulating layer 204. In the past, after forming 205, an island-shaped semiconductor layer was formed. However, in this case, the island-shaped semiconductor layer was not formed, and the Then, an electrode layer 207 is formed on the semiconductor layer 205. Then, a multi-tone mask is formed on the electrode layer 207. A resist mask 231 having a recess or a protrusion is formed using a mask (see FIG. 7(A)). ).

[0144] The resist mask 231 is a resist mask consisting of a plurality of regions (two regions in this example) with different thicknesses. In the resist mask 231, the thick region is made of resist. The thin areas are called convex portions of the resist mask 231, and the thin areas are called concave portions of the resist mask 231. .

[0145] In the resist mask 231, the electrode 207a functioning as a source electrode and the drain electrode A protrusion is formed in the portion where the electrode 207b, which functions as a pole, is formed, and the electrodes 207a and A recess is formed in the portion sandwiched between the portions where the electrode 207b is formed.

[0146] Next, the electrode layer 207 and the semiconductor layer 205 are selectively removed using a resist mask 231. At the same time, etching is performed to form island-shaped semiconductor layers 205 (see FIG. 7(B)).

[0147] Next, the resist mask 231 is retracted (reduced) to form a resist mask 231a. A resist mask 231b is formed. To make the resist mask recede (shrink), oxygen propellant is used. By reducing (shrinking) the resist mask, The electrode layer 207 in the portion sandwiched between the resist mask 231a and the resist mask 231b is It is exposed (see Figure 7(C)).

[0148] Next, the electrode layer 2 in the portion sandwiched between the resist mask 231a and the resist mask 231b is 07 is selectively etched using the resist mask 231a and the resist mask 231b. By this process, the electrodes 207a and 207b are formed. The layer 205 is only partially etched, forming a semiconductor layer having a groove (recess). The end of the conductor layer 205 protrudes outward beyond the ends of the electrodes 207a and 207b. (See FIG. 7D). Next, the resist mask 231a and the resist mask 231 b is removed (see FIG. 7(E)).

[0149] By using a multi-tone mask, multiple photolithography steps can be performed in one step. This allows for the replacement of the process with a conventional process, thereby improving the productivity of semiconductor devices. .

[0150] In this embodiment, the electrode 207a and the solder are formed in the sixth photolithography step. When forming a contact hole for connecting the source wiring 209, the thin film transistor Openings are formed in the insulating layer 204b, the insulating layer 208a, and the insulating layer 208b so as to surround the insulating layer. The thin film transistor 253 has a structure in which the layer 211 contacts the insulating layer 204a through the opening. A cross-sectional view of the thin film transistor 253 is shown in FIG.

[0151] The thin film transistor 253 illustrated in FIG. 38 is similar to the thin film transistor 250 in that it has a channel. The thin film transistor is a thin film transistor of a etch type, and is made of an insulating layer 201 provided on a substrate 200 and an insulating A gate wiring 202 provided on the layer 201 and a gate wiring provided on the gate wiring 202 203, an insulating layer 204a provided on the gate wiring 203, and a an insulating layer 204b formed on the insulating layer 204b; a semiconductor layer 205 formed on the insulating layer 204b; A pair of electrodes 207a and 207b are provided on the substrate 205, and the electrodes 207a and 207b are b, an insulating layer 208a provided on the semiconductor layer 205, and a The insulating layer 208a is electrically connected to the insulating layer 208b through openings provided in the insulating layer 208a and the insulating layer 208b. A source wiring 209 in contact with the electrode 207a and a source wiring 209 provided on the source wiring 209 10, an insulating layer 211 provided on the source wiring 210, and the insulating layer 211 and the insulating layer 208 a) and an electrode 212 that contacts the electrode 207b through an opening provided in the insulating layer 208b; It has.

[0152] Here, the insulating layer 204b, the insulating layer 208a, and the insulating layer 208b are formed by the sixth photolithography. In the film, openings are selectively formed to expose the insulating layer 204a, and the insulating layer 21 1 covers the upper and side surfaces of the insulating layer 208b, the side surfaces of the insulating layer 208a and the insulating layer 204b. , and contacts the insulating layer 204a through the opening.

[0153] Here, the insulating layer 211 and the insulating layer 204a are made of an insulating film containing nitrogen, and are resistant to moisture and hydrogen ions. Nya, OH ― It does not contain impurities such as chlorine, and is an inorganic material that blocks these from entering from the outside. It is an insulating film.

[0154] Therefore, by using the structure shown in FIG. 38, the insulating layer 211 made of an insulating film containing nitrogen and the insulating layer Layer 204a can seal the thin film transistor 253, so that the insulating layer 21 In the manufacturing process after the formation of 1, it is possible to prevent moisture from entering from the outside. Even after the device is completed as a display device, such as a liquid crystal display device, it is possible to protect it from external water for a long period of time. This can prevent the intrusion of particles and improve the long-term reliability of the device.

[0155] In this embodiment, a structure in which one thin film transistor is surrounded by an insulating film containing nitrogen is shown. However, there is no particular limitation, and a configuration in which a plurality of thin film transistors are surrounded by an insulating film containing nitrogen may also be used. Alternatively, a plurality of thin film transistors in the pixel portion may be surrounded by an insulating film containing nitrogen. The insulating layer 211 is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. It is only necessary to provide a region in contact with the edge layer 204a.

[0156] In addition, a conductive film containing Al as a main component as a wiring material with low electrical resistance is used as the gate wiring 203. The pixel wiring 209 may also be used as the source wiring 209. This will be explained using Figure 39. Figure 39(A) is a top view showing the plane configuration of a pixel. 39(B) to 39(C) are cross-sectional views showing the stacked structure of the pixel. The dashed lines A1-A2, B1-B2, and C1-C2 in A) represent the cross sections in Figure 39(B). A1-A2, B1-B2, and C1-C2 correspond to the cross sections D1- The chain line D2 corresponds to the cross section D1-D2 in FIG. 39(C).

[0157] The cross sections A1-A2 and D1-D2 are cross sections of the thin film transistor 252 used in the pixel portion. The layer structure is shown, and the thin film transistor 252 is one example of a bottom gate structure.

[0158] In the cross sections A1-A2 and D1-D2, an insulating layer 201 provided on a substrate 200 and , a gate wiring 203 provided on the insulating layer 201, and an insulating layer provided on the gate wiring 203. a layer 204, a semiconductor layer 205 provided on the insulating layer 204, and a semiconductor layer 206 provided on the semiconductor layer 205. A pair of electrodes 207a and 207b, and a pair of electrodes 207a, 207b, and a semiconductor An insulating layer 208 is provided on the layer 205, and an electrode is formed through an opening provided in the insulating layer 208. A source wiring 209 in contact with 207a, and an insulating layer 211 provided on the source wiring 209. , an electrode that contacts the electrode 207b through an opening provided in the insulating layer 211 and the insulating layer 208; 212 and

[0159] The cross section B1-B2 shows the stacked structure of the storage capacitor (also called Cs capacitor). In B1-B2, an insulating layer 201 is formed on a substrate 200, and a storage capacitor wiring 2 is formed on the insulating layer 201. 13, an insulating layer 204 on the storage capacitor wiring 213, an electrode 207b on the insulating layer 204, and An insulating layer 208 is formed on the electrode 207b, an insulating layer 211 is formed on the insulating layer 208, and an electrode is formed on the insulating layer 211. and a pole 212.

[0160] The cross section C1-C2 shows the stacked structure at the intersection of the gate wiring and the source wiring. In the cross section C1-C2, an insulating layer 201 is formed on a substrate 200, and a gate insulating layer 202 is formed on the insulating layer 201. A gate wiring 203, an insulating layer 204 on the gate wiring 203, and an insulating layer 205 on the insulating layer 204. 8, a source wiring 209 on the insulating layer 208, and an insulating layer 211 on the source wiring 209. At the wiring intersection, a semiconductor layer is formed between the insulating layer 204 and the insulating layer 208. The structure may be such that:

[0161] As a conductive film mainly composed of Al, which is used as a wiring material with low electrical resistance, pure aluminum is used. Titanium (Ti), tantalum (Ta), tungsten (W), Molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), nickel Ni, Platinum (Pt), Copper (Cu), Gold (Au), Silver (Ag), Manganese (Mn) , a heat resistance improving element or a hillock preventing element such as carbon (C) or silicon (Si); Or aluminum alloys containing alloy materials or compounds containing these elements as the main components It is preferable to use a conductive film mainly composed of Al and a conductive film composed of W, Ta, Mo, Ti, C. It is also possible to use a laminated conductive film containing an element such as r that has a melting point higher than that of Al.

[0162] In the example of the pixel configuration of the display device shown in FIG. 39, an aluminum film is formed on a molybdenum film as a conductive film. A conductive film mainly composed of aluminum is laminated, and then a molybdenum film is formed on the conductive film mainly composed of aluminum. Conductive films with a three-layer structure made of laminated buten films and conductive films made of laminated titanium and aluminum Just use

[0163] In a bottom gate transistor, the gate electrode is formed early in the process. A material that can withstand the heat treatment that follows after the gate electrode is formed is selected. However, the heat treatment included in the process described in this embodiment mode is mild. Therefore, a wide range of materials can be used for the gate electrode, and the performance required for the display device can be met. For example, a conductive film containing Al as its main component has a relatively low electrical resistance and is inexpensive. It is useful because it has excellent processability, but its heat resistance temperature is relatively low. According to the process of the present invention, even a conductive film containing Al as a main component can be used for a gate electrode. can.

[0164] In addition, a thin film transistor having light-transmitting properties can be provided. The thin film transistor provided in the pixel portion of the display device described in the second embodiment is The compound semiconductor layer 205 and the light-transmitting conductive film are connected to the gate wiring 203, the electrode 207a, and the A case where the electrode 207b is applied will be described.

[0165] When applied to the thin film transistor of the pixel configuration shown in FIG. 2B, An insulating layer 201 is provided on the gate electrode 201, a gate wiring 202 is provided on the insulating layer 201, and a gate A light-transmitting gate wiring 203 provided on the wiring 202 and a light-transmitting gate electrode 204 provided on the gate wiring 203 are provided. The insulating layer 204 is formed on the insulating layer 204, the semiconductor layer 205 is formed on the insulating layer 204, and the semiconductor layer 20 A pair of light-transmitting electrodes 207a and 207b are provided on the substrate 5, and the electrode 207a , an insulating layer 208 provided on the electrode 207b and the semiconductor layer 205, and a A source wiring 209 contacts the electrode 207a through the opening, and a a source wiring 210 provided on the insulating layer 211; The electrode 21 contacts the electrode 207b through an opening provided in the insulating layer 208 and the edge layer 211. 2 and a light-transmitting thin film transistor having the same.

[0166] In addition, a thin film transistor having a bottom gate structure and having a channel protection layer as shown in FIG. Specifically, an insulating layer 201 is provided on a substrate 200, and a dielectric film is provided on the insulating layer 201. and a light-transmitting gate wiring 202 provided on the gate wiring 202. a gate wiring 203, an insulating layer 204 provided on the light-transmitting gate wiring 203, and an insulating layer 2 A semiconductor layer 205 is provided on the semiconductor layer 204, and a channel protection layer 205 is provided on the semiconductor layer 205. 25, and a pair of electrodes 207a and 207b having light-transmitting properties provided on the channel protection layer 225. and an insulating layer provided on the electrode 207a, the electrode 207b, and the semiconductor layer 205. 208, and the source wiring 2 contacting the electrode 207a through an opening provided in the insulating layer 208. 09, a source wiring 210 provided on the source wiring 209, and a The insulating layer 211 is electrically connected to the insulating layer 208 through openings provided in the insulating layer 211 and the insulating layer 208. and an electrode 212 in contact with the electrode 207b. do.

[0167] Many of the oxide semiconductors that can be applied to the oxide semiconductor layer 205 described in Embodiment 2 are visible It transmits light. In addition, a conductive material having light-transmitting properties, such as an insulator containing tungsten oxide, Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, titanium oxide-containing indium tin oxide (hereinafter referred to as ITO ), indium zinc oxide, indium tin oxide doped with silicon oxide, In- Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Z nO-based, Sn-Al-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based , Sn-O-based, Zn-O-based oxide semiconductors, etc. are deposited by sputtering or the like, This can be applied to the gate wiring 203, the electrode 207a, and the electrode 207b.

[0168] The light-transmitting oxide semiconductor layer 205 and the light-transmitting conductive film are formed on the gate wiring 203. Since the thin film transistors used for the electrodes 207a and 207b have a light-transmitting property, Therefore, the aperture ratio of the pixel portion is not impaired.

[0169] Note that the light-transmitting conductive oxide serves as an n+ layer in a region in contact with the oxide semiconductor layer. This allows for the creation of thin-film transistors with low contact resistance and low parasitic resistance. We can provide it.

[0170] The above process prevents the increase in wiring resistance and allows for the production of semiconductors, such as display devices, with high display quality. The present invention also provides a device including insulating layers located above and below the conductive layer containing Cu. The insulating layer contains silicon nitride, and the conductive layer containing Cu is sandwiched or wrapped between the insulating layers. This prevents Cu diffusion and provides a highly reliable semiconductor device.

[0171] The oxide semiconductor layer in which the impurity concentration is suppressed, which is manufactured by the method exemplified in this embodiment, By applying this technology, it is possible to provide highly reliable semiconductor devices. In addition, a thin film transistor using an oxide semiconductor having a high operating speed can be provided. Thin-film transistors using oxide semiconductors are relatively simple to manufacture and have sufficient reliability. We can provide you with a GISTA.

[0172] Furthermore, according to this embodiment, the threshold voltage is controlled, the operating speed is high, and the manufacturing process is relatively simple. A simple and sufficiently reliable method for manufacturing a thin film transistor using an oxide semiconductor can provide.

[0173] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0174] (Embodiment 3) In this embodiment, the display device 30 shown in FIG. 1 in the first embodiment is gate-driven. 9 shows an example of the configuration of a thin film transistor used in the source driving circuit 91 or the source driving circuit 92. .

[0175] The driver circuit for driving the pixel section is composed of an inverter circuit, a capacitor, a resistor, etc. In this embodiment, two thin film transistors are used in the driver circuit. The configuration of the inverter circuit consisting of two n-channel TFTs is explained. When combining them to form an inverter circuit, they are formed using enhancement type TFTs. In the case of EEMOS circuits, enhancement and depletion transistors are used. In some cases, a transistor is formed by combining it with an EDMOS transistor (hereinafter referred to as an EDMOS circuit). When the threshold voltage of the n-channel TFT is positive, the When the threshold voltage of the n-channel TFT is negative, it is called a depletion-type transistor. This definition is used throughout the specification.

[0176] The cross-sectional structure of the inverter circuit of the driver circuit is shown in FIG. A top view of the circuit is shown in Figure 8(C). In Figure 8(C), a cross section taken along the chain line Z1-Z2 8(A). The first thin film transistor 430a and the second thin film transistor 430b shown in FIG. The thin film transistor 430b is an inverted staggered thin film transistor with a bottom gate structure.

[0177] The first thin film transistor 430a shown in FIG. 8A is formed on a substrate 4 on which an insulating layer 410 is formed. A first gate wiring 401a is provided on the insulating layer 400, and an insulating layer 401b is provided on the first gate wiring 401a. 11 and an insulating layer 412 are provided, and a first semiconductor layer 403a is provided on the insulating layer 412. Electrodes 405a and 405b are provided on the first semiconductor layer 403a. The second thin film transistor 430b is also formed on the substrate 400 on which the insulating layer 410 is formed. A gate wiring 401b is provided, and an insulating layer 411 and an insulating layer 412 is provided, and a second semiconductor layer 403b is provided on the insulating layer 412, and the second semiconductor Electrodes 405b and 405c are provided on layer 403b. The second electrode 401 is connected to the second electrode 402 through a contact hole 404 formed in the insulating layer 411 and the insulating layer 412. The electrode 405a, the electrode 405b, and the electrode 405 are directly connected to the gate wiring 401b. An insulating layer 413, an insulating layer 414, and an insulating layer 415 are formed on the electrode 40c. The electrodes 5a to 405c are extended as shown in FIG. 8(C), and are thin in the driving circuit. It also functions as wiring that electrically connects the film transistors.

[0178] Here, the first gate wiring 401a and the second gate wiring 401b are the same as those in the first embodiment. The gate wiring 203 is formed using the same material and method as the gate wiring 203 shown in the second embodiment. In addition, the first semiconductor layer 403a and the second semiconductor layer 403b can be formed by the same method as in the embodiment. The semiconductor layer 205 is formed using the same material and method as the semiconductor layer 205 shown in Embodiment 1 or 2. In addition, the electrodes 405a, 405b, and 405c can be formed in the same manner as in the first embodiment. Alternatively, the same material as the pair of electrodes 207a and 207b shown in the second embodiment may be used. The insulating layers 410 to 415 can be formed by using a method similar to that described above. Insulating layer 201, insulating layers 204a, 204b, insulating layer 204a, and insulating layer 204b shown in Embodiment 1 or 2 The insulating layer 208a, 208b and the insulating layer 211 can be formed using the same material and method. Cut.

[0179] The contact hole 404 is formed by the fourth photolithography process shown in the second embodiment. In this step, a mask is formed on the insulating layer 412, and the insulating layer 412 and the insulating layer 4 11 is formed by selectively etching the contact hole 404. By directly connecting the electrode 405c and the second gate wiring 401b, good contact is achieved. In addition, the contact between the electrode 405c and the second Compared with the case where the gate wiring 401b is connected via another conductive film, for example, a transparent conductive film, Therefore, the number of contact holes can be reduced, thereby reducing the occupation rate of the thin film transistor. The area can be reduced and the distance between thin film transistors in the driving circuit can be shortened.

[0180] As described above, the distance between thin film transistors in the drive circuit can be shortened, and the wiring resistance can be reduced. Since the amount of the ions can be sufficiently reduced, the ions can be used as wiring for electrically connecting each thin film transistor. It is not necessary to use a conductive layer containing Cu. Since a sufficient distance can be maintained between the stator and the wiring made of a conductive layer containing Cu, the oxide This prevents Cu from diffusing into the semiconductor layer. Wiring that has a relatively long route distance, such as power supply lines that apply potential and common wiring, is affected by wiring resistance. Since it is relatively susceptible to noise, it is preferable to use wiring made of a conductive layer containing Cu.

[0181] As described in the second embodiment, the heat treatment included in the process described in this embodiment Since the resistance is mild, a wide range of materials can be used for the gate electrode, and the performance required for display devices can be achieved. For example, a conductive film containing Al as its main component has a relatively low electrical resistance, It is inexpensive and has excellent workability, making it useful, but its heat resistance is relatively low. According to the process of the embodiment, even a conductive film containing Al as a main component can be used for a gate electrode. It is possible.

[0182] As shown in the first embodiment, the gate driving circuit 91 is connected to the gate wirings (20_1 to 20_2). _n (where n is a natural number)), and the source driver circuit 92 is connected to the source wirings (60_1 to 60_m( where m is a natural number) and are connected to gate wiring (20_1 to 20_n (where n is a natural number) The number of the wirings) and the source wirings (60_1 to 60_m (where m is a natural number)) are conductive layers containing Cu. Therefore, the wiring resistance can be sufficiently reduced even in the display area where the wiring is long. can be reduced.

[0183] The electrode 405a is a power supply line of the ground potential (ground power supply line). The electrode 405c may be a power supply line (negative power supply line) to which a voltage VDL is applied. It is electrically connected to the power supply line (positive power supply line) to which VDD is applied.

[0184] The equivalent circuit of the EEMOS circuit is shown in Figure 8(B). The path connection corresponds to the equivalent circuit shown in FIG. 8B, and the first thin film transistor 430a and The second thin film transistor 430b is an enhancement type n-channel transistor. Here is an example.

[0185] Note that the threshold voltage can be controlled by providing gate electrodes above and below the oxide semiconductor layer. The first thin film transistor 430a and the second thin film transistor 430b are enhancement The n-channel transistor may be of the same type.

[0186] In addition to the EEMOS circuit, the first thin film transistor 430a is also an enhancement The second thin film transistor 430b is a depletion type n-channel transistor. By using an n-channel transistor, an EDMOS circuit can be created. In this case, instead of connecting the electrode 405c to the second gate wiring 401b, the electrode 405b and the second gate wiring 401b are connected.

[0187] Enhancement type n-channel transistor and depletion type n-channel transistor are mounted on the same substrate. The method for fabricating the first and second semiconductor layers 403a and 403b is, for example, The conductive layer 403b is fabricated using a different material and under different film formation conditions. A gate electrode for threshold control is provided on the upper side of the layer to control the threshold. Apply a voltage to the gate electrode for threshold control so that the other TFT is on. The EDMOS circuit may be configured so that the transistor is normally off.

[0188] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0189] (Fourth embodiment) In this embodiment, a protection circuit using a semiconductor element will be described with reference to FIGS. 9 and 10. In addition, the structure of the connection portion that connects different common wirings formed through an insulating film is This will be explained with reference to FIG.

[0190] An example of a circuit applicable to the protection circuit 97 is shown in FIG. The nonlinear elements 170a and 170b are made up of die It is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. It can be formed in the same process as the transistor in the pixel portion, and for example, By connecting the drain terminal to the diode, it can have the same characteristics as a diode.

[0191] The first terminal (gate) and the third terminal (drain) of the nonlinear element 170a are connected to the common wiring 45. The second terminal (source) is connected to the source wiring 60_1. The first terminal (gate) and the third terminal (drain) of 70b are connected to the source wiring 60_1, The second terminal (source) is connected to the common wiring 45. That is, the protection circuit shown in FIG. The circuit consists of two transistors, each with its rectifying direction opposite to each other, connected to a common wiring 4 5 and the source wiring 60_1. Between the lines 60_1, a transistor whose rectification direction is from the common wiring 45 to the source wiring 60_1 is provided. The transistors whose rectification direction is from the source wiring 60_1 to the common wiring 45 are connected. This is the configuration.

[0192] When the source line 60_1 is positively or negatively charged due to static electricity or the like, the protection circuit A current flows in a direction that cancels out the charge. For example, when the source line 60_1 is positively charged, Then, a current flows in the direction that releases the positive charge to the common wiring 45. Electrostatic breakdown or threshold voltage shift of the pixel transistor connected to the source wiring 60_1 In addition, the charged source wiring 60_1 and the insulating layer are prevented from crossing each other. This can prevent dielectric breakdown of the insulating layer between the wiring and other wirings.

[0193] The protection circuit is not limited to the above configuration. For example, the rectification direction may be from the common wiring 45 to the source wiring 46. A plurality of transistors facing the source wiring 60_1 and a plurality of transistors facing the source wiring 60_2, each of which has a rectification direction common to the source wiring 60_1. A configuration may be adopted in which a plurality of transistors are connected to the common wiring 45. The source wiring 60_1 is connected with a plurality of nonlinear elements to prevent a surge voltage from being applied to the source wiring 60_1. Not only when a voltage is applied, but also when the common wiring 45 is charged with static electricity or the like, This can prevent the electric charges from flowing directly into the source wiring 60_1. In addition, the protection circuit can be configured using an odd number of nonlinear elements.

[0194] The protection circuit in FIG. 9A is provided on the source wiring 60_1 and the common wiring 45. The same configuration can be applied to the protection circuits of other parts. The semiconductor element of the present invention can be applied to the nonlinear element 170a and the nonlinear element 170b. Cut.

[0195] Next, an example of manufacturing a protection circuit over a substrate using a semiconductor element of one embodiment of the present invention is shown in FIG. 9(B 9B and 10. Note that FIG. 9B shows the wiring and the connection between the wiring. 10 is an example of a cross-sectional view, and FIG. 10 is a cross-sectional view taken along the Q1-Q2 cutting line, the Q3-Q4 cutting line, and This is a cross-sectional view corresponding to the Q5-Q6 cutting line.

[0196] The configuration shown in FIG. 9B is a configuration in which the common wiring 45 and the source wiring 60_1 are connected to the nonlinear element 170a and 10 is a top view of a portion connected by a nonlinear element 170b, which is an example of a protection circuit 97. FIG.

[0197] The nonlinear element 170a has a gate wiring 111a, which is connected to the common wiring 45. Either the source electrode or the drain electrode of the nonlinear element 170a is connected to the source wiring. 60_1, and the other is made up of a first electrode 115a. a is connected to the common wiring 45 .

[0198] The nonlinear element 170b has a gate wiring 111b, which is connected to a contact hole. The source wiring 60 is connected to the source electrode 115b via the contact hole 126, the second electrode 115b, and the contact hole 125. The source electrode and the drain electrode of the nonlinear element 170b are connected to the first electrode 11. The nonlinear element 170b is made up of a semiconductor layer 113 and a second electrode 115a. Has.

[0199] Next, the configuration of the common wiring 45, the source wiring 60_1, and the nonlinear element 170b will be described with reference to FIG. 10 will be used to explain.

[0200] The common wiring 45 is formed in the same wiring layer as the gate wiring. The gate wiring 45a and the gate wiring 45b are formed by laminating them on the insulating film 101. An insulating layer 102 is formed on the gate wiring 45b, and an insulating layer 117 is formed on the insulating layer 102. An insulating layer 118 is formed on the insulating layer 117 .

[0201] The source wiring 60_1 is formed on the insulating layer 102. The source wiring 60_1b is formed by stacking on the source wiring 60_1a. An insulating film 119 is formed on 60_1.

[0202] The nonlinear element 170b has a gate wiring 111b on an insulating film 101 provided on a substrate 100. The insulating layer 102 is disposed on the gate wiring 111b. The semiconductor layer 113 is disposed on the line 111b, and the end of the semiconductor layer 113 is overlapped with the gate wiring 111b. The electrode 115a and the electrode 115b are in contact with the gate wiring 111b. An insulating layer 117 is in contact with the semiconductor layer 113 sandwiched between the ends of the electrodes 115a and 115b. An insulating layer 118 is formed on the insulating layer 117. It is constructed by laminating an edge layer 102a and an insulating layer 102b.

[0203] The electrode 115b is connected to the gate wiring via a contact hole 125 provided in the insulating layer 102. The electrode 115b is directly connected to the substrate 111b via a contact hole 126. The insulating layer 118 is connected to the source wiring 60_1. A membrane 119 is formed.

[0204] The conductive film that becomes the electrodes 115a and 115b may be made of Ti, Mo, W, Al, Cr, C An element selected from u, Ta, or an alloy containing the above elements as components, or The conductive film is not limited to a single layer containing the above elements, but may be two or more layers. The above stack can be used.

[0205] In particular, the conductive film in contact with the semiconductor layer 113 is preferably made of a metal having an affinity for oxygen. A junction is formed between the oxide semiconductor and the metal. Titanium is particularly preferable among metals with oxygen affinity. In this embodiment, a titanium film (thickness 100 nm) and an aluminum film (thickness 200 nm) A three-layer conductive film is formed using a titanium film (thickness 100 nm) instead of a titanium film. A titanium nitride film may also be used.

[0206] Such a junction structure is formed between the semiconductor layer 113 and the electrode 115a, and between the semiconductor layer 113 and the electrode 115b. b, the operation of the nonlinear element 170a and the nonlinear element 170b is stabilized. In other words, thermal stability is increased, and stable operation is possible. This improves the circuit's functionality and stabilizes its operation. It also reduces junction leakage and reduces nonlinearity. The parasitic resistance of the element 170a and the nonlinear element 170b and the variation thereof can be reduced.

[0207] The nonlinear element 170a and the nonlinear element 170b have the same configuration in the main part. The nonlinear element 170b has the same structure as the thin film transistor of the pixel portion described in the first embodiment. Therefore, in this embodiment, the nonlinear element 170a and the nonlinear element 170b can be applied. A detailed description of the thin film transistor 170b will be omitted. can be produced using the same process.

[0208] An example of the connection between common wirings will be described with reference to FIG. 11. Note that FIG. 11(A) shows the wiring and FIG. 11(B) is an example of a top view of a connection portion between wirings, and FIG. 11(B) is an example of a R1-R2 switch in FIG. 11(A). 10 is a cross-sectional view corresponding to the R3-R4 cutting line.

[0209] As already explained, the common wiring 45 is formed by stacking the gate wiring 45b on the gate wiring 45a. The common wiring 65 has the same configuration as the source wiring 60_1. That is, the common wiring 65 has a configuration in which a source wiring 65b is stacked on a source wiring 65a. The source wiring 65a is formed of the same conductive film as the source wiring 60_1a, and the source wiring 65b is formed of the same conductive film as the source wiring 60_1a. It is formed of the same conductive film as the source wiring 60_1b.

[0210] At the connection portion 95, the common wiring 45 and the common wiring 65 are electrically connected. The common wiring 45 and the common wiring 65 are formed by an insulating layer 102, an insulating layer 103, and an insulating layer 104. The contact is made through a contact hole 127 formed in the edge layer 117 and the insulating layer 118. .

[0211] The connection portion 95 is made of a gate wiring 45b and a solder containing a conductive material containing an element having a melting point higher than that of Cu. The source wiring 65a is connected to the substrate 10, realizing a highly reliable connection. The gate wiring 45a and the source wiring 65b made of this material suppress the wiring resistance.

[0212] The common connection part 96 is provided in the outer region of the pixel part, and is made of conductive particles (plastic particles). The substrate has a connection part that is placed opposite to the surface of the substrate through a gold-plated particle, etc. As an example of the common connection portion 96, a gate wiring 45a is connected to the gate wiring 45b. A structure in which 45b is formed on the laminated conductive layers will be described with reference to FIG.

[0213] The common connection portion 96 is electrically connected to the common wiring 45. The gate electrode 96 is electrically connected to the gate wiring 45a. The wiring 45b is formed on the conductive layer via a contact hole 128 formed in the insulating layer 102. The electrode 115c is electrically connected to the conductive layer. 117 and the common wiring 65 through contact holes formed in the insulating layer 118. A conductive layer 66 having the same transparent conductive layer as the electrode 212 functioning as a pixel electrode is laminated. The conductive layer 129 is formed from a conductive film.

[0214] The gate wiring 45a and the source wiring 60 connected to the protection circuit exemplified in this embodiment The wiring 1b is made of a conductive material containing Cu and has low wiring resistance.

[0215] The gate wiring 45b is made of a material having a melting point higher than that of Cu, such as W, Ta, Mo, Ti, or Cr. By forming the gate wiring 45a using a conductive material containing silicon, the gate wiring 45a is in contact with the gate wiring 45a and is covered with the gate wiring 45a. Therefore, migration of the port wiring 45a can be suppressed, and the reliability of the semiconductor device can be improved. The insulating layers located above and below the gate wiring 45a containing Cu can be formed by using silicon nitride. The insulating layer is made of an insulating material containing Cu, and the gate wiring 45a containing Cu is sandwiched or wrapped between the insulating layers. By doing so, Cu diffusion can be prevented.

[0216] In addition, in the protection circuit exemplified in this embodiment, the first terminal (gate) of the nonlinear element is connected to the second terminal It is directly connected to the first terminal (source) or the third terminal (drain) through a contact hole. As a result, the interface and the contact hole formed by one connection are each This is less than when connecting via another wiring layer.

[0217] Furthermore, if the number of interfaces required for connection is small, the electrical resistance can be reduced. If the number of contact holes is small, the area occupied by the connection portion can be reduced.

[0218] Therefore, the protection circuit exemplified in this embodiment can suppress the connection resistance. The protection circuit operates stably. Also, since only one contact hole is required for connection, The area occupied by the protection circuit can be reduced, thereby enabling the display device to be made smaller.

[0219] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0220] (Embodiment 5) In this embodiment, the gate terminal portion of the display device shown in FIG. 1 in the first embodiment is 7 shows an example of the configuration of the gate signal line terminals of the gate terminal section 7 and the source signal line terminals of the source terminal section 8.

[0221] 12(A1) and 12(A2) are a top view and a cross-sectional view of the gate signal line terminal, respectively. FIG. 12(A1) corresponds to a cross-sectional view taken along the line C1-C2 in FIG. 12(A2). As shown in FIG. 12(A1), the gate signal line terminal is formed by forming an insulating layer 360 on a substrate 300. The gate wiring 351a is formed on the insulating layer 360, and the end of the gate wiring 351a A gate wiring 351b is formed to cover the gate wiring 351b, and an insulating layer 361 is formed on the gate wiring 351b. An edge layer 362, an insulating layer 363, an insulating layer 364, and an insulating layer 365 are formed. A transparent conductive layer 355 is formed on the gate wiring 351b. The gate wiring 351a and the gate wiring 351b are collectively called the gate wiring 351. The insulating layers 361 to 365 function as first terminals of the signal line terminals. The end of the gate wiring 351b is patterned, and the end of the gate wiring 351b is exposed and directly connected to the transparent conductive layer 355. The transparent conductive layer 35 directly contacts the end of the gate wiring 351b, which is the first terminal. 5 is a terminal electrode for connection that functions as an input terminal. The gate wiring 351b and the transparent conductive layer 355 are the same as those shown in Embodiments 1 and 2. The gate wiring 202, the gate wiring 203, and the electrode 212 are formed using the same material and method. The insulating layers 360 to 365 can be formed in the same manner as in Embodiment 1 and Embodiment 2. The insulating layer 201, the insulating layers 204a, 204b, the insulating layers 208a, 208b, and the insulating layers 208c, 208d, 208e, and the insulating layers 201, 204a, 204b, and the insulating layers 208c, 208e, and the insulating layers 204a, 204b, and the insulating layers 204a, 204 The insulating layer 211 can be formed using the same material and method as the insulating layer 211.

[0222] The gate wiring 351a is formed of a conductive material containing Cu, so that the gate signal line terminal and In addition, the wiring resistance of the lead-in wiring from the gate signal line terminal can be reduced. The gate wiring 351b is made of an element having a melting point higher than that of Cu, such as W, Ta, Mo, Ti, or Cr. By forming the conductive material containing the Therefore, migration of the port wiring 351a can be suppressed, and the reliability of the semiconductor device can be improved. In addition, the gate wiring 351a containing Cu can be formed by insulating the insulating layer 360 containing silicon nitride and the insulating layer By sandwiching the gate wiring 351a with the gate electrode 361, Cu diffusion from the gate wiring 351a can be prevented. .

[0223] 12(B1) and 12(B2) are a top view and a cross-sectional view of the source signal line terminal, respectively. FIG. 12(B1) is a cross-sectional view taken along the line D1-D2 in FIG. 12(B2). As shown in FIG. 12(B1), the source signal line terminal is formed by forming an insulating layer 3 on a substrate 300. 60, an insulating layer 361 and an insulating layer 362 are formed, and an electrode 352 is formed on the insulating layer 362. An insulating layer 363 and an insulating layer 364 are formed on the electrode 352, and a source electrode 365 is formed on the insulating layer 364. A wiring 354a is formed, a source wiring 354b is formed on the source wiring 354a, and a source An insulating layer 365 is formed on the wiring 354b, and a transparent conductive layer is formed on the insulating layer 365 and the electrode 352. Here, the source wiring 354a and the source wiring 354b are joined together. The insulating layers 363 to 365 are patterned at their ends. The end of the electrode 352 is exposed and in direct contact with the transparent conductive layer 355. A contact hole is formed in the insulating layer 364 and the second source signal line terminal. The electrode 352, which functions as the first terminal, is connected to the source wiring 354. The transparent conductive layer 355 in direct contact with the end of the electrode 352 is a connection terminal that functions as an input terminal. Here, the electrode 352, the source wiring 354a, the source wiring 354b, and The transparent conductive layer 355 is the same as the pair of electrodes 207a and 207b shown in the first and second embodiments. and electrode 207b, source wiring 209, source wiring 210 and electrode 212, and The insulating layers 360 to 365 can be formed by using the same method. The insulating layer 201, the insulating layers 204a, 204b, and the insulating layer The insulating layer 208a, 208b and the insulating layer 211 can be formed using the same material and method. can.

[0224] The source wiring 354b is formed of a conductive material containing Cu, so that the source signal line terminal and Also, the wiring resistance of the lead-in wiring from the source signal line terminal can be reduced. The source wiring 354a is made of an element having a melting point higher than that of Cu, such as W, Ta, Mo, Ti, or Cr. Conductive materials containing, or alloys of the above elements, or tantalum nitride (TaN ), titanium nitride (TiN), molybdenum nitride (MoN), etc. are used to form the source wiring 354b By forming the source wiring 354b so as to contact the semiconductor layer 354b, migration of the source wiring 354b is suppressed. The reliability of the semiconductor device can be improved. The source wiring 354b is sandwiched between the insulating layer 364 and the insulating layer 365 containing silicon dioxide. This can prevent Cu diffusion from the substrate.

[0225] In this embodiment, the gate wiring 351 having a stacked structure includes the gate wiring 3 as the first terminal. 51b is connected to the transparent conductive layer 355 which functions as an input terminal. The form is not limited to this. As shown in Figures 13(A1) and 13(A2), The first terminal is composed of only the gate wiring 351a, and the gate wiring 351a is connected to the transparent conductive layer 3 13(A1) in FIG. 13(A2) may be configured to be in direct contact with 55. This corresponds to a cross-sectional view taken along line C1-C2.

[0226] In this embodiment, the source wiring 354 is connected to the input terminal 352 via the electrode 352, which is the second terminal. In the example shown, the transparent conductive layer 355 functions as an input terminal. As shown in FIG. 13(B1) and FIG. 13(B2), the second terminal and In the source wiring 354 that functions as a transparent conductive layer 355, the source wiring 354b is directly connected to the transparent conductive layer 355. Here, FIG. 13(B1) is D1-D2 in FIG. 13(B2). It corresponds to a cross-sectional view along the line.

[0227] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0228] Note that the structure described in this embodiment mode may be combined with structures described in other embodiments as appropriate. It is possible to do so.

[0229] (Embodiment 6) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0230] The thin film transistors arranged in the pixel portion are formed according to any one of the first to fourth embodiments. The thin film transistors described in Embodiments 1 to 4 are n-channel TFTs. Therefore, some of the driver circuits can be configured with n-channel TFTs. The thin film transistors in the pixel portion are formed on the same substrate.

[0231] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 has a signal line driver circuit 5303 and a signal line driver circuit 5304. are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. In the intersections of the signal lines and the wiring, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control I) is connected to the timing control circuit 5305 via a connection part such as a C).

[0232] In FIG. 18A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of externally provided components such as drive circuits, thereby reducing costs. In addition, when a driving circuit is provided outside the substrate 5300, it becomes necessary to extend the wiring, and the wiring The number of connections increases. If a driver circuit is installed on the same board 5300, the number of connections between the wiring can be reduced. This can reduce the number of defects, thereby improving reliability and yield.

[0233] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal The timing control circuit 5305 also supplies the second scanning line driving circuit (GCLK1). For example, a start signal for the second scanning line driving circuit (GSP2) (S It supplies a clock signal (GCLK2) for the scanning line driver circuit. The timing control circuit 5305 controls the signal line driver circuit 5304 to supply a signal line driver circuit start signal. signal (SSP), clock signal for signal line driver circuit (SCLK), data for video signal ( DATA) (also simply called video signal), and latch signal (LAT). Each clock signal may be a plurality of clock signals with different periods, or may be a clock signal that is generated by inverting the clock signal. It may be supplied together with the signal (CKB) inverted by the first scanning line driver. It is possible to omit either the second scanning line driver circuit 5302 or the second scanning line driver circuit 5303.

[0234] In FIG. 18B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the The second scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, thin-film transistors have lower field-effect mobility than transistors using single-crystal semiconductors. The driving circuit formed on the substrate 5300 can be configured by the film transistor. Therefore, it is possible to increase the size of the display device, reduce the number of processes, reduce costs, or improve yields. This can be achieved.

[0235] The thin film transistors described in any of Embodiments 1 to 4 are n-channel TFTs. In FIG. 19(A) and FIG. 19(B), a signal line driver circuit configured with an n-channel TFT is shown. An example of the configuration and operation will be described below.

[0236] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) The thin film transistors 5603_1 to 5603_k are n-channel TFTs. An example will be explained.

[0237] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the first terminals of the thin film transistors 5603_1 to 5603_k. are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0238] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0239] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k. The thin film transistor 56 has a function of supplying the potential of the signal lines S1 to Sk. Each of 03_1 to 5603_k functions as a switch.

[0240] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0241] Next, the operation of the signal line driver circuit of FIG. 19(A) will be explained with reference to the timing chart of FIG. 19(B). 19B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0242] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0243] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 5603_1 to 5603_k are turned on, so the wiring 5604_1 to 5604_k and the signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to the selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. Then, the video signal data (DATA) is sent to the pixels belonging to the selected row in order of k columns. It will be written.

[0244] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0245] The shift register 5601 and the switching circuit 5602 are the same as those in the third embodiment. In this case, a circuit configured with a thin film transistor shown in FIG. The polarity of all the transistors in the transistor 5601 is set to n-channel or p-channel. It can be configured with only one polarity.

[0246] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIGS. 20 and 21.

[0247] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal ( A selection signal is generated by inputting a clock (CLK) and a start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scanning line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Therefore, the transistors of the pixels in one line must be turned on simultaneously, so a buffer The resistor is capable of passing a large current.

[0248] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number equal to or greater than 3 (see FIG. 20(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the previous stage (called OUT(n-1)) (n is a natural number greater than or equal to 2) is input. In addition, the first pulse output circuit 10_1 receives a pulse from the third pulse output circuit 10_3, which is two stages later. Similarly, in the n-th pulse output circuit 10_n at the second stage or later, a signal from the second stage is input. The signal from the (n+2)th pulse output circuit 10_(n+2) in the subsequent stage (subsequent signal OUT(n +2) is input. Therefore, the pulse output circuit of each stage outputs the pulse to the subsequent stage and / or The first output signal (OUT(1)(SR) to O) is input to the pulse output circuit of the previous stage. UT(N)(SR)), a second output signal (OUT(1) electrically connected to another wiring, etc. OUT(N)) is output. As shown in FIG. 20(A), The last two stages are not input with the next stage signal OUT(n+2). A second start pulse SP2 is sent from the sixth wiring 16, and a third start pulse SP3 is sent from the seventh wiring 17. Alternatively, you can configure the shift register to input the pulses SP3 and SP4. For example, the (N+1)th signal that does not contribute to the pulse output to the pixel unit may be used. ) pulse output circuit 10_(N+1), (N+2)th pulse output circuit 10_(N+2) (also called a dummy stage), and a second start pulse (SP2) and Alternatively, a signal equivalent to the start pulse (SP3) of No. 3 may be generated.

[0249] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is input to the GCL It is sometimes called K or SCLK, but here we will explain it as CK.

[0250] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0251] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 20B, the input terminal 25, the first output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output.

[0252] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0253] The first pulse output circuit 10_1 includes a first transistor 31 to an eleventh transistor 4 1 (see FIG. 20(C)). In addition, the first input terminal 21 to the fifth input terminal In addition to the terminal 25, the first output terminal 26, the second output terminal 27, and the first high power supply potential VD A power supply line 51 to which a second high power supply potential D is supplied, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential Vcc is supplied. The first transistor 31 to the eleventh transistor 32 are connected to a power supply line 53 through which a voltage VSS is supplied. A signal or a power supply potential is supplied to 41. Here, the power supply voltage of each power supply line in FIG. The magnitude relationship of the potentials is such that the first power supply potential VDD is equal to or higher than the second power supply potential VCC, and the second The power supply potential VCC of the first clock is set to a potential higher than the third power supply potential VSS. The signal (CK1) to the fourth clock signal (CK4) alternate between H level and L level at regular intervals. It is a repeating signal, but when it is high it is VDD and when it is low it is VSS. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, The potential applied to the gate electrode of the transistor can be kept low without affecting the This reduces the shift in the threshold voltage of the transistor and suppresses degradation.

[0254] In FIG. 20C, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; is electrically connected to the fourth input terminal 24. The second transistor 32 is is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. The gate electrode of the fourth transistor 34 is electrically connected to the gate electrode of the fourth transistor 35. The third transistor 33 has a first terminal electrically connected to the first input terminal 21, The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53, The second terminal is connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 of No. 6 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second Electrically connected to the gate electrode of the transistor 32 and the gate electrode of the fourth transistor 34 The seventh transistor has a gate electrode electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a second terminal connected to the gate electrode of the second transistor 32. The gate electrode of the fourth transistor 34 is electrically connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to each other. The gate electrode is electrically connected to the power supply line 52. The first terminal of the sigma 40 is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. do.

[0255] In FIG. 20C, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. (See FIG. 21(A)).

[0256] FIG. 21(A) shows the pulse output circuit described in FIG. 20(C) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the signals input to or output from the second output terminal 27.

[0257] Specifically, a first clock signal CK1 is input to the first input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a second input terminal CK3 is input. The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0258] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. The gate is a semiconductor element in which a channel region is formed in the region overlapping the gate. By controlling the gate potential, the drain and source are connected via the channel region. The source and drain are thin film transistors. Which is the source or drain depends on the transistor structure and operating conditions. Therefore, it is difficult to define the regions that function as the source and drain. In some cases, they are not called sources or drains. In such cases, for example, they are called first It may be written as terminal or second terminal.

[0259] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift chart is shown in FIG. 21(B). In this case, the period 61 in FIG. 21(B) corresponds to the vertical blanking period, and the period 62 corresponds to the gate selection period. do.

[0260] As shown in FIG. 21A, the ninth transistor, whose gate is supplied with the second power supply potential VCC, By providing the transistor 39, the following occurs before and after the bootstrap operation: There are advantages like this.

[0261] If the ninth transistor 39, to whose gate electrode the second power supply potential VCC is applied, is not present, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes greater than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate and source, the gate and drain In both cases, a large bias voltage is applied, which causes a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 rises, but the potential of the second terminal of the first transistor 31 does not rise. That is, by providing the ninth transistor 39, the first transistor The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0262] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0263] Note that the semiconductor layers of the first to eleventh transistors 31 to 41 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and This allows for increased field effect mobility and reduced degradation. In addition, a transistor using an oxide semiconductor, Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is This allows the number of power supply lines to be reduced, thereby enabling the circuit to be made smaller.

[0264] The gate electrode of the seventh transistor 37 is connected to the clock signal supplied from the third input terminal 23. A lock signal, supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38 The clock signal to be output is input to the gate electrode of the seventh transistor 37 by the second input terminal 22. the gate electrode of the eighth transistor 38 is connected to the third input terminal 23 The same effect can be achieved by switching the wiring so that the clock signal is supplied by At this time, in the shift register shown in FIG. The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The first transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the resistor 38, the second input terminal 22 and the third input terminal 2 The potential drop at node B caused by the potential drop at node 3 is applied to the gate of the seventh transistor 37. The potential of the gate electrode of the eighth transistor 38 decreases. On the other hand, in the shift register shown in FIG. 21(A), the seventh shift The seventh transistor 37 and the eighth transistor 38 are both in an on state. 37 is on, the eighth transistor 38 is off, then the seventh transistor 37 is By turning off the eighth transistor 38, the second input terminal 22 and The potential drop at the node B caused by the potential drop at the third input terminal 23 is This can be reduced to a single time due to a drop in the potential of the gate electrode of the transistor 38. The clock signal CK3 is input to the gate electrode of the seventh transistor 37 from the third input terminal 23. The gate electrode of the eighth transistor 38 receives the clock signal from the second input terminal 22. It is preferable to have a wiring relationship in which CK2 is supplied because the fluctuation of the potential of node B This is because the number of times can be reduced and noise can also be reduced.

[0265] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0266] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0267] (Embodiment 7) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. A semiconductor device (also called a display device) having a display function can be manufactured. The transistor and part or the whole of the driver circuit are formed on the same substrate as the pixel section, On-panel formation is possible.

[0268] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0269] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is Each of the plurality of pixels includes a means for supplying a current to the display element. Alternatively, only the pixel electrode (also called pixel electrode layer) of the display element may be formed. After forming the conductive film that will become the pixel electrode and before etching to form the pixel electrode, It can be a state, and any form applies.

[0270] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0271] The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 14(A1) and 14(A2) show the thin film transistors 4010 and 4011 and the liquid crystal display device. The element 4013 is sealed between the second substrate 4006 and the panel 4008 by a sealant 4005. 14(A1) and 14(A2) are plan views of the same, and FIG. 14(B) is a cross-sectional view taken along line MN in FIG. 14(A1) and (A2). Equivalent.

[0272] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0273] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, the TAB method, etc. can be used. This is an example of mounting the signal line driver circuit 4003 by the OG method, and FIG. 14(A2) is an example of mounting the signal line driver circuit 4003 by the TAB method. This is an example in which the signal line driver circuit 4003 is implemented by the above.

[0274] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 14B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4041 and 4042 are formed on the thin film transistors 4010 and 4011. 4001, 4042, and 4021 are provided on the first substrate 4001. 43 is provided on the gate electrode layer of the thin film transistor, and an insulating layer 4044 and an insulating layer 404 5 is provided on the insulating layer 4020. A source wiring 4046 is provided on the insulating layer 4020. The thin film transistor is connected to the insulating layer 4020 through contact holes formed in the insulating layer 4041. The transistor 4010 is connected to the source electrode or the drain electrode.

[0275] The thin film transistors 4010 and 4011 are made of the oxide thin film transistors shown in any of Embodiments 1 to 4. A highly reliable thin film transistor including a semiconductor layer can be applied. In this example, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

[0276] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is formed on the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the layer at a position overlapping the channel forming region of the nitride semiconductor layer, In this case, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0277] The thin film transistor manufactured according to the process described in the second embodiment is highly purified. For example, when the oxide semiconductor layer is formed, impurities (hydrogen atoms, H To prevent contamination with compounds containing hydrogen atoms such as 2O or compounds containing carbon atoms, The oxide is then pumped out using an ion pump or the like. The semiconductor layer is subjected to a heat treatment, and a so-called back channel of the thin film transistor is formed. By forming an oxide insulating film in the region, impurities are transported from the oxide semiconductor layer to the oxide insulating film. Go to.

[0278] In addition, by providing a conductive layer 4040 in a position overlapping with the channel forming region, By shielding the thin film transistor from static electricity, The amount of electrically induced carriers can be reduced.

[0279] The oxide semiconductor layer is highly purified and shielded from static electricity, so that the oxide semiconductor layer The carrier density decreases. For example, the carrier density of the oxide semiconductor layer is 1×10 14 / cm 3 The oxide semiconductor layer with the carrier density suppressed in this way can be used as a thin film transistor. By using it in a transistor, the off-state current (I off ) can provide a thin film transistor with small In addition, the off-state current (I off ) is suppressed, and the thin film transistor is applied to a display device. As a result, a display device with low power consumption can be provided.

[0280] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0281] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film A room can be used.

[0282] The spacers 4035 are columnar spacers obtained by selectively etching the insulating film. The distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. The spacer 4035 may be a spherical spacer. In addition, the counter electrode layer 4031 is provided over the same substrate as the thin film transistor 4010. The common connection portion is electrically connected to the common potential line. The counter electrode layer 4031 and the common potential line can be electrically connected via the conductive particles. The conductive particles are contained in the sealing material 4005 .

[0283] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. Since it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small.

[0284] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0285] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer (color The polarizing plate is placed in the order of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and may be provided on the polarizing side. This may be appropriately set depending on the materials of the plate and colored layer and the manufacturing process conditions.

[0286] On the thin film transistors 4010 and 4011, a protective insulating film including a channel forming region is formed. An insulating layer 4041 is formed in contact with the semiconductor layer. The insulating layer 208 may be formed using a material and a method similar to those of the insulating layer 208 described in Embodiment 1 and Embodiment 2. In this case, the insulating layer 4041 is formed by sputtering in the same manner as in the first and second embodiments. A silicon oxide film is formed by a method.

[0287] In addition, in order to reduce the surface irregularities caused by the thin film transistor, a planarizing insulating film is formed on the insulating layer 4020. The insulating layer 4021 is formed to function as a film. Heat-resistant organic materials such as acrylic, benzocyclobutene, polyamide, and epoxy are used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane San-based resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. Note that the insulating layer 4021 can be formed by stacking a plurality of insulating films made of these materials. may be formed.

[0288] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0289] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed by using a baking machine. By using both, it becomes possible to manufacture a semiconductor device efficiently.

[0290] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0291] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0292] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0293] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0294] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0295] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0296] In FIG. 14, a signal line driver circuit 4003 is separately formed and mounted on a first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0297] FIG. 23 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed herein. 1 shows an example of a semiconductor device configured as a liquid crystal display module.

[0298] FIG. 23 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0299] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0300] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0301] The liquid crystal display device is manufactured using any of the display devices described in any of Embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, This prevents an increase in wiring resistance, thereby enabling the liquid crystal display device to operate at a high speed and with low power consumption. Therefore, it is possible to provide a liquid crystal display device that can accommodate a large screen and a high-definition screen. This can be done.

[0302] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0303] (Embodiment 8) An example of electronic paper will be shown as one mode of the semiconductor device.

[0304] The thin film transistor of the first embodiment uses an element electrically connected to the switching element. The present invention may be applied to electronic paper that drives electronic ink by electrophoretic display. The device (electrophoretic display) is also called, and has the same readability as paper and is superior to other display devices. It has the advantage of being able to consume very little power and have a thin, lightweight shape.

[0305] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0306] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0307] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0308] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. For example, in the thin film transistor of the first embodiment, An active matrix substrate obtained by a photodiode may be used.

[0309] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0310] Figure 22 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device may be the thin film transistor shown in Embodiments 1 and 2. It can be fabricated in the same way as a thin-film transistor containing an oxide semiconductor layer, and is a highly reliable thin-film transistor. It is a star.

[0311] The electronic paper in Figure 22 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0312] The thin film transistor 581 formed on the substrate 580 is a thin film transistor of a bottom gate structure. The substrate 580 is covered with an insulating layer 583 that is in contact with the semiconductor layer. An insulating layer 592 and an insulating layer 593 are formed on the gate electrode layer of the thin film transistor. An insulating layer 582 is formed on the insulating layer 583, and an insulating layer 597 and an insulating layer 598 are formed on the insulating layer 583. In addition, a source wiring 599a and a source wiring 599b are formed on the insulating layer 583. The thin film transistor is connected to the insulating layer 583 via a contact hole formed in the insulating layer 597. The thin film transistor 581 is connected to the source electrode layer or the drain electrode layer of the thin film transistor 581. The source electrode layer or drain electrode layer is formed on the first electrode layer 587 and the insulating layer 585. The first electrode layer 587 and the substrate 596 are in contact with each other through an opening, and are electrically connected. Between the second electrode layer 588 and the black area 590a and the white area 590b, A spherical particle 589 is provided, which includes a cavity 594 filled with a liquid, The particle 589 is surrounded by a filler 595 such as a resin (see FIG. 22). The electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. The common connection portion is used to connect the second electrode to the substrate via conductive particles disposed between the pair of substrates. The pole layer 588 can be electrically connected to a common potential line.

[0313] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0314] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0315] The above electronic page can be manufactured by the manufacturing method of a thin film transistor described in any of Embodiments 1 to 3. By fabricating a thin film transistor for each pixel, It is possible to suppress display unevenness caused by variations in threshold voltage.

[0316] The electronic paper is manufactured using the display device described in any of Embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, This prevents an increase in wiring resistance, thereby enabling the electronic paper to operate at higher speeds and consume less power. This allows for the provision of electronic paper that can be used on large screens and high-resolution screens. This can be done.

[0317] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0318] (Embodiment 9) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0319] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0320] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0321] FIG. 16 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0322] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The figure shows an n-channel transistor using an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0323] The pixel 6400 includes a switching transistor 6401 and a light-emitting element driving transistor 6402. 402, a light emitting element 6404 and a capacitor element 6403. The gate of the gate electrode 6401 is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) The second electrode (one of the source and drain electrodes) is connected to a signal line 6405, and the second electrode (the other of the source and drain electrodes) is connected to a signal line 6405. The other end is connected to the gate of the light-emitting element driving transistor 6402. The transistor 6402 has a gate connected to a power supply line 6407 through a capacitor element 6403. The first electrode is connected to a power supply line 6407, and the second electrode is connected to a first electrode (pixel The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0324] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0325] The capacitor element 6403 is substituted for the gate capacitance of the light-emitting element driving transistor 6402. It is possible to omit it. Regarding the gate capacitance of the light-emitting element driving transistor 6402 Alternatively, a capacitance may be formed between the channel region and the gate electrode.

[0326] In the case of a voltage input voltage driving method, the gate of the light emitting element driving transistor 6402 The light emitting element driving transistor 6402 is either fully turned on or off. In other words, the light emitting element driving transistor 6402 The light emitting element driving transistor 6402 is operated in the linear region. Therefore, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the light emitting element driving transistor 6402. The signal line 6405 is connected to the power supply line voltage + transistor for driving the light emitting element. Apply a voltage higher than the Vth of 6402.

[0327] Also, when analog grayscale driving is performed instead of digital time grayscale driving, the signal input is different. By doing so, the same pixel configuration as in FIG. 16 can be used.

[0328] When analog gradation driving is performed, a light emitting element is connected to the gate of the light emitting element driving transistor 6402. Apply a voltage equal to or greater than the forward voltage of 6404 and the Vth of the light-emitting element driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage required to achieve a desired luminance. At least the forward threshold voltage is included. By inputting a video signal that operates in the region, a current is passed to the light emitting element 6404. In order to operate the light emitting element driving transistor 6402 in the saturation region, The potential of the transistor 407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into analog, a current corresponding to the video signal flows to the light emitting element 6404, Analog gray scale driving is possible.

[0329] Note that the pixel configuration shown in Fig. 16 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0330] Next, the configuration of the light emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be explained using an example in which the FT is an n-channel type. 17(B) and 17(C) are TFTs for driving light-emitting elements used in the semiconductor devices of FIGS. The TFTs 7001, 7011, and 7021 are thin film TFTs shown in the first and second embodiments. It can be manufactured in the same way as a transistor and is a highly reliable thin film transistor containing an oxide semiconductor layer. be.

[0331] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. The top surface emission, which extracts light from the surface on the substrate side, the bottom surface emission, which extracts light from the surface on the substrate side and the surface on the opposite side from the substrate, There are light-emitting elements with a double-sided emission structure that extracts light from the can also be applied.

[0332] A light emitting element with a bottom emission structure will be described with reference to FIG.

[0333] In FIG. 17(A), a TFT 7011 for driving a light emitting element is an n-channel type, and a light emitting element 7012 17A shows a cross-sectional view of a pixel when light emitted from the cathode 7013 is emitted to the cathode 7013 side. In the example, a light-transmitting conductive film 701 electrically connected to a light-emitting element driving TFT 7011 is The cathode 7013 of the light emitting element 7012 is formed on the cathode 7013. The EL layer 7 7014 and an anode 7015 are laminated in this order. An insulating layer 7031 is also formed on the substrate. On the gate electrode layer of the light-emitting element driving TFT 7011, an insulating layer 7032 and an insulating layer 70 36 is formed on the source electrode layer and the drain electrode layer of the light-emitting element driving TFT 7011. Insulating layers 7037, 7038, and 7039 are formed on the insulating layer 7038. The source wiring 7018a and the source wiring 7018b are formed, and the insulating layer 7037 and the insulating The source of the light-emitting element driving TFT 7011 is connected to the source of the light-emitting element driving TFT 7011 through a contact hole formed in the layer 7038. The light-transmitting conductive film 7017 is connected to the insulating layer 7037 and the light-transmitting conductive film 7017. The light emitting element driving TFT 701 is connected to the contact holes formed in the TFTs 7038 and 7039. The drain electrode layer of the first transistor is electrically connected to the drain electrode layer of the first transistor.

[0334] The light-transmitting conductive film 7017 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Conductive materials with transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane can be used.

[0335] The cathode 7013 can be made of various materials, but a material with a small work function, for example Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr In addition to metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb, Er, etc. Rare earth metals are preferred. In FIG. 17(A), the thickness of the cathode 7013 is set to a level that allows light to pass through. (Preferably, about 5 nm to 30 nm) For example, an aluminum film having a thickness of 20 nm is A ZnO film is used as the cathode 7013 .

[0336] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The conductive film 7017 and the cathode 7013 may be formed by the same mask. It is possible to etch it using a etchant, which is preferable.

[0337] The periphery of the cathode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide, aluminum, and the like. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes The partition wall 7019 is formed by using a photosensitive resin material, and has an opening on the cathode 7013. The side wall of the opening is shaped to be an inclined surface formed with a continuous curvature. When a photosensitive resin material is used for the partition wall 7019, a resist mask is preferably used. The step of forming a mask can be omitted.

[0338] The EL layer 7014 formed on the cathode 7013 and the partition wall 7019 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7013 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, hole transport layer, and hole injection layer are laminated in this order. There is no need to set it up.

[0339] The stacking order is not limited to the above, and a hole injection layer, a hole transport layer, and a light emitting layer may be stacked on the cathode 7013. However, when comparing power consumption, the cathode layer may be stacked in this order. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7013 in this order. Layering is preferable because it consumes less power.

[0340] In addition, various materials can be used for the anode 7015 formed on the EL layer 7014. However, materials with large work functions, such as titanium nitride, ZrN, Ti, W, Ni, Pt, Cr, etc., and transparent conductive materials such as ITO, IZO (indium zinc oxide), and ZnO. It is also preferable to provide a shielding film 7016 on the anode 7015, such as a metal that blocks light or a light that reflects light. In this embodiment, an ITO film is used as the anode 7015, and a shielding film 7 A Ti film is used as 016.

[0341] The region where the EL layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light emitting element 7012. In the case of the element structure shown in FIG. 17A, the light emitted from the light emitting element 7012 is emitted toward the cathode 7013 as indicated by the arrow.

[0342] Note that FIG. 17A shows an example in which a light-transmitting conductive film is used as a gate electrode layer. The light emitted from the light emitting element 7012 passes through the color filter layer 7033 and is emitted. Can.

[0343] The color filter layer 7033 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0344] The color filter layer 7033 is covered with an overcoat layer 7034, which is further provided with a protective insulating layer. In FIG. 17(A), the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 has irregularities caused by the color filter layer 7033. It has the function of flattening the surface.

[0345] In addition, a protective insulating layer 7035, an overcoat layer 7034, and insulating layers 7037 and 7038, The contact hole formed in the partition wall 7039 and reaching the drain electrode layer is In FIG. 17(A), the contact layer 7030 is placed at a position where it overlaps with the drain electrode layer 7030. The layout of the hole and the partition wall 7019 is designed to overlap, improving the aperture ratio. can be done.

[0346] Next, a light emitting element with a dual emission structure will be described with reference to FIG.

[0347] In FIG. 17B, a light-transmitting TFT 7021 is electrically connected to the light-emitting element driving TFT 7022. A cathode 7023 of the light-emitting element 7022 is formed on the conductive film 7027. An EL layer 7024 and an anode 7025 are laminated in this order on the substrate. 7041 is formed on the gate electrode layer of the light emitting element driving TFT 7021, and an insulating layer 7042 and and an insulating layer 7046 are formed, and the source electrode layer and the drain electrode layer of the light-emitting element driving TFT 7021 are formed. Insulating layers 7047, 7048, and 7049 are formed on the insulating electrode layer. On the insulating layer 708, a source wiring 7028a and a source wiring 7028b are formed. The light-emitting element driving TFT 7 is connected to the insulating layer 7048 through a contact hole formed in the insulating layer 7047. The light-transmitting conductive film 7027 is connected to the source electrode layer of the insulating layer 7021. Through the contact holes formed in 7047, 7048, and 7049, the light emitting element driving T It is electrically connected to the drain electrode layer of the FT7021.

[0348] The light-transmitting conductive film 7027 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Conductive materials with transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane can be used.

[0349] The cathode 7023 can be made of various materials, but a material with a small work function, for example Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr In addition to metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb, Er, etc. Rare earth metals are preferred. In this embodiment, the cathode 7023 has a thickness large enough to transmit light. (Preferably, about 5 nm to 30 nm) For example, an aluminum film having a thickness of 20 nm is A ZnO film is used as the cathode 7023 .

[0350] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The conductive film 7027 and the cathode 7023 may be formed by the same mask. It is possible to etch it using a etchant, which is preferable.

[0351] The periphery of the cathode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide, aluminum, and the like. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes The partition wall 7029 is formed by using a photosensitive resin material, and has an opening on the cathode 7023. The side wall of the opening is shaped to be an inclined surface formed with a continuous curvature. When a photosensitive resin material is used for the partition wall 7029, a resist mask is preferably used. The step of forming a mask can be omitted.

[0352] The EL layer 7024 formed on the cathode 7023 and the partition wall 7029 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7023 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, hole transport layer, and hole injection layer are laminated in this order. There is no need to set it up.

[0353] The stacking order is not limited to the above, and a hole injection layer, a hole transport layer, and a light emitting layer may be stacked on the cathode 7023. However, when comparing power consumption, the cathode layer may be stacked in this order. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7023 in this order. Layering is preferable because it consumes less power.

[0354] In addition, various materials can be used for the anode 7025 formed on the EL layer 7024. However, materials with a large work function, such as transparent conductive materials such as ITO, IZO, and ZnO, In this embodiment, an ITO film containing silicon oxide is used as the anode 7025.

[0355] The region where the EL layer 7024 is sandwiched between the cathode 7023 and the anode 7025 is the light emitting element 7022 In the case of the element structure shown in FIG. 17B, the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0356] Note that FIG. 17B shows an example in which a light-transmitting conductive film is used as a gate electrode layer. The light emitted from the light emitting element 7022 to the cathode 7023 side is reflected by the color filter layer 7043. It is emitted through the

[0357] The color filter layer 7043 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0358] The color filter layer 7043 is covered with an overcoat layer 7044, which is further provided with a protective insulating layer. Covered by layer 7045.

[0359] In addition, a protective insulating layer 7045, an overcoat layer 7044, and insulating layers 7047 and 7048, The contact hole formed in the partition wall 7049 and reaching the drain electrode layer is The contact hole reaching the drain electrode layer and the partition wall 7029 are arranged in a position overlapping with each other. By using a layout in which the electrodes are stacked, the aperture ratio on the anode 7025 side and the cathode 7023 side are almost the same. can be considered almost identical.

[0360] In addition, a light-transmitting conductive film formed over the protective insulating layer 7045 and the insulating layer 7042 The contact hole reaching 7027 is arranged at a position overlapping with the partition wall 7029 .

[0361] However, if a light-emitting element with a dual-side emission structure is used and both display surfaces are full color, Since light from the anode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate with a filter layer above the anode 7025.

[0362] Next, a light emitting element with a top emission structure will be described with reference to FIG.

[0363] In FIG. 17(C), the TFT 7001 for driving the light emitting element is an n-channel type, and the light emitting element 7002 17(C) shows a cross-sectional view of a pixel when light emitted from the cathode exits the anode 7005 side. The cathode 700 of the light emitting element 7002 electrically connected to the light emitting element driving TFT 7001 is 3 is formed, and an EL layer 7004 and an anode 7005 are laminated in this order on the cathode 7003. An insulating layer 7051 is formed on the substrate, and the gate of the TFT 7001 for driving the light emitting element is formed on the insulating layer 7051. An insulating layer 7052 and an insulating layer 7056 are formed on the gate electrode layer, and a light-emitting element driving TFT On the source electrode layer and the drain electrode layer of 7001, insulating layers 7057, 7058, and 7059 are formed. In addition, a source wiring 7008a and a source wiring 7008b are formed on the insulating layer 7058. 8b is formed, and contact holes formed in the insulating layer 7057 and the insulating layer 7058 are formed. It is connected to the source electrode layer of the light-emitting element driving TFT 7001 via a 7003 is connected to the insulating layers 7057, 7058, and 7059 through contact holes formed therein. The drain electrode layer of the light-emitting element driving TFT 7001 is electrically connected to the drain electrode layer of the light-emitting element driving TFT 7001 .

[0364] The cathode 7003 can be made of various materials, but a material with a small work function, for example Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr In addition to metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb, Er, etc. Rare earth metals are preferred.

[0365] The periphery of the cathode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide, aluminum, and the like. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes The partition wall 7009 is formed by using a photosensitive resin material, and has an opening on the cathode 7003. The side wall of the opening is shaped to be an inclined surface formed with a continuous curvature. When a photosensitive resin material is used for the partition wall 7009, a resist mask is preferably used. The step of forming a mask can be omitted.

[0366] The EL layer 7004 formed on the cathode 7003 and the partition wall 7009 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7003 is composed of multiple layers, an electron injection layer, an electron transport layer, and a light emitting layer are disposed on the cathode 7003. The layer, hole transport layer, and hole injection layer are laminated in this order. There is no need to set it up.

[0367] The stacking order is not limited to the above, and a hole injection layer, a hole transport layer, and a light emitting layer may be stacked on the cathode 7003. The cathode 700 may be laminated in this order, i.e., the electron transport layer and the electron injection layer. 3 will function as the anode.

[0368] In Figure 17(C), hole injection is performed on a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order. The electron injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked in this order, and Mg:A A laminate of a g-alloy thin film and an ITO film is formed.

[0369] However, when comparing power consumption, the cathode 7003 is covered with an electron injection layer, an electron transport layer, a light emitting layer, It is preferable to stack the hole transport layer and the hole injection layer in this order, as this reduces power consumption.

[0370] The anode 7005 is formed using a conductive material that transmits light, such as titanium oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, oxide Indium oxide containing titanium, indium tin oxide containing titanium oxide, indium stannate Indium tin oxide with added silicon dioxide, indium zinc oxide, A conductive film having such a structure may be used.

[0371] The region where the EL layer 7004 is sandwiched between the cathode 7003 and the anode 7005 forms the light emitting element 7002. In the case of the pixel shown in FIG. 17(C), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0372] In FIG. 17(C), the drain electrode layer of the light-emitting element driving TFT 7001 is an insulating The cathode 7003 and the cathode 7004 are connected to each other through contact holes formed in the layers 7057, 7058, and 7059. The planarization insulating layer 7053 is made of polyimide, acrylic, benzocyclobutene, Resin materials such as propylene, polyamide, and epoxy can be used. , low-k materials, siloxane resins, PSG (phosphor glass), BPS G (phosphor boron glass), etc. can be used. Insulation formed from these materials The planarization insulating layer 7053 may be formed by stacking a plurality of films. The method for forming 53 is not particularly limited, and may be a sputtering method, an SOG method, a spin coating method, or the like, depending on the material. Coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, Set printing, etc.), doctor knife, roll coater, curtain coater, knife coater etc. can be used.

[0373] In addition, a partition wall 7009 is provided to insulate the cathode 7003 from the cathode of an adjacent pixel. The partition wall 7009 is made of organic resin film such as polyimide, acrylic, polyamide, epoxy, etc., or inorganic insulating film. The partition wall 7009 is formed by using an insulating film or organic polysiloxane. An opening is formed on the cathode 7003 using a material, and the sidewall of the opening has a continuous curvature. It is preferable to form the partition wall 7009 so that the inclined surface is formed. When a resin material is used, the step of forming a resist mask can be omitted.

[0374] In the structure of FIG. 17C, when full color display is performed, for example, the light emitting element 70 02 is a green light emitting element, one of the adjacent light emitting elements is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also included, making a total of four A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0375] In the structure of FIG. 17(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By combining a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0376] Of course, a single-color display may be performed. For example, a lighting device may be formed using white light. Alternatively, a monochromatic light emitting device may be used to form an area color type light emitting device.

[0377] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0378] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0379] In addition, a thin film transistor (TFT for driving light-emitting elements) that controls the driving of light-emitting elements and a light-emitting element However, if a current flows between the light-emitting element driving TFT and the light-emitting element, A control TFT may be connected.

[0380] In addition, the present invention can be applied to a liquid crystal display device as long as it has a configuration in which no light emitting element and no partition wall are provided. The case of a liquid crystal display device is shown in FIG.

[0381] The case where the light emitting element driving TFT 7061 is an n-channel type is shown. The pixel includes a light-transmitting conductive film 7067 electrically connected to the driver TFT 7061 . An insulating layer 7071 is formed on the substrate, and serves as a gate electrode for the TFT 7061 for driving the light emitting element. An insulating layer 7072 and an insulating layer 7076 are formed on the electrode layer, and a light-emitting element driving TFT 706 Insulating layers 7077, 7078, and 7079 are formed on the source electrode layer and the drain electrode layer of 1. In addition, a source wiring 7068a and a source wiring 7068b are formed on the insulating layer 7078. The insulating layer 7077 and the insulating layer 7078 are connected to each other through contact holes formed in the insulating layer 7077 and the insulating layer 7078. The light-transmitting conductive layer is connected to the source electrode layer of the light-emitting element driving TFT7061. The conductive film 7067 has contact holes formed in the insulating layers 7077, 7078, and 7079. It is electrically connected to the drain electrode layer of the light emitting element driving TFT 7061 via a transistor.

[0382] The light-transmitting conductive film 7067 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Conductive materials with transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane can be used.

[0383] In FIG. 37, the light emitted from the backlight passes through the color filter layer 7063. The color filter layer 7063 is formed by a droplet discharge method such as an ink jet method. , a printing method, an etching method using photolithography technology, or the like.

[0384] The color filter layer 7063 is covered with an overcoat layer 7064, which is further provided with a protective insulating layer. In FIG. 37, the overcoat layer 7064 is thin. As shown in the figure, the overcoat layer 7064 eliminates the unevenness caused by the color filter layer 7063. It has a flattening function.

[0385] Furthermore, by providing a liquid crystal layer over the light-transmitting conductive film 7067, can also be applied.

[0386] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be explained with reference to FIG. 15. FIG. 15(A) shows a thin film formed on a first substrate. A panel in which a film transistor and a light-emitting element are sealed between a second substrate and the panel by a sealant. 15(B) is a plan view of the same, and FIG. 15(B) corresponds to a cross-sectional view taken along line HI in FIG. 15(A).

[0387] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0388] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 15B, a thin film transistor 4510 included in a pixel portion 4502 and a signal A thin film transistor 4509 included in a signal line driver circuit 4503a is shown as an example. Insulating layers 4541, 4542, and 4543 are provided on the transistors 4509 and 4510. An insulating layer 4544 is provided over the thin film transistor 4510. An insulating layer 4545 is provided over a first substrate 4501, and a gate electrode layer of a thin film transistor An insulating layer 4546 and an insulating layer 4547 are provided on the insulating layer 4542. A source wiring 4548 is provided, and a gate insulating layer 4541 and a gate insulating layer 4542 are formed in the gate insulating layer 4541 and the gate insulating layer 4542. The source electrode layer or the drain electrode of the thin film transistor 4510 is connected to the semiconductor substrate 4510 through the contact hole. It is connected to the polar layer.

[0389] The thin film transistors 4509 and 4510 are made of the oxide thin film transistors described in Embodiments 1 to 3. A highly reliable thin film transistor including a semiconductor layer can be applied. In this example, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0390] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4543. A conductive layer 4540 is provided in a position overlapping with the channel formation region. By providing the layer at a position overlapping the channel forming region of the nitride semiconductor layer, In this case, the amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. The conductive layer 4540 may have the same potential as the gate electrode layer of the thin film transistor 4509. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4540 may be GND, 0V, or may be in a floating state.

[0391] The thin film transistor 4509 is in contact with the semiconductor layer including the channel formation region as a protective insulating film. The insulating layer 4541 is formed by the insulating layer 20 shown in Embodiment 1. 8. In addition, the surface irregularities caused by the thin film transistor can be reduced. In order to reduce the thickness, the insulating layer 4544 is covered with the insulating layer 4544, which functions as a planarization insulating film. The insulating layer 4541 is formed by a sputtering method using the insulating layer 208 described in Embodiment 1. A silicon oxide film is formed.

[0392] An insulating layer 4544 is formed as a planarization insulating film. The insulating layer 4021 may be formed using the same material and method as the insulating layer 4021 shown in Embodiment 7. Acrylic is used as the insulating layer 4544 which is an insulating layer.

[0393] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0394] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0395] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0396] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0397] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0398] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0399] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0400] The second substrate located in the direction of light extraction from the light emitting element 4511 must be transparent. In that case, use a glass plate, plastic plate, polyester film or acrylic A light-transmitting material such as a film is used.

[0401] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0402] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0403] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and implemented, and the configuration is not limited to that of FIG.

[0404] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0405] The light-emitting display device is manufactured using any of the display devices described in any of Embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby enabling the light emitting display device to operate at a high speed and with low power consumption. Therefore, it is possible to provide a light emitting display device that can accommodate a large screen and a high-definition screen. This can be done.

[0406] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0407] (Embodiment 10) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. It can be used for in-car advertising, displaying on various cards such as credit cards, etc. An example of the electronic device is shown in Figures 24 and 25.

[0408] FIG. 24(A) shows a poster 2631 made of electronic paper. When printed materials are used, the advertisements are replaced manually, but when electronic paper is used, The display of the advertisement can be changed in a short time. Also, the display is stable without any distortion. The poster may be configured to be capable of transmitting and receiving information wirelessly.

[0409] A poster 2631 can be manufactured using any of the display devices described in any of Embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby enabling the display device to operate at a higher speed and consume less power. Therefore, it is possible to provide a poster 2631 that can be displayed on a large screen and a high-resolution screen. This can be done.

[0410] FIG. 24(B) shows an advertisement 2632 inside a vehicle such as a train. When using printed paper, advertisements are exchanged manually, but with electronic paper, This allows you to change the display of your advertisements in a short time without requiring a lot of manpower. It is possible to obtain a stable image without any distortion. It may also be possible to use the following.

[0411] An in-vehicle advertisement 2632 can be manufactured using the display device described in any of Embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby enabling the display device to operate at a higher speed and consume less power. Therefore, it is possible to provide in-car advertisements 2632 that can be used on large screens and high-definition screens. This can be done.

[0412] 25 shows an example of an electronic book. For example, an electronic book 2700 includes a housing 2701 and a The housing 2701 and the housing 2703 are The shaft 2711 is an integral part of the device, and the device can be opened and closed around the shaft 2711. This configuration allows the device to function like a paper book.

[0413] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 25) and An image can be displayed on the display unit 2707 in FIG.

[0414] 25 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a board, a pointing device, etc. Also, the back and sides of the housing may be On the front, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable). The configuration includes a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. Good too.

[0415] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0416] (Embodiment 11) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras and digital video cameras cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices), (c), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples include:

[0417] FIG. 26(A) shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0418] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0419] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0420] A television set 9600 is manufactured using the display device described in any of Embodiments 1 to 5. By doing so, the gate wiring and source wiring can be formed of a conductive material containing Cu. Therefore, an increase in wiring resistance can be prevented. Since it can be powered, it is possible to make a television device 96 that can accommodate large screens and high-definition screens. 00 can be provided.

[0421] FIG. 26(B) shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0422] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0423] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0424] FIG. 27(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 27(A) also includes a speaker unit 9884, a recording medium insertion unit 988, 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 27(A) can be The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 27(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0425] FIG. 27(B) shows an example of a slot machine, which is a large gaming machine. 900 has a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and any other configuration may be used as long as it includes at least the semiconductor device disclosed in this specification. The configuration may be such that ancillary equipment is provided as appropriate.

[0426] FIG. 28A is a perspective view showing an example of a portable computer.

[0427] The portable computer of FIG. 28(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display portion 9303 and a keyboard. The lower housing 9302 having the card 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to input data on the keyboard, the hinge unit can be opened. The user can perform input operations by looking at the display portion 9303.

[0428] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the lower housing 9302. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted. There are.

[0429] The upper housing 9301 further includes a display unit 93 that can be slid into the upper housing 9301 and stored therein. 07, which allows for a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display section.

[0430] The display portion 9303 or the storable display portion 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses a light-emitting display panel made of inorganic light-emitting elements.

[0431] The portable computer shown in FIG. 28(A) is configured with a receiver and the like, and is also used for television broadcasting. It is possible to receive broadcasts and display images on the display unit. The display unit 9307 is slid open while the hinge unit connecting the display unit 9307 to the body 9302 is kept closed. The entire screen is exposed by tilting the screen, and the user can watch TV broadcasts by adjusting the screen angle. In this case, the hinge unit is opened to prevent the display unit 9303 from displaying anything. It only activates the circuitry to display the TV broadcast, so it consumes the minimum amount of power. This is useful in portable computers with limited battery capacity.

[0432] FIG. 28(B) shows a portable telephone that can be worn on the user's arm like a wristwatch. FIG. 10 is a perspective view showing an example of a story.

[0433] This mobile phone includes a main body having at least a communication device with a telephone function and a battery, A band part 9204 for attaching the body to the arm, an adjustment part for adjusting the fastening state of the band part to the arm It is composed of a joint part 9205, a display part 9201, a speaker 9207, and a microphone 9208. There are.

[0434] The main body also has an operation switch 9203, which is used for power input and display switching. In addition to the switch and the switch to start shooting, for example, when you press a button, a program for the Internet Each function can be associated with another function, such as being started.

[0435] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 28(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0436] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0437] The mobile phone shown in FIG. 28(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in a memory or the like. The system is configured with a storage device and the like, so that television broadcasts can be recorded in the memory. The mobile phone shown in FIG. 1 may have a function for collecting location information such as GPS.

[0438] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in Figure 28(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force-actuable panel.

[0439] Although FIG. 28(B) illustrates an electronic device that is worn on the arm, it is not limited to this. It is sufficient that the device has a portable shape.

[0440] (Embodiment 12) In this embodiment mode, the thin film transistor described in Embodiment 1 is used as one mode of a semiconductor device. An example of a display device having the same will be described with reference to FIGS. 29 to 32. In this embodiment, An example of a liquid crystal display device using a liquid crystal element will now be described with reference to FIGS. 29 to 32. The TFTs 628 and 629 used in the liquid crystal display device of FIG. 32 are the thin film transistors shown in the first embodiment. A transistor having electrical characteristics that can be manufactured in the same manner as in Embodiment Mode 2 can be applied. TFT628 and TFT629 are thin film transistors with high performance and reliability. The thin film transistor has a semiconductor layer as a channel formation region. As an example of the film transistor, the thin film transistor shown in FIG. 1 will be used. However, the present invention is not limited to this.

[0441] This section describes a VA (Vertical Alignment) type liquid crystal display device. A liquid crystal display device is a type of device that controls the alignment of liquid crystal molecules in a liquid crystal display panel. In A-type liquid crystal display devices, the liquid crystal molecules are perpendicular to the panel surface when no voltage is applied. In this embodiment, pixels are divided into several regions (sub-regions). The molecules are divided into small pixels (subpixels) and tilted in different directions. This is called domainization or multi-domain design. In the following explanation, multi-domain design is The liquid crystal display device under consideration will now be described.

[0442] 30 and 31 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of a substrate on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. 29. Also, FIG. 31 is a plan view of the substrate side on which the counter electrode is formed. The following description will be given with reference to these figures.

[0443] FIG. 29 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is superimposed on the counter substrate 601. The figure shows the state after the liquid crystal is injected.

[0444] A colored film 636 (the first colored film) is formed at a position where a spacer (not shown) is formed on the opposing substrate 601. A first colored film, a second colored film, a third colored film (not shown), and a counter electrode layer 640 are formed. Protrusions 644 are formed on the counter electrode layer 640. This structure controls the alignment of the liquid crystal. The height of the protrusion 644 and the spacer for the alignment layer 624 are different. Similarly, an alignment film 646 is formed on the counter electrode layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601 .

[0445] The spacers may be columnar spacers or bead spacers. The spacers may be formed on the pixel electrode layer 624 formed on the substrate 600 .

[0446] On the substrate 600 on which the insulating layer 661 is formed, a TFT 628 and a pixel electrode layer connected thereto are formed. The pixel electrode layer 624 includes a TFT 628, a storage capacitor 630, and a The insulating layer 664 covers the wiring 616 and the storage capacitor 630, and the insulating layer 66 5, through the insulating layer 666 on the insulating layer 665 and the insulating layer 622 on the insulating layer 666, respectively. The insulating layer 665 is connected to the wiring 618 through a contact hole 623. The source wiring 616 is formed by laminating the wiring 616a and the source wiring 616b. , through contact holes formed in the insulating layer 665 and the insulating layer 664 , The TFT 628 is connected to the source electrode layer or the drain electrode layer. The thin film transistor shown in embodiment 1 can be used appropriately.

[0447] The storage capacitor 630 is a first capacitor formed at the same time as the gate wiring 602 of the TFT 628. The capacitance wiring 604 is a capacitance wiring, and the insulating layer 662 and the insulating layer 663 are formed on the gate wiring 602. The wiring 618 is formed at the same time as the second capacitance wiring 617. The gate wiring 602 is a stack of gate wirings 602a and 602b. b functions as a gate electrode layer of the TFT 628. The capacitance wiring 604 also functions as a capacitance wiring 60 4a and 604b are stacked.

[0448] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0449] 30 shows a planar structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in Embodiment 1. The pixel electrode layer 624 is formed using a slit 625. The slit 625 is formed by This is to control the crystal orientation.

[0450] The TFT 629 shown in FIG. 30 and the pixel electrode layer 626 and storage capacitor 631 connected thereto are The TFT 628, the pixel electrode layer 624, and the storage capacitor 630 can be formed in the same manner. The capacitance wiring 605 forming the storage capacitance section 631 can be formed in the same manner as the capacitance wiring 604. The capacitor wirings 605a and 605b are stacked. The source wiring 616 and the gate wiring 602 are connected to the pixels (pixels) of this liquid crystal display panel. The pixel electrode layer 624 is composed of a pixel electrode layer 626. 24 and the pixel electrode layer 626 are sub-pixels.

[0451] 31 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is the same as the pixel electrode layer 624. On the counter electrode layer 640, a protrusion for controlling the alignment of the liquid crystal is formed. 31, the pixel electrode layer 624 formed on the substrate 600 is The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are indicated by dashed lines. 6 shows the state in which the electrode layer 626 is disposed on top of the other.

[0452] The equivalent circuit of this pixel structure is shown in Figure 32. Both TFT628 and TFT629 have gate electrodes. The line 602 is connected to the source line 616. In this case, the capacitance line 604 and the capacitance line 60 By making the potential of the liquid crystal element 651 and the liquid crystal element 652 different, the operation of the liquid crystal element 651 and the operation of the liquid crystal element 652 can be made different. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, This allows for precise control of the orientation of the liquid crystal to widen the viewing angle.

[0453] When a voltage is applied to the pixel electrode layer 624 in which the slit 625 is provided, a The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the 644 in an alternating interdigitated pattern, a diagonal electric field is effectively generated, By controlling the orientation, the direction in which the liquid crystal is oriented varies depending on the location. The multi-domain technology widens the viewing angle of the LCD panel.

[0454] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 33 to 36. In the configuration of the invention described below, the same parts as those of the above-mentioned VA type liquid crystal display device are used. Alternatively, the same reference numerals may be used in different drawings to designate parts having similar functions, and the same reference numerals may be used in different drawings to designate parts having similar functions. The explanation of this will be omitted.

[0455] 33 and 34 show the pixel structure of a VA type liquid crystal display panel. 33 is a plan view of the above-mentioned embodiment, and shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure.

[0456] This pixel structure has multiple pixel electrodes in one pixel, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independently The system has a configuration for controlling the temperature.

[0457] The pixel electrode layer 624 is formed by passing through the insulating layer 664, the insulating layer 665, and the insulating layer 666. In the contact hole 623, the wiring 618 is connected to the TFT 628. The pixel electrode layer 626 is formed by passing through the insulating layer 664, the insulating layer 665, and the insulating layer 666. The wiring 619 is connected to the TFT 629 through a contact hole 627. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are connected to different gate signals. On the other hand, the source wiring, which functions as a data line, 616 is connected to the TFT 616 via contact holes formed in the insulating layers 664 and 665. It is connected to the source electrode layers of TFT628 and TFT629 and is common to TFT628 and TFT629. The thin film transistors shown in Embodiment Mode 1 are used for the TFTs 628 and 629. It can be used as appropriate. Also, a capacitance wiring 690 is provided. Similar to the pixel structure of a liquid crystal display panel, the gate wiring 602 is made up of gate wirings 602a and 602b. The gate wiring 603 is a stack of gate wirings 603a and 603b. The wiring 616 is a stack of source wirings 616a and 616b, and the capacitance wiring 690 is a capacitance wiring 6 The insulating layers 661 to 666 are also laminated layers of the above-mentioned VA type. It is formed in the same manner as the pixel structure of a liquid crystal display panel.

[0458] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes and are separated by a slit 625. The pixel electrode layer 626 surrounds the outside of the pixel electrode layer 624 that spreads in a V shape. The voltage applied to the pixel electrode layer 624 and the pixel electrode layer 626 is applied to the TFT 628. The orientation of the liquid crystal is controlled by varying the polarity of the TFT 629. The equivalent circuit is shown in Figure 36. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate The TFT 628 and the TFT 629 are both connected to the source wiring 603. The gate wiring 602 and the gate wiring 603 are connected to each other. This allows the liquid crystal elements 651 and 652 to operate differently. By individually controlling the operations of the TFT 628 and the TFT 629, the liquid crystal element 651 and the liquid crystal The orientation of the liquid crystal in the liquid crystal element 652 can be precisely controlled to widen the viewing angle.

[0459] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 35 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is common to different pixels. The electrode is made of a metal, and a slit 641 is formed in it. The slits 625 on the element electrode layer 624 and pixel electrode layer 626 sides are arranged so as to interdigitate with each other. By doing so, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. This allows the orientation direction of the liquid crystal to vary depending on the location, thereby widening the viewing angle. In addition, in FIG. 32, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are indicated by dashed lines. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. It shows how it is placed.

[0460] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 64 are formed. The pixel electrode layer 626 and the liquid crystal element 651 are overlapped with each other. The liquid crystal layer 650 and the counter electrode layer 640 are overlapped to form a liquid crystal element 652 . The pixel structure of the display panel described with reference to FIGS. 33 to 36 has a liquid crystal element 651 and a liquid crystal element It has a multi-domain structure in which a sub-sub ...

[0461] By using the display devices shown in the first to fifth embodiments, the above-described liquid crystal display It is possible to fabricate a display device. Although the liquid crystal display device of this type has been described, the present embodiment is not limited to this. For example, a liquid crystal is driven by applying an electric field horizontally to the liquid crystal molecules in the cell, thereby expressing gradation. In-plane switching type liquid crystal display devices (such as IPS type liquid crystal display devices) and TN type liquid crystal display devices It may also be a device.

[0462] The liquid crystal display device is manufactured using any of the display devices described in any of Embodiments 1 to 5. This allows the gate wiring and source wiring to be formed from a conductive material containing Cu, It is possible to prevent an increase in wiring resistance, thereby achieving higher speed and lower power consumption of the display device. Therefore, it is possible to provide a liquid crystal display device that can accommodate a large screen and a high-definition screen. do.

[0463] (Embodiment 13) In this embodiment, a first substrate having a thin film transistor and a second substrate serving as an opposing substrate are An example of manufacturing a display panel in which the above-mentioned components are bonded together will be described below.

[0464] In the production process of LCD and EL display panels, static electricity can affect electronic circuits and cause electrical This may cause fluctuations in the product's characteristics or damage to the circuit. There are also problems that become easier.

[0465] In particular, when an insulating substrate is used, it is easy to become charged with static electricity. It is made of a soft material such as glass or resin.

[0466] Static electricity occurs when two objects are rubbed, touched, or separated, and one of them becomes positively charged and the other The electrons move between two objects due to friction, etc. This phenomenon of generating an electric charge is called electrification. When electrification occurs, if the material of the object is an insulator, The generated charge does not flow to the surface and accumulates as static electricity.

[0467] Furthermore, thin film transistors using oxide semiconductor layers are susceptible to static electricity. There is a risk that the electrical characteristics of the capacitor will fluctuate and deviate from the design range.

[0468] Therefore, a first substrate having a thin film transistor and a second substrate serving as an opposing substrate are bonded together. After the thin film transistor is grounded, the static electricity stored in the thin film transistor is released to the ground side, and the amount of charge is gradually attenuated. The heat treatment is carried out in a state where the heat is more easily removed. At least one of the heating processes performed when manufacturing a panel can be used as the process The amount of static electricity can be reduced without increasing the number of components.

[0469] The manufacturing of a liquid crystal display panel will be described below with reference to FIG.

[0470] First, a thin film transistor 710 having an oxide semiconductor layer and a pixel A first substrate 701 is prepared, on which an electrode 730 is formed. A driving circuit is provided on the same substrate as the thin film transistor 711 of the driving circuit. The thin film transistor 711 is fabricated in the same process as the transistor 710. The pixel electrode 730 is formed on the interlayer insulating film 742. A conductive layer 740 is formed above the transistor 711 to provide electrostatic shielding. The electrode layer 740 is made of the same material as the pixel electrode 730 .

[0471] After the pixel electrodes are formed, the substrate is washed and dried at 150°C for 2 minutes. The alignment film is a liquid horizontal alignment film formed by offset printing or screen printing. A forming material (or a vertical alignment film forming material), such as polyimide, is selectively applied and baked. After pre-baking at 80°C for 2 minutes using a hot plate, The plate is baked in a 230°C oven for 40 minutes. After baking, it is rubbed and then washed. Wash and dry at 150°C for 2 minutes.

[0472] In addition, a color filter, an alignment film, a sealing material, etc. are formed on the second substrate 706 which is the opposing substrate. The process for carrying out the above is shown below.

[0473] First, a black resin layer pattern that will become a black matrix is formed on the second substrate 706. Then, green resin layer pattern, blue resin layer pattern, and red resin layer pattern are formed. The green resin layer pattern, the blue resin layer pattern, and the red resin layer pattern are color fields. Then, an overcoat layer is formed to cover these resin layer patterns.

[0474] Next, a silicon oxide-doped indium tin oxide film is sputtered onto the overcoat layer. In order to reduce the resistance of the counter electrode 731, Heat for a certain time.

[0475] Next, a columnar spacer 735 is formed on the counter electrode 731. The columnar spacer 735 is It can be obtained by selectively etching an organic resin film such as an acrylic resin film.

[0476] Next, the substrate is washed and dried at 150° C. for 2 minutes. The alignment film is formed by printing a liquid water droplet on the substrate using offset printing or screen printing. A horizontal alignment film forming material (or a vertical alignment film forming material), such as polyimide, is selectively applied. The film is formed by baking. It was pre-baked at 80°C for 2 minutes using a hot plate. After that, it is baked in a clean oven at 230℃ for 40 minutes. After baking, it is rubbed. Then, wash and dry at 150°C for 2 minutes.

[0477] The sheet is then printed using a screen printing method, an ink jet device, or a dispensing device. The sealing material may be an acrylic photo-curable resin. The material contains filler (diameter 6μm~24μm) and has a viscosity of 40~400 Pa·s. It is preferable to select a sealing material that will not dissolve in the liquid crystal that will come into contact with it later. This sealing material forms a closed loop and surrounds the display area.

[0478] Also, the counter electrode 731 and the common connection part 702 provided on the first substrate are electrically connected. Therefore, the sealing material 704 containing conductive particles is also applied by an inkjet device or a dispenser. The common connection portion 702 is formed by bonding the first substrate and the second substrate. The electrode is placed in a position that overlaps the sealing material, and is electrically connected to the counter electrode via conductive particles contained in the sealing material. Or, the area that does not overlap with the sealing material (excluding the pixel area) is A connection part is provided, and a paste containing conductive particles is applied separately from the sealing material so as to overlap the common connection part. The common connection portion 702 is electrically connected to the pixel electrode 73. 0 and the conductive layer 740 are formed from the same material and in the same process.

[0479] Until the sealing material is formed, the second substrate 706 is protected from elements such as thin film transistors even if it is charged with static electricity. However, since the first substrate is to be bonded to the second substrate in a later process, It is preferable to reduce the amount of charge on the second substrate 706 before the alignment. The amount of charge on the second substrate 706 may be reduced by using a laser or the like, or the counter electrode 731 may be set to a fixed potential. For example, the above-mentioned heat treatment such as firing may be carried out while the semiconductor device is electrically connected to a ground potential.

[0480] Next, liquid crystal is dropped onto the alignment film of the second substrate 706. The liquid crystal material is dropped using a liquid crystal display or a dispenser. Not specified, TN LCD, OCB LCD, STN LCD, VA LCD, ECB type LCD, GH LCD, high Molecular dispersion liquid crystal, discotic liquid crystal, etc. can be used.

[0481] Next, the pair of substrates are bonded together under reduced pressure. Then, a first substrate 701 having a thin film transistor 710 is attached to the first substrate 701. Immediately after bonding, the seal material 705 is irradiated with ultraviolet light.

[0482] Next, in order to further harden the sealing material 705, the sealing material 705 is heated at a temperature of 80° C. to 200° C. for 0.5 hours. The heat treatment is carried out for 10 hours or more and 10 hours or less. The bonded pair of substrates is then placed in a furnace 780 of a heating device. The furnace 780 was placed on a stainless steel floor electrically connected to the ground potential. Then, a common connection terminal 715 electrically connected to the common connection portion 702 is Heating is performed while the external terminal 716, which is connected to the ground potential, is connected. The electrical connection of the connection part 702 is not limited to the ground potential (also called GND), and may be a fixed This heat treatment hardens the sealant 705 and removes the charged At the same time, static electricity can be suitably removed.

[0483] In this embodiment, heating is performed at 120° C. for 1 hour.

[0484] In addition, an enlarged cross-sectional view of the display area during heat treatment while connected to the ground potential is shown in FIG. As shown in FIG. 40(B), a counter electrode 731 electrically connected to the ground potential, A liquid crystal layer 708 is provided between the thin film transistor 710 and the electrically connected pixel electrode 730. However, by heating the liquid crystal layer 708, the thin film transistor 710 is charged. The static electricity 790 is released to the ground side through the liquid crystal layer 708. The schematic diagram using an equivalent circuit is shown in Figure 40(C). A path 791 through which static electricity 790 charged in the transistor 710 escapes to the ground side through the liquid crystal layer. The static electricity generated by the heat treatment gradually escapes to the ground via a path 791. This will attenuate the noise and make it easier to resolve.

[0485] By heat treating the opposing electrode with the ground potential, a normally-off thin-film transistor is formed. This allows stable production of LCD panels, improving the yield of LCD panels. Cut.

[0486] In addition, when multiple panels are to be produced from one substrate, after bonding a pair of substrates together, The first substrate is cut using a cutting device such as a scriber, a breaker, or a roll cutter. Or both substrates can be cut. In this way, multiple panels can be made from one substrate. can.

[0487] Next, a heat treatment for aligning the liquid crystal orientation, i.e., a realignment treatment (for example, 80°C to 200°C, 10 The heating is carried out at 100°C to 170°C for 10 minutes to 1 hour, preferably at 100°C to 170°C for 10 minutes to 1 hour.

[0488] In this embodiment, the realignment treatment is performed at 120° C. for 1 hour. Alternatively, as shown in FIG. 40(A), the heat treatment may be performed with the counter electrode at ground potential. In this embodiment, the heat treatment for hardening the sealing material and the heat treatment for aligning the liquid crystal are performed. Although the example in which the heat treatment and the heat treatment are performed separately has been shown, they may be performed in the same heat treatment.

[0489] Through the above steps, a liquid crystal display panel can be formed.

[0490] Furthermore, the present invention is not limited to a liquid crystal display device, and may be applied to an electronic pen that drives the electronic ink shown in the eighth embodiment. Display panels such as LCDs can also be heat treated to reduce static electricity. For example, the electrode provided on the second substrate that seals the electronic ink is electrically connected to the ground potential. a sealant for fixing the second substrate to the first substrate on which the thin film transistor is provided is cured; The heat treatment is performed in a state where the electrode provided on the second substrate is at a ground potential. By doing so, normally-off thin film transistors can be stably fabricated. This can improve the yield of active matrix electronic paper.

[0491] Furthermore, the present invention is not limited to liquid crystal display devices, and static electricity may also be applied to the EL display panel shown in the ninth embodiment. A heat treatment can be performed to reduce the electrical charge.

[0492] When an EL display panel is manufactured, an oxide semiconductor is formed on a first substrate according to the second embodiment. a first electrode electrically connected to the thin film transistor having a layer covering the periphery of the first electrode; After forming the barrier ribs, heating is performed. This heating is performed at 200°C for 1 hour in a nitrogen atmosphere. Then, a heat treatment was further performed in a vacuum at 150° C. for 1 hour, and an organic layer was formed on the first electrode of the first substrate. A layer containing the compound is deposited.

[0493] Next, a second electrode is formed on the layer containing an organic compound by evaporation or sputtering. The second electrode is provided above the thin film transistor in the display area so as to overlap it. The second electrode can also be provided above the thin film transistor of the driving circuit so as to overlap it. When the second electrode is set to a common potential, the second electrode and the ground potential are electrically connected in the subsequent heat treatment. It is preferable to connect the

[0494] Next, a second substrate having a recess in which a desiccant is fixed is used and fixed to the first substrate with a sealant. In the case of an EL display panel, the temperature must be higher than 80°C. If the heating temperature is too high, the light emitting element may deteriorate. Therefore, the temperature should be kept at 80°C for 0.5 hours or more and 10 hours. Heat treatment is carried out for the following period.

[0495] By performing heat treatment with the second electrode at ground potential, a normally-off thin-film transistor This allows stable production of EL display panels, improving the yield. can.

[0496] In addition, when sealing the light emitting element using a thin stainless steel substrate as the second substrate, When adhesive (such as epoxy resin) used to fix a stainless steel substrate hardens, When using a stainless steel substrate, the heat treatment is performed while the substrate is electrically connected to the ground potential. Not only the thin film transistors in the display area, but also the thin film transistors of the driver circuits formed on the same substrate All thin-film transistors, including the thin-film transistors, are overlapped by a stainless steel substrate, which is a conductive material. The stainless steel substrate overlapping the transistor is heated at a fixed potential, for example, ground potential. By doing this, normally-off thin film transistors can be stably manufactured. The yield of flexible EL display panels can be improved.

[0497] Heat treatment is performed with the electrode overlapping the thin film transistor at a fixed potential, for example, ground potential. This allows for the effective removal of static electricity from the substrate during the manufacturing process of the semiconductor device. can be done.

[0498] (Embodiment 14) In this embodiment, the In—Ga—Zn—O-based oxide semiconductor film described in Embodiment 2 is In a thin film transistor with a channel etch structure used as the active layer of a thin film transistor , a metal film used as a source electrode or a drain electrode, and an In-Ga-Zn-O oxide Near the interface with the semiconductor film, a layer with a higher indium concentration than other regions (In-rich layer) and titanium oxide film (TiO X ) formation phenomenon is investigated using computational science. Ta.

[0499] First, the indium, gallium, and zinc that make up the In-Ga-Zn-O oxide semiconductor The energy required for each oxide to form an oxygen vacancy (vacancy formation energy) Guy E def ) and determine which metal oxides are more likely to form oxygen vacancies. We conducted a study on this matter.

[0500] The defect formation energy E def The definition of A is expressed by the following formula 1. Indium alone, gallium alone, zinc alone, or indium, gallium, and zinc It means that E(O) is the energy of the oxygen atom, E(A m O n-1 ) is an oxygen deficiency Oxide A m O n-1 represents the energy of

[0501] (Equation 1) E def =(E(A m O n-1 )+E(O))-E(A m O n )

[0502] Vacancy concentration n and vacancy formation energy E def The relationship is approximately expressed by the following formula 2. where N is the number of oxygen positions when no defects are formed, and k B Habol T is the Tsmann constant, and T represents the temperature.

[0503] (Equation 2) n=N×exp(-E def / k B T)

[0504] The calculation was performed using the density functional theory program CASTEP. The plane wave basis pseudopotential method was used, and the functional was GGA-PBE. The energy used was 500 eV. The number of k-point grids was 3 × 3 × 1 for IGZO and 1 for I 2x2x2 for n2O3, 2x3x2 for Ga2O3, 4 for ZnO ×4×1.

[0505] The crystal structure of IGZO crystal is symmetrical R-3 (international code: 148) For the 84-atom structure with doubled a-axis and b-axis, Ga and Zn are the lowest energy For In2O3, a bixbyite structure of 80 atoms was used. The structure is a β-Gallia structure with 80 atoms for Ga2O3 and an 8 The wurtzite structure with 0 atoms was used.

[0506] From Equation 2, the defect formation energy E def As increases, the concentration of oxygen vacancies, n, i.e. It can be seen that the amount of oxygen vacancy becomes smaller. In the following Table 1, A is the amount of indium alone. , vacancy formation energy for gallium alone, zinc alone, indium, gallium, and zinc E def Indicates the value of

[0507] IGZO (Model 1) has three indium atoms and one zinc atom adjacent to the oxygen atom. Defect formation energy E def The structure is shown in Figure 41(A).

[0508] IGZO (Model 2) has three indium atoms and one gallium atom adjacent to each other in the crystal. Oxygen vacancy formation energy E def The structure is shown in Figure 41(B).

[0509] IGZO (Model 3) has two zinc atoms and two gallium atoms adjacent to oxygen atoms in the crystal. Defect formation energy E def The structure is shown in Figure 41(C).

[0510] [Table 1]

[0511] Defect formation energy E def The larger the value of is, the easier it is to form an oxygen vacancy state. It requires energy, which means that it tends to bond more strongly with oxygen. The defect formation energy E def From the value of It is clear that oxygen is easily released near indium.

[0512] The formation of oxygen vacancies in In-Ga-Zn-O oxide semiconductors is caused by the formation of a source electrode or The metal used as the drain electrode extracts oxygen from the oxide semiconductor. It is thought that the electrical conductivity of oxide semiconductors increases when oxygen vacancies are formed. Therefore, if the oxygen extraction occurs, the oxide semiconductor film is It is expected that the electrical conductivity will increase.

[0513] Next, we confirm whether the metal is extracting oxygen from the oxide semiconductor. To achieve this, quantum molecular dynamics was applied to the stacked structure of In-Ga-Zn-O oxide semiconductor film and metal. QMD calculations were performed.

[0514] The structure to be calculated was created as follows. First, a structure was created using the classical molecular dynamics (CMD) method. The amorphous In-Ga-Zn-O oxide semiconductor (In:Ga:Zn:O =1:1:1:4 (total 84 atoms) was subjected to structural optimization using first-principles calculations. The optimized unit cell is further cut to obtain an a-IGZO layer, on which metal atoms (W, Mo, Ti) crystals were stacked and the structure was optimized. Using this structure as a starting point, 623. Quantum molecular dynamics (QMD) calculations were performed at 0 K. Note that only the interfacial interactions were estimated. Therefore, the bottom edge of the a-IGZO layer and the top edge of the metal layer were fixed.

[0515] The calculation conditions for the classical molecular dynamics calculation are shown below. Explorer was used. a-IGZO was fabricated under the following conditions. A calculation cell with a side length of 1 nm A total of 84 atoms were randomly arranged in the In:Ga:Zn:O=1:1:1:4 ratio, and the density was 5.9g / cm 3 The temperature was gradually decreased from 5500K to 1K in the NVT ensemble. After that, structural relaxation was performed at 1K for 10 ns. The time step was 0.1 fs, and the total calculation time was 10 The potential was set to Born-Mayer-H between the metal and oxygen, and between the oxygen and oxygen. The charge is the Lennard Jones type. In: +3, Ga: +3, Zn: +2, O: -2.

[0516] The calculation conditions for the QMD calculation are shown below. The calculation program is the first-principles calculation software CASTE P was used. The functional was GGA-PBE, and the pseudopotential was Ultrasoft. The cutoff energy was 260 eV, and the number of k-points was 1 × 1 × 1. The calculation was performed using the NVT ensemble at a temperature of 623 K. The total calculation time was 2.0 ps with a time step of The width is 1.0 fs.

[0517] The results of the above calculations are shown in Figures 42 to 44. In Figures 42 to 44, the white circles represent metal atoms. The black circles represent oxygen atoms. Figure 42 shows the structure when a metal layer made of W is used. 42(A) shows the structure before QMD calculation, and FIG. 42(B) shows the structure after QMD calculation. FIG. 43 shows a structure in which a metal layer made of Mo is used, and FIG. 43(A) shows Q Figure 43(B) shows the structure before the MD calculation, and Figure 43(B) shows the structure after the QMD calculation. Figure 44 shows the metal layer made of Ti. 44(A) shows the structure before QMD calculation, and FIG. 44(B) shows the structure after QMD calculation. This is the structure after D calculation.

[0518] From Figures 43(A) and 44(A), in the case of Mo and Ti, the metal is already in the metal phase during the structural optimization. Oxygen that has moved to the metal layer can be seen. From the comparison, it was found that the most oxygen migration was observed in the case of Ti. It is thought that Ti is the best electrode for creating oxygen vacancies in GZO.

[0519] It is thought that titanium oxide is formed when the oxygen extracted by titanium reacts with the titanium. Therefore, the titanium oxide film formed between the oxide semiconductor film and the titanium film has conductivity. We verified whether it exists.

[0520] Titanium dioxide has a rutile structure (high-temperature tetragonal crystal), an anatase structure (low-temperature tetragonal crystal), It has several crystal structures, including the brookite structure (orthorhombic). When heated, the rutile type changes to the most stable structure, rutile type. The crystal structure of titanium dioxide with a rutile structure is shown in Figure 45. The rutile structure is tetragonal, and the space group that indicates the symmetry of the crystal is P42 / mnm. .

[0521] For the titanium dioxide structure above, the density functional method using the GGA-PBE functional was used to obtain The density of states was calculated. The structure was optimized, including the cell structure, while maintaining symmetry. The density of states was calculated using the density functional theory. The pseudopotential method was used, and the cutoff energy was set to 380 eV.

[0522] FIG. 46 shows the density of states diagram for titanium dioxide with a rutile structure. Titanium dioxide with a hexagonal structure has a band gap, so it is in an insulating or semiconducting state. It can be seen that the band gap is small in density functional theory. The actual band gap of titanium dioxide is about 3.0 eV, which is the density of states in Figure 46. The band gap is larger than that shown in the diagram.

[0523] Next, Figure 47 shows the density of states of titanium dioxide with a rutile structure when there is an oxygen deficiency. Specifically, the calculation involves removing O atoms from titanium oxide, which has 24 Ti atoms and 48 O atoms. Titanium oxide with one missing Ti24 atom and one missing O47 atom was used as a model. In the density of states diagram shown in 7, the Fermi level is shifted to the inside of the conduction band, making it metallic, and oxygen It can be seen that when there are defects, titanium dioxide exhibits N-type conductivity.

[0524] Next, FIG. 48 shows the density of states of titanium monoxide (TiO). It can be seen that the tungsten has a metallic density of states.

[0525] Therefore, the density of states of titanium dioxide shown in FIG. 46 and the density of states of titanium dioxide having oxygen vacancies shown in FIG. From the density of states diagram of titanium oxide shown in Fig. 48 and the density of states diagram of titanium monoxide shown in Fig. 49, it is clear that the Titanium dioxide (TiO 2-δ ) has N-type conductivity over the range 0<δ<1 Therefore, it is predicted that the composition of the titanium oxide film is titanium monoxide, oxygen deficiency, Even if the titanium dioxide film contains any of the In-Ga-Zn It is thought that the current flow between the -O-based oxide semiconductor film and the titanium film is less likely to be obstructed.

[0526] FIG. 49 shows the energy distribution between the source and drain electrodes of a thin film transistor. 49 is a band diagram. In FIG. 49, an In-Ga-Zn- Using an O-based film (IGZO), the oxide semiconductor film is TiO between the drain electrode x However, TiO x The thickness of the film is 0.1 nm or more and 10 nm or less. In, Ga, Zn, etc.), and also the above pair of TiO x Each of the membranes is in contact with The composite layer is made of In-Ga-Zn-O (IGZO) film in the area other than the composite layer. The electron affinity of TiO is 4.3 eV. x The film was connected to the source or drain electrode at 4.3 eV. The Ti layer is shown as 4.1 eV and the composite layer as 4.5 eV. The band position changes so that the Fermi level of the material is aligned. When IGZO is not oxidized, the Fermi level is in the band gap because the number of carriers is small. In the TiOx film and composite layer, the Fermi level is located near the center because of the large number of carriers. Therefore, in Figure 49, the position of the conduction band of each material is determined by the above electron affinity. As shown in Figure 49, the composite layers have almost no difference in electron affinity. Therefore, between the oxide semiconductor film and the source electrode, and between the oxide semiconductor film and the drain electrode, A good connection structure can be achieved. [Explanation of symbols]

[0527] 7 Gate terminal 8 Source terminal 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 20 Gate wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Output terminal 27 Output terminal 30 Display device 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 44 Common wiring 45a Gate wiring 45b Gate wiring 45 Common wiring 46 Common wiring 51 Power line 52 Power line 53 Power line 60 Source wiring 61 period 62 period 65 Common wiring 65a Source wiring 65b Source wiring 66 Conductive layer 71 terminals 74 terminals 75 terminals 81 terminals 84 terminals 85 terminals 91 Gate drive circuit 92 Source driver circuit 93 pixels 94 pixel area 95 Connection 96 Common connection 97 Protection circuit 100 boards 101 insulating film 102 Insulating layer 102a Insulating layer 102b insulating layer 111a Gate wiring 111b Gate wiring 113 Semiconductor layer 115a electrode 115b electrode 115c electrode 117 Insulating Layer 118 Insulating Layer 119 Insulating Film 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Contact Holes 129 Conductive Layer 170a Nonlinear element 170b Nonlinear element 200 boards 201 Insulating layer 202 Gate wiring 203 Gate wiring 204 Insulation layer 204a Insulating layer 204b Insulating layer 205 Semiconductor layer 207 Electrode layer 207a Electrode 207b Electrode 208 Insulating layer 208a Insulating layer 208b Insulating layer 209 Source wiring 210 Source wiring 211 Insulating layer 212 Electrode 213 Holding capacitor wiring 214 Holding capacitor wiring 216 Opening 217 Opening 225 Channel Protection Layer 231 Resist mask 231a Resist mask 231b Resist mask 250 Thin Film Transistors 251 Thin-film transistor 252 Thin-film transistor 253 Thin-Film Transistor 300 boards 351 Gate wiring 351a Gate wiring 351b Gate wiring 352 Electrode 354 Source wiring 354a Source wiring 354b Source wiring 355 Transparent conductive layer 360 Insulation Layer 361 Insulating Layer 362 Insulating Layer 363 Insulating Layer 364 Insulating Layer 365 Insulation Layer 400 boards 401a Gate wiring 401b Gate wiring 403a Semiconductor layer 403b Semiconductor layer 404 Contact Hole 405a electrode 405b electrode 405c electrode 410 Insulating layer 411 Insulating layer 412 Insulating layer 413 Insulating Layer 414 Insulating Layer 415 Insulating Layer 430a Thin-film transistor 430b thin film transistor 580 board 581 Thin-film transistor 582 Insulating layer 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 591 Insulating Layer 592 Insulating layer 594 Cavity 595 Filling material 596 PCB 597 Insulating Layer 598 Insulating Layer 599a Source wiring 599b Source wiring 600 boards 601 Opposing substrate 602 Gate wiring 602a Gate wiring 602b Gate wiring 603 Gate wiring 603a Gate wiring 604 Capacitance wiring 604a Capacitive wiring 604b Capacitive wiring 605 Capacitance wiring 605a Capacitive wiring 605b Capacitive wiring 616 Source wiring 616a Source wiring 616b Source wiring 617 Capacitance wiring 618 Wiring 619 Wiring 622 Insulation Layer 623 Contact Hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 636 Colored film 637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Alignment Film 648 Alignment Film 650 LCD layer 651 Liquid crystal element 652 Liquid crystal element 661 Insulating layer 662 Insulating layer 663 Insulating Layer 664 Insulating Layer 665 Insulation Layer 666 Insulating Layer 690 Capacitance wiring 690a capacitance wiring 690b capacitor wiring 701 PCB 702 Common connection part 704 Sealing material 705 Sealing material 706 PCB 708 Liquid Crystal Layer 710 Thin Film Transistor 711 Thin-film transistor 715 Common connection terminal 716 External terminal 730 pixel electrode 731 Counter electrode 735 Spacer 740 Conductive Layer 742 Interlayer insulating film 780 Furnace 790 Static Electricity 791 routes 801a Gray Tone Mask 801b Halftone Mask 802 Transparent substrate 803 Light blocking part 804 Diffraction Grating 805 Light transmittance 806 Light blocking part 807 Semi-transparent part 808 Light transmittance 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2631 Poster 2632 In-car advertising 2700 e-books 2701 Housing 2703 Housing 2705 Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 Thin Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4035 Spacer 4040 Conductive layer 4041 Insulation layer 4043 Insulation layer 4044 Insulation layer 4045 Insulation layer 4046 Source wiring 4047 Insulation layer 4341 Transistor 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4541 Insulation layer 4542 Insulation layer 4543 Insulation layer 4544 Insulation layer 4545 Insulation layer 4546 Insulation layer 4547 Insulation layer 4548 Source wiring 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin-film transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Light-emitting element driving transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Light-emitting element driving TFT 7002 Light-emitting element 7003 Cathode 7004 EL layer 7005 Anode 7008a Source wiring 7008b Source wiring 7009 Bulkhead 7011 Light-emitting element driving TFT 7012 Light-emitting element 7013 Cathode 7014 EL layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7018a Source wiring 7018b Source wiring 7019 Bulkhead 7021 Light-emitting element driving TFT 7022 Light-emitting element 7023 Cathode 7024 EL layer 7025 Anode 7027 Conductive film 7028a Source wiring 7028b Source wiring 7029 Bulkhead 7030 Drain electrode layer 7031 Insulation layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7036 Insulation layer 7037 Insulation layer 7038 Insulation layer 7039 Insulation layer 7041 Insulation layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7046 Insulation layer 7047 Insulation layer 7048 Insulation layer 7049 Insulation layer 7051 Insulation layer 7052 Insulation layer 7053 Planarization insulating layer 7056 Insulation layer 7057 Insulation layer 7058 Insulation layer 7059 Insulation layer 7061 Light-emitting element driving TFT 7063 Color filter layer 7064 Overcoat layer 7065 Protective insulation layer 7067 Conductive film 7068a Source wiring 7068b Source wiring 7071 Insulation layer 7072 Insulation layer 7076 Insulation layer 7077 Insulation layer 7078 Insulation layer 7079 Insulation layer 9201 Display section 9202 Display button 9203 Operation switch 9204 Band Club 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

[Claim 1] The display device has a pixel portion and a terminal portion on a glass substrate, The terminal section has a function of connecting an external power supply and a gate drive circuit. the pixel portion has a transistor, the transistor includes a first conductive layer on the glass substrate, a first insulating layer on the first conductive layer, and a semiconductor layer on the first insulating layer; the terminal portion includes a second conductive layer on the glass substrate, a third conductive layer on the second conductive layer, a second insulating layer on the third conductive layer, a third insulating layer on the second insulating layer, and a fourth conductive layer on the third insulating layer; the first conductive layer and the second conductive layer comprise copper; the fourth conductive layer has a light-transmitting property, the third conductive layer has a region in contact with an upper surface of the second conductive layer; the fourth conductive layer contacts a side surface of the second insulating layer and a side surface of the third insulating layer; the fourth conductive layer has a region; the fourth conductive layer is electrically connected to the third conductive layer through the region; The region does not overlap the second insulating layer and the third insulating layer, and overlaps the third conductive layer.

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