Receiving device and program

Abstract

To improve a frame synchronization performance, and improve a synchronization tolerance at low C / N.SOLUTION: A receiving device 1 comprises a frame synchronization part 40 including: a first cross-correlation part 407 that derives a first cross-correlation value between an IQ signal and a first reference signal for two slots for each symbol address; a second cross-correlation part 408 that derives a second cross-correlation value between an IQ signal and a second reference signal for two slots for each symbol address; a cyclic delay part 409 that cyclically delays the symbol address of the first cross-correlation value or the second cross-correlation value by the number of symbols of one slot; an accumulation part 410 that accumulates the cross-correlation value with cyclic delay and the cross-correlation value without cyclic delay over a predetermined number of slots to derive a cross-correlation accumulation value; a double interpolation part 411 that interpolates peaks so that peaks of the cross-correlation accumulation value appear for each number of symbols of one slot; and a frame synchronization detection part 412 that detects a symbol address corresponding to the peaks.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a receiving device and a program. [Background technology]

[0002] Among the various standards for digital broadcasting currently in operation, satellite broadcasting is an example in which broadcast wave signals are multiplexed and transmitted using transmitters (satellite repeaters) installed on broadcast satellites so that multiple broadcasters can transmit independent TSs (Transport Streams). ISDB-S3 (see, for example, Non-Patent Document 1) is a known standard that has been adopted for satellite digital broadcasting. Other standards include ISDB-S, DVB-S2, and DVB-S2X.

[0003] Fig. 8 is a diagram showing an example of the configuration of a satellite broadcasting system 100. The satellite broadcasting system 100 shown in Fig. 8 includes a transmitting device 2, a satellite repeater 3 which is an actual satellite, and a plurality of receiving devices 1 (receiving devices 1-1 to 1-N). Note that receiving device 1 will be described as a general receiving device that complies with the ISDB-S3 standard.

[0004] The transmitter 2 converts the generated modulated wave signal into a predetermined frequency band, and then uplinks it to the satellite repeater 3 .

[0005] The satellite repeater 3 is a transmitter that transmits the modulated wave signal sent from the transmitting device 2. The satellite repeater 3 includes an input multiplexer filter (hereinafter referred to as an "IMUX filter") 31, which is an input filter placed before the amplifier, a traveling wave tube amplifier (hereinafter referred to as a "TWTA") 32, and an output multiplexer filter (hereinafter referred to as an "OMUX filter") 33, which is an output filter placed after the amplifier.

[0006] The satellite repeater 3 performs band extraction for each channel from the received broadcast wave signal using the IMUX filter 31, amplifies the power for each channel using the TWTA 32, suppresses unnecessary out-of-band frequency components using the OMUX filter 33, combines the broadcast wave signals for all channels using a subsequent combiner (not shown), and downlinks the broadcast wave signals to multiple receiving devices 1.

[0007] Figure 9 shows the frame structure of a modulated signal conforming to the ISDB-S3 system. One time division multiplexing frame consists of 120 slots. In each slot, a 24-symbol frame synchronization signal and a 32-symbol pilot signal are followed by a 136-symbol main signal and a 4-symbol TMCC (Transmission and Multiplexing Configuration and Control) signal, repeated 66 times. In the figure, the TMCC signal is referred to as "T * "

[0008] In the case of the ISDB-S3 system, there are five modulation methods for the main signal: π / 2 shift BPSK, QPSK, 8PSK, 16APSK, and 32APSK. The pilot signal is linked to the modulation method of the main signal. The TMCC signal contains information related to transmission control, and specifies the modulation method, coding rate, etc. of the main signal. The modulation method for the TMCC signal is π / 2 shift BPSK.

[0009] In the case of the ISDB-S3 system, there are three types of frame synchronization signals: Fsync (0x52F866) located in the first 24 symbols of slot #1, which is the frame start position; Ssync (0x36715A) located in the first 24 symbols of even-numbered slots; and !Fsync (0xAD0799) located in the first 24 symbols of odd-numbered slots excluding slot #1, and the modulation method for these is π / 2 shift BPSK. Fsync and !Fsync have a bit-inverted relationship, and in the IQ signal of π / 2 shift BPSK, they are rotated 180 degrees. [Prior art documents] [Non-patent literature]

[0010] [Non-Patent Document 1] "Transmission Method for Advanced Wideband Satellite Digital Broadcasting (ISDB-S3)", ARIB STD-B44 Version 2.1, Association of Radio Industries and Businesses Summary of the Invention [Problem to be solved by the invention]

[0011] In the conventional method described below, the tolerance of frame synchronization is strengthened by accumulating the cross-correlation value Rn. However, since the comparison of the absolute values of the cross-correlation values Rn of Fsync and Ssync is performed before accumulation, errors in discrimination occur in low C / N transmission systems, and sufficient performance is not achieved.

[0012] The present invention has been made in view of the above circumstances, and aims to improve the frame synchronization performance and to increase the synchronization tolerance at low C / N times. [Means for solving the problem]

[0013] The gist of the present invention for solving the above problems is as follows.

[0014] (1) A receiving device comprising a frame synchronization unit having: a first cross-correlation unit that derives a first cross-correlation value between two slots of IQ signals and a first reference signal that is a known IQ signal for each symbol address; a second cross-correlation unit that derives a second cross-correlation value between the two slots of IQ signals and a second reference signal that is a known IQ signal for each symbol address; a cyclic delay unit that cyclically delays the symbol address of either the first cross-correlation value or the second cross-correlation value by the number of symbols in one slot; an accumulation unit that accumulates the cyclically delayed cross-correlation value and the non-cyclically delayed cross-correlation value over a predetermined number of slots to derive a cross-correlation cumulative value; a double interpolation unit that interpolates peaks so that peaks of the cross-correlation cumulative value appear for each number of symbols in one slot; and a frame synchronization detection unit that detects the symbol address corresponding to the peak.

[0015] (2) A first cross-correlation unit that derives a cross-correlation value between an IQ signal for odd-numbered slots and a first reference signal that is a known IQ signal for each symbol address, and then derives a cross-correlation value between an IQ signal for a subsequent even-numbered slot and a second reference signal that is a known IQ signal for each symbol address; a second cross-correlation unit that derives a cross-correlation value between an IQ signal for the odd-numbered slots and the second reference signal for each symbol address, and then derives a cross-correlation value between an IQ signal for the subsequent even-numbered slot and the first reference signal for each symbol address; a second accumulator that accumulates the cross-correlation values derived by the second cross-correlation unit over the predetermined number of slots to derive a second cross-correlation accumulated value; an absolute value comparator that takes absolute values of the first cross-correlation accumulated value and the second cross-correlation accumulated value and determines the cross-correlation accumulated value having a larger peak value; and a frame synchronization detector that detects a symbol address corresponding to the peak of the cross-correlation accumulated value determined by the absolute value comparator.

[0016] (3) A receiving device according to (1) or (2), comprising: a frequency coarse adjustment unit that estimates and corrects a frequency error using an IQ signal input to the receiving device; a root roll-off filter that performs waveform shaping of the IQ signal input from the frequency coarse adjustment unit; a symbol synchronization unit that performs symbol synchronization by thinning to symbol points while obtaining symbol timing from the IQ signal including non-symbol points input from the root roll-off filter; the frame synchronization unit that performs frame synchronization with the IQ signal for which symbol synchronization has been established; a frequency fine adjustment unit that estimates and corrects a frequency error by comparing the first reference signal and the second reference signal with the IQ signal for which frame synchronization has been established; and a phase correction unit that estimates and corrects a phase error by comparing the reference signal with the IQ signal input from the frequency fine adjustment unit.

[0017] (4) A program for causing a computer to function as the receiving device according to any one of (1) to (3). [Effects of the Invention]

[0018] According to the present invention, it is possible to improve the frame synchronization performance and increase the synchronization tolerance at low C / N times. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 10 is a block diagram showing an example of the configuration of a synchronization unit in a generalized receiving device. [Figure 2] 3 is a block diagram showing an example of the configuration of a frame synchronization unit in the receiving device according to the first embodiment. FIG. [Figure 3] FIG. 2 is a conceptual diagram illustrating processing by a frame synchronization unit in the receiving device according to the first embodiment. [Figure 4] 10 is an example of a simulation result showing frame synchronization performance of a conventional system and the first embodiment. [Figure 5] FIG. 10 is a block diagram showing an example of the configuration of a frame synchronization unit in a receiving device according to a second embodiment. [Figure 6] FIG. 10 is a conceptual diagram illustrating processing by a frame synchronization unit in a receiving device according to a second embodiment. [Figure 7] 10 is an example of a simulation result showing frame synchronization performance in the receiving device according to the second embodiment. [Figure 8] FIG. 1 is a diagram showing a schematic configuration of a satellite broadcasting system via a general satellite repeater. [Figure 9] FIG. 1 is a diagram showing the frame structure of a modulated signal conforming to the ISDB-S3 standard. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of a frame synchronization unit in a conventional receiving device. [Figure 11] FIG. 10 is a conceptual diagram illustrating processing by a frame synchronization unit in a conventional receiving device. [Figure 12] 1 is a diagram illustrating a problem with a frame synchronization unit in a conventional receiving device. DETAILED DESCRIPTION OF THE INVENTION

[0020] The following describes in detail an embodiment of the present invention with reference to the drawings. The receiving device according to this embodiment is based on the ISDB-S3 frame structure, but the present invention can be applied to any transmission system that has multiple types of known signals and has periodicity, and improved synchronization performance can be expected.

[0021] 1 is a block diagram showing an example of the configuration of a synchronization unit in a receiving device 1. The receiving device 1 is a device in which a modulated wave signal modulated by a predetermined modulation method passes through a predetermined transmission path and is demodulated into a predetermined IQ signal. Modulation methods for the predetermined IQ signal include π / 2 shift BPSK, QPSK, 8PSK, 16APSK, 32APSK, etc.

[0022] The receiving device 1 includes a coarse frequency tuning unit 10, a root roll-off filter 20, a symbol synchronization unit 30, a frame synchronization unit 40, a fine frequency tuning unit 50, and a phase correction unit 60.

[0023] The coarse frequency adjustment unit 10 roughly estimates and corrects the frequency error based on the IQ signal input to the receiving device 1, and outputs the result to the root roll-off filter 20. For details, see, for example, Reference 1 below. [Reference 1] IEEE Transact. Comm. vol. 41, no. 6, pp.988-997, June 1993

[0024] The root roll-off filter 20 performs waveform shaping on the IQ signal input from the frequency coarse adjustment unit 10 and outputs the result to the symbol synchronization unit 30 .

[0025] The symbol synchronizer 30 obtains symbol timing from the IQ signal including non-symbol points input from the root roll-off filter 20, thins out the signal to symbol points, and achieves symbol synchronization. The symbol synchronizer 30 outputs the signal after symbol synchronization has been established to the frame synchronizer 40. For details, see, for example, Reference 2 below. [Reference 2] IEEE Transact. Comm. vol. com-34, no. 5, pp.423-429, May 1986

[0026] The frame synchronization unit 40 establishes frame synchronization with the IQ signal for which symbol synchronization has been established by the symbol synchronization unit 30, and outputs the frame-synchronized IQ signal to the frequency fine tuning unit 50. Details will be described later.

[0027] The frequency fine tuning unit 50 estimates and corrects the frequency error by comparing the first reference signal and the second reference signal with an IQ signal (frame-synchronized IQ signal) in which frame synchronization corresponding to the time division is established, and outputs the result to the phase correction unit 60.

[0028] The phase corrector 60 estimates and corrects the phase error by comparing the reference signal with the IQ signal after frequency fine adjustment corresponding to the time division.

[0029] <Frame synchronization processing> Regarding the processing by the frame synchronization unit 40, a conventional frame synchronization unit 40' will first be described for comparison with the present invention.

[0030] Fig. 10 is a block diagram showing an example of the configuration of a conventional frame synchronization unit 40' that takes into account the frame structure of the ISDB-S3 system shown in Fig. 9. Fig. 11 is a conceptual diagram showing the operation of frame synchronization unit 40' using a frame structure. Frame synchronization unit 40' includes first cross-correlation unit 401, second cross-correlation unit 402, absolute value comparison unit 403, accumulator 404, frame synchronization detection unit 405, and delay correction unit 406.

[0031] The first cross-correlation unit 401 derives a first cross-correlation value (cross-correlation coefficient) between the input IQ signal input from the symbol synchronization unit 30 and a first reference signal (Fsync) that is a known IQ signal for each symbol address, and outputs the value to the absolute value comparison unit 403. The second cross-correlation unit 402 derives a second cross-correlation value between the input IQ signal input from the symbol synchronization unit 30 and a second reference signal (Ssync) that is a known IQ signal for each symbol address, and outputs the value to the absolute value comparison unit 403.

[0032] At this time, the IQ signal is swept over 9296 symbols equivalent to one slot to obtain the cross-correlation characteristics. That is, the horizontal axis of the cross-correlation characteristics is the symbol address n from 1 to 9296, and the vertical axis of the cross-correlation characteristics is the cross-correlation value Rn(s) derived by the following formula (1). Here, x is the input IQ signal, c is the reference signal, s is the slot address, L is the number of symbols of the frame synchronization signal, * indicates the complex conjugate. There are three types of frame synchronization signals in the ISDB-S3 system, as shown in Figure 9. * After multiplication, Fsync = !Fsync, so the result is a distinction between two types: Fsync and Ssync. Furthermore, L is the number of symbols in the frame synchronization signal, which is 24.

[0033]

number

[0034] Absolute value comparison section 403 takes the absolute values of the first cross-correlation value input from first cross-correlation section 401 and the second cross-correlation value input from second cross-correlation section 402, and compares their peak values (real numbers). Absolute value comparison section 403 then determines the one with the larger peak value as the correct reference signal, and outputs the corresponding cross-correlation value (complex number) to accumulation section 404.

[0035] The accumulator 404 accumulates the cross-correlation values input from the absolute value comparator 403 to obtain a cross-correlation accumulated value An. The cross-correlation accumulated value An is derived from the following equation (2). Here, N indicates the number of accumulations, and T indicates the number of symbols to be swept. The larger the value of N, the more likely it is that white noise will converge to 0, making it easier for the cross-correlation value to peak. In other words, increasing the value of N is an effective measure in a low C / N transmission system.

[0036]

number

[0037] The frame synchronization detection unit 405 detects the symbol address corresponding to the peak of the cross-correlation cumulative value An (real number) from the characteristics of the cross-correlation cumulative value An input from the accumulator 404 , and outputs it to the delay correction unit 406 .

[0038] The delay correction unit 406 performs delay correction on the original input IQ signal, and the frame synchronization process is completed.

[0039] 12 is a diagram illustrating the problems with the conventional frame synchronization unit 40'. As described above, the frame synchronization unit 40' compares the absolute values of the cross-correlation values Rn with Fsync and Ssync using absolute value comparison unit 403 before accumulation by accumulator 404. Accumulating the cross-correlation values Rn strengthens the tolerance of frame synchronization, but because the determination of Fsync or Ssync is made before accumulation, errors can occur in the determination by absolute value comparison unit 403, particularly in a low C / N transmission system, and sufficient performance cannot be achieved.

[0040] First Embodiment Next, the frame synchronization unit 40 in the receiving device 1 according to the first embodiment will be described in terms of the differences from a conventional frame synchronization unit 40'.

[0041] Fig. 2 is a block diagram showing an example configuration of frame synchronization unit 40. Fig. 3 is a conceptual diagram showing the operation of frame synchronization unit 40 using a frame configuration. Frame synchronization unit 40 includes first cross-correlation unit 407, second cross-correlation unit 408, cyclic delay unit 409, accumulation unit 410, double interpolation unit 411, frame synchronization detection unit 412, and delay correction unit 406.

[0042] The first cross-correlation unit 407 derives the first cross-correlation value between the IQ signal for two slots input from the symbol synchronization unit 30 and the first reference signal (Fsync), which is a known IQ signal, for each symbol address and outputs it to the cyclic delay unit 409.

[0043] The second cross-correlation unit 408 derives the second cross-correlation value between the IQ signal for two slots input from the symbol synchronization unit 30 and a second reference signal (Ssync), which is a known IQ signal, for each symbol address and outputs it to the accumulation unit 410.

[0044] The cyclic delay unit 409 cyclically delays the symbol address of either the first cross-correlation value or the second cross-correlation value by the number of symbols in one slot (9296 symbols), and outputs the result to the accumulator 410. In this embodiment, the first cross-correlation value is cyclically delayed. In a two-slot IQ signal, the interval between frame synchronization signals is 9296 symbols, and therefore the interval between the peak position of the first cross-correlation value and the peak position of the second cross-correlation value is also 9296 symbols. Therefore, by cyclically delaying one of the cross-correlation values by 9296 symbols within two slots, it is expected that the peaks will appear at the same symbol address. The cyclic delay means that if a delay of 9296 symbols would exceed 18592, the count will start again from 1.

[0045] The accumulation unit 410 accumulates the cross-correlation value input from the cyclic delay unit 409 and the second cross-correlation value input from the second cross-correlation unit 408 over a predetermined number of slots to derive a cross-correlation accumulated value, and outputs it to the double interpolation unit 411.

[0046] Double interpolation section 411 interpolates the peaks of the cross-correlation cumulative value input from accumulator 410 so that the peaks appear every number of symbols in one slot, and outputs the result to frame synchronization detection section 412. That is, since the peak positions of the cross-correlation cumulative value occur at intervals of the number of symbols for two slots (18,592 symbols), interpolation is performed so that the peaks appear at intervals of 9,296 symbols.

[0047] The frame synchronization detector 412 detects the symbol address corresponding to the peak of the cross-correlation cumulative value input from the double interpolator 411 and outputs it to the delay corrector 406 .

[0048] The delay correction unit 406 adjusts the timing of the symbol position in the slot based on the symbol address detected by the frame synchronization detection unit 412 .

[0049] In this way, frame synchronization according to the present invention utilizes the property that Fsync and Ssync alternately appear for each slot in the ISDB-S3 system, and distinguishes between them after accumulation. In the first embodiment, the number of sweep symbols for deriving the cross-correlation is set to 18,592, which is equivalent to two slots, and then the first cross-correlation value (complex number) and the second cross-correlation value (complex number) are derived in the same manner as in the conventional method (see equation (1)). In the conceptual diagram shown in Figure 3, the first cross-correlation value is Rn(1)_f to Rn(s-1)_f, and the second cross-correlation value is Rn(1)_s to Rn(s-1)_s.

[0050] Here, it is clear from the above properties that the symbol addresses of the peak positions that are the correct solutions for the first cross-correlation value and the second cross-correlation value are spaced 9296 symbols apart, so if the horizontal axis of either cross-correlation characteristic is shifted by 9296 symbols and then accumulated, the result will be the same as using both Fsync and Ssync. In the first embodiment, both the first cross-correlation value cyclically delayed by 9296 symbols and the second cross-correlation value are accumulated (see equation (2)).

[0051] FIG. 4 shows an example of a simulation result demonstrating that frame synchronization performance is improved by the receiver 1 according to the first embodiment. The system configuration of the first embodiment is as shown in FIG. 8, and is an ideal transmission path free from the effects of nonlinear distortion, etc., due to the satellite repeater 3. The transmitter 2 and receiver 1 are assumed to conform to the ISDB-S3 standard, and the frame synchronization performance of the receiver 1 was compared between a conventional system and a system proposed by the present invention. The common transmission signal parameters were set as follows: π / 2-shift BPSK for the main signal, a symbol rate of 33.7561 Mbaud, a roll-off factor of 0.03, and a frequency offset from transmission to reception of 1.5 MHz. The uplink C / N ratio was set to ∞, and the downlink C / N ratio was varied, decreasing in 1 dB steps. The frame synchronization limit C / N was used as the limit C / N for correct symbol address detection, and the results were compared. Regarding the cumulative number of times, the conventional type is 20 times, while the proposed type is 10 times to sweep symbols for twice the number of slots (N in equation (2) is 20 and 10, respectively), and the total number of symbols used is the same.

[0052] Figure 4(a) shows the simulation results of the frame synchronization unit 40'. In this example, the correct peak is at symbol address 1. However, when comparing this peak from the absolute values of the first cross-correlation value and the second cross-correlation value, an incorrect determination may occur. This error is particularly noticeable at low C / N ratios, with the accuracy rate of determination at around 50% when C / N is around -7 dB. Even if only correct cross-correlation values are accumulated, the performance is limited to about 10 accumulations. Therefore, when the C / N is reduced in 1 dB increments, peak values can be detected up to C / N = -5 dB but become undetectable at C / N = -6 dB.

[0053] FIG. 4(b) shows the simulation results of the frame synchronization unit 40. In this example, the correct answer is that the peak occurs at symbol address 9297. While the conventional frame synchronization limit C / N is -5 dB, the frame synchronization limit C / N of this embodiment has been improved to -9 dB. From the above results, it is clear that the configuration of this embodiment is advantageous in terms of improving the synchronization performance of the receiving device 1. Furthermore, as a result of strengthening the tolerance of frame synchronization by the frame synchronization unit 40, the performance of frequency fine tuning and phase correction in stages subsequent to the frame synchronization unit 40 is also improved, improving the synchronization performance of the receiving device 1 as a whole.

[0054] <Second embodiment> Next, the frame synchronization unit 40a in the receiving device 1 according to the second embodiment will be described.

[0055] Fig. 5 is a block diagram showing an example of the configuration of frame synchronization unit 40a. Fig. 6 is a conceptual diagram showing the operation of frame synchronization unit 40a using a frame configuration. Frame synchronization unit 40a includes a timing adjustment unit 413, a first cross-correlation unit 414, a second cross-correlation unit 415, a first accumulator 416, a second accumulator 417, an absolute value comparison unit 418, a frame synchronization detection unit 419, and a delay correction unit 406.

[0056] The timing adjustment unit 413 adjusts the timing so that alternate reference can be made on a slot-by-slot basis, so that the first cross-correlation unit 414 references a first reference signal (Fsync) in the first slot and a second reference signal (Ssync) in the next slot in chronological order. The timing adjustment unit 413 also adjusts the timing so that alternate reference can be made on a slot-by-slot basis, so that the second cross-correlation unit 415 references a second reference signal (Ssync) in the first slot and a first reference signal (Fsync) in the next slot in chronological order. At the same time, the timing adjustment unit 413 adjusts the timing so that the reference signals of the first cross-correlation unit 414 and the second cross-correlation unit 415 are inverted in chronological order.

[0057] When all IQ signals input from the symbol synchronization unit 30 are divided into slot units (9296 symbols) starting from the first symbol, the first cross-correlation unit 414 derives cross-correlation values between the IQ signals for odd-numbered slots and the first reference signal (Fsync) for each symbol address, and then derives cross-correlation values between the IQ signals for the subsequent even-numbered slots and the second reference signal (Ssync) for each symbol address. The first cross-correlation unit 414 derives cross-correlation values for all slots in that order.

[0058] When all IQ signals input from the symbol synchronization unit 30 are divided into slot units (9296 symbols) starting from the first symbol, the second cross-correlation unit 415 derives the cross-correlation value between the IQ signals for odd-numbered slots and the second reference signal (Ssync) for each symbol address, and then derives the cross-correlation value between the IQ signals for the subsequent even-numbered slots and the first reference signal (Fsync) for each symbol address. The second cross-correlation unit 415 derives the cross-correlation values for all slots in that order.

[0059] The first accumulator 416 accumulates the cross-correlation values input from the first cross-correlation unit 414 over a predetermined number of slots to derive a first cross-correlation accumulated value, and outputs it to the absolute value comparator 418 .

[0060] Second accumulator 417 accumulates the cross-correlation values input from second cross-correlation unit 415 over a predetermined number of slots to derive a second cross-correlation accumulated value, and outputs this to absolute value comparator 418 .

[0061] The absolute value comparison unit 418 takes the absolute values of the first cross-correlation cumulative value input from the first accumulator 416 and the second cross-correlation cumulative value input from the second accumulator 417, determines the cross-correlation cumulative value with the larger peak value, and outputs it to the frame synchronization detection unit 419.

[0062] The frame synchronization detector 419 detects the symbol address corresponding to the peak of the cross-correlation cumulative value input from the absolute value comparator 418 .

[0063] The delay correction unit 406 adjusts the timing of the symbol position in the slot based on the symbol address detected by the frame synchronization detection unit 419 .

[0064] As described above, in the frame synchronization according to the second embodiment, similarly to the first embodiment, the property that Fsync and Ssync alternately appear in each slot in the ISDB-S3 system is utilized, and discrimination is performed after accumulation. However, the number of sweep symbols is 9296, as in the conventional method. Cross-correlation values (complex numbers) are derived in the slot order of the cross-correlation between the input IQ signal and the reference signal (Fsync), and then the cross-correlation between the input IQ signal and the reference signal (Ssync) of the next slot (see equation (1)). Furthermore, cross-correlation values (complex numbers) are derived in the reverse slot order of the cross-correlation between the input IQ signal and the reference signal (Ssync), and then the cross-correlation between the input IQ signal and the reference signal (Fsync) of the next slot (see equation (1)). Then, each cross-correlation value is accumulated (see equation (2)).

[0065] In the conceptual diagram shown in Fig. 6, the cross-correlation cumulative value An_fs calculated by the first accumulator 416 is compared with the cross-correlation cumulative value An_sf calculated by the second accumulator 417 for determination. In the example of Fig. 6, the accuracy rate of An_fs is 100%, and the accuracy rate of An_sf is 0%, so the comparison is always 100% or 0%, which means that the probability of error is lower than in the past, and there is correlation between all the accumulated counts, so performance can be improved. Furthermore, compared to the first embodiment, all processing is 9296 symbol sweeps, so hardware simplification can be expected.

[0066] FIG. 7 shows an example of a simulation result demonstrating the improvement in frame synchronization performance of the receiving device 1 according to the second embodiment. The system and transmission parameters of the second embodiment were set to the same values as those of the first embodiment, the downlink C / N ratio was reduced in 1 dB steps, and the limit C / N ratio for correct symbol address detection was defined as the frame synchronization limit C / N ratio. The cumulative number of runs was set to 20 (N=20 in Equation (2)), as in the conventional system. In this example, the peak at the first symbol address is correct. According to the simulation results shown in FIG. 7, the frame synchronization limit C / N ratio was −9 dB, demonstrating the same performance improvement as in the first embodiment. These results clearly demonstrate that the configuration of this embodiment is advantageous in terms of improving the synchronization performance of the receiving device 1. Furthermore, as a result of the enhanced frame synchronization tolerance provided by the frame synchronization unit 40a, the performance of frequency fine tuning and phase correction downstream of the frame synchronization unit 40a is also improved, thereby improving the synchronization performance of the receiving device 1 as a whole.

[0067] <Program> A computer capable of executing program instructions can also be used to function as the above-described receiving device 1. Here, the computer may be a general-purpose computer, a dedicated computer, a workstation, a PC (Personal Computer), a mobile terminal, etc. The program instructions may be program code, code segments, etc. for performing the necessary tasks.

[0068] The computer includes a processor, a storage unit, an input unit, an output unit, and a communication interface. The processor may be a CPU (Central Processing Unit), an MPU (Micro Processing Unit), a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), an SoC (System on a Chip), or the like, and may be configured with multiple processors of the same or different types. The processor reads and executes programs from the storage unit to control the above components and perform various arithmetic processing. Note that at least a portion of these processing contents may be implemented by hardware. The input unit is an input interface that accepts user input operations and acquires information based on the user operations, such as a pointing device, keyboard, or microphone. The output unit is an output interface that outputs information, such as a display or speaker. The communication interface is an interface for communicating with external devices.

[0069] The program may be recorded on a computer-readable recording medium. Using such a recording medium, the program can be installed on a computer. Here, the recording medium on which the program is recorded may be a non-transitory recording medium. The non-transitory recording medium is not particularly limited, and may be, for example, a CD-ROM, a DVD-ROM, or a USB (Universal Serial Bus) memory. Furthermore, the program may be downloaded from an external device via a network.

[0070] The above-described receiving device 1 may be configured with one or more semiconductor chips. The semiconductor chip may be equipped with a CPU that executes a program that describes the processing content for realizing each function of the receiving device 1.

[0071] Although the above-described embodiments have been described as typical examples, it will be apparent to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited by the above-described embodiments, and various modifications or alterations can be made without departing from the scope of the claims. For example, it is possible to integrate multiple building blocks shown in the block diagrams of the embodiments, or to divide one building block. [Explanation of symbols]

[0072] 1. Receiving device 2. Transmitting device 3 Satellite repeater 10 Coarse frequency tuning section 20 Root Roll-Off Filter 30 Symbol Synchronization Unit 31 IMUX Filter 32 TWTA 33 OMUX filter 40, 40a Frame synchronization section 50 Frequency fine adjustment section 60 Phase correction section 100 Satellite Broadcasting System 406 Delay Correction Unit 407,414 First cross-correlation section 408,415 Second cross-correlation section 409 Cyclic Delay Unit 410 Accumulation Division 411 2x interpolation section 412,419 Frame synchronization detector 413 Timing adjustment unit 416 First Cumulative Division 417 Second Cumulative Division 418 Absolute value comparison unit

Claims

1. a first cross-correlation unit that derives a first cross-correlation value between an IQ signal for two slots and a first reference signal that is a known IQ signal for each symbol address; a second cross-correlation unit that derives a second cross-correlation value between the IQ signals for the two slots and a second reference signal that is a known IQ signal for each symbol address; a cyclic delay unit that cyclically delays the symbol address of either the first cross-correlation value or the second cross-correlation value by the number of symbols in one slot; an accumulator that accumulates the cyclically delayed cross-correlation value and the non-cyclically delayed cross-correlation value over a predetermined number of slots to derive a cross-correlation accumulated value; a double interpolation unit that interpolates the peaks so that the peaks of the cross-correlation cumulative values appear for each number of symbols in one slot; a frame synchronization detector for detecting a symbol address corresponding to the peak; A receiving device comprising a frame synchronization unit having the following:

2. a first cross-correlation unit that derives a cross-correlation value between an IQ signal for odd-numbered slots and a first reference signal that is a known IQ signal for each symbol address, and then derives a cross-correlation value between an IQ signal for subsequent even-numbered slots and a second reference signal that is a known IQ signal for each symbol address; a second cross-correlation unit that derives a cross-correlation value between the IQ signal for the odd-numbered slots and the second reference signal for each symbol address, and then derives a cross-correlation value between the IQ signal for the subsequent even-numbered slots and the first reference signal for each symbol address; a first accumulator that accumulates the cross-correlation values derived by the first cross-correlation unit over a predetermined number of slots to derive a first cross-correlation accumulated value; a second accumulator that accumulates the cross-correlation values derived by the second cross-correlation unit over the predetermined number of slots to derive a second cross-correlation accumulated value; an absolute value comparison unit that takes absolute values of the first cross-correlation cumulative value and the second cross-correlation cumulative value and determines the cross-correlation cumulative value having a larger peak value; a frame synchronization detector for detecting a symbol address corresponding to the peak of the cross-correlation cumulative value determined by the absolute value comparator; A receiving device comprising a frame synchronization unit having the following:

3. a frequency coarse adjustment unit that estimates and corrects a frequency error based on an IQ signal input to the receiving device; a root roll-off filter that performs waveform shaping on the IQ signal input from the frequency coarse adjustment unit; a symbol synchronization unit that performs symbol timing from the IQ signal including non-symbol points input from the root roll-off filter, decimating the IQ signal to symbol points, and performing symbol synchronization; the frame synchronization unit that performs frame synchronization on the IQ signal for which the symbol synchronization has been established; a frequency fine tuning unit that estimates and corrects a frequency error by comparing the first reference signal and the second reference signal with the IQ signal for which frame synchronization has been established; a phase correction unit that estimates and corrects a phase error by comparing the reference signal with the IQ signal input from the frequency fine tuning unit; 3. The receiving device according to claim 1, comprising:

4. A program for causing a computer to function as the receiving device according to claim 1 or 2.

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