Method and system for formation of stabilized tetragonal barium titanate

Abstract

To achieve a high EO effect in an EO device (for example, an optical switch or an optical modulator) at a low temperature such as a cryogenic temperature.SOLUTION: An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers, a waveguide core adjacent to the layer stack, a waveguide cladding layer, and a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 62 / 927,373, filed October 29, 2019, for "Method and System for Forming Stabilized Tetragonal Barium Titanate," which is incorporated herein by reference in its entirety. [Background technology]

[0002] Electro-optic (EO) devices, such as EO modulators and switches, have been used in various optical systems, such as optical communication and optical computing systems. For example, optical phase modulators can be used in integrated optical systems, optical communication transmitters or transceivers, and the like. EO modulators or switches can utilize various EO effects, such as free-carrier electrorefraction, free-carrier electroabsorption, the Pockels effect, and the Kerr effect, to modify optical properties during operation, such as changing the phase or amplitude of light propagating through a specific path within the EO modulator or switch. EO devices using materials with higher EO effects can operate with lower control voltages, lower power consumption, and often at higher speeds. Summary of the Invention

[0003] The technology disclosed herein generally relates to electro-optical (EO) devices. More specifically, embodiments disclosed herein relate to techniques for achieving high EO effects in EO devices (e.g., optical switches or optical modulators) at low temperatures, such as cryogenic temperatures. In one particular embodiment, an EO device including an EO material stack characterized by a high electro-optic coefficient at low temperatures (e.g., cryogenic temperatures) is utilized to improve the modulation and / or switching performance of the EO device at low temperatures. The EO material stack can include interleaved and interlocked thin EO material layers and interlayers. While the EO material in the EO material layer can change its crystal structure at different operating temperatures when used in bulk, the interlayer can have a lattice structure that does not change with operating temperature. Thus, the thin EO material layers interlocked with the interlayer can maintain their lattice structure, and therefore the EO coefficient, as the operating temperature changes. The technology disclosed herein can be used in a wide variety of photonic and optoelectronic devices operating at low temperatures.

[0004] According to certain embodiments, an electro-optic device may include a substrate and a waveguide on the substrate. The waveguide may include a stack including multiple electro-optic material layers interleaved with multiple intermediate layers. The waveguide may also include a waveguide core adjacent to the stack, a waveguide cladding layer, and a pair of electrodes in electrical contact with the multiple electro-optic material layers. The multiple intermediate layers may be configured to maintain a first lattice structure at room temperature and cryogenic temperatures. The multiple electro-optic material layers may maintain a second lattice structure and crystalline phase at room temperature and cryogenic temperatures. In some embodiments, the multiple intermediate layers and the multiple electro-optic material layers may be characterized by a square lattice structure at cryogenic temperatures. In some embodiments, the multiple electro-optic material layers may be characterized by in-plane polarization at cryogenic temperatures.

[0005] In some embodiments of the electro-optic device, the plurality of electro-optic material layers may include ferroelectric crystals or ferroelectric thin films. The ferroelectric crystals may include at least one of BaTiO3, (Ba,Sr)TiO3, Pb(Zr,Ti)O3, or (Pb,La)(Zr,Ti)O3. In some embodiments, the plurality of electro-optic material layers may be characterized by a Pockels coefficient greater than 300 pm / V at cryogenic temperatures. The plurality of intermediate layers may include at least one of MgO, LaAlO3, (Ba,Sr)TiO3, BaHfO3, BaMoO3, BaNbO3, BaZrO3, SrHfO3, SrTiO3, SrMoO3, SrNbO3, or SrZrO3. In some embodiments, the ratio between the thickness of each of the plurality of electro-optic material layers and the thickness of each of the plurality of intermediate layers may be 20:1 or less.

[0006] In some embodiments of the electro-optic device, the waveguide core may include one or more electro-optic material layers within the plurality of electro-optic material layers. The waveguide cladding layer may be in physical contact with an electro-optic material layer within the plurality of electro-optic material layers and may be characterized by a thermal expansion coefficient and an optical refractive index different from those of the electro-optic material layer. The waveguide cladding layer may include, for example, at least one of Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, SiOCN, and HfO2.

[0007] In some embodiments, the EO device may further include an epitaxial seed layer between the substrate and the waveguide. The epitaxial seed layer may include, for example, at least one of MgO, LaAlO3, BaHfO3, BaZrO3, SrHfO3, SrTiO3, SrMoO3, and SrZrO3. In some embodiments, the EO device may further include a buffer layer between the epitaxial seed layer and the substrate. Each of the pair of electrodes may be in physical contact with each of the multiple electro-optic material layers. In some embodiments, a waveguide cladding layer may be between the substrate and the stack. The waveguide may be a section of a Mach-Zehnder interferometer, a resonator, an optical switch, an electro-optic modulator, or the like.

[0008] According to certain embodiments, the wafer may include a substrate and a stack on the substrate. The stack may include multiple electro-optic material layers and multiple intermediate layers interleaved with the multiple electro-optic material layers. The multiple intermediate layers may maintain a first lattice structure at room temperature and cryogenic temperatures, and the multiple electro-optic material layers may maintain a second lattice structure and crystalline phase at room temperature and cryogenic temperatures. In some embodiments, the first lattice structure and the second lattice structure may be the same lattice structure, such as a square lattice structure. In some embodiments, the wafer may also include an epitaxial seed layer between the substrate and the stack, in which case the epitaxial seed layer may include at least one of MgO, LaAlO3, BaHfO3, BaZrO3, SrHfO3, SrTiO3, or SrZrO3. In some embodiments, the wafer may also include an oxide layer of the substrate between the epitaxial seed layer and the substrate.

[0009] In some embodiments of the wafer, the plurality of electro-optic material layers may include at least one of BaTiO3, (Ba,Sr)TiO3, Pb(Zr,Ti)O3, or (Pb,La)(Zr,Ti)O3. The plurality of intermediate layers may include at least one of MgO, LaAlO3, (Ba,Sr)TiO3, BaHfO3, BaZrO3, SrHfO3, SrZrO3, or SrNbO3. In some embodiments, the ratio between the thickness of each of the plurality of electro-optic material layers and the thickness of each of the plurality of intermediate layers may be 20:1 or less.

[0010] According to certain embodiments, a method can include depositing a seed layer on a substrate; epitaxially depositing a first electro-optic material layer on the seed layer; annealing the substrate, seed layer, and first electro-optic material layer in an oxygen environment to form an oxide buffer layer between the substrate and the seed layer; depositing a first intermediate layer on the first electro-optic material layer, the first intermediate layer including a material capable of maintaining a first lattice structure at room temperature and at cryogenic temperatures; depositing a second electro-optic material layer on the first intermediate layer; and annealing the second electro-optic material layer and the first intermediate layer. The first electro-optic material layer and the second electro-optic material layer can include electro-optic materials characterized by a second lattice structure at cryogenic temperatures that is different from a third lattice structure at room temperature. In some embodiments, the third lattice structure and the first lattice structure can be the same lattice structure, such as a square lattice structure. In some embodiments, the ratio between the thickness of the first electro-optic material layer and the thickness of the first intermediate layer can be 20:1 or less.

[0011] In some embodiments, annealing the substrate, the seed layer, and the first electro-optic material layer may include annealing at a temperature higher than a softening temperature of the oxide buffer layer. The method may also include depositing a second intermediate layer on the second electro-optic material layer, the second intermediate layer including a material that maintains the first lattice structure at room temperature and cryogenic temperatures, depositing a third electro-optic material layer on the second intermediate layer, and annealing the third electro-optic material layer and the second intermediate layer.

[0012] In some embodiments, the method may include patterning the third electro-optic material layer to form a waveguide core and depositing a dielectric cladding layer on the waveguide core. Patterning the third electro-optic material layer may include etching the third electro-optic material layer using the second intermediate layer as an etch stop. In some embodiments, the method may include etching trenches in the first, second, and third electro-optic material layers and the first and second intermediate layers, and filling the trenches with a conductive material. Etching the trenches may include etching the first, second, and third electro-optic material layers using an oxide buffer layer as an etch stop.

[0013] In some embodiments, the method may include forming a waveguide on the third electro-optic material layer. In some embodiments, forming a waveguide on the third electro-optic material layer may include forming a waveguide core on the third electro-optic material layer and depositing a dielectric cladding layer on the waveguide core. In some embodiments, forming a waveguide core on the third electro-optic material layer may include depositing a layer of high refractive index material on the third electro-optic material layer and patterning the layer of high refractive index material. In some embodiments, forming a waveguide core on the third electro-optic material layer may include depositing a dielectric layer on the third electro-optic material layer, depositing a layer of high refractive index material on the dielectric layer, and patterning the layer of high refractive index material. In some embodiments, forming a waveguide on the third electro-optic material layer may include bonding a wafer including the waveguide to the third electro-optic material layer.

[0014]

[0014] The present disclosure achieves many advantages over the prior art. For example, the example methods, devices, and systems disclosed herein can preserve the lattice structure, and therefore the EO coefficients (e.g., the tetragonal phase and Pockels coefficients of BaTiO3) of ferroelectric materials at low temperatures, such as cryogenic temperatures, thereby improving the performance of EO devices, such as EO switches or EO modulators, at cryogenic temperatures. In this manner, reduced electric fields or bias signals can be used to achieve the refractive index modulation and / or phase modulation desired for optical modulation or switching, thereby reducing power consumption and improving device efficiency and / or speed. Furthermore, the embodiments disclosed herein enable greater changes in the effective refractive index at lower temperatures than using prior art techniques. As a result, device lengths can be shortened, thereby reducing optical losses and the physical dimensions of the EO device. These and other embodiments, along with many of their advantages and features, are described in more detail below in conjunction with the text and accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1A] 1 is a simplified diagram illustrating an example of an optical switch including a Mach-Zehnder interferometer in accordance with certain embodiments. [Figure 1B] 1B is a cross-sectional view of an example of a phase adjustment section of one implementation of the optical switch shown in FIG. 1A according to certain embodiments. [Figure 2] 1 shows effective Pockels coefficients in ABO3 perovskite crystals (eg, BaTiO3 crystals) with different crystal lattice orientations at temperatures from about 4 K to about 340 K, according to certain embodiments. [Figure 3A] 1 illustrates the phase transitions of BaTiO3 at different temperatures according to certain embodiments. [Figure 3B] 1 illustrates the phase transitions of BaTiO3 at different temperatures according to certain embodiments. [Figure 3C] 1 illustrates the phase transitions of BaTiO3 at different temperatures according to certain embodiments. [Figure 3D] 1 illustrates the phase transitions of BaTiO3 at different temperatures according to certain embodiments. [Figure 4] 1 is a simplified flowchart illustrating an example method for fabricating an EO device including an EO material layer characterized by a substantially constant EO coefficient from room temperature to cryogenic temperatures, according to certain embodiments. [Figure 5A] 1 illustrates an example of a substrate having a seed layer grown thereon, according to certain embodiments. [Figure 5B] 4 illustrates the internal stress and crystal lattice orientation of a layer of ferroelectric material epitaxially deposited on a seed layer, according to certain embodiments. [Figure 5C] 4 illustrates the internal stress and crystal lattice orientation of a layer of ferroelectric material epitaxially deposited on a seed layer after high temperature oxidation annealing, according to certain embodiments. [Figure 5D] 1 illustrates the internal stress and crystal lattice orientation of layers of ferroelectric material interleaved with intermediate layers in a processed wafer, according to certain embodiments. [Figure 5E] 1 illustrates the internal stress and crystal lattice orientation of layers of ferroelectric material interleaved with intermediate layers in a waveguide structure, according to certain embodiments. [Figure 6]10 illustrates the improved crystalline quality after annealing as indicated by ion channeling in an example epitaxial layer before and after annealing, according to certain embodiments. [Figure 7] 1 shows example X-ray diffraction data illustrating heterophase lattice constant relaxation in an example epitaxial layer at high temperatures, according to certain embodiments. [Figure 8] 1 is a simplified cross-sectional view of an example of a waveguide structure including an EO material layer that maintains the tetragonal phase at cryogenic temperatures, in accordance with certain embodiments. [Figure 9] 1 is a simplified cross-sectional view of another example of a waveguide structure including an EO material layer that maintains the tetragonal phase at cryogenic temperatures, in accordance with certain embodiments. [Figure 10] 1 is a simplified cross-sectional view of yet another example of a waveguide structure including an EO material layer that maintains the tetragonal phase at cryogenic temperatures, in accordance with certain embodiments. [Figure 11] 1 is a simplified flowchart illustrating an example method for fabricating processed wafers and / or EO devices including an EO material layer characterized by a substantially constant EO coefficient from room temperature to cryogenic temperatures, according to certain embodiments. [Figure 12] FIG. 1 is a simplified system block diagram of an example hybrid quantum computing system including an electro-optical device, according to certain embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0016]

[0031] The technology disclosed herein generally relates to electro-optical (EO) devices. More specifically, embodiments disclosed herein relate to techniques for achieving high EO effects in EO materials (e.g., ferroelectric materials) at low temperatures, such as cryogenic temperatures, and utilizing the high EO effects of EO materials in EO devices, such as optical modulators and switches, to reduce power consumption and improve efficiency and speed during operation of the EO devices at low temperatures. By way of example only, embodiments are provided in the context of integrated optics, including active optical devices, but the technology disclosed herein is not limited to this example and is broadly applicable to a variety of optical and optoelectronic systems. Various embodiments of the invention, including methods, processes, materials, wafers, systems, devices, and the like, are described herein.

[0017]

[0032] EO devices using materials with higher EO effects can operate at lower control voltages, lower power consumption, and higher speeds than devices using materials with relatively low EO coefficients. In some applications, such as linear optical quantum computing applications, EO devices can operate at very low temperatures, such as cryogenic temperatures (e.g., about 4 K). The EO effects, such as the Pockels coefficients, of some EO materials can be significantly degraded at low temperatures. For example, BaTiO 3( BTO can be used in electro-optical switches due to its high Pockels coefficient (e.g., greater than about 900 picometers / V at room temperature) and compatibility with silicon CMOS processes. However, the Pockels coefficient of BTO at about 4 K can decrease to less than about one-third of the Pockels coefficient at room temperature. Therefore, the efficiency of electro-optical switches can decrease significantly at cryogenic temperatures. As defined herein, room temperature is defined as a temperature of about 20°C, more specifically, a temperature between 18°C and 22°C. As defined herein, cryogenic temperatures are defined as temperatures below −150°C, more specifically, a temperature between −150°C and −273°C.

[0018]

[0033] According to certain embodiments, it is determined that the decrease in the EO effect (e.g., the Pockels coefficient) of some EO materials at low temperatures can be caused by a crystalline phase transition of the EO material's crystal lattice at different temperatures. For example, BTO can undergo a crystalline phase transition from a tetragonal phase at room temperature to an orthorhombic phase below room temperature, and then to a rhombohedral phase toward cryogenic temperatures. The crystalline phase transition from the tetragonal phase to the rhombohedral phase can contribute to the decrease in the Pockels effect from room temperature to cryogenic temperatures. Therefore, according to certain embodiments, the EO effect of an EO material can be maintained at a high level (e.g., a level close to that at room temperature) at low temperatures by maintaining the tetragonal lattice structure of the EO material at low temperatures. In some embodiments, this can be achieved, for example, by interlocking a thin layer of EO material with an interlayer that does not undergo a lattice structure (or crystalline phase) change and polarization change or that undergoes a crystalline phase transition at a temperature different from that of the EO material when the operating temperature is decreased from room temperature to cryogenic temperatures, thereby preventing the crystalline phase transition of the EO material. The interlayer can help maintain stress within the EO material and prevent the EO material layer from changing its lattice structure and polarization as the operating temperature decreases. As a result, the EO coefficient of the EO material can be maintained at a level close to that at room temperature. Therefore, EO devices including interleaved structures can maintain high efficiency and speed at cryogenic temperatures.

[0019]

[0034] According to certain embodiments, the active photonic devices described herein can utilize powerful electro-optic effects, such as the Pockels effect, to efficiently modulate and / or switch optical signals at low temperatures. For example, the techniques disclosed herein are applicable to optical modulators in which the intensity of transmitted light can be modulated, for example, according to a sinusoidal or square function, as well as optical switches in which light can be selected from one input port (e.g., a waveguide) among one or more input ports and output to one output port (e.g., a waveguide) among one or more output ports.

[0020]

[0035] According to certain embodiments, EO materials can be used in devices with different waveguide structures and / or waveguide structures fabricated by different processes. For example, EO materials can be used as a waveguide core, a lower cladding layer, and / or an upper cladding layer in a waveguide structure. In various embodiments, the waveguide core can be deposited on or etched into the EO material layer, or can be formed on a semiconductor substrate and then bonded to a wafer or device containing the EO material layer.

[0021]

[0036] Some exemplary embodiments will now be described with reference to the accompanying drawings, which form a part of this specification. The following description provides only certain embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the following description of the embodiments will provide those skilled in the art with an enabling description for implementing one or more embodiments. It will be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure. In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of particular embodiments of the present invention. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and descriptions are not intended to be limiting. The words "example" or "exemplary" are used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" or "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0022]

[0037] Silicon photonic integrated circuits (PICs) can provide superior performance (e.g., lower loss, higher speed, higher bandwidth, and thermal insulation) than electrical integrated circuits (EICs) and can be used for quantum communication or quantum computing, where photons can be used as qubits due to their quantum nature and optical interconnects can be used to provide higher bandwidth for digital data transfer between cryogenic processors and room-temperature environments. However, due in part to the lack of efficient electro-optical modulation for optical switching and / or modulation at low temperatures, the performance of PICs at cryogenic temperatures may need to be improved. For example, some integrated optical switches operating at cryogenic temperatures may use thermo-optic phase shifters or plasma distributed switches, which may suffer from several inherent limitations. Thermo-optic switches, which use heat to change the refractive index of a material, may require significant cooling power and may have low bandwidth and switching speed. Plasma distributed switches can use high doping levels to compensate for charge carriers frozen out at low temperatures, thus allowing the use of compact resonators that may have high resistance, high insertion loss, and low bandwidth.

[0023]

[0038] Some electro-optical materials can exhibit a linear electro-optic effect, in which the refractive index of a material can change proportionally to the strength of an electric field applied to the material. This linear electro-optic effect, called the Pockels effect, can occur in non-centrosymmetric materials, such as lithium niobate (LiNbO), lithium tantalate (LiTaO), potassium dihydrogen phosphate (KDP), beta-barium borate (BBO), potassium titanyl phosphate (KTP), and crystalline materials of some compound semiconductors, such as gallium arsenide (GaAs) and indium phosphide (InP). Electro-optical switches based on the Pockels effect can have low propagation loss, high bandwidth, and low static power consumption at room temperature. Furthermore, electro-optical switches based on the Pockels effect may not suffer from the inherent limitations of thermo-optical and plasma dispersion effects at cryogenic temperatures.

[0024]

[0039] FIG. 1A is a simplified diagram illustrating an example of an optical switch 100 including a Mach-Zehnder interferometer 120 according to certain embodiments. In the example illustrated in FIG. 1, optical switch 100 includes two input ports (input port 1 and input port 2) and two output ports (output port 1 and output port 2). The input and output ports of optical switch 100 may be implemented using, for example, optical waveguides operable to support single-mode or multimode optical beams. Optical switch 100 may be implemented using Mach-Zehnder interferometer 120 integrated with a set of 50 / 50 beam splitters (or directional couplers), such as first 50 / 50 beam splitter 105 and second 50 / 50 beam splitter 107. As shown in FIG. 1, input port 1 and input port 2 may be optically coupled to first 50 / 50 beam splitter 105, which may receive light from input port 1 or input port 2. The first 50 / 50 beam splitter 105 can direct approximately 50% of the input light from input port 1 to the first waveguide 110 and approximately 50% of the input light from input port 1 to the second waveguide 112 via evanescent coupling. Similarly, the first 50 / 50 beam splitter 105 can direct approximately 50% of the input light from input port 2 to the first waveguide 110 and approximately 50% of the input light from input port 2 to the second waveguide 112. Thus, the input light from the input ports can be approximately equally split and directed to the first waveguide 110 and the second waveguide 112.

[0025]

[0040] Mach-Zehnder interferometer 120 can include a phase adjustment section 122 that includes a waveguide 124 and electrodes 126. A voltage signal V can be applied across waveguide 124 via electrodes 126 in phase adjustment section 122 to adjust the refractive index of waveguide 124 and therefore the phase delay of the light after passing through phase adjustment section 122. Because the light in first waveguide 110 and second waveguide 112 is in phase after propagating through first 50 / 50 beam splitter 105, the phase adjustment in phase adjustment section 122 can introduce a predetermined phase difference between the light propagating in waveguides 130 and 132. As will be apparent to those skilled in the art, the phase relationship between the light propagating in waveguides 130 and 132 results in output light being present at output port 1 (e.g., if the light beams are in phase) or output port 2 (e.g., if the light beams are out of phase), thereby providing a switching function as the light is directed to output port 1 or output port 2 based on the voltage signal V applied at phase adjustment section 122. Although a single active arm is shown in FIG. 1, in some other embodiments, both arms of Mach-Zehnder interferometer 120 can include a phase adjustment section.

[0026]

[0041] As shown in FIG. 1, electro-optical switch technology, compared to all-optical switch technology, applies an electrical bias (e.g., voltage signal V in FIG. 1) across the active region of the switch to create optical variations. The electric field or current induced by the application of the bias voltage can cause a change in one or more optical properties of the active region, such as refractive index or optical absorption. In addition to the power dissipated by the flow of current (if the current is induced by the application of a bias voltage), E 2 Energy may be dissipated by the creation of an electric field, which may have an energy density of κ / 8π (in cgs), where E is the electric field and κ is the dielectric constant.

[0027]

[0042] Although one example of a Mach-Zehnder interferometer implementation is shown in Figure 1, other switch architectures and / or other phase adjustment devices may be used in various embodiments, including ring resonator designs, disk resonator designs, Mach-Zehnder modulators, generalized Mach-Zehnder modulators, etc. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0028]

[0043] The aforementioned phase adjustment can be achieved using electro-optical effects, such as the Pockels effect and / or the Kerr effect. The Pockels effect changes or induces birefringence in an optical medium subjected to an electric field, with the birefringence being proportional to the applied electric field. The Pockels effect can occur in crystals lacking inversion symmetry, such as perovskite crystals, ferroelectric crystals, or other non-centrosymmetric media, such as electric field-poled polymers or glasses. In the Kerr effect, the refractive index change (or birefringence) is proportional to the power (e.g., square) of the applied electric field. While all materials can have the Kerr effect, some materials can have a stronger Kerr effect than others. In general, the Pockels effect can be a much stronger electro-optical effect than the Kerr effect.

[0029]

[0044] Ferroelectric crystals generally have spontaneous polarization that can be reoriented by an electric field or stress. The spontaneous polarization can be caused by a non-centrosymmetric crystal structure that can be stable over a certain temperature range. Ferroelectric crystals that exhibit the Pockels effect include BaTiO 3( BTO), (Ba,Sr)TiO 3( BST), (Pb(Zr,Ti)O 3( PZT), (Pb,La)(Zr,Ti)O 3( PLZT), (Sr,Ba)NbO 6(Examples include barium titanate (BTO) and barium nitrate (SBN). For example, barium titanate (BTO) has a relatively large Pockels coefficient at room temperature. Furthermore, BTO can be grown on large Si substrates and integrated into Si photonic platforms using silicon CMOS processes. Therefore, BTO can be used in a variety of electronic applications due to its excellent ferroelectric properties, high dielectric constant, low dielectric loss, chemical and mechanical stability, and CMOS process compatibility.

[0030]

[0045] 1B is a cross-sectional view of an example phase adjustment section 150 (e.g., phase adjustment section 122) in one implementation of the optical switch 100 shown in FIG. 1A according to certain embodiments. Phase adjustment section 150 may use an EO effect, such as the Pockels effect described above. Phase adjustment section 150 may include a substrate 152, an optional buffer layer 154, a seed layer 156, an EO material layer 158, a waveguide core 162, a waveguide cladding layer 160, and an electrode 164. EO material layer 158 may have a high Pockels coefficient and may include, for example, a perovskite ferroelectric or other ferroelectric crystal, such as barium titanate (BaTiO or BTO), as described herein.

[0031]

[0046] The substrate 152 may include a semiconductor substrate such as a silicon wafer, a germanium wafer, a germanium-on-silicon wafer, or a silicon-on-insulator (SOI) wafer. The seed layer 156 may have a lattice structure similar to that of the EO material layer 158 and may include, for example, MgO, BaHfO, BaZrO, LaAlO, SrHfO, SrTiO, SrMoO, or SrZrO. The seed layer 156 may be deposited (e.g., epitaxially grown) on the substrate 152. In some embodiments, a buffer layer 154 may be positioned between the seed layer 156 and the substrate 152. The buffer layer 154 may include, for example, an oxide layer of the substrate, such as a SiO layer. In one example, the buffer layer 154 (e.g., SiO) may be formed by high-temperature oxidation annealing of the seed layer 156 (e.g., SrTiO) and the substrate 152 (e.g., Si) in an oxygen ambient.

[0032]

[0047] The EO material layer 158 may be epitaxially deposited on the seed layer 156. The waveguide core 162 may be formed directly on the EO material layer 158, for example, by deposition and photolithography, or may be formed indirectly on the EO material layer 158 with a buffer layer between the EO material layer 158 and the waveguide core 162. The buffer layer may be used to prevent interaction between the EO material layer 158 and the waveguide core 162 and / or to serve as an etch stop layer for forming the waveguide core 162. The waveguide core 162 may include, for example, Si, SiN, SiGe, an EO material (e.g., BTO), etc. The waveguide cladding layer 160 may include a dielectric material having a refractive index lower than that of the waveguide core 162, such as an oxide, nitride, oxynitride, oxycarbide, etc. (e.g., SiO, SiN, SiON, SiCO, etc.), and may be deposited on the waveguide core 162. A trench may be etched in the waveguide cladding layer 160 and filled with a conductive material, such as a metal, to form an electrode 164. The electrode 164 can be used to apply a bias voltage, and therefore an electric field, across the EO material layer 158 to modulate the refractive index of the EO material layer for phase adjustment.

[0033]

[0048] As mentioned above, some perovskite ferroelectrics, such as barium titanate, can have a large Pockels coefficient at room temperature. The Pockels coefficient of a perovskite ferroelectric material may be different for different crystal lattice orientations. Furthermore, the Pockels coefficient of a perovskite ferroelectric material may be different at different operating temperatures. For example, at low temperatures, the Pockels coefficient of a ferroelectric material may be significantly reduced.

[0034]

[0049] Figure 2 shows the effective Pockels coefficients for BaTiO3 with different crystal lattice orientations at temperatures from about 4 K to about 340 K, as reported in, for example, Felix Eltes et al., "An integrated Cryogenic Optical Modulator," J. App. Phys. (2019). In Figure 2, the x-axis corresponds to the operating temperature from 4 K to 340 K, and the y-axis corresponds to the Pockels coefficient (pm / V). Curve 210 shows the corresponding Pockels coefficients at different temperatures for a BTO layer with a 45° lattice orientation. Curve 220 shows the corresponding Pockels coefficients at different temperatures for a BTO layer with a 22.5° lattice orientation. Curve 230 shows the corresponding Pockels coefficients at different temperatures for a BTO layer with a 67.5° lattice orientation. Curve 240 shows the corresponding Pockels coefficients at different temperatures for a BTO layer with a 90° lattice orientation. Curves 210-240 show that the Pockels effect of BTO is anisotropic and therefore the EO effect can be a function of the crystal lattice orientation in the BTO layer of the EO device.

[0035]

[0050] Curves 210-240 also show the temperature dependence of the Pockels coefficient. For example, Figure 2 shows that when the crystal lattice orientation in the BTO layer is about 45°, the Pockels coefficient can be highest between about 200 K and about 260 K, such as about 240 K, in which case the Pockels coefficient can be greater than 700 pm / V. Below about 240 K, the magnitude of the Pockels coefficient can gradually decrease to about 200 pm / V at 4 K, which is less than one-third of the Pockels coefficient at room temperature. Furthermore, there can be a sharp decrease in the Pockels coefficient between about 140 K and about 100 K.

[0036]

[0051] Although the Pockels coefficient of BaTiO3 may decrease significantly at 4 K compared to the Pockels coefficient at room temperature, the value (e.g., about 200 pm / V) may still be larger than some other materials at room temperature. The impact of the decreased Pockels coefficient on the energy efficiency of EO switching may be partially compensated for by the decreased dielectric constant of BaTiO3 at low temperatures. Furthermore, the electrical conductivity of BaTiO3 may decrease at low temperatures, which may help reduce the static power consumption of BaTiO3 devices in cryogenic environments.

[0037]

[0052] To improve the performance of Pockels-effect-based EO devices at cryogenic temperatures, it may be desirable to maintain the high room-temperature Pockels coefficient of an EO material at cryogenic temperatures. According to certain embodiments, it has been determined that a decrease in the Pockels effect may be caused, at least in part, by changes in the strain and polarization of a crystal with temperature, as well as by crystalline phase and polarization transitions of the crystal at a particular temperature. This is because, as noted above, the Pockels effect can occur in crystals lacking inversion symmetry (e.g., non-centrosymmetric), and the non-zero elements of the Pockels tensor may depend on the crystal symmetry. Therefore, if an EO material can maintain its room-temperature crystal structure at cryogenic temperatures, the Pockels coefficient of the EO material at cryogenic temperatures can be improved.

[0038]

[0053] Figures 3A-3D show the crystalline phase transitions of ABO3 perovskite crystals (e.g., BaTiO3) at different temperatures. Barium titanate (BaTiO3) can generally enter a paraelectric phase with no net polarization above the Curie temperature (e.g., at approximately 120°C). Figure 3A shows a cubic crystalline structure 310 in BaTiO3 above the Curie temperature. Larger barium ions (A ions) generally occupy the corners. Smaller titanate ions (B ions) generally reside at the center of the cube. Oxygen anions generally reside at the face centers. Unlike many other oxide crystals, oxygen anions in perovskite crystals may not form a closely packed structure. Therefore, temperature changes and stresses within the perovskite crystal can cause the crystal structure of the perovskite crystal (e.g., BaTiO3) to change. At about the Curie temperature, the crystal may undergo a phase transition (also called a polar phase transition) and may adopt a polar tetragonal phase within a temperature range of about 5°C to about 120°C.

[0039]

[0054] FIG. 3B shows polar tetragonal crystal structure 320 in BaTiO3 within the temperature range of about 5° C. to about 120° C. Upon cooling from the Curie temperature, polar tetragonal crystal structure 320 can form. The formation of the tetragonal structure can permanently polarize the unit cell, which results in the polarization of the six equivalent cubic crystal structures 310. <100> This results in spontaneous polarization along the c-axis, which can be parallel to either of the α-axis. Thus, the polar tetragonal phase can have six stable polarization directions parallel to the edges of the unit cell, resulting in six different crystal varieties.

[0040]

[0055] FIG. 3C shows the orthorhombic crystal structure 330 of BaTiO3 within the temperature range of about -90° C. to about 5° C. As shown in FIG. 3C, upon further cooling below about 5° C., the unit cell of BaTiO3 becomes aligned along the plane diagonals ( <110> ) direction 332, the tetragonal crystal structure 320 may be further distorted, changing to an orthorhombic crystal structure 330. The cubic crystal structure 310 has 12 equivalent <110> There may be directions, which may result in 12 possible polar directions in the orthorhombic phase. The orthorhombic phase may be stable from about 5°C up to about -90°C.

[0041]

[0056] FIG. 3D shows the rhombohedral crystal structure 340 in BaTiO at temperatures below about −90° C. As shown in FIG. 3D, upon further cooling below about −90° C., the unit cell of BaTiO reorganizes along the body-centered diagonal ( <111> ) direction 342, which may result in a rhombohedral symmetry structure. <111> There are eight possible equivalent polar directions in the rhombohedral phase along the direction.

[0042]

[0057] Thus, bulk BaTiO3 crystals can transition from the tetragonal phase at room temperature to the orthorhombic phase at temperatures below about 270 K, and then to the rhombohedral phase at temperatures below about 180 K. Such crystal structures and phase transitions can be observed in many perovskite ferroelectrics. The phase transition can change the elements of the Pockels tensor and alter the magnitude of the effective Pockels coefficients.

[0043]

[0058] As mentioned above, crystal structure and phase transitions can also affect the available polarization directions. At the microstructural level, regions with uniform electric polarization can form domains, with each domain being a region containing a single crystal variant. The interfaces between domains can be called domain walls. Ferroelectric crystals can adopt stable, minimum-energy configurations of domains and domain walls. In many cases, a global minimum may not be achieved, and stable states may be local energy minima, and energy minimization can result in crystals with multiple domains separated by domain walls that are oriented to minimize energy by maintaining compatibility of strain and polarization across the walls.

[0044]

[0059] Therefore, by maintaining the room-temperature crystal structure and polarization direction at cryogenic temperatures, the Pockels coefficient of the EO material can be improved. For example, according to certain embodiments, the EO material layer can include interleaved thin EO material layers and interlayers. The interlayers can have a lattice structure that does not change at operating temperatures. Thus, the thin EO material layers interleaved with the interlayers can maintain their lattice structure and polarization direction, and therefore the EO coefficient, without undergoing a phase transition when the operating temperature changes, as described above with respect to FIGS. 3A-3D.

[0045]

[0060] FIG. 4 is a simplified flowchart 400 illustrating an example of a method for fabricating an EO device including an EO material layer characterized by a substantially constant EO coefficient from room temperature to cryogenic temperatures, according to certain embodiments. Note that while FIG. 4 describes operations in a sequential flow, some operations may occur in parallel or simultaneously. Some operations may be performed in a different order. A process may have additional steps not included in the diagram. Some operations may be optional and therefore may be omitted in various embodiments. Also, some operations may be performed in conjunction with other operations.

[0046]

[0061] In block 410, a seed layer (e.g., seed layer 156) may be deposited on a substrate (e.g., substrate 152). As previously mentioned, the substrate may be a semiconductor wafer, such as a monocrystalline silicon wafer, a germanium wafer, a germanium-on-silicon wafer, or a silicon-on-insulator (SOI) wafer. The substrate may include semiconductor wafers of various sizes, such as 4 inches, 6 inches, 8 inches, 10 inches, 12 inches, or larger. Generally, it is desirable to use larger wafers to improve productivity. For example, a 12-inch silicon wafer may be used as the substrate.

[0047]

[0062] The seed layer may have a lattice structure similar to that of the EO material used in the EO device, for example, SrTiO 3( The seed layer may include STO, MgO, LaAlO, etc. The seed layer may be epitaxially deposited or grown on the substrate using, for example, molecular beam epitaxy (MBE). In one embodiment, Sr and Ti may be deposited on the surface of a silicon wafer in an oxygen environment to form an amorphous SrTiO layer, which may then be crystallized at a higher temperature to form an epitaxial crystalline SrTiO layer. The lattice mismatch between Si and STO may be about 2%, and high-quality STO may be nearly coherent with silicon if the STO layer thickness is, for example, less than about 5 nm.

[0048]

[0063] 5A illustrates an example of a substrate 510 (e.g., a semiconductor wafer) having an epitaxial seed layer 520 according to certain embodiments. In the example illustrated in FIG. 5, the substrate 510 may comprise a silicon or SOI wafer. The epitaxial seed layer 520 may comprise a coherent epitaxial STO layer, which may have a thickness of, for example, a few nanometers or tens of nanometers, e.g., less than about 8 nm or less than about 5 nm.

[0049]

[0064] Referring back to FIG. 4 , in block 420, a first thin EO material layer may be deposited on the seed layer, for example, by epitaxial deposition. The first thin EO material layer may include, for example, a ferroelectric material or a perovskite ferroelectric material, such as BaTiO (BTO), (Ba,Sr)TiO (BST), (Pb(Zr,Ti)O (PZT), or (Pb,La)(Zr,Ti)O (PLZT). The first thin EO material layer may have a thickness of, for example, less than 100 nm. The lattice mismatch between BTO and silicon may be about 4%, and when the thickness of the BTO layer is less than about 100 nm, the BTO layer may be partially coherent with Si / STO, which may result in compressive stress within the BTO layer. Therefore, the first thin EO material layer (e.g., BTO) deposited on the seed layer may have out-of-plane polarization due to the compressive stress.

[0050]

[0065] FIG. 5B illustrates the internal stress and crystal lattice orientation of a layer 530 of EO material epitaxially deposited on a seed layer 520, according to certain embodiments. The EO material may include, for example, BaTiO (BTO), (Ba,Sr)TiO (BST), (Pb(Zr,Ti)O (PZT), (Pb,La)(Zr,Ti)O (PLZT), etc., as previously described. As deposited, the layer 530 of EO material (e.g., BTO on STO / Si) may primarily contain domains with a tetragonal crystal structure 525 due to compressive stress, as shown in FIG. 5B, where the c-direction of the tetragonal crystal structure 525 is perpendicular to the layer 530 (i.e., out-of-plane orientation). The layer 530 may be a thin layer, such as less than 100 nm or thinner, in order for the ferroelectric material in the layer 530 to adhere to the intermediate layer with a tetragonal crystal structure at low temperatures.

[0051]

[0066] In block 430 of FIG. 4 , the substrate, seed layer, and first thin EO material layer may be annealed in an oxygen ambient at a higher temperature, such as above the melting point of SiO. For example, the annealing temperature may be above 600° C., e.g., 750° C. or higher. The high-temperature annealing may help relieve stress and form a buffer layer at the interface between the substrate (e.g., Si) and the seed layer (e.g., STO). The buffer layer may include an oxide layer, such as a SiO layer. For example, silicon at the interface between the substrate and the seed (e.g., STO) layer may be oxidized at a high annealing temperature and in an oxygen ambient to form a SiO layer. When the annealing temperature exceeds the melting point of the buffer layer (e.g., about 600° C.), the buffer layer (e.g., SiO) may soften, thereby allowing the seed layer and first thin EO material layer to separate from the substrate and relieve stress in the seed layer and first thin EO material layer. Therefore, the softening of SiO2 during high temperature annealing can change the stress in the EO material (e.g., BTO) from compressive stress to natural stress, which can improve the quality of the seed layer and the first thin EO material layer.

[0052]

[0067] At high temperatures, there can be a large difference in the coefficient of thermal expansion (CTE) between BTO (e.g., about 3.5E-6 / °C) and silicon (e.g., about 2.6E-6 / °C). Therefore, when the buffer layer (e.g., SiO2) hardens below 550°C during cooling, the large CTE difference between silicon and BTO can cause the stress of BTO to undergo a natural to tensile stress transition. Therefore, at room temperature, the net or dominant stress of BTO can change from compressive to tensile stress, which can cause the polarization to change from out-of-plane polarization to in-plane orientation. Therefore, the annealing temperature can be selected so that the BTO is under tensile stress and has in-plane polarization after cooling due to the stress caused by the large difference in CTE between BTO and silicon.

[0053]

[0068] 5C illustrates the internal stress and crystal lattice orientation of a layer 530 of EO material epitaxially deposited on a seed layer 520 after high-temperature oxidation annealing, according to certain embodiments. As illustrated, due to the tensile stress in the layer 530 after annealing as described above, the layer 530 of ferroelectric material (e.g., BTO on STO / Si) may primarily contain domains having a tetragonal crystal structure 535 whose c-direction is parallel to the layer 530 (i.e., in-plane bias). FIG. 5C also illustrates a buffer layer 540, such as an oxide layer (e.g., SiO), formed by oxidation of the substrate during the high-temperature oxidation annealing.

[0054]

[0069] FIG. 6 illustrates the improved crystal quality after annealing, as indicated by ion channeling measured using Rutherford backscattering spectroscopy (RBS) / channeling for an example epitaxial layer (e.g., a SrTiO epitaxial layer) before and after annealing according to certain embodiments. In RBS / channeling, atoms displaced from lattice sites can interact with the channeled beam, resulting in an increased scattering yield. Curve 610 in FIG. 6 illustrates the total number of backscattered particles (e.g., ions) detected in different channels (energy of the backscattered particles) backscattered by the SrTiO epitaxial layer before annealing. As shown, before annealing, the SrTiO epitaxial layer contains a high proportion of substitutional Sr and Ti atoms. Curve 620 in FIG. 6 illustrates the total number of backscattered particles detected in different channels backscattered by the SrTiO epitaxial layer after annealing. Curve 620 shows that the number or percentage of substituted Sr and Ti atoms is significantly reduced, and therefore the quality of the crystalline SrTiO epitaxial layer is significantly improved. Although not shown in FIG. 6, the quality of the BTO epitaxial layer can be similarly improved by an annealing process.

[0055]

[0070] FIG. 7 shows example X-ray diffraction data illustrating heterophase lattice constant relaxation at high temperatures for an example epitaxial layer (e.g., a SrTiO epitaxial layer). The SrTiO epitaxial layer can be deposited on a silicon wafer using, for example, MBE. FIG. 7 shows that heterophase thermal lattice expansion can be a linear function of temperature at temperatures below about 600°C. The heterophase lattice constant can begin to relax at about 600°C, indicating that STO is under compressive stress below about 600°C and that the compressive stress can be released at temperatures above 600°C.

[0056]

[0071] 4 , in block 440, a thin interlayer can be deposited on a first EO material layer (e.g., a BTO layer), and a thin EO material layer (e.g., another BTO layer) can be deposited on the interlayer. The interlayer and EO material layer can also be annealed using high-temperature oxidation annealing, as described above, to relax the BTO and improve crystalline quality to ensure in-plane polarization in the thin BTO layer. The thin interlayer and thin EO material layer can be alternately deposited and annealed in each of multiple process cycles to form a stack of interleaved, interlocked interlayer and EO material layers until the total thickness of the EO material layers reaches a target thickness.

[0057]

[0072] In various embodiments, the interlayer may include a crystalline structure similar to that of the EO material and may not undergo a phase transition at low temperatures. Thus, at cryogenic temperatures, the interlayer may have a crystalline structure similar to that of the EO material at room temperature. The interlayer may include, for example, certain oxides such as MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrZrO3, or other oxides with lattice constants close to those of the tetragonal crystal structure of BTO. The interlayer may limit the transition of BTO from its tetragonal phase at room temperature to other phases at lower temperatures.

[0058]

[0073] 5D illustrates the internal stress and crystal lattice orientation of layers of EO material interleaved with intermediate layers in an example of a processed wafer 500 according to certain embodiments. In the example shown in FIG. 5D, processed wafer 500 can include a substrate 510 (e.g., a silicon wafer), a buffer layer 540 (e.g., a SiO buffer layer), a seed layer 520 (e.g., an STO layer having a thickness of less than about 8 nm), and multiple thin EO material layers 530, 532, 534, such as thin BTO layers, each having a thickness of less than about 100 nm. Between the multiple thin EO material layers 530, 532, 534 are multiple intermediate layers 550, 552, such as layers of MgO, BST, BaHfO, BaZrO, SrHfO, SrZrO, SrNbO, or other oxides. Each interlayer 550 or 552 can have a thickness of, for example, less than about 10 nm and can be used to separate the thin BTO layers from one another and to apply tensile stress to the thin BTO layers. In some embodiments, the ratio between the thickness of each EO material layer and the thickness of each interlayer can be about 20:1, 10:1, 8:1, 5:1, or less. The net or dominant stress in the EO material layer can be tensile. As previously mentioned, the layer stack, including the interlayers and thin EO material layers, can be annealed at high temperature to relax the EO material, improve material quality, and ensure in-plane polarization in the EO material layer (e.g., the c-axis of the crystal structure is parallel to the EO material layer), as indicated by the tetragonal crystal structure 535.

[0059]

[0074] Also, as previously mentioned, a stack of interdigitated thin EO material layers and interlayers (e.g., a BTO / MgO stack) can maintain tensile stress in the EO material at low temperatures, and thus can maintain the tetragonal crystal structure 535 of the EO material at low temperatures (e.g., cryogenic temperatures) due to the tensile stress. Thus, the EO effect, such as the Pockels effect, of the EO material at cryogenic temperatures can be close to the Pockels effect of the EO material at room temperature.

[0060]

[0075] In block 450, a waveguide may be formed on or bonded to a stack of interleaved thin EO material layers and interlayers. For example, in some embodiments, a waveguide layer, such as a silicon, SiGe, or Si3N4 layer, may be deposited directly on the stack, the silicon, SiGe, or Si3N4 layer may be patterned using photolithography to form a waveguide core, and then a cladding layer (also called a capping layer) may be deposited on the waveguide core to form the waveguide. The silicon, SiGe, or Si3N4 layer may be deposited indirectly on the stack with a buffer layer interposed therebetween. The buffer layer may prevent interaction between the waveguide core and the EO material and / or serve as an etch stop for patterning the waveguide layer. In some embodiments, the waveguide core and upper and / or lower cladding layers may be formed on a second substrate and then bonded to a stack of alternating thin EO material layers and intermediate layers (e.g., fabricated wafer 500), where the fabricated wafer 500 substrate may be subsequently removed, for example, by horizontal wet etching (e.g., using a sacrificial layer) or other lift-off techniques, such as laser lift-off techniques. In some embodiments, some of the thin EO material layers may be used to form the waveguide core.

[0061]

[0076] The cladding layer of the waveguide may comprise a dielectric or EO material having a refractive index lower than that of the waveguide core. The cladding layer may include, for example, Si3N4, oxides (e.g., SiO2, Al2O3, and MgO), or high-κ materials (e.g., hafnium oxide (HfO2)). In some embodiments, an amorphous dielectric cladding layer having compressive stress (e.g., Si3N4, SiO2, Al2O3, etc.) may be deposited on the stack of alternating thin EO material layers and interlayers at a temperature less than about 550°C. The cladding layer can apply tensile stress to the stack of alternating thin EO material layers and interlayers to further maintain the tetragonal phase of the EO material. The cladding layer may also be used as a dielectric layer for wafer-to-wafer bonding or die-to-wafer bonding. In some embodiments, the cladding layer can be used as an etch stop layer for certain etching processes. Several example waveguide structures and EO device configurations using stacks of alternating thin EO material layers and interlayers are described in detail below.

[0062]

[0077] FIG. 5E illustrates the internal stress and crystal lattice orientation of layers of EO material interleaved with intermediate layers in a waveguide structure 505 according to certain embodiments. As shown, a waveguide core 560 may be adjacent to the fabricated wafer 500 and may be covered by a waveguide cladding layer 570. The waveguide cladding layer 570 may include an amorphous dielectric cladding layer (e.g., Si3N4, SiO2, Al2O3, etc.) that exerts tensile stress on the stack of thin EO material layers to maintain the tetragonal phase of the EO materials at low temperatures. For example, SiO2 and BTO may have very different CTE properties at low temperatures (e.g., cryogenic temperatures), with the CTE of SiO2 becoming negative (i.e., expanding as the temperature decreases) at low temperatures. Therefore, upon cooling to cryogenic temperatures, the SiO2 cladding layer may exert a tensile stress on the BTO layer due to the large difference in CTE between the BTO and SiO2 cladding layers. Therefore, the dominant stress in the EO material layer may be tensile at temperatures from room temperature to cryogenic temperatures. Thus, the layer of EO material can maintain a tetragonal crystal structure and an in-plane polarization, with the c-axis of the crystal structure parallel to the layer of EO material.

[0063]

[0078] In block 460, electrical connections can be made to the EO material layers in the stack to apply voltage signals to the EO material layers. For example, trenches can be etched into the cladding layers and through the EO material layers in the stack, and a thin layer of conductive liner material such as TiN or Ti and TiN can first be coated on the trench sidewalls to promote adhesion and prevent diffusion, after which a conductive electrode material (e.g., W or Co) can fill the trench to form an electrode for the EO device. Alternatively, a conductive barrier material (e.g., TaN) and a liner (e.g., Ta, Co, or Ru) can first be coated on the trench sidewalls, followed by the deposition of a Cu conductive electrode. In this manner, each of the EO material layers can be in contact with the electrode and can receive a voltage signal to change its refractive index due to the electric field induced by the voltage signal.

[0064]

[0079] 8 is a simplified cross-sectional view of an example of a waveguide structure 800 including an EO material layer capable of maintaining a tetragonal phase at cryogenic temperatures, in accordance with certain embodiments. The waveguide structure 800 may include a first portion 802 and a second portion 804 that are bonded together, for example, by wafer-to-wafer fusion bonding. The first portion 802 may include a stack of thin EO material layers 830, 832, 834, and 836 interleaved with thin intermediate layers 840, 842, and 844. As discussed above with respect to FIGS. 4 and 5B-5D, the EO material layers 830, 832, 834, and 836 can include ferroelectric crystals such as BaTiO (BTO), (Ba,Sr)TiO (BST), (Pb(Zr,Ti)O (PZT), and (Pb,La)(Zr,Ti)O (PLZT). The intermediate layers 840, 842, and 844 can include, for example, MgO, BST, BaHfO, BaZrO, SrHfO, SrNbO, SrTiO, SrZrO, or other oxides.

[0065]

[0080] The EO material layers and interlayers may be alternated such that the EO material layers and interlayers are interdigitated with one another to form a stack of alternating layers. The EO material layers and interlayers may be thin, and the ratio of the thickness of each EO material layer to the thickness of each interlayer may be about 20:1, 10:1, 8:1, 5:1, or less. In one example, each EO material layer may be about 100 nm or less thick, and each interlayer may be about 10 nm or less thick. The total thickness of the EO material layers in the stack may be greater than a certain value, such as greater than about 300 nm. The stack of alternating layers may be formed on a seed layer 820, which may be deposited on, for example, a semiconductor substrate (e.g., a silicon substrate) (not shown in FIG. 8 ), as described above. For example, the high-temperature oxidation annealing process described above may be used to form a buffer layer 810 between the seed layer 820 and the semiconductor substrate.

[0066]

[0081] The second portion 804 may include a waveguide formed on a substrate 860, which may be a semiconductor substrate (e.g., a silicon handle wafer) or a glass, quartz, ceramic, or metal substrate. The waveguide may include a waveguide core 870 and a waveguide cladding layer 880. The waveguide core 870 may include a material having a high refractive index, such as silicon, SiN, or SiGe. The waveguide cladding layer 880 may include a dielectric material that may have a refractive index lower than that of the waveguide core 870. The waveguide cladding layer 880 may include an amorphous dielectric cladding layer, such as Si3N4, SiO2, Al2O3, MgO, SiON, SiCN, SiCON, or SiCO. The waveguide cladding layer 880 may be used as a dielectric layer for wafer-to-wafer bonding and die transfer. The waveguide cladding layer 880, when bonded to the first portion 802, can apply a tensile stress to the stack of alternating thin EO material layers and interlayers to maintain the tetragonal phase of the EO material at low temperatures, as described above. The second portion 804 of the waveguide structure 800 can also include other passive or active devices formed on the substrate 860.

[0067]

[0082] After first portion 802 and second portion 804 are bonded together, the semiconductor substrate on which the stack of thin EO material layers 830, 832, 834, and 836 and thin intermediate layers 840, 842, and 844 is formed may be thinned or removed, for example, by backlapping, backgrinding, horizontal wet etching, or a lift-off technique (e.g., laser lift-off). A trench can then be etched into first portion 802 from the buffer layer 810 side down to the interface between first portion 802 and second portion 804, where waveguide cladding layer 880 can be used as an etch stop for the etching process. A conductive material, such as Ti, TiN, and TaN, along with an electrode metal (e.g., Cu, W, Co, etc.), can be deposited or otherwise fill the trench to form electrode 850.

[0068]

[0083] Electrode 850 can be used to apply voltage signals to the thin EO material layers 830, 832, 834, and 836 via edge contacts rather than surface contacts. The edge contacts can apply voltage signals directly to the EO material layers without going through an intermediate layer, which may have a dielectric constant different from that of the EO material. For example, MgO may have a lower dielectric constant than BTO. Therefore, the edge contacts can help eliminate electric field interference caused by the intermediate layer due to the difference in dielectric constants. In some embodiments, the intermediate layer (e.g., a BST layer) can have a dielectric constant similar to that of the EO material (e.g., BTO), and the voltage signals can be applied to the EO material layers using surface contacts.

[0069]

[0084] FIG. 9 is a simplified cross-sectional view of another example of a waveguide structure 900 including an EO material layer capable of maintaining a tetragonal phase at cryogenic temperatures, according to certain embodiments. The waveguide structure 900 can include a substrate 910, which can be similar to the substrate 152 or 510 described above. In one example, the substrate 910 comprises a large (e.g., 12-inch) silicon wafer. The waveguide structure 900 can also include a buffer layer 922 and a seed layer 920 on the substrate 910. The buffer layer 922 can be similar to the buffer layer 154, 540, or 810 described above. An example of the buffer layer 922 is a SiO layer. The seed layer 920 can be similar to the seed layer 156, 520, or 820 described above. An example of the seed layer 920 is an STO layer. As previously mentioned, the buffer layer 922 can be formed by high temperature oxidation annealing of a seed layer 920 deposited on a substrate 910 (e.g., a silicon wafer), in which case the substrate 910 can be oxidized at the interface between the seed layer 920 and the substrate 910 to form a buffer layer 922 between the seed layer 920 and the substrate 910.

[0070]

[0085] The waveguide structure 900 may include multiple EO material layers 930, 932, 934, etc., and multiple intermediate layers 940, 942, etc. As previously described, the EO material layers 930, 932, 934 may include ferroelectric crystals such as BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. The intermediate layers 940 and 942 may include, for example, MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, SrZrO3, or other oxides. The EO material layers and intermediate layers may be alternately deposited on the seed layer 920. The EO material layers and interlayers may be interleaved and interdigitated with one another to form a stack of alternating layers. The EO material layers and interlayers may be thin layers, and the ratio of the thickness of each EO material layer to the thickness of each interlayer may be about 20:1, 10:1, 8:1, 5:1, or less. In one example, each EO material layer may be about 100 nm or less thick, and each interlayer may be about 10 nm or less thick. The total thickness of the EO material layers in the stack may be greater than a certain value, such as greater than about 300 nm.

[0071]

[0086] A waveguide including a waveguide core 950 and a cladding layer 960 may be formed on a stack of alternating layers, for example, as described above with respect to block 450 of Figure 4 and Figure 5E. The waveguide core 950 may include, for example, Si, SiGe, or SiN, and the cladding layer 960 may include, for example, Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, HfO2, etc.

[0072]

[0087] A trench can then be etched through the cladding layer 960 and the stack of alternating layers, from the cladding layer 960 down to the seed layer 920 or buffer layer 922, which may be used as an etch stop for the etching process. A conductive material, such as a metal (e.g., Cu, W, Co, etc.), can be deposited or otherwise fill the trench to form an electrode 970. As discussed above with respect to FIG. 8 , the electrode 970 can be used to apply a voltage signal to the EO material layers 930, 932, 934 via an edge contact rather than a surface contact to avoid electric field interference caused by the intermediate layers 940 and 942, which may have a different dielectric constant than that of the EO material layers 930, 932, 934.

[0073]

[0088] FIG. 10 is a simplified cross-sectional view of yet another example of a waveguide structure 1000 including an EO material layer capable of maintaining a tetragonal phase at low temperatures, according to certain embodiments. The waveguide structure 1000 can include a substrate 1010, which can be similar to the substrate 152, 510, or 910 described above. The waveguide structure 1000 can also include a buffer layer 1022 and a seed layer 1020 on the substrate 1010. The buffer layer 1022 can be similar to the buffer layer 154, 540, 810, or 922 described above. An example of the buffer layer 1022 is a SiO layer. The seed layer 1020 can be similar to the seed layer 156, 520, 820, or 920 described above. An example of the seed layer 1020 is an STO layer. As previously mentioned, the buffer layer 1022 can be formed by high temperature oxidation annealing of a seed layer 1020 deposited on a substrate 1010 (e.g., a silicon wafer), in which case the substrate 1010 can be oxidized at the interface between the seed layer 1020 and the substrate 1010 to form a buffer layer 1022 between the seed layer 1020 and the substrate 1010.

[0074]

[0089] The waveguide structure 1000 can include multiple EO material layers 1030, 1032, 1034, 1036, etc., and multiple intermediate layers 1040, 1042, 1044, etc. As previously described, the EO material layers 1030, 1032, 1034, 1036 can include ferroelectric crystals such as BaTiO (BTO), (Ba,Sr)TiO (BST), (Pb(Zr,Ti)O (PZT), (Pb,La)(Zr,Ti)O (PLZT), etc. The intermediate layers 1040, 1042, and 1044 can include, for example, MgO, BST, BaHfO, BaZrO, SrHfO, SrNbO, SrTiO, SrZrO, or other oxides. The EO material layers and intermediate layers can be alternately layered on the seed layer 1020. The EO material layers and interlayers may be deposited in a layered fashion, whereby the EO material layers and interlayers are interleaved and interdigitated with one another to form a stack of alternating layers. The EO material layers and interlayers may be thin layers, and the ratio of the thickness of each EO material layer to the thickness of each interlayer may be about 20:1, 10:1, 8:1, 5:1, or less. In one example, each EO material layer may be about 100 nm or less in thickness, and each interlayer may be about 10 nm or less in thickness. The total thickness of the EO material layers in the stack may be greater than a certain value, such as greater than about 300 nm.

[0075]

[0090] The waveguide structure 1000 may further include a waveguide including a cladding layer 1050 and a waveguide core including several layers of alternating layers. In the example shown in FIG. 10 , the waveguide core may include EO material layers 1034 and 1036 and intermediate layers 1042 and 1044, which may be patterned, for example, by photolithography. In some embodiments, the intermediate layers 1044 and 1042 may be used as etch stops for etching the EO material layers 1034 and 1036. For example, the intermediate layer 1044 may be used as an etch stop for etching the EO material layer 1036 using a first recipe, and then the intermediate layer 1044 may be etched using a second recipe, and the intermediate layer 1042 may be used as an etch stop for etching the EO material layer 1034 using the first recipe. In this manner, the waveguide core may be formed as a mesa structure including several EO material layers and intermediate layers.

[0076]

[0091] Cladding layer 1050 can be formed on the waveguide core, for example, as described above with respect to block 450 of FIG. 4 and FIG. 5E. Cladding layer 1050 can include, for example, Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, SiOCN, HfO2, etc. Trenches can be etched from cladding layer 1050 and some layers in the stack of alternating layers down to seed layer 1020 or buffer layer 1022, which may be used as an etch stop for etching the trenches. A conductive material, such as a metal (e.g., Cu, W, Co, etc.), can be deposited or otherwise fill the trenches to form electrode 1060. As described above, electrode 1060 can be used to apply voltage signals to EO material layers 1030 and 1032 via edge contacts and / or to apply voltage signals to EO material layers 1034 and 1036.

[0077]

[0092] The aforementioned waveguide structures 800, 900, and 1000 can each include a stack of alternating layers, including alternating EO material layers and interlayers. The EO material layers and interlayers can be thin and have similar lattice structures at room temperature, and thus can be interlocked after the fabrication process. The interlayers can include materials that do not undergo phase transitions when the operating temperature changes. Thus, the interlocking between the thin EO material layers and the interlayers can prevent the EO material layers from undergoing phase transitions when the operating temperature changes, for example, to cryogenic temperatures. Therefore, the EO material layers can substantially maintain their room-temperature lattice structure (e.g., tetragonal phase) and polarization (e.g., in-phase polarization), and therefore the EO effect (e.g., Pockels coefficient), at cryogenic temperatures. The waveguide structures 800, 900, and 1000 can be used in optical switches, EO modulators, or other active photonic devices that operate at cryogenic temperatures using phase tuning or refractive index modulation, such as the aforementioned Mach-Zehnder interferometer 120 or optical switch 100.

[0078]

[0093] Various embodiments of the waveguide structures and EO devices disclosed herein can utilize single transverse mode waveguides (e.g., waveguide core widths in the submicron to micron range) or multimode waveguides (with wider waveguide cores supporting two or more transverse modes). Various materials, layers, and structures can be formed to fabricate EO devices using, for example, epitaxial growth, deposition, layer transfer, etc. While techniques for improving the Pockels effect at cryogenic temperatures are described in some embodiments, the techniques disclosed herein can be used to improve other EO effects at different temperatures. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0079]

[0094] FIG. 11 is a simplified flowchart 1100 illustrating an example method for fabricating processed wafers and / or EO devices including an EO material layer characterized by a substantially constant EO coefficient from room temperature to cryogenic temperatures, according to certain embodiments. Note that while FIG. 11 describes operations in a sequential flow, some operations may occur in parallel or simultaneously. Some operations may be performed in a different order. A process may include additional steps not included in the diagram. Some operations may be optional and therefore may be omitted in various embodiments. Also, some operations may be performed in conjunction with other operations.

[0080]

[0095] In block 1110, the operations may include depositing a seed layer on a substrate. The substrate may be, for example, a semiconductor substrate (e.g., a silicon wafer), a glass substrate, a quartz substrate, a ceramic substrate, etc., as previously described. The seed layer may be epitaxially grown on the substrate using, for example, MBE techniques, and may be, for example, SrTiO 3( STO), MgO, or LaAlO3.

[0081]

[0096] In block 1120, the operations may include epitaxially depositing a first electro-optic material layer on the seed layer using, for example, MBE techniques. The seed layer may have a lattice structure similar to that of the first EO material layer and / or the substrate, and may include, for example, a ferroelectric material such as BTO, BST, PZT, or PLZT, or a perovskite ferroelectric material. The material in the first EO material layer may have a square lattice structure at room temperature and, when used in bulk, may change its lattice structure and crystalline phase at lower temperatures. The first EO material layer may have a thickness of, for example, less than 100 nm.

[0082]

[0097] In block 1130, the operations may include annealing the substrate, the seed layer, and the first electro-optic material layer in an oxygen environment to form an oxide buffer layer between the substrate and the seed layer. The annealing may be performed, for example, at a temperature higher than the softening temperature of the oxide buffer layer, for example, higher than 600°C (e.g., 750°C or higher). The high-temperature annealing may help form an oxide buffer layer (e.g., SiO) at the interface between the substrate (e.g., Si) and the seed layer (e.g., STO). If the annealing temperature is higher than the softening temperature of the oxide buffer layer, the oxide buffer layer may soften, and thus the seed layer and the first EO material layer may be separated from the substrate, allowing stress within the seed layer and the first EO material layer to be released.

[0083]

[0098] In block 1140, the operations may include depositing a first intermediate layer on the first electro-optic material layer. The first intermediate layer may include a crystal structure similar to that of the first EO material layer and may not undergo a phase transition at low temperatures. Thus, the first intermediate layer may include a material capable of maintaining the first lattice structure at room temperature and cryogenic temperatures (e.g., at about 4 K). The first intermediate layer may include, for example, at least one of MgO, (Ba,Sr)TiO3, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, and SrZrO3.

[0084]

[0099] In block 1150, the operations may include depositing a second electro-optic material layer on the first interlayer. The second electro-optic material layer may be similar to the first electro-optic material layer. In block 1160, the operations may include annealing the second electro-optic material layer and the first interlayer at a high temperature to relax the second EO material layer, improve material quality, and ensure in-plane polarization in the second EO material layer.

[0085]

[0100] In some embodiments, additional interlayers and EO material layers can be alternately deposited until the total thickness of the EO material layer is greater than the desired value. In some embodiments, the additional layers, including the alternating interlayers and EO material layers, can be annealed using high-temperature annealing. The first interlayer, second interlayer, and additional interlayers can have thicknesses of, for example, less than about 10 nm and can be used to separate the EO material layers from each other and apply tensile stress to the EO material layers to limit phase transitions in the EO material layers. In some embodiments, the ratio between the thickness of each EO material layer and the thickness of each interlayer can be about 20:1, 10:1, 8:1, 5:1, or less. Because the interlayers cannot change their lattice structure and crystalline phase at lower temperatures (e.g., cryogenic temperatures), the interlayers can limit the EO material layer from changing its room-temperature lattice structure and crystalline phase at lower temperatures. Therefore, the EO material layer can have a high EO effect (e.g., Pockels effect) at lower temperatures. For example, the EO material layer can include BTO and have a Pockels coefficient greater than 300 pm / V at cryogenic temperatures.

[0086]

[0101] Optionally, in block 1170, a waveguide may be formed on the stack of interleaved intermediate layers and EO material layers. The waveguide may be a section of a Mach-Zehnder interferometer, a resonator, an optical switch, an electro-optic modulator, or the like. In some embodiments, the waveguide may include a waveguide core including a dielectric material or a semiconductor material, or one or more electro-optic material layers within the electro-optic material layers. In some embodiments, the waveguide may include a waveguide cladding layer in physical contact with an electro-optic material layer within the electro-optic material layers and may be characterized by a thermal expansion coefficient different from that of the electro-optic material layer. The waveguide cladding layer may include, for example, at least one of Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, SiOCN, and HfO2.

[0087]

[0102] In some embodiments, forming the waveguide may include patterning one or more electro-optic material layers to form a waveguide core and depositing a dielectric cladding layer on the waveguide core. Patterning the one or more electro-optic material layers may include etching the one or more electro-optic material layers using the intermediate layer as an etch stop layer. In some embodiments, forming the waveguide may include depositing a layer of high refractive index material on a stack of layers including the intermediate layer and the EO material layer, patterning the layer of high refractive index material to form a waveguide core, and depositing a dielectric cladding layer on the waveguide core. In some embodiments, forming the waveguide may include bonding a wafer including the waveguide to the stack of layers including the intermediate layer and the EO material layer. In some embodiments, the method may also include etching a trench in the stack of layers including the intermediate layer and the EO material layer and filling the trench with a conductive material. In some embodiments, etching the trench in the stack of layers may include using an oxide buffer layer as an etch stop layer.

[0088]

[0103] FIG. 12 is a simplified system block diagram of an example hybrid quantum computing system 1200 including an electro-optical device (e.g., a switch) according to certain embodiments. To operate at low temperatures, e.g., liquid helium temperatures, embodiments of the present invention incorporate the electro-optical switches described herein into a system including a cooling system. Accordingly, embodiments of the present invention provide a hybrid computing system, for example, as shown in FIG. 12. The hybrid quantum computing (QC) system 1200 includes a user interface device 1204 communicatively coupled to a hybrid quantum computing subsystem 1206. The user interface device 1204 can be any type of user interface device, e.g., a terminal including a display, keyboard, mouse, touchscreen, etc. Furthermore, the user interface device itself can be a computer, such as a personal computer (PC), laptop, tablet computer, etc.

[0089]

[0104] In some embodiments, user interface device 1204 provides an interface through which a user can interact with hybrid QC subsystem 1206. For example, user interface device 1204 can execute software such as a text editor, an interactive development environment (IDE), a command prompt, a graphical user interface, etc., that allows a user to program or otherwise interact with the QC subsystem to execute one or more quantum algorithms. In other embodiments, hybrid QC subsystem 1206 may be pre-programmed, and user interface device 1204 may simply be an interface through which a user can initiate quantum computations, monitor progress, and receive results from hybrid QC subsystem 1206. Hybrid QC subsystem 1206 further includes a classical computing system 1208 coupled to one or more quantum computing chips 1210. In some examples, classical computing system 1208 and quantum computing chip 1210 may be coupled to other electronic components 1212, such as pulsed pump lasers, microwave oscillators, power supplies, network hardware, etc.

[0090]

[0105] In some embodiments utilizing cryogenic operation, quantum computing system 1209 may be housed in a cryostat, such as cryostat 1214. In some embodiments, quantum computing chip 1210 may include one or more constituent chips, such as hybrid electronic chip 1216 and integrated photonics chip 1218, which may include various waveguide structures and / or EO devices disclosed herein. Signals may be routed on-chip and off-chip in any number of ways, for example, via optical interconnects 1220 and other electronic interconnects 1222. Additionally, hybrid quantum computing system 1200 may employ quantum computing processes, such as measurement-based quantum computing (MBQC), that use one or more cluster states of qubits.

[0091]

[0106] As will be apparent to those skilled in the art, substantial variations may be made depending on the particular implementation. For example, customized hardware may be used and / or particular elements may be implemented in hardware, software (including portable software such as applets), or both. Furthermore, connection to other computing devices, such as network input / output devices, may be employed.

[0092]

[0107] With reference to the accompanying figures, components that may include memory may include non-transitory machine-readable media. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any storage medium that participates in providing data that causes a machine to operate in a specific manner. In the embodiments provided above, various machine-readable media may participate in providing instructions / code to a processor and / or other device for execution. Additionally or alternatively, machine-readable media may be used to store and / or transport such instructions / code. In many implementations, the computer-readable medium is a physical and / or tangible storage medium. Such media may take many forms, including, but not limited to, non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and / or optical media, punch cards, paper tape, any other physical medium with a pattern of holes, RAM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), FLASH-EPROM, any other memory chip or cartridge, a carrier wave as described below, or any other medium from which a computer can read instructions and / or code.

[0093]

[0108] The methods, systems, and devices described herein are examples. Various embodiments may omit, substitute, or add various procedures or components as appropriate. For example, features described with respect to particular embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. Various components of the diagrams provided herein may be implemented in hardware and / or software. Also, technology evolves, and therefore, many of the elements are examples that do not limit the scope of the disclosure to those specific examples.

[0094]

[0109] It has proven convenient at times, primarily for reasons of common usage, to refer to signals as bits, information, values, elements, symbols, characters, variables, terms, numbers, numerals, and the like. It should be understood, however, that all of these or similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless otherwise indicated, and as is clear from the above description, throughout this specification, descriptions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” “ascertaining,” “identifying,” “associating,” “measuring,” “performing,” and the like will be understood to refer to specific apparatus operations or processes, such as a special purpose computer or similar special purpose electronic computing device. Thus, in the context of this specification, a special purpose computer or similar special purpose electronic computing device can manipulate or transform signals, which are typically represented as physical electronic, electrical, or magnetic quantities, in the memories, registers, or other information storage, transmission, or display devices of the special purpose computer or similar special purpose electronic computing device.

[0095]

[0110] Those skilled in the art will appreciate that the information and signals used to communicate the messages described herein may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0096]

[0111] As used herein, the terms "and," "or," and "and / or" can have a variety of meanings that are expected to depend, at least in part, on the context in which such terms are used. In general, "or," when used to associate a list, such as A, B, or C, is intended to refer to A, B, and C, which are used herein in an inclusive sense, as well as A, B, or C, which are used herein in an exclusive sense. Furthermore, as used herein, the term "one or more" may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an example, and claimed subject matter is not limited to this example. Furthermore, the term "at least one of," when used to associate a list, such as A, B, or C, can be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0097]

[0112] Throughout this specification, references to "one example," "one example," "particular example," or "exemplary implementation" mean that a particular feature, structure, or characteristic described in connection with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Thus, appearances of the phrases "in one example," "in one example," "particular example," "in a particular implementation," or other similar phrases in various places throughout this specification do not necessarily all refer to the same features, examples, and / or limitations. Furthermore, particular features, structures, or characteristics may be combined in one or more examples and / or characteristics.

[0098]

[0113] In some implementations, operations or processing may involve physical manipulations of physical quantities. Typically, though not necessarily, such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, or otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, or the like. It should be understood, however, that all of these or similar terms are to be associated with the appropriate physical quantities and are merely convenient labels. Unless otherwise indicated, and as will be apparent from the description herein, it is understood that throughout this specification, descriptions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” or the like refer to operations or processes of a specific apparatus, such as a special purpose computer, a special purpose computing apparatus, or a similar special purpose electronic computing device. Thus, in the context of this specification, a special purpose computer or a similar special purpose electronic computing device can manipulate or transform signals that are typically represented as physical electronic or magnetic quantities in the memories, registers, or other information storage, transmission, or display devices of the special purpose computer or a similar special purpose electronic computing device.

[0099]

[0114] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will recognize that the claimed subject matter may be practiced without these specific details. In other instances, methods and apparatuses known to those skilled in the art have not been described in detail so as not to obscure the claimed subject matter. Therefore, it is intended that the claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may include all embodiments falling within the scope of the appended claims and equivalents thereof.

Claims

1. A substrate; a laminate on the substrate; Equipped with The laminate is a plurality of layers of electro-optic material; a plurality of intermediate layers interleaved with the plurality of electro-optic material layers; Including, the plurality of intermediate layers maintain a first lattice structure at room temperature and at cryogenic temperatures; the plurality of electro-optic material layers maintain a second lattice structure and a crystalline phase at the room temperature and the cryogenic temperature. Wafer.

2. The wafer of claim 1 further comprising an epitaxial seed layer between the substrate and the stack.

3. The epitaxial seed layer is made of SrTiO3, LaAlO ３ 3. The wafer of claim 2, further comprising at least one of: MgO;

4. The wafer of claim 2 further comprising an oxide layer of the substrate between the epitaxial seed layer and the substrate.

5. The wafer of claim 1 , wherein the plurality of electro-optic material layers are characterized by a square lattice structure at the cryogenic temperature.

6. The plurality of electro-optic material layers are BaTiO ３ , (Ba,Sr)TiO ３ , Pb(Zr,Ti)O ３ , or (Pb,La)(Zr,Ti)O ３ The wafer of claim 1 , comprising at least one of:

7. The intermediate layers are made of MgO, (Ba, Sr)TiO ３ , BaHfO ３ , BaZrO ３ , SrHfO ３ , SrZrO ３ , or SrNbO ３ The wafer of claim 1 , comprising at least one of:

8. 2. The wafer of claim 1, wherein the ratio between the thickness of each of the plurality of electro-optic material layers and the thickness of each of the plurality of intermediate layers is 20:1 or less.

9. depositing a seed layer on a substrate; epitaxially depositing a first layer of electro-optic material on the seed layer; annealing the substrate, the seed layer, and the first electro-optic material layer in an oxygen environment to form an oxide buffer layer between the substrate and the seed layer; depositing a first intermediate layer on the first electro-optic material layer, the first intermediate layer comprising a material that maintains a first lattice structure at room temperature and at cryogenic temperatures; depositing a second layer of electro-optic material on the first intermediate layer; annealing the second electro-optic material layer and the first intermediate layer; A method comprising:

10. 10. The method of claim 9, wherein the first layer of electro-optic material and the second layer of electro-optic material comprise electro-optic materials characterized by the cryogenic second lattice structure that is different from the room temperature third lattice structure.

11. The method of claim 10 , wherein the third lattice structure is the same crystal structure as the first lattice structure.

12. 10. The method of claim 9, wherein annealing the substrate, the seed layer, and the first layer of electro-optic material comprises annealing at a temperature above a softening temperature of the oxide buffer layer.

13. depositing a second intermediate layer on the second electro-optic material layer, the second intermediate layer comprising the material that maintains the first lattice structure at the room temperature and the cryogenic temperature; depositing a third electro-optic material layer on the second intermediate layer; annealing the third electro-optic material layer and the second intermediate layer; The method of claim 9 further comprising:

14. patterning the third layer of electro-optic material to form a waveguide core; depositing a dielectric cladding layer on the waveguide core; The method of claim 13 further comprising:

15. 15. The method of claim 14, wherein the step of patterning the third electro-optic material layer comprises etching the third electro-optic material layer using the second intermediate layer as an etch stop layer.

16. The method of claim 13 further comprising forming a waveguide on the third layer of electro-optic material.

17. The step of forming the waveguide on the third electro-optic material layer comprises: forming a waveguide core on the third electro-optic material layer; depositing a dielectric cladding layer on the waveguide core; 17. The method of claim 16, comprising:

18. 17. The method of claim 16, wherein forming the waveguide on the third electro-optic material layer comprises bonding a wafer containing the waveguide to the third electro-optic material layer.

19. etching trenches in the first, second, and third electro-optic material layers and the first and second intermediate layers; filling the trench with a conductive material; 17. The method of claim 16, further comprising:

20. 10. The method of claim 9, wherein the ratio between the thickness of the first electro-optic material layer and the thickness of the first intermediate layer is 20:1 or less.

Images