Semiconductor design method and device

Abstract

To provide a semiconductor design method and a device.SOLUTION: A semiconductor design method may include steps of: inputting a first type of design data into a first deep learning model; inputting a second type of design data into a second deep learning model of a different type from that of the first deep learning model; generating a fusion feature by fusing a calculation result of the second deep learning model with a feature generated by calculation up through a first layer of the first deep learning model; inputting the fusion feature into a second layer that follows the first layer of the first deep learning model; and performing a task related to routability of a circuit after calculation of the first deep learning model is completed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor design method and apparatus. [Background technology]

[0002] Semiconductor design can be broadly divided into logical design and physical design. The logical design process defines specifications, including the functions and performance of a semiconductor chip, and then implements the chip's functions using logic gates and circuits, performing simulations to confirm operation. The logical design process can generate RTL (Register Transfer Level) code as its output, which can be written in hardware engineering languages such as Verilog or VHDL (VHSIC Hardware Description Language).

[0003] The physical design process involves designing the physical configuration of the chip to be actually manufactured based on the logical design. During the physical design process, detailed processes such as floorplanning, power planning, placement, routing, and verification can be performed to generate the chip's geometric structure and design data that can be used in the actual manufacturing process. Specifically, floorplanning involves planning the overall layout of the chip, determining the location of functional blocks, and optimizing the connections between the blocks. Power planning involves formulating a plan for supplying and distributing power to the chip and designing the power grid. In placement, circuit components (e.g., unit elements, cells, etc. in a netlist) defined in the logical design are placed in physical locations, and the wiring step involves generating electrical paths connecting the placed circuit components. These detailed processes can be carefully performed to satisfy design rules or performance targets determined in connection with chip manufacturing. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the invention is to provide a semiconductor design method and apparatus that can minimize delays and overheads caused by iterative optimization methods in conventional semiconductor design by predicting routability based on a deep learning model.

[0005] Another problem to be solved is to provide a semiconductor design method and apparatus that can provide improved performance in routability prediction by encoding design data of semiconductor chips in various types and training a deep learning model. [Means for solving the problem]

[0006] A semiconductor design method according to one embodiment may include the steps of: inputting a first type of design data into a first deep learning model; inputting a second type of design data into a second deep learning model of a different type from the first deep learning model; fusing a calculation result of the second deep learning model with a feature of the first deep learning model for which calculation up to a first layer has been completed to generate a fusion feature; inputting the fusion feature into a second layer of the first deep learning model that follows the first layer; and performing a task related to circuit routability after calculation of the first deep learning model is completed.

[0007] In some embodiments, the first deep learning model may include a graph-based deep learning model, and the first type of design data may include graph-based circuit design data; the second deep learning model may include an image-based deep learning model, and the second type of design data may include image-based circuit design data.

[0008] In some embodiments, the semiconductor design method further includes converting image-based features of the second deep learning model, for which calculations up to a third layer have been completed, into graph-based features, and generating the fused features may include fusing the converted graph-based features with features of the first deep learning model, for which calculations up to the first layer have been completed, to generate the fused features.

[0009] In some embodiments, converting to the graph-based features may include obtaining grid cell information corresponding to the image-based features; and combining the grid cell information with the image-based features.

[0010] In some embodiments, converting to graph-based features may include upsampling the image-based features; and converting the upsampled image-based features to the graph-based features.

[0011] In some embodiments, the first deep learning model may include an image-based deep learning model, and the first type of design data may include image-based circuit design data; the second deep learning model may include a graph-based deep learning model, and the second type of design data may include graph-based circuit design data.

[0012] In some embodiments, the semiconductor design method may further include converting graph-based features of the second deep learning model, for which calculations up to a third layer have been completed, into image-based features, and generating the fused features may include fusing the converted image-based features with features of the first deep learning model, for which calculations up to the first layer have been completed, to generate the fused features.

[0013] In some embodiments, the step of converting into image-based features may include arranging the graph-based features in an image format; and combining the arranged image with features of the first deep learning model for which calculations up to the first layer have been completed.

[0014] In some embodiments, the step of converting into image-based features may further include a step of downsampling the arranged image in consideration of the resolution of features for which calculations up to the first layer of the first deep learning model have been completed.

[0015] In some embodiments, the circuit routability related tasks may include a congestion prediction task or a design rule violation prediction task.

[0016] According to one embodiment, a semiconductor design method may include the steps of: obtaining a graph-based first feature of a GNN (Graph Neural Network) that has completed calculations up to a first layer; obtaining an image-based second feature of a CNN (Convolutional Neural Network) that has completed calculations up to a second layer; fusing the first feature and the second feature to generate a third feature; inputting the third feature into a layer subsequent to the first layer of the GNN in a first operating mode, and performing a prediction related to routability of the circuit; and inputting the third feature into a layer subsequent to the second layer of the CNN in a second operating mode, and performing a prediction related to routability of the circuit.

[0017] In some embodiments, generating the third feature may include upsampling the second feature; obtaining grid cell information corresponding to the upsampled second feature; and combining the grid cell information and the upsampled second feature to generate the third feature.

[0018] In some embodiments, generating the third feature may include arranging the first feature in an image form; downsampling the arranged image; and combining the downsampled arranged image with the second feature to generate the third feature.

[0019] According to one embodiment, a semiconductor design apparatus includes one or more processors and one or more memory devices, wherein the one or more memory devices include program code, and the program code is executed via the one or more processors to input a first type of design data to a first deep learning model, input a second type of design data to a second deep learning model of a different type from the first deep learning model, fuse a calculation result of the second deep learning model with a feature of the first deep learning model for which calculation up to a first layer has been completed to generate a fusion feature, input the fusion feature to a second layer of the first deep learning model that follows the first layer, and perform a task related to circuit routability after calculation of the first deep learning model is completed.

[0020] In some embodiments, the program code may convert image-based features of the second deep learning model, for which calculations up to a third layer have been completed, into graph-based features, and generating the fused features may include fusing the converted graph-based features with features of the first deep learning model, for which calculations up to the first layer have been completed, to generate the fused features.

[0021] In some embodiments, converting to the graph-based features may include obtaining grid cell information corresponding to the image-based features and combining the grid cell information with the image-based features.

[0022] In some embodiments, converting to the graph-based features may include upsampling the image-based features and converting the upsampled image-based features to the graph-based features.

[0023] In some embodiments, the program code may convert graph-based features of the second deep learning model, for which calculations up to a third layer have been completed, into image-based features, and generating the fused features may include fusing the converted image-based features with features of the first deep learning model, for which calculations up to the first layer have been completed, to generate the fused features.

[0024] In some embodiments, converting to the image-based features may include arranging the graph-based features in an image format and combining the arranged image with features of the first deep learning model for which calculations up to the first layer have been completed.

[0025] In some embodiments, converting to image-based features may further include downsampling the arranged image in consideration of the resolution of features for which calculations up to the first layer of the first deep learning model have been completed. [Effects of the Invention]

[0026] According to an embodiment, by predicting routability based on a deep learning model, it is possible to minimize delays and overheads caused by iterative optimization methods in conventional semiconductor design. In addition, by encoding semiconductor chip design data into various types and training the deep learning model, it is possible to improve the performance of routability prediction. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a diagram illustrating a semiconductor design apparatus according to an embodiment; [Figure 2] 2 to 5 are diagrams for explaining the operation of the semiconductor design apparatus according to an embodiment. [Figure 3]2 to 5 are diagrams for explaining the operation of the semiconductor design apparatus according to an embodiment. [Figure 4] 2 to 5 are diagrams for explaining the operation of the semiconductor design apparatus according to an embodiment. [Figure 5] 2 to 5 are diagrams for explaining the operation of the semiconductor design apparatus according to an embodiment. [Figure 6] 1 is a flowchart illustrating a semiconductor design method according to an embodiment. [Figure 7] 1 is a flowchart illustrating a semiconductor design method according to an embodiment. [Figure 8] FIG. 1 is a block diagram illustrating a computing device according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. In order to clearly explain the present invention in the drawings, parts that are not relevant to the description will be omitted, and similar parts will be designated by similar reference numerals throughout the specification.

[0029] Throughout the specification and claims, when a part is said to "comprise" a certain element, this does not mean that it excludes other elements, but that it may further include other elements, unless otherwise specified. Terms including ordinal numbers such as first, second, etc. may be used to describe various elements, but the elements are not limited by these terms. These terms are used only to distinguish one element from another.

[0030] The terms "unit," "machine," "module," and the like used herein may refer to a unit capable of processing at least one function or operation described herein, which may be implemented in hardware or circuits, software, or a combination of hardware or circuits and software. Furthermore, at least some of the configurations or functions of the semiconductor design methods and apparatuses according to the embodiments described below may be implemented in a program or software, which may be stored in a computer-readable medium.

[0031] FIG. 1 is a diagram illustrating a semiconductor design apparatus according to an embodiment.

[0032] Referring to FIG. 1 , a semiconductor design apparatus according to an embodiment may execute a program loaded into one or more memory devices through one or more processors. For example, the semiconductor design apparatus may be embodied as a computing device 50 as described below in connection with FIG. 8 . In this case, the one or more processors may correspond to processor 510 of computing device 50, and the one or more memory devices may correspond to memory 530 of computing device 50. The program may be executed by the one or more processors and perform a function for predicting wireability based on a deep learning model. In this specification, the functions performed by the program are expressed using the term “… unit” to logically distinguish them.

[0033] A semiconductor design apparatus according to an embodiment may include a fusion feature generator 10, a graph-based deep learning model 22, and an image-based deep learning model 32.

[0034] The physical design process of a semiconductor chip includes detailed steps such as floor planning, power planning, placement, routing, and verification. In particular, placement and routing can involve more detailed steps. For example, after floor planning, detailed steps such as global placement, detailed placement, trial routing, global routing, and detailed routing verification can be performed. Here, the global placement step involves planning the overall layout of the chip and determining the general locations of each functional block and standard cell. The detailed placement step involves placing circuit elements in precise locations on the chip based on the general locations determined in the global placement. After placement is complete, initial routing is attempted and trial routing is performed to verify the validity of the placement and routing strategy. If problem areas are identified before actual routing, the routing strategy can be adjusted. Next, in the global wiring step, the electrical connection paths between each component of the chip are roughly determined based on the connection information of, for example, a netlist, and in the detailed wiring verification step, after the detailed wiring is completed, it can be verified whether the design rules are complied with and whether performance targets are achieved.

[0035] It should be noted that if a design rule violation or performance target unachievability occurs in the detailed routing verification step, it may be necessary to return to the previous step and perform iterative optimization, or if the problem exceeds the level that can be resolved by returning to the previous step, it may be necessary to return to the floorplanning step and change the overall layout of the chip. This can cause significant delays and overhead in semiconductor design. To minimize this delay and overhead, the semiconductor design apparatus according to embodiments can predict routability based on a deep learning model. Predicting routability not only optimizes the limited space on the chip and provides placement and routing that comply with design rules, but also analyzes routing congestion in the early design steps and identifies and adjusts problem areas in advance. Here, the deep learning model may be a type of artificial neural network that extracts high-level features from input data through multiple processing layers and performs tasks such as classification, recognition, and prediction based on the extracted features.

[0036] The graph-based deep learning model 22 may have a neural network structure specialized for processing chip design information (e.g., circuit information) encoded in graph data. A graph is composed of nodes and edges between the nodes, and each node may have various neighbors, so graph data may generally have an atypical form. The graph-based deep learning model 22 may learn new characteristics of a node by aggregating information about the node's characteristics and its neighbors based on the graph data (i.e., graph-based design data 20) in which the chip design information is encoded. In this process, the graph-based deep learning model 22 may select neighbors with high importance or apply weights to node connections. In some embodiments, the graph-based deep learning model 22 may be implemented using various neural networks with GNN architectures, such as a graph neural network (GNN), a graph convolutional network (GCN), a graph attention network (GAT), or a graph sample and aggregation (GraphSAGE). In particular, in some embodiments, the graph-based deep learning model 22 may be implemented using a heterogeneous graph neural network (GNN). Here, the heterogeneous GNN may be a type of GNN specifically designed to process heterogeneous graphs including different types of nodes and edges. That is, the heterogeneous GNN can model complex relationships between different types of nodes and edges.

[0037] The image-based deep learning model 32 may have a neural network structure specialized for processing chip design information (e.g., circuit information) encoded in image data. Here, an image refers to something organized into a grid of pixels, and since each pixel has a fixed neighbor, image data may generally have a stylized form. The image-based deep learning model 32 may be specialized for learning a spatial hierarchical structure and recognizing and analyzing visual patterns based on image data (i.e., image-based design data 30) in which chip design information is encoded. In some embodiments, the image-based deep learning model 32 may be implemented using a convolutional neural network (CNN) or various neural networks having a CNN architecture.

[0038] When using only a graph-based model, the inductive bias of spatially related data cannot be reflected in the neural network structure, resulting in unnecessary overload.On the other hand, when using only an image-based model, the relationship between spatially separated but topologically connected pixels or information between cells and nets cannot be used for learning.In addition, when semiconductor chips vary in size, chip design information must be encoded into images of specific sizes, which can result in a loss of information as one pixel corresponds to multiple cells.

[0039] To solve this problem, the semiconductor design apparatus according to the present embodiment encodes chip design information with graph data and image data to generate graph-based design data 20 and image-based design data 30, and can predict routability using both the graph-based deep learning model 22 and the image-based deep learning model 32. The fusion feature generator 10 operates between the graph-based deep learning model 22 and the image-based deep learning model 32, and can generate a fusion feature by fusing a feature calculated from the graph-based deep learning model 22 with a feature calculated from the image-based deep learning model 32, and provide the fusion feature to the graph-based deep learning model 22 or the image-based deep learning model 32.

[0040] Specifically, the graph-based deep learning model 22 receives the graph-based design data 20 as input and is provided with the fused features from the fused feature generator 10. Based on the input, the graph-based deep learning model 22 can predict the routability of a circuit and output the output graph 24. The output graph 24 can be appropriately processed and converted into, for example, a wiring congestion prediction graph 26 for intensively analyzing the degree of wiring congestion among the routability of a circuit, depending on the implementation or analysis purpose. In this case, the fused feature generator 10 can generate a fused feature by fusing the calculation results of the image-based deep learning model 32 with features obtained by completing calculations up to the intermediate layer among the multiple layers constituting the graph-based deep learning model 22, and provide the fused feature to the graph-based deep learning model 22.

[0041] Meanwhile, the image-based deep learning model 32 receives the image-based design data 30 as input and is provided with fused features from the fused feature generator 10. Based on the input, the image-based deep learning model 32 can predict the wiring feasibility of a circuit and output an output image 34. The output image 34 can be appropriately processed and converted depending on the implementation or analysis purpose, for example, as a wiring congestion prediction image 36 for intensively analyzing the wiring congestion level among the wiring feasibility of the circuit. In this case, the fused feature generator 10 can generate a fused feature by fusing the calculation results of the graph-based deep learning model 22 with features obtained by completing calculations up to the intermediate layer among the multiple layers constituting the image-based deep learning model 32, and provide the fused feature to the image-based deep learning model 32.

[0042] In this way, by converting graph-based features into image-based features and fusing them, or converting image-based features into graph-based features and fusing them, problems that may occur when using only the graph-based model or only the image-based model as described above can be solved. Hereinafter, the operation of the semiconductor design apparatus according to the embodiment will be described in detail with reference to FIGS.

[0043] 2 to 5 are diagrams for explaining the operation of the semiconductor design apparatus according to an embodiment.

[0044] 2, deep learning models 221 and 222 may correspond to graph-based deep learning model 22 in FIG. 1, and deep learning models 321 and 322 may correspond to image-based deep learning model 32 in FIG. 1. As described above, deep learning models 221 and 222 and deep learning models 321 and 322 may be of different types. That is, deep learning models 221 and 222 may include graph-based deep learning models, and deep learning models 321 and 322 may include image-based deep learning models.

[0045] The semiconductor design device may input first-type design data 20 to deep learning models 221 and 222. Here, the first-type design data may include graph-based circuit design data. The semiconductor design device may also input second-type design data 30 to deep learning models 321 and 322. Here, the second-type design data may include image-based circuit design data.

[0046] Semiconductor circuit design data can be expressed in terms of, for example, cells, nets, and pins. A cell is a unit that represents a basic function of a circuit and can be a single component such as a logic gate (AND, OR, NOT, etc.), a flip-flop, or a latch, or a collection of more complex functions composed of a combination of these elements. A net defines the signal path within a circuit and can represent the electrical connection between two or more cells. A pin is a cell interface and corresponds to a point that receives signals from outside the cell or outputs signals from the cell. Each cell can have one or more input and output pins. This topological information can be encoded in the form of a graph. This type of design data can be classified as type 1. The deep learning model 221 can use the graph constructed using this topological information as input.

[0047] Meanwhile, after the placement step, the position information of the cells can be processed in the form of an image. For example, one pixel can be represented as a grid cell (or G-cell), and a collection of grid cells included in one net can be represented as a grid net (or G-net). Based on such geometric grid cell information, the occupancy or density of each cell can be encoded in the form of an image. This corresponds to the second type of design data. The deep learning model 321 can use the image composed of such geometric features as input.

[0048] In particular, the deep learning models 221 and 222 are implemented as heterogeneous GNNs, thereby enabling them to process graphs consisting of different types of nodes and edges, such as cells, nets, pins, and grid cells. In this case, attributes such as the cell position, node name (instance name), standard cell and IP (Intellectual Property) names, cell size, and the number of connected nets (degree) can be used as graph features related to cells, attributes such as the net name and the number of connected cells (degree) can be used as graph features related to nets, and attributes such as the pin name and the index of the connected cells and nets can be used as graph features related to pins.

[0049] Meanwhile, the deep learning models 321 and 322 are implemented as CNNs, and an image representing the position of a macro as 0 or 1 can be used as an input feature for a macro image feature, or an image representing distribution information of a network can be used as an input feature for RUDY (Rectangular Uniform wire Density).

[0050] The semiconductor design device may generate a fused feature by fusing the calculation results of the deep learning model 321 with features of the deep learning model 221 for which calculations have been completed up to the first layer, through the fused feature generation unit 10. Then, the semiconductor design device may input the fused feature to the second layer of the deep learning model 222, which is subsequent to the first layer of the deep learning model 221. After the calculations of the deep learning models 221 and 222 are completed, the semiconductor design device may perform a task related to circuit routability using the output graph 24. Meanwhile, the semiconductor design device may input second-type design data 30 to the deep learning models 321 and 322. Here, the second-type design data may include image-based circuit design data. Also, the semiconductor design device may input first-type design data 20 to the deep learning models 221 and 222. Here, the first-type design data may include graph-based circuit design data.

[0051] The semiconductor design device may generate a fused feature by fusing the calculation result of the deep learning model 221 with a feature of the deep learning model 321 for which calculations have been completed up to the first layer through the fused feature generation unit 10. Then, the semiconductor design device may input the fused feature to the second layer of the deep learning model 322, which is subsequent to the first layer of the deep learning model 321. After the calculations of the deep learning models 321 and 322 are completed, the semiconductor design device may perform a task related to the routability of the circuit using the output image 34.

[0052] That is, the fusion feature generation unit 10 can convert image-based features into graph forms and graph-based features into image forms so that the deep learning models 221 and 222 and the deep learning models 321 and 322 can exchange information with each other during learning. This allows semiconductor circuit information to be encoded in various forms without loss, thereby improving model performance.

[0053] 3, the first type design data 20 and the second type design data 30 can be processed in a manner in which grid cell features corresponding to graph-based features and image-based features are mutually shared in the intermediate layers of deep learning models 221 and 222 and deep learning models 321 and 322. Since pixel information of the image is encoded in the GNN in the form of grid cells, the image-graph conversion module 110 can upsample the image to match the original image size, combine it with the grid cell features, and transmit it to the next graph layer. The graph-image conversion module 120 can convert the graph into an image format, downsample it to match the size of the image-based features, combine it with the existing image-based features, and transmit it to the next image layer.

[0054] That is, the fused feature generation unit 10 may convert image-based features 421, for which calculations up to the third layer of the deep learning model 321 have been completed, into graph-based features through the image graph conversion module 110. Furthermore, the fused feature generation unit 10 may generate fused features 41 by fusing the converted graph-based features with features, for which calculations up to the first layer of the deep learning model 221 have been completed. In some embodiments, if necessary, the fused feature generation unit 10 may upsample the image-based features 421 through the upsampling module 112. In this case, the image graph conversion module 110 may convert the upsampled image-based features into graph-based features.

[0055] Meanwhile, the fused feature generation unit 10 may convert graph-based features 411, for which calculations up to the third layer of the deep learning model 221 have been completed, into image-based features through the graph-image conversion module 120. In addition, the fused feature generation unit 10 may generate a fused feature 42 by fusing the converted image-based features 422 with features 421, for which calculations up to the first layer of the deep learning model 321 have been completed. In some embodiments, if necessary, the fused feature generation unit 10 may perform downsampling on the result of the graph-image conversion module 120 through the downsampling module 122, taking into account the resolution of the features 421, for which calculations up to the first layer of the deep learning model 321 have been completed.

[0056] In the case of wiring congestion prediction, if the results are to be obtained in the form of an image, learning can be performed by applying an MSE (Mean Squared Error) loss function to the output image 34, and if the results are to be obtained in the form of a graph, learning can be performed by applying the MSE loss function to the predicted values of the grid cell nodes as in the output graph 24. In wiring congestion prediction, the RMSE values for the cases where only GNNs were used, only CNNs were used, and where GNNs and CNNs were used in combination according to the embodiment were obtained as shown in Table 1 below.

[0057] [Table 1]

[0058] According to the embodiment, it can be confirmed that the performance is excellent when GNN and CNN are used together.

[0059] Circuit routability-related tasks that can be performed using such a semiconductor design system include a congestion prediction task or a design rule violation prediction task. Changing the input features and output features enables the execution of various types of routing-related tasks. For example, if the congestion value that was the target for the input feature used in the congestion prediction task is used as an input value and the learning target is predicted to be a design rule violation represented by an image, the same model structure can be used to perform the design rule violation prediction task. Table 2 below shows examples of circuit routability-related tasks that can be performed using a semiconductor design system according to an embodiment.

[0060] [Table 2]

[0061] Referring to FIG. 4, the image graph conversion module 110 may acquire grid cell information from a feature map (FM1) corresponding to an image-based feature in order to convert the image-based feature, i.e., a feature 421 for which calculations up to the first layer of the deep learning model 321 have been completed, into a graph-based feature. Here, the feature map (FM1) is the feature 421 for which calculations up to the first layer of the deep learning model 321 have been completed, or is a feature map obtained by upsampling the feature 421 through the upsampling module 112. The image graph conversion module 110 may convert the image-based feature into a graph-based feature by combining the grid cell information and the image-based feature, thereby generating a fused feature 41. Here, combining the grid cell information and the image-based feature may be implemented by a concatenation operation, a sum operation, an attention operation, or the like, on the grid cell information and the image-based feature. The image graph conversion module 110 may transmit the generated fused feature 41 to the deep learning model 222.

[0062] That is, the graph-based features (H1, H2) corresponding to the grid cells (G5, G8), respectively, are combined with the image-based features (F1, F2), respectively, so that the image-based features (F1, F2) can be finally generated as the graph-based fused feature 41. Since the corresponding positions of the grid cells (G5, G8) on the image can be identified using the grid cell index (e.g., node identifier), it is possible to identify that the image-based features corresponding to the grid cells (G5, G8) are features (F1, F2) from the attributes of the grid cells (G5, G8).

[0063] 5, the graph-image conversion module 120 may generate a feature map (FM2) by arranging the graph-based features in an image format to convert graph-based features, i.e., features 411 for which calculations up to the first layer of the deep learning model 221 have been completed, into image-based features. Then, the downsampling module 122 may combine an arranged image 422 downsampled with features 421 for which calculations up to the first layer of the deep learning model 321 have been completed, thereby generating a fused feature 42. Combining the downsampled arranged image 422 with features 421 for which calculations up to the first layer of the deep learning model 321 has been completed may be implemented by performing a concatenation operation, a sum operation, an attention operation, etc., on the downsampled arranged image 422 and features 421 for which calculations up to the first layer of the deep learning model 321 have been completed. The fused feature generation unit 10 may transmit the generated fused feature 42 to the deep learning model 322.

[0064] That is, the graph-based features H1 and H2 corresponding to the grid cells G5 and G8, respectively, are rearranged in the form of an image and reshaped into tensors, and downsampling, for example, max pooling, can be applied to fit the resolution of the CNN layer 322. In this way, the features 422 generated by stacking the graph-based features at corresponding positions on the image can be combined with the image-based features 421 to finally generate image-based fused features 42.

[0065] FIG. 6 is a flowchart illustrating a semiconductor design method according to an embodiment.

[0066] Referring to FIG. 6, a semiconductor design method according to one embodiment may include a step of inputting a first type of design data into a first deep learning model (S601), a step of inputting a second type of design data into a second deep learning model of a different type from the first deep learning model (S602), a step of fusing the calculation results of the second deep learning model with features of the first deep learning model for which calculations up to the first layer have been completed to generate a fused feature (S603), a step of inputting the fused feature into a second layer of the first deep learning model that follows the first layer (S604), and a step of performing tasks related to circuit routability after calculations of the first deep learning model are completed (S605).

[0067] For more detailed information about the semiconductor design method, please refer to the description provided in relation to the embodiments in this specification, and therefore, a duplicated description will be omitted here.

[0068] FIG. 7 is a flowchart illustrating a semiconductor design method according to an embodiment.

[0069] Referring to FIG. 7, a semiconductor design method according to one embodiment may include the steps of: acquiring a graph-based first feature of a GNN for which operation has been completed up to a first layer (S701); acquiring an image-based second feature of a CNN for which operation has been completed up to a second layer (S702); fusing the first feature and the second feature to generate a third feature (S703); inputting the third feature into a layer subsequent to the first layer of the GNN in a first operating mode to perform a circuit routability-related prediction (S704); and inputting the third feature into a layer subsequent to the second layer of the CNN in a second operating mode to perform a circuit routability-related prediction (S705).

[0070] Here, the first operation mode may be an operation mode in which the routing possibility is ultimately obtained as graph data, and the second operation mode may be an operation mode in which the routing possibility is ultimately obtained as image data. For example, if it is desired to obtain a predicted result of the routing congestion in the form of a graph, the semiconductor design apparatus may be operated in the first operation mode, and if it is desired to obtain a predicted result of the routing congestion in the form of an image, the semiconductor design apparatus may be operated in the second operation mode.

[0071] That is, in the first operating mode, step (S703) may include the steps of upsampling the second feature, obtaining grid cell information corresponding to the upsampled second feature, and generating a third feature by combining the grid cell information and the upsampled second feature. Meanwhile, in the second operating mode, step (S703) may include the steps of arranging the first feature in an image form, downsampling the arranged image, and generating a third feature by combining the downsampled arranged image and the second feature.

[0072] In both cases, graph-based features are converted into image-based features and then fused, or image-based features are converted into graph-based features and then fused, which avoids the problems that may occur when using only the graph-based model or the image-based model described above, minimizing design delays and overhead and improving the performance of routability prediction.

[0073] For other details regarding the semiconductor design method, please refer to the description provided in connection with the embodiments of this specification, and therefore, a duplicate description will be omitted here.

[0074] FIG. 8 is a block diagram illustrating a computing device according to one embodiment.

[0075] Referring to FIG. 8, the semiconductor design method and apparatus according to the embodiment may be implemented using a computing device 50.

[0076] Computing device 50 may include at least one of a processor 510, memory 530, user interface input devices 540, user interface output devices 550, and storage devices 560, which communicate via a bus 520. Computing device 50 may also include a network interface 570 that is electrically connected to network 40. Network interface 570 may send and receive signals to and from other entities via network 40.

[0077] The processor 510 may be embodied in various types, such as a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a neural processing unit (NPU), or a microcontroller unit (MCU), and may be any semiconductor device that executes instructions stored in the memory 530 or the storage device 560. The processor 510 may be configured to implement the functions and methods described above in connection with the embodiments.

[0078] The memory 530 and the storage device 560 may include various forms of volatile or non-volatile storage media. For example, the memory may include a read only memory (ROM) 531 and a random access memory (RAM) 532. In this embodiment, the memory 530 may be located inside or outside the processor 510, and the memory 530 may be connected to the processor 510 via various known means.

[0079] In some embodiments, at least some of the configurations or functions of the semiconductor design method and apparatus according to the embodiments may be embodied in a program or software executed by the computing device 50, and the program or software may be stored in a computer-readable medium. Specifically, a computer-readable medium according to an embodiment may have a program recorded thereon that causes a computer including a processor 510 that executes a program or instructions stored in the memory 530 or the storage device 560 to execute steps included in the semiconductor design method according to the embodiments.

[0080] In some embodiments, at least some of the configurations or functions of the semiconductor design methods and apparatuses according to the embodiments may be implemented using hardware or circuitry of the computing device 50, or may be implemented in separate hardware or circuitry that can be electrically connected to the computing device 50.

[0081] According to the embodiments described above, by predicting routability based on a deep learning model, it is possible to minimize delays and overheads caused by iterative optimization methods in conventional semiconductor design. Furthermore, by encoding semiconductor chip design data into various types and training the deep learning model, it is possible to provide improved performance of routability prediction.

[0082] Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art to which the present invention pertains, utilizing the basic concept of the present invention defined in the following claims, also fall within the scope of the present invention. [Explanation of symbols]

[0083] 10 Fusion feature generation section 20 Graph-based design data 22 Graph-based deep learning models 24 Output Graph 26 Wiring congestion forecast graph 30 Image base design data 32 Image-based deep learning model 34 Output image 36 Wiring congestion forecast image 40 Network 41, 42 Fusion Features 50 Computing Devices

Claims

1. inputting a first type of design data into a first deep learning model; inputting a second type of design data into a second deep learning model of a different type from the first deep learning model; generating a fusion feature by fusing a calculation result of the second deep learning model with a feature of the first deep learning model for which calculation up to a first layer has been completed; inputting the fused features into a second layer subsequent to the first layer of the first deep learning model; and A semiconductor design method comprising a step of performing circuit routability related tasks after the first deep learning model has completed its calculations.

2. The first deep learning model includes a graph-based deep learning model; The first type of design data includes graph-based circuit design data, The second deep learning model includes an image-based deep learning model; The semiconductor design method of claim 1 , wherein the second type of design data includes image-based circuit design data.

3. The method further includes converting the image-based features of the second deep learning model, for which calculations up to a third layer have been completed, into graph-based features; The step of generating the fused feature comprises:

3. The semiconductor design method of claim 2, further comprising: fusing the converted graph-based features with features of the first deep learning model for which calculations up to the first layer have been completed, to generate the fused features.

4. The step of converting to graph-based features includes: obtaining grid cell information corresponding to the image-based features; and The semiconductor design method of claim 3 , further comprising the step of combining the grid cell information with the image-based features.

5. The step of converting to graph-based features includes: performing upsampling on the image-based features; and The semiconductor design method of claim 3 , further comprising converting the upsampled image-based features into the graph-based features.

6. The first deep learning model includes an image-based deep learning model; The first type of design data includes image-based circuit design data, The second deep learning model includes a graph-based deep learning model; The semiconductor design method of claim 1 , wherein the second type of design data includes graph-based circuit design data.

7. The method further includes converting the graph-based features of the second deep learning model, for which calculations up to a third layer have been completed, into image-based features; The step of generating the fused feature comprises:

7. The semiconductor design method of claim 6, further comprising: generating the fused feature by fusing the converted image-based feature with a feature of the first deep learning model for which calculations up to the first layer have been completed.

8. The step of converting into image-based features includes: arranging the graph-based features in an image format; and The semiconductor design method of claim 7 , further comprising a step of combining the arranged image with features of the first deep learning model for which calculations up to the first layer have been completed.

9. The step of converting into image-based features includes:

9. The semiconductor design method of claim 8, further comprising: downsampling the arranged image in consideration of a resolution of a feature of the first deep learning model for which calculations up to the first layer have been completed.

10. The circuit routability related tasks are:

2. The semiconductor design method according to claim 1, further comprising a congestion prediction task or a design rule violation prediction task.

11. Obtaining a graph-based first feature of a GNN (Graph Neural Network) on which calculations have been completed up to the first layer; Obtaining image-based second features for which calculations have been completed up to the second layer of a Convolutional Neural Network (CNN); fusing the first feature and the second feature to generate a third feature; inputting the third feature into a layer of the GNN subsequent to the first layer in a first operating mode to perform circuit routability-related predictions; and The semiconductor design method includes inputting the third feature to a layer of the CNN subsequent to the second layer in a second operating mode to make a routability-related prediction for the circuit.

12. The step of generating the third feature includes: performing upsampling on the second features; obtaining grid cell information corresponding to the upsampled second feature; and 12. The semiconductor design method of claim 11, further comprising combining the grid cell information and the upsampled second feature to generate the third feature.

13. The step of generating the third feature includes: arranging the first features in an image configuration; downsampling the aligned image; and 12. The semiconductor design method of claim 11, further comprising combining the downsampled aligned image and the second feature to generate the third feature.

14. one or more processors and one or more memory devices; the one or more memory devices contain program code; the program code is executed by the one or more processors; inputting the first type of design data into the first deep learning model; inputting a second type of design data into a second deep learning model of a different type from the first deep learning model; A fusion feature is generated by fusing a calculation result of the second deep learning model with a feature of the first deep learning model for which calculation up to a first layer has been completed; inputting the fused features into a second layer subsequent to the first layer of the first deep learning model; A semiconductor design device that performs tasks related to circuit routability after the first deep learning model has completed its calculations.

15. The program code Converting image-based features for which calculations up to the third layer of the second deep learning model have been completed into graph-based features; generating the fused feature comprises: The semiconductor design device of claim 14 , further comprising generating the fused feature by fusing the converted graph-based feature with a feature of the first deep learning model for which calculations up to the first layer have been completed.

16. The converting into graph-based features includes: obtaining grid cell information corresponding to the image-based feature; The semiconductor design system of claim 15 further comprising combining the grid cell information with the image-based features.

17. The converting into graph-based features includes: performing upsampling on the image-based features; The semiconductor design apparatus of claim 15 , further comprising converting the upsampled image-based features into the graph-based features.

18. The program code Converting graph-based features of the second deep learning model, for which calculations up to the third layer have been completed, into image-based features; generating the fused feature comprises: The semiconductor design device of claim 14 , further comprising fusing the converted image-based features with features of the first deep learning model for which calculations up to the first layer have been completed to generate the fused features.

19. converting the image-based features to The graph-based features are arranged in an image format; The semiconductor design device of claim 18 , further comprising combining the arranged image with features of the first deep learning model for which calculations up to the first layer have been completed.

20. converting the image-based features to 20. The semiconductor design device of claim 19, further comprising: performing downsampling on the arranged image in consideration of a resolution of a feature of the first deep learning model for which calculations up to the first layer have been completed.

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