Memory device

Abstract

To provide a memory device with a small number of wiring lines in a NAND flash memory with a three-dimensional structure having a large number of stacked memory cell layers.SOLUTION: A decoder is constructed using an OS transistor. Because the OS transistor can be formed using methods including a thin-film technique, the decoder can be stacked above a three-dimensional NAND flash memory. This reduces the number of wiring lines that run roughly perpendicular to the memory cell layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory device, and more particularly to a NAND flash memory with a three-dimensional structure.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the invention disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter. [Background technology]

[0003] NAND flash memory is known as a nonvolatile storage device used in solid state drives (SSDs) used in information processing devices such as personal computers (PCs) and servers, as well as in universal serial buses (USBs) and SD cards. In recent years, NAND flash memory has seen an increase in storage capacity due to advances such as miniaturization of semiconductor processes, multi-level storage of two or more bits (four levels) of data in one memory cell, and three-dimensionalization in which multiple memory cell layers are stacked.

[0004] Meanwhile, transistors having an oxide semiconductor or metal oxide in a channel formation region of the transistor (also referred to as oxide semiconductor transistors or OS (oxide semiconductor) transistors) are known. OS transistors have attracted attention because they have a characteristic that the drain current (also referred to as off-current) when the transistor is in an off state is extremely small (see, for example, Non-Patent Documents 1 and 2). In addition, since OS transistors can be formed by a thin-film method or the like, they can be stacked on, for example, other transistors formed on a semiconductor substrate.

[0005] Furthermore, oxide semiconductors have been found to have a c-axis aligned crystalline (CAAC) structure and a nanocrystalline (nc) structure, which are neither single-crystalline nor amorphous (see Non-Patent Documents 1 and 3). Non-Patent Documents 1 and 3 disclose techniques for manufacturing transistors using oxide semiconductors having a CAAC structure. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys., vol.53, 04ED18 (2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-Patent Document 3] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186 Summary of the Invention [Problem to be solved by the invention]

[0007] In NAND flash memories (also referred to in this specification as three-dimensional NAND flash memories, or 3D NAND) in which multiple memory cell layers are stacked, the number of stacked memory cell layers is increasing, leading to an increase in storage capacity. Stacked memory cell layers with 96 layers have been put into practical use, and in recent years, development of memory cell layers with 100 layers or more is underway.

[0008] However, as the number of stacked memory cell layers in a three-dimensional NAND flash memory increases, the number of wiring lines arranged roughly perpendicular to the memory cell layers to transmit information to each memory cell layer also increases, resulting in an increase in chip area (reducing chip area efficiency).

[0009] An object of one embodiment of the present invention is to provide a NAND flash memory having a three-dimensional structure in which the number of wirings provided substantially perpendicular to the memory cell layers is small.Another object of one embodiment of the present invention is to provide a NAND flash memory having a three-dimensional structure in which the increase in the number of wirings provided substantially perpendicular to the memory cell layers is small even when the number of stacked memory cell layers is increased.Another object of one embodiment of the present invention is to provide a NAND flash memory having a three-dimensional structure in which chip area efficiency is high.

[0010] It should be noted that one embodiment of the present invention does not necessarily have to solve all of the above problems, but may solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a memory device having a first layer, a second layer, and a third layer. A decoder is provided in the first layer, a memory cell portion is provided in the second layer, and a circuit is provided in the third layer. The circuit has a function of controlling the decoder and the memory cell portion, and the decoder has a function of selecting or deselecting a part of the memory cell portion. At least a part of the second layer is stacked above the third layer, and at least a part of the first layer is stacked above the second layer.

[0012] Another embodiment of the present invention is a memory device having a first layer, a second layer, and a third layer. A decoder is provided in the first layer, a memory cell portion is provided in the second layer, and a circuit is provided in the third layer. The circuit has a function of controlling the decoder and the memory cell portion, and a function of outputting a selection signal to the decoder. The memory cell portion has a NAND memory element with a three-dimensional structure, and the decoder has a function of outputting a signal to the memory cell portion to select or deselect a part of the memory cell portion in accordance with the selection signal. At least a part of the second layer is stacked above the third layer, and at least a part of the first layer is stacked above the second layer.

[0013] In the above embodiment, the third layer includes a single crystal silicon substrate, the circuit includes a first transistor formed in the single crystal silicon substrate, and the decoder includes a second transistor, the second transistor including a metal oxide in a channel formation region.

[0014] In the above embodiment, the third layer includes an SOI substrate, the circuit includes a first transistor formed in the SOI substrate, and the decoder includes a second transistor, the second transistor including a metal oxide in a channel formation region.

[0015] Another embodiment of the present invention is an electronic device including the storage device of any of the above embodiments. [Effects of the Invention]

[0016] According to one embodiment of the present invention, a three-dimensional NAND flash memory can be provided in which the number of wirings arranged substantially perpendicular to the memory cell layers is small. Alternatively, according to one embodiment of the present invention, a three-dimensional NAND flash memory can be provided in which the increase in the number of wirings arranged substantially perpendicular to the memory cell layers is small even when the number of stacked memory cell layers is increased. Alternatively, according to one embodiment of the present invention, a three-dimensional NAND flash memory with high chip area efficiency can be provided.

[0017] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of these effects. Effects other than these will become apparent from the description in the specification, claims, drawings, etc., and other effects can be extracted from the description in the specification, claims, drawings, etc. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a schematic perspective view showing an example of the configuration of a storage device. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a storage device. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a portion of the storage device. [Figure 4] FIG. 4 is a block diagram illustrating an example of the configuration of a circuit included in the storage device. [Figure 5] 5A to 5C are circuit diagrams illustrating examples of the configuration of circuits included in a storage device. [Figure 6] FIG. 6 is a cross-sectional view showing an example of the configuration of a storage device. [Figure 7] FIG. 7 is a cross-sectional view showing an example of the configuration of a storage device. [Figure 8] 8A to 8C are cross-sectional views showing examples of the structure of a transistor. [Figure 9] 9A is a top view illustrating an example of the structure of a transistor, and FIGS. 9B and 9C are cross-sectional views illustrating an example of the structure of a transistor. [Figure 10] 10A is a top view illustrating an example of the structure of a transistor, and FIGS. 10B and 10C are cross-sectional views illustrating the example of the structure of a transistor. [Figure 11] 11A and 11B are cross-sectional views showing examples of the structure of a transistor. [Figure 12] 12A and 12B are cross-sectional views showing examples of the structure of a transistor. [Figure 13] Fig. 13A is a diagram illustrating the classification of IGZO crystal structures, Fig. 13B is a diagram illustrating the XRD spectrum of a CAAC-IGZO film, and Fig. 13C is a diagram illustrating the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 14] Fig. 14A is a perspective view showing an example of a semiconductor wafer, Fig. 14B is a perspective view showing an example of a chip, and Figs. 14C and 14D are perspective views showing an example of an electronic component. [Figure 15] 15A to 15J are perspective views or schematic diagrams illustrating an example of an electronic device. [Figure 16] 16A to 16E are perspective views or schematic diagrams illustrating an example of an electronic device. [Figure 17] 17A to 17C are diagrams illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0020] In addition, the following multiple embodiments can be combined as appropriate. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0021] In the drawings attached to this specification, the components are classified by function and shown as block diagrams that are independent of each other, but in reality, it is difficult to completely separate the components by function, and one component may be involved in multiple functions.

[0022] In addition, in the drawings, etc., the size, layer thickness, region, etc. may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values shown in the drawings.

[0023] In addition, in drawings, etc., identical elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same symbols, and repeated explanations may be omitted.

[0024] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0025] Furthermore, in this specification and the like, terms indicating arrangement such as "above" and "below" do not limit the positional relationship of components to "directly above" or "directly below." For example, the expression "gate electrode on a gate insulating layer" does not exclude other components between the gate insulating layer and the gate electrode.

[0026] In addition, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and do not imply any numerical limitation.

[0027] Furthermore, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL is described as wiring GL[2].

[0028] Furthermore, in this specification, "electrically connected" includes a connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the transmission and reception of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitive elements, and other elements with various functions. Furthermore, even when something is expressed as "electrically connected," there may be no physical connection in the actual circuit, and only wiring may be extended.

[0029] Furthermore, in this specification and the like, the terms "electrode" and "wiring" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa.

[0030] In addition, in this specification, a "terminal" in an electric circuit refers to a part where a current or potential is input (or output) or a signal is received (or transmitted). Therefore, a part of a wiring or an electrode may function as a terminal.

[0031] Generally, a "capacitor element" has a configuration in which two electrodes face each other with an insulator (dielectric) interposed therebetween. In this specification, the term "capacitor element" also includes a configuration in which two wires face each other with an insulator interposed therebetween, or a configuration in which two wires are arranged with an insulator interposed therebetween, in addition to a configuration in which two electrodes face each other with an insulator interposed therebetween.

[0032] Furthermore, in this specification and the like, the term "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, the terms "voltage" and "potential difference" can be used interchangeably.

[0033] In this specification and the like, a transistor is an element having at least three terminals including a source, a drain, and a gate. A channel formation region is formed between the source (source terminal, source region, or source electrode) and the drain (drain terminal, drain region, or drain electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0034] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain may be used interchangeably in this specification and the like.

[0035] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate voltage Vgs relative to the source is lower than the threshold voltage Vth for an n-channel transistor, and a state in which the gate voltage Vgs relative to the source is higher than the threshold voltage Vth for a p-channel transistor. In other words, the off-state current of an n-channel transistor may be referred to as the drain current when the gate voltage Vgs relative to the source is lower than the threshold voltage Vth.

[0036] In the above description of off-state current, the drain may be read as the source. That is, the off-state current may refer to the source current when a transistor is in an off state. The off-state current may also be referred to as leakage current, which has the same meaning as the off-state current. In this specification and the like, the off-state current may also refer to the current that flows between the source and drain when a transistor is in an off state.

[0037] In this specification and the like, the on-state current may refer to a current that flows between a source and a drain when a transistor is in an on state (also referred to as a conductive state).

[0038] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, etc.

[0039] For example, when a metal oxide is used in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be called a metal oxide semiconductor. That is, a transistor having a metal oxide in a channel formation region can be called an "oxide semiconductor transistor" or an "OS transistor." Similarly, a "transistor using an oxide semiconductor" is also a transistor having a metal oxide in a channel formation region.

[0040] In this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide. A metal oxide containing nitrogen may also be referred to as a metal oxynitride. Details of metal oxides will be described later.

[0041] (Embodiment 1) In this embodiment, a configuration example of a storage device according to one embodiment of the present invention will be described.

[0042] <Storage device configuration example> 1 is a schematic perspective view showing an example of the configuration of a memory device 100 according to one embodiment of the present invention. The memory device 100 has a circuit layer A1, a circuit layer A2, a wiring layer A3, a NAND flash layer NFL, and conductors M1 to M3.

[0043] 1, the memory device 100 has a structure in which a NAND flash layer NFL is stacked above a circuit layer A2, a wiring layer A3 is stacked above the NAND flash layer NFL, and a circuit layer A1 is stacked above the wiring layer A3. Note that the wiring layer A3 is considered to be included in the circuit layer A1, and hereinafter, a description thereof will be omitted unless necessary.

[0044] The circuit layer A2 and the circuit layer A1 are electrically connected via a conductor M1, and the circuit layer A1 and the NAND flash layer NFL are electrically connected via a conductor M2 and a conductor M3.

[0045] The circuit layer A1, the NAND flash layer NFL, and the circuit layer A2 are each provided with a circuit that can function by utilizing the semiconductor characteristics, with the circuit layer A1 provided with a decoder DEC, the NAND flash layer NFL provided with a memory cell unit MCL, and the circuit layer A2 provided with a circuit OSC. Also, as an example, the decoder DEC is located in an area overlapping with a plurality of conductors M1 electrically connected to the circuit layer A2 and a plurality of conductors M2 electrically connected to the NAND flash layer NFL.

[0046] In the storage device 100, the circuit layer A2, the NAND flash layer NFL, and the wiring layer A3 form a storage unit, and the storage unit can be, for example, a NAND flash memory with a three-dimensional structure.

[0047] The storage unit is not limited to a three-dimensional NAND flash memory, but may be a two-dimensional NAND flash memory or a NOR flash memory. It may also be a storage unit using nonvolatile storage elements such as MRAM (Magnetoresistive RAM), PRAM (Phase change RAM), ReRAM (Resistive RAM), or FeRAM (Ferroelectric RAM), or a combination of the above storage units.

[0048] The circuit OSC has the function of controlling the memory cell unit MCL and the decoder DEC. The memory cell unit MCL has multiple memory cells, and data is written and read by a write circuit, a read circuit, and the like included in the circuit OSC. When the circuit OSC selects one of multiple pages included in the NAND flash layer NFL, the circuit OSC outputs a selection signal to the decoder DEC via multiple conductors M1 electrically connected to the circuit layer A2. In this configuration example, the selection signal sent from the circuit layer A2 to the decoder DEC is a digital signal.

[0049] The decoder DEC has a function of selecting one page of the NAND flash layer NFL in response to the selection signal. As an example, the decoder DEC has a function of outputting a high-level potential to the selected page of the NAND flash layer NFL via the conductors M2 and M3, and outputting a low-level potential to the unselected pages of the NAND flash layer NFL via the conductors M2 and M3. Note that the conductor M1 includes other wirings, such as wirings that transmit signals other than the above-mentioned selection signal and power supply lines that supply a constant potential.

[0050] The circuit OSC is configured using transistors formed on a substrate SUB. The substrate SUB may be, for example, a single-crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, or a compound semiconductor substrate made of silicon germanium. The substrate SUB may also be an SOI substrate, a semiconductor substrate on which semiconductor elements such as strained transistors or FIN-type transistors are provided, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, or a sapphire substrate. Furthermore, the substrate SUB may be a flexible substrate.

[0051] In this embodiment mode, a case will be described where a single crystal silicon substrate is used as the substrate SUB. Note that a transistor having silicon in a channel formation region is referred to as a Si transistor in this specification and the like.

[0052] The decoder DEC can be configured using, for example, OS transistors. When the decoder DEC is configured using OS transistors, the OS transistors can be formed using a method such as a thin-film method, and therefore the decoder DEC can be stacked above the circuit OSC and the memory cell unit MCL. Specifically, for example, the circuit OSC and the memory cell unit MCL can be configured using Si transistors, and the decoder DEC can be configured above them using OS transistors. Note that the OS transistors are transistors that have a metal oxide in their channel formation region.

[0053] Furthermore, the decoder DEC can be fabricated using a process different from that for the circuit OSC and the memory cell unit MCL. Because OS transistors can be formed at a lower temperature than Si transistors, configuring the decoder DEC using OS transistors can reduce the thermal impact on the Si transistors included in the circuit OSC and the memory cell unit MCL. Furthermore, because the decoder DEC is superimposed above the circuit OSC and the memory cell unit MCL, an increase in the circuit area of the memory device 100 can be suppressed.

[0054] Incidentally, if the circuit layer A1 does not have a decoder DEC (the storage device 100 does not have a decoder DEC), the number of wires required to transmit a selection signal from the circuit layer A2 to the NAND flash layer NFL via the circuit layer A1 is equal to the number of pages included in the NAND flash layer NFL. On the other hand, if the circuit layer A1 has a decoder DEC, the selection signal from the circuit layer A2 to the circuit layer A1 is a digital signal. By converting the selection signal from the circuit layer A2 to the circuit layer A1 into a digital signal, the number of wires from the circuit layer A2 to the circuit layer A1, i.e., the number of conductors M1, can be reduced compared to when the circuit layer A1 does not have a decoder DEC.

[0055] For example, let us say that the number of pages in the NAND flash layer NFL is X (X is 2 k where k is an integer satisfying the above, and k is an integer greater than or equal to 1), if a decoder DEC is not provided on circuit layer A1, at least X wires are required from circuit layer A2 to circuit layer A1. On the other hand, if a decoder DEC is provided on circuit layer A1, the number of wires from circuit layer A2 to circuit layer A1 can be set to "Y+log2X" wires (Y is an integer greater than or equal to 0). Note that Y represents the number of wires other than those for selection signals, such as the power supply for decoder DEC.

[0056] Thus, by providing the decoder DEC on the circuit layer A1, the number of conductors M1 can be reduced. That is, even if the number of stacked NAND flash layers NFL is increased and the number of pages included in the NAND flash layer NFL is increased, by providing the decoder DEC on the circuit layer A1, the number of wires from the circuit layer A2 to the circuit layer A1 can be reduced, and the chip area can be prevented from increasing (the chip area efficiency can be improved).

[0057] Furthermore, since the number of wirings from circuit layer A2 to circuit layer A1 is reduced, the influence of parasitic resistance can be reduced, and for example, the increase in power consumption due to parasitic resistance can be reduced. Furthermore, since the number of wirings from circuit layer A2 to circuit layer A1 is reduced, the influence of parasitic capacitance can be reduced, and for example, a decrease in the drive frequency of the memory device due to parasitic capacitance can be prevented.

[0058] Next, a configuration example of the storage device 100 will be described using the block diagram shown in Fig. 2. In the drawings described in this specification, the flow of main signals is indicated by arrows or lines, and power lines and the like may be omitted.

[0059] <Memory cell section MCL> The memory cell unit MCL has a memory cell array MCA. The memory cell array MCA has a plurality of strings SRG. The strings SRG are electrically connected to wiring BL. The strings SRG have a plurality of transistors CTr electrically connected in series, and a selection transistor BTr and a transistor STr. One transistor CTr functions as a cell transistor and is included in a memory cell MC of the string SRG.

[0060] Generally, a cell transistor is a transistor that operates with normally-on characteristics and has a control gate and a charge storage layer. The charge storage layer is provided in a region overlapping the channel formation region via a tunnel insulating film, and the control gate is provided in a region overlapping the charge storage layer via a blocking film. When a write potential is applied to the control gate and a predetermined potential is applied to either the first terminal or the second terminal of the cell transistor, a tunnel current is generated and electrons are injected from the channel formation region of the cell transistor into the charge storage layer. As a result, the threshold voltage of the cell transistor with electrons injected into the charge storage layer increases. Note that a floating gate may be used instead of the charge storage layer.

[0061] The channel formation regions of the transistors BTr, CTr, and STr preferably have one or more materials selected from, for example, silicon, germanium, gallium arsenide, silicon carbide (SiC), and the metal oxides described in embodiment 3.

[0062] In particular, when the channel formation region contains one or more metal oxides selected from indium, an element M (such as aluminum, gallium, yttrium, or tin), and zinc, the metal oxides may function as wide-gap semiconductors, and the transistors BTr, CTr, and STr having the metal oxides in their channel formation regions have characteristics of extremely small off-state current. In other words, the leakage current in the transistors BTr, CTr, and STr in the off state can be reduced, which may reduce the power consumption of the storage device.

[0063] Although FIG. 2 shows an example in which the transistors BTr and STr are formed in the memory cell unit MCL, the transistors BTr and STr may be formed in the circuit OSC.

[0064] The memory cell array MCA has a plurality of memory cells MC in the string SRG. The plurality of memory cells MC are arranged in a matrix. The memory cell array MCA in FIG. 2 has m memory cells MC in each column and n memory cells MC in each row, for a total of m×n memory cells MC (m and n are integers of 2 or greater). In FIG. 2, the memory cell MC located in the i-th row and j-th column (i is an integer of 1 or greater and m or less, and j is an integer of 1 or greater and n or less) is represented as MC[i,j]. However, in FIG. 2, only the memory cell MC[1,1], memory cell MC[i,1], memory cell MC[m,1], memory cell MC[1,j], memory cell MC[i,j], memory cell MC[m,j], memory cell MC[1,n], memory cell MC[i,n], and memory cell MC[m,n] are illustrated, and the other memory cells MC are not illustrated.

[0065] The wirings DL, WL, BL, CL, BSL, and SSL shown in FIG. 2 correspond to the conductors M1 to M3 shown in FIG. 1. For example, the wiring DL is a wiring through which the circuit OSC outputs a selection signal to the decoder DEC and corresponds to the conductor M1, and the wirings WL are a plurality of word lines and correspond to the conductors M2 and M3. Each of the wirings WL is electrically connected to a memory cell MC for each row. The wirings BL are a plurality of bit lines and each of the wirings BL is electrically connected to a memory cell MC for each column, and the wiring CL is a power supply line. The wirings BL and CL are electrically connected to the memory cell array MCA, for example, via the conductor M1 and the wiring layer A3.

[0066] Next, the connection configuration of the string SRG electrically connected to the wiring BL will be described. One of the source or drain of the transistor BTr is electrically connected to the wiring BL, and one of the source or drain of the transistor STr is electrically connected to the wiring CL. The other of the source or drain of the transistor BTr is electrically connected to one end of the plurality of transistors CTr electrically connected in series, and the other of the source or drain of the transistor STr is electrically connected to the other end of the plurality of transistors CTr electrically connected in series.

[0067] The wiring BSL and the wiring SSL function as wirings for selecting a string to be subjected to an operation such as writing, reading, erasing, etc. The wiring BSL is electrically connected to the gate of a transistor BTr included in the memory cell unit MCL, and the wiring SSL is electrically connected to the gate of a transistor STr included in the memory cell unit MCL.

[0068] 2, the memory cell portion MCL has a configuration in which one string SRG is electrically connected to one wiring BL, but one embodiment of the present invention is not limited to this. For example, as shown in FIG. 3, the memory cell portion MCL may have a configuration in which multiple strings SRG are electrically connected to one wiring BL. Note that the block diagram in FIG. 3 illustrates only the memory cell portion MCL and a part of the circuit OSC.

[0069] <Circuit OSC> The circuit OSC includes a control circuit CTR, a circuit PRPH, and an output circuit OUTP. For example, control signals CS (clock signal, chip enable signal, write enable signal, address signal, etc.) and a data signal WDATA are input to the control circuit CTR from outside the memory device 100.

[0070] The control circuit CTR has a function of accessing the circuit PRPH to write data to the memory cell unit MCL and a function of reading data from the memory cell unit MCL.

[0071] That is, when a write command and a data signal WDATA are input by a control signal CS from outside the memory device 100, the control circuit CTR writes the data signal WDATA to the memory cell unit MCL. Also, when a read command is input by a control signal CS from outside the memory device 100, the control circuit CTR reads data from the memory cell unit MCL and outputs it to the output circuit OUTP. The output circuit OUTP outputs it as a data signal RDATA to outside the memory device 100. It is assumed that the write command and read command include an address signal.

[0072] The control circuit CTR may also have a function of detecting and correcting errors (also called ECC: Error Check and Correct) when reading data from the memory cell unit MCL. Note that the signals processed by the control circuit CTR and the functions of the control circuit CTR are not limited to these, and other signals may be input (or output) as needed, and the control circuit CTR may have other functions.

[0073] The circuit PRPH includes, for example, a circuit WLD, a circuit BLD, and a circuit CVC. The circuit WLD functions as a word line driver circuit. In this embodiment, the circuit WLD is electrically connected to the wiring DL and outputs a selection signal to the decoder DEC. The circuit BLD functions as a bit line driver circuit and is electrically connected to the wiring BL. The circuit CVC functions as a power supply that generates a constant potential and outputs the constant potential and is electrically connected to the wiring CL. The circuit CVC does not have to be included in the circuit PRPH and may be provided outside the memory device 100, for example. In this case, the memory device 100 is configured so that a constant potential is applied to the memory cell unit MCL from outside.

[0074] <Decoder DEC> Next, the decoder DEC included in the circuit layer A1 will be described.

[0075] Because the circuit layer A1 is stacked above the NAND flash layer NFL, it can be fabricated using a process different from that for the circuit layer A2 and the NAND flash layer NFL. Furthermore, the circuits included in the circuit layer A1 can be fabricated using the same process. For example, the same process can be the process for forming OS transistors.

[0076] Incidentally, among the metal oxides contained in the channel formation region of an OS transistor, n-type semiconductors can be fabricated using metal oxides containing indium (e.g., In oxide) or zinc (e.g., Zn oxide). However, fabrication of p-type semiconductors can be difficult in terms of mobility and reliability. Therefore, when the circuit layer A1 is configured using OS transistors, the circuit is preferably a unipolar circuit.

[0077] Fig. 4 shows an example of the circuit configuration of the decoder DEC included in the circuit layer A1 shown in Fig. 1. Note that the circuit layer A2 is also shown in order to show the electrical connection with the decoder DEC.

[0078] 4 has a function of receiving a selection signal transmitted from the circuit layer A2 via a wiring DL and selecting one page of the NAND flash layer NFL in accordance with the selection signal. Furthermore, the decoder DEC has a function of outputting a high-level potential via a wiring WL to the selected page of the NAND flash layer NFL and outputting a low-level potential via a wiring WL to the unselected pages of the NAND flash layer NFL, for example.

[0079] The wiring DL corresponds to the wiring included in the conductor M1 in Fig. 1, for example, and the wiring WL corresponds to the wiring included in the conductor M2 and the conductor M3 in Fig. 1.

[0080] Here, the number of pages in the NAND flash layer NFL is assumed to be X, for example. Therefore, the number of wirings WL is X. Furthermore, the digital signal transmitted from the circuit layer A2 is assumed to be Y+log2X bits, for example. Therefore, the number of wirings DL is Y+log2X.

[0081] Furthermore, from the above, it is assumed that the circuit layer A2 here has a function of generating a signal of "Y+log2X" bits that indicates the address of one page included in the NAND flash layer NFL.

[0082] The decoder DEC includes, for example, inverter circuits INV[1] through INV[Y+log2X], inverter circuits OIV[1] through OIV[X], and NAND circuits NA[1] through NA[X].

[0083] The wiring DL[t] (t is an integer greater than or equal to 1 and less than or equal to Y+log2X) is electrically connected to the input terminal of the inverter circuit INV[t]. The wiring DL[t] is also electrically connected to one or more selected from the first input terminals of each of the NAND circuits NA[1] to NA[X]. The output terminal of the inverter circuit INV[t] is also electrically connected to one or more selected from the second input terminals of each of the NAND circuits NA[1] to NA[X].

[0084] The decoder DEC has a different circuit configuration depending on the values of X and Y. Therefore, the above description of the decoder DEC omits detailed explanation of the electrical connections of the circuits included in the decoder DEC. Also, in Figure 4, the detailed circuit configuration of the decoder DEC is not shown.

[0085] The output terminal of the NAND circuit NA[s] (s is an integer greater than or equal to 1 and less than or equal to X) is electrically connected to the input terminals of the inverter circuits OIV[1] to OIV[X], and the output terminals of the inverter circuits OIV[1] to OIV[X] are electrically connected to the wiring WL[s].

[0086] Note that the wiring DL[t], inverter circuit INV[t], NAND circuit NA[s], inverter circuit OIV[s], and wiring WL[s] are not shown in FIG.

[0087] <Unipolar circuit> Next, we will explain configuration examples of the inverter circuits INV[1] to INV[Y+log2X], inverter circuits OIV[1] to OIV[X], and NAND circuits NA[1] to NA[X] included in the decoder DEC.

[0088] As described above, since the decoder DEC is included in the circuit layer A1, it is preferable that the inverter circuits INV[1] to INV[Y+log2X], inverter circuits OIV[1] to OIV[X], and NAND circuits NA[1] to NA[X] included in the decoder DEC be unipolar circuits using OS transistors.

[0089] FIG. 5A is a unipolar circuit, and shows an example of the configuration of an inverter circuit that can be applied to inverter circuits INV[1] to INV[Y+log2X], inverter circuits OIV[1] to OIV[X], and the like.

[0090] A terminal IT shown in FIG. 5A corresponds to the input terminal of the inverter circuit, and a terminal OT corresponds to the output terminal of the inverter circuit.

[0091] The inverter circuit includes, for example, transistors TrA1 to TrA4 and a capacitor CA1.

[0092] In this specification, the transistors TrA1 to TrA4 are preferably transistors that can be manufactured using the same process as other circuits included in the circuit layer A1. Furthermore, the material contained in each of the channel formation regions of the transistors TrA1 to TrA4 is preferably the same as the material contained in the channel formation regions of the other transistors included in the circuit layer A1. For example, each of the transistors TrA1 to TrA4 is preferably an OS transistor.

[0093] The first terminal of the transistor TrA1 is electrically connected to the gate of the transistor TrA1 and the wiring VHL, the second terminal of the transistor TrA1 is electrically connected to the first terminal of the transistor TrA2, the gate of the transistor TrA3, and the first terminal of the capacitor CA1, and the second terminal of the transistor TrA2 is electrically connected to the wiring VLL. The terminal IT is electrically connected to the gate of the transistor TrA2 and the gate of the transistor TrA4. The first terminal of the transistor TrA3 is electrically connected to the wiring VHL, and the second terminal of the transistor TrA3 is electrically connected to the first terminal of the transistor TrA4, the second terminal of the capacitor CA1, and the terminal OT. The second terminal of the transistor TrA4 is electrically connected to the wiring VLL.

[0094] The wirings VHL and VLL each function as a wiring that applies a constant potential. In particular, the potential applied by the wiring VHL is preferably a high-level potential (hereinafter referred to as VDD), and the potential applied by the wiring VLL is preferably a low-level potential (hereinafter referred to as VSS).

[0095] Next, the operation of the inverter circuit will be described. For example, when VSS is input to the terminal IT, the transistors TrA2 and TrA4 are turned off. Furthermore, since the transistor TrA1 is diode-connected, the potential at the first terminal of the capacitor CA1 (the gate of the transistor TrA3) rises. If the threshold voltage of the transistor TrA1 is V thA1When the voltage at the first terminal of the capacitor CA1 (the gate of the transistor TrA3) is VDD-V thA1 When the potential of the transistor TrA3 reaches , the transistor TrA1 turns off. In other words, the first terminal of the capacitor CA1 (the gate of the transistor TrA3) becomes electrically floating. At this time, the gate voltage relative to the source of the transistor TrA3 becomes higher than the threshold voltage of the transistor TrA3, and the transistor TrA3 turns on. If the terminal OT is not connected to a line that provides a constant potential, the potential of the terminal OT increases due to the current flowing from the line VHL. Because the first terminal of the capacitor CA1 (the gate of the transistor TrA3) is electrically floating, when the potential of the terminal OT increases, the potential of the first terminal of the capacitor CA1 (the gate of the transistor TrA3) also increases due to the capacitive coupling of the capacitor CA1. This allows the transistor TrA3 to remain on, and the potential of the terminal OT eventually becomes VDD.

[0096] Furthermore, for example, when VDD is input to terminal IT, transistors TrA2 and TrA4 are turned on. At this time, the potential of the first terminal of capacitor CA1 (the gate of transistor TrA3) is equal to or higher than VSS and equal to or lower than VDD. At this time, the voltage of the gate relative to the source of transistor TrA3 is assumed to be lower than the threshold voltage of transistor TrA3, and transistor TrA3 is turned off. Furthermore, because transistor TrA4 is turned on, current flows from terminal OT to line VLL, and finally the potential of terminal OT becomes VSS.

[0097] 5A, when the first terminal of the capacitor CA1 (the gate of the transistor TrA3) is in an electrically floating state, the capacitor CA1 electrically connected between the second terminal and gate of the transistor TrA3 can maintain the voltage of the gate relative to the source of the transistor TrA3. Therefore, when the potential of VSS is input to the terminal IT, the potential of the terminal OT can be increased to VDD.

[0098] The inverter circuit shown in FIG. 5A can be modified to the inverter circuit shown in FIG. 5B. The inverter circuit shown in FIG. 5B is configured such that backgates are provided to the transistors TrA1 to TrA4 of the inverter circuit shown in FIG. 5A. While the inverter circuit shown in FIG. 5B includes backgates for all of the transistors TrA1 to TrA4, backgates may be provided for one or more selected transistors from the transistors TrA1 to TrA4 shown in FIG. 5A. Although the backgate connection is not shown in FIG. 5B, the electrical connection of the backgate can be determined during the design stage. For example, in a transistor having a backgate, the gate and backgate may be electrically connected to increase the on-state current of the transistor. Furthermore, in a transistor having a backgate, a wiring electrically connected to an external circuit or the like may be provided to apply a potential to the backgate of the transistor from the external circuit or the like in order to change the threshold voltage of the transistor. Note that backgates may be provided not only in FIG. 5B but also in transistors described elsewhere in the specification or illustrated in other drawings.

[0099] FIG. 5C is a configuration example of a NAND circuit that is a unipolar circuit and can be applied to the NAND circuits NA[1] to NA[X].

[0100] In FIG. 5C, terminals IT1 and IT2 correspond to input terminals of the NAND circuit, and terminal OT corresponds to the output terminal of the NAND circuit.

[0101] The NAND circuit includes transistors TrB1 to TrB6 and a capacitor CB1.

[0102] In this specification, like the transistors TrA1 to TrA4, the transistors TrB1 to TrB6 are preferably transistors that can be manufactured by the same process as other circuits included in the circuit layer A1. Furthermore, the material contained in each of the channel formation regions of the transistors TrB1 to TrB6 is preferably the same as the material contained in the channel formation regions of other transistors included in the circuit layer A1. For example, each of the transistors TrB1 to TrB6 is preferably an OS transistor.

[0103] The first terminal of the transistor TrB1 is electrically connected to the gate of the transistor TrB1 and the wiring VHL. The second terminal of the transistor TrB1 is electrically connected to the first terminal of the transistor TrB2, the gate of the transistor TrB4, and the first terminal of the capacitor CB1. The second terminal of the transistor TrB2 is electrically connected to the first terminal of the transistor TrB3, and the second terminal of the transistor TrB3 is electrically connected to the wiring VLL. The terminal IT1 is electrically connected to the gate of the transistor TrB2 and the gate of the transistor TrB5. The terminal IT2 is electrically connected to the gate of the transistor TrB3 and the gate of the transistor TrB6. The first terminal of the transistor TrB4 is electrically connected to the wiring VHL. The second terminal of the transistor TrB4 is electrically connected to the second terminal of the capacitor CB1, the first terminal of the transistor TrB5, and the terminal OT. The second terminal of the transistor TrB5 is electrically connected to the first terminal of the transistor TrB6, and the second terminal of the transistor TrB6 is electrically connected to the wiring VLL.

[0104] For the wiring VHL and wiring VLL, please refer to the explanations of the wiring VHL and wiring VLL in FIG. 5A.

[0105] Next, an example of the operation of the NAND circuit of FIG. 5C will be described. In this NAND circuit, for example, when a potential of VSS is input to at least one of terminal IT1 or terminal IT2, at least one of transistors TrB5 and TrB6 is turned off, resulting in a non-conduction state between the wiring VLL and terminal OT. Furthermore, similar to the example of the operation of the inverter circuit of FIG. 5A, when the first terminal of capacitor CB1 (the gate of transistor TrB4) is electrically floating, the NAND circuit can maintain the voltage of the gate of transistor TrB4 relative to the source thereof by using capacitor CB1, which is electrically connected between the second terminal and gate of transistor TrB4. Therefore, when a potential of VSS is input to terminal IT1 and / or terminal IT2, the potential of terminal OT can be increased to VDD.

[0106] Furthermore, for example, in the NAND circuit, when a potential of VDD is input to each of terminals IT1 and IT2, transistors TrB5 and TrB6 are turned on, resulting in conduction between line VLL and terminal OT. The potential of the first terminal of capacitor CB1 (the gate of transistor TrB4) is equal to or higher than VSS and equal to or lower than VDD. At this time, the voltage of the gate relative to the source of transistor TrB4 is assumed to be lower than the threshold voltage of transistor TrB4, turning transistor TrB4 off. Therefore, when a potential of VDD is input to each of terminals IT1 and IT2, the potential of terminal OT becomes VSS.

[0107] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0108] (Embodiment 2) In this embodiment, an example of the structure of the transistors constituting the memory device 100 described in the above embodiment will be described. Fig. 6 shows an example of the cross-sectional structure of the circuit layer A2 and the NAND flash layer NFL, and Fig. 7 shows an example of the cross-sectional structure of the NAND flash layer NFL and the circuit layer A1. Note that this embodiment describes a case where a single-crystal silicon substrate is used for the substrate SUB, the NAND flash layer NFL has a NAND memory element with a three-dimensional structure, and an OS transistor is formed in the circuit layer A1.

[0109] 6 and 7, the transistor 300 is formed in the circuit layer A2, the transistor 700, a plurality of transistors 800, and a transistor 900 are formed in the NAND flash layer NFL, and the transistor 500 is formed in the circuit layer A1.

[0110] The transistor 700 corresponds to the transistor BTr in Fig. 2, the transistor 800 corresponds to the transistor CTr in Fig. 2, and the transistor 900 corresponds to the transistor STr in Fig. 2. The transistor 300 is one of the transistors that make up the circuit OSC, the transistor 500 is one of the transistors that make up the decoder DEC, and the capacitive element 600 corresponds to, for example, the capacitor CA1.

[0111] The transistor 500 has a second gate (also referred to as a bottom gate or a back gate) in addition to a first gate (also referred to as a top gate, a front gate, or simply a gate). The transistor 500 is a transistor having a metal oxide in a channel formation region (an OS transistor). Since the transistor 500 can be formed by a thin film method or the like, in the above embodiment, the decoder DEC can be formed using the transistor 500, and thus the decoder DEC can be stacked above the circuit OSC and the memory cell unit MCL.

[0112] 8A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 8B is a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 8C is a cross-sectional view of the transistor 300 in the channel width direction. As shown in Figs. 6 and 7, in the memory device 100 described in this embodiment, the NAND flash layer NFL is provided above the circuit layer A2, and the circuit layer A1 is provided above the circuit layer A2 and the NAND flash layer NFL.

[0113] <Configuration example of circuit layer A2> The transistor 300 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, a low-resistance region 314a functioning as a source region or a drain region, and a low-resistance region 314b.

[0114] 8C , the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0115] The transistor 300 may be either a p-channel type or an n-channel type.

[0116] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaN (gallium nitride), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0117] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0118] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0119] Since the work function is determined by the conductor material, the Vth of the transistor can be adjusted by changing the conductor material. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum laminated on the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0120] Note that the transistor 300 shown in FIG. 6 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0121] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300.

[0122] The insulators 320, 322, 324, and 326 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0123] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 300 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0124] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or the transistor 300 to a region where the transistor 500 is provided.

[0125] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0126] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS) analysis. For example, the amount of desorbed hydrogen from the insulator 324 is calculated as 10×10 per area of the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0127] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0128] Conductors 328, 330, and the like are embedded in insulators 320, 322, 324, and 326. Conductors 328 and 330 function as plugs or wiring. Conductors that function as plugs or wiring may be collectively designated by the same reference numeral. In this specification, the wiring and the plug connecting to the wiring may be integral. That is, a portion of the conductor may function as the wiring, and a portion of the conductor may function as the plug.

[0129] As materials for each plug and wiring (such as conductor 328 and conductor 330), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used alone or in a laminated form. It is preferable to use high melting point materials such as tungsten and molybdenum that can achieve both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0130] Although omitted in FIG. 6, a wiring layer may be provided on insulator 326 and conductor 330. For example, it is preferable to provide an insulator having a barrier property against hydrogen on insulator 326 and conductor 330, similar to insulator 324, and form a conductor having a barrier property against hydrogen on the insulator. By forming a conductor having a barrier property against hydrogen in the opening of the insulator having a barrier property against hydrogen, transistor 300 and transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0131] As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Also, by laminating tantalum nitride and tungsten having high conductivity, the diffusion of hydrogen from transistor 300 can be suppressed while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator having a barrier property against hydrogen. Note that in FIG. 6, an insulator 350 having a barrier property against hydrogen is provided on insulator 326 and conductor 330.

[0132] <Configuration Example of NAND Flash Layer NFL> 6 is provided above the circuit layer A2. The NAND flash layer NFL also includes, above the circuit layer A2, insulators 111 to 117, insulators 121, 122, insulators 131, 132, and 133, conductors 151 to 156, and semiconductors 141 to 143.

[0133] The insulator 111 is provided above the circuit layer A2, and when the insulator 111 functions as a base film, it is preferable that the insulator 111 be formed by, for example, a film formation method that provides good flatness.

[0134] For example, a material containing silicon oxide or silicon oxynitride can be used as the insulator 111. Alternatively, for example, an insulator containing a material selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. can be used in a single layer or a stacked layer.

[0135] The conductor 151 is provided by being stacked on the insulator 111. The conductor 151 may function as the wiring CL in FIG.

[0136] The conductor 151 may be made of, for example, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used. Alternatively, a conductive material containing oxygen and a metal element contained in the metal oxide described in Embodiment 3 may be used. Alternatively, a conductive material containing nitrogen and a metal element such as titanium or tantalum may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Alternatively, for example, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen or water that gets mixed in from surrounding insulators, etc.

[0137] There is no particular limitation on the method for forming the conductor 151. For example, the conductor 151 can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE (Molecular Beam Epitaxy) method, an ALD (Atomic Layer Deposition) method, a PLD (Pulsed Laser Deposition) method, etc.

[0138] An insulator 112, a conductor 152, an insulator 113, a conductor 153, and an insulator 114 are stacked in this order on the conductor 151. Moreover, above the insulator 114, a conductor 154, an insulator 115, a conductor 155, an insulator 116, a conductor 156, and an insulator 117 are provided.

[0139] The insulators 112 to 117 can be formed using, for example, a material similar to that of the insulator 111. For the insulators 112 to 117, it is preferable to use, for example, a material with a low dielectric constant. By using a material with a low dielectric constant for the insulators 112 to 117, the capacitance value of parasitic capacitance generated by the conductors 152 to 156 and the insulators 112 to 117 can be reduced. Therefore, the driving speed of the memory cell portion MCL can be improved.

[0140] There is no particular limitation on the method for forming the insulators 112 to 117. For example, the insulators can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, and the like), an MBE method, an ALD method, a PLD method, or the like.

[0141] The conductor 152 functions as the gate of the transistor 900 (transistor STr in FIG. 2) and the wiring SSL in FIG. 2. The conductors 153 to 155 function as the gates of the transistors 800 (transistors CTr in FIG. 2) and the wiring WL in FIG. 2. The conductor 156 functions as the gate of the transistor 700 (transistor BTr in FIG. 2) and the wiring BSL in FIG. 2.

[0142] The conductors 152 to 156 can be formed using, for example, a material similar to that of the conductor 151. The conductors 152 to 156 can be formed using a method similar to that of the conductor 151.

[0143] Openings are provided in the insulators 112 to 117 and the conductors 152 to 156. The openings are provided with the insulators 121 and 122, the insulators 131 to 133, and the semiconductors 141 to 143.

[0144] The semiconductor 141 is provided so as to be in contact with a part of the side surface and the bottom surface of the opening. Specifically, the semiconductor 141 is provided on a part of the conductor 151 and is provided so as to cover a part of the insulator 112 on the side surface of the opening.

[0145] The semiconductor 141 is preferably, for example, silicon with an impurity diffused therein. The impurity may be an n-type impurity (donor). The n-type impurity may be, for example, phosphorus or arsenic. The impurity may be a p-type impurity (acceptor). The p-type impurity may be, for example, boron, aluminum, or gallium. The silicon may be, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon. In addition to silicon, metal oxides with high carrier density may be used as the semiconductor 141. Compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, and SiGe may be used.

[0146] Note that the materials used for the semiconductors 142 and 143 described later are preferably the same as the semiconductor 141, and the carrier density of the semiconductor 142 may preferably be lower than that of the semiconductors 141 and 143.

[0147] For example, when silicon in which p-type impurities are diffused is used as the semiconductor 141, it is preferable to add p-type impurities such as boron, aluminum, or gallium to the semiconductor 141 after forming the semiconductor 141 on the conductor 151. This forms a p-type region in the semiconductor 141. Furthermore, when silicon in which n-type impurities are diffused is used, it is preferable to add n-type impurities such as phosphorus or arsenic to the semiconductor 141 after forming the semiconductor 141 on the conductor 151. This forms an n-type region in the semiconductor 141.

[0148] For example, when a metal oxide is used as the semiconductor 141, a metal element or the like is preferably added to the semiconductor 141 after the semiconductor 141 is formed over the conductor 151. This can increase the carrier density in the semiconductor 141. In particular, when a metal oxide described in Embodiment 3 is used as the semiconductor 141, the semiconductor 141 preferably has an n-type region (n + Alternatively, instead of adding a metal element or the like to the semiconductor 141, water, hydrogen, or the like may be added and then heat treatment may be performed to generate oxygen vacancies in the semiconductor 141. An n-type region is formed in the region of the semiconductor 141 where oxygen vacancies have occurred, which results in an increase in the carrier density of the semiconductor 141.

[0149] The insulator 121 is provided so as to be in contact with part of the side surface of the opening. Specifically, the insulator 121 is provided so as to cover part of the semiconductor 141 and the conductor 152 on the side surface of the opening.

[0150] The insulator 121 functions as a gate insulating film of the transistor 900.

[0151] The insulator 121 can be, for example, silicon oxide or silicon oxynitride. In particular, when a metal oxide is used as the semiconductor 142 described later, the insulator 121 is preferably a material from which oxygen is released by heating. By providing the insulator 121 containing oxygen in contact with the metal oxide used as the semiconductor 142, oxygen vacancies in the metal oxide can be reduced, and the reliability of the transistor 900 can be improved.

[0152] Although there is no particular limitation on the method for forming the insulator 121, a method for forming the insulator 121 with high film-forming properties is required because the insulator 121 is formed on the side surfaces of the openings provided in the insulator 112, the conductor 152, and the insulator 113. Examples of the method for forming the insulator 121 with high film-forming properties include the ALD method.

[0153] The insulator 131 is provided so as to be in contact with part of the side surface of the opening. Specifically, the insulator 131 is provided so as to cover the conductors 153 to 155 on the side surface of the opening. Therefore, the insulator 131 is provided so as to cover the insulators 114 and 115 on the side surface of the opening.

[0154] The insulator 132 is provided so as to be in contact with the insulator 131. The insulator 133 is provided so as to be in contact with the insulator 132. That is, the insulators 131 to 133 are stacked in order from the side surface of the opening toward the center.

[0155] The insulator 131 functions as a gate insulating film of the transistor 800. The insulator 132 functions as a charge storage layer of the transistor 800. The insulator 133 functions as a tunnel insulating film of the transistor 800.

[0156] The insulator 131 is preferably made of, for example, silicon oxide or silicon oxynitride. Alternatively, the insulator 131 can be made of, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium. Alternatively, the insulator 131 may be made of a stack of these materials. By making the insulator 131 thicker than the insulator 133, charge can be transferred from the semiconductor 142 (described later) to the insulator 132 through the insulator 133.

[0157] For example, silicon nitride or silicon nitride oxide can be used as the insulator 132. However, materials that can be used for the insulator 132 are not limited to these.

[0158] The insulator 133 is preferably formed using, for example, silicon oxide or silicon oxynitride. Alternatively, the insulator 133 may be formed using, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium. Alternatively, the insulator 133 may be formed using a stack of these materials.

[0159] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0160] The insulator 122 is provided so as to contact a part of the side surface of the opening, specifically so as to cover the conductor 156 on the side surface of the opening.

[0161] The insulator 122 functions as a gate insulating film for the transistor 700 .

[0162] The insulator 122 can be formed using, for example, a material similar to that of the insulator 121. The insulator 122 can be formed using a method similar to that of the insulator 121.

[0163] The semiconductor 142 is provided in the opening so as to be in contact with the side surfaces of the insulators 121, 133, and 122 that have been formed.

[0164] The semiconductor 142 functions as channel formation regions of the transistor 700, the transistor 800, and the transistor 900, and as wiring for electrically connecting the transistor 700, the transistor 800, and the transistor 900 in series.

[0165] It is preferable to use, for example, silicon as the semiconductor 142. Furthermore, as the silicon, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used. Furthermore, other than silicon, metal oxides can sometimes be used as the semiconductor 142. Furthermore, compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, and SiGe can sometimes be used.

[0166] The semiconductor 143 is provided to fill the opening after the semiconductor 141, the semiconductor 142, the insulator 121, the insulator 122, the insulator 131, the insulator 132, and the insulator 133 are formed in the opening. Specifically, the semiconductor 143 is provided so as to be in contact with the top of the insulator 122 and the top of the semiconductor 142 and in contact with the side surface of the insulator 117.

[0167] The semiconductor 143 is preferably made of, for example, the same material as the semiconductor 141. Therefore, it is preferable that the semiconductors 141 and 143 have the same polarity.

[0168] Note that the memory device 100 according to an embodiment of the present invention is not limited to the configuration of the NAND memory element included in the memory cell unit MCL shown in Fig. 6. The NAND memory element applied to the memory device 100 may have a configuration different from that of the NAND memory element shown in Fig. 6.

[0169] <Configuration example of circuit layer A1> An insulator 382 and an insulator 384 are stacked in this order above the insulator 117 (see FIG. 6 or FIG. 7). A conductor 386 is formed on the insulator 382 and the insulator 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be formed using the same material as the conductors 328 and 330.

[0170] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen and hydrogen.

[0171] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0172] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0173] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0174] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0175] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. Using a material with a relatively low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulator 512 and the insulator 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0176] A conductor 518, a conductor constituting the transistor 500 (the conductor 503), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or wiring connected to the capacitor 600. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0177] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0178] Above the insulator 516 is the transistor 500 .

[0179] As shown in FIGS. 8A and 8B, the transistor 500 includes a conductor 503 disposed so as to be embedded in an insulator 514 and an insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a disposed apart from each other on the oxide 530b, and and conductor 542b, an insulator 580 disposed on conductor 542a and conductor 542b and having an opening formed thereon overlapping between conductor 542a and conductor 542b, a conductor 560 disposed in the opening, an insulator 550 disposed among oxide 530b, conductor 542a, conductor 542b, and insulator 580, and conductor 560, and an oxide 530c disposed among oxide 530b, conductor 542a, conductor 542b, insulator 580, and insulator 550.

[0180] 8A and 8B, it is preferable that insulator 544 be disposed between oxide 530a, oxide 530b, conductor 542a, and conductor 542b and insulator 580. It is preferable that conductor 560 include conductor 560a disposed inside insulator 550 and conductor 560b disposed so as to be embedded inside conductor 560a. It is preferable that insulator 574 be disposed on insulator 580, conductor 560, and insulator 550, as shown in FIGS.

[0181] In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530. The conductor 542a and the conductor 542b may be collectively referred to as the conductor 542.

[0182] Although the transistor 500 has a three-layer structure of oxides 530a, 530b, and 530c in and around the channel formation region, the present invention is not limited to this structure. For example, the transistor may have a single layer of oxide 530b, a two-layer structure of oxides 530b and 530a, a two-layer structure of oxides 530b and 530c, or a stacked structure of four or more layers. Although the transistor 500 has a two-layer structure, the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 shown in FIGS. 7, 8A, and 8B is merely an example, and the transistor may have any structure suitable for the circuit configuration and driving method.

[0183] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of memory devices.

[0184] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0185] The conductor 560 may function as a first gate electrode. The conductor 503 may function as a second gate electrode. In this case, the Vth of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the Vth of the transistor 500 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0186] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0187] Furthermore, in this specification, the S-channel structure is characterized in that the side surfaces and peripheries of the oxide 530 in contact with the conductors 542a and 542b, which function as source and drain electrodes, are I-type, just like the channel formation region. Furthermore, the side surfaces and peripheries of the oxide 530 in contact with the conductors 542a and 542b are in contact with the insulator 544, so they can be I-type, just like the channel formation region. Note that in this specification, I-type can be treated as the same as high-purity intrinsic oxide, as described later. The S-channel structure disclosed in this specification differs from the fin structure and planar structure. The S-channel structure enhances resistance to the short-channel effect, in other words, makes it possible to create a transistor that is less susceptible to the short-channel effect.

[0188] Conductor 503 has the same configuration as conductor 518, with conductor 503a being formed in contact with the inner walls of the openings of insulators 514 and 516, and conductor 503b being formed further inside.

[0189] The insulators 520, 522, 524, and 550 function as gate insulating films.

[0190] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0191] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide from which oxygen is released by heating is an oxide from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0192] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0193] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0194] The insulator 522 is preferably a single layer or multilayer insulator containing, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0195] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing an oxide of one or both of aluminum and hafnium. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0196] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0197] Furthermore, it is preferable that the insulator 520 be thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0198] The insulators 520, 522, and 524 may each have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be those made of different materials.

[0199] The transistor 500 preferably uses a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, tin, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used for the oxide 530. Alternatively, In-Ga oxide or In-Zn oxide may be used for the oxide 530.

[0200] The metal oxide functioning as an oxide semiconductor may be formed by sputtering, atomic layer deposition (ALD), or chemical vapor deposition (CVD) such as metal organic chemical vapor deposition (MOCVD). Metal oxides functioning as oxide semiconductors will be described in other embodiments.

[0201] Furthermore, it is preferable to use a metal oxide with a low carrier density for the transistor 500. To reduce the carrier density of a metal oxide, the impurity concentration in the metal oxide may be reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0202] In particular, hydrogen contained in metal oxide reacts with oxygen bonded to metal atoms to form water, which can form oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region of a metal oxide, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies can function as donors, generating electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to exhibit normally-on characteristics.

[0203] Defects in which hydrogen has entered oxygen vacancies can function as donors for metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated using carrier density rather than donor concentration. Therefore, in this specification and the like, carrier density assuming a state in which no electric field is applied may be used as a parameter for metal oxides, rather than donor concentration. In other words, the "carrier density" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0204] Therefore, when a metal oxide is used for the oxide 530, it is preferable that the hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0205] When a metal oxide is used for the oxide 530, the carrier density of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier density of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0206] Furthermore, when a metal oxide is used for the oxide 530, contact between the conductor 542 (conductor 542a and conductor 542b) and the oxide 530 may cause oxygen in the oxide 530 to diffuse into the conductor 542, resulting in the oxidation of the conductor 542. The oxidation of the conductor 542 is likely to result in a decrease in the conductivity of the conductor 542. The diffusion of oxygen in the oxide 530 into the conductor 542 can be rephrased as the conductor 542 absorbing the oxygen in the oxide 530.

[0207] Furthermore, oxygen in the oxide 530 may diffuse into the conductor 542 (conductor 542a and conductor 542b), forming a heterogeneous layer between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. Since the heterogeneous layer contains more oxygen than the conductor 542, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 542, the heterogeneous layer, and the oxide 530b can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and may be called an MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0208] It should be noted that the above-mentioned different layer is not limited to being formed between the conductor 542 and the oxide 530b, and for example, the different layer may be formed between the conductor 542 and the oxide 530c, between the conductor 542 and the oxide 530b, and between the conductor 542 and the oxide 530c.

[0209] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0210] In addition, the semiconductor material that can be used for the oxide 530 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 530. For example, a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material or a two-dimensional material) that functions as a semiconductor is preferably used as the semiconductor material. In particular, a layered material that functions as a semiconductor is preferably used as the semiconductor material.

[0211] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0212] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0213] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 530. Specific examples of transition metal chalcogenides that can be used as the oxide 530 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0214] The oxide 530 has the oxide 530a below the oxide 530b, which can prevent impurities from diffusing from structures formed below the oxide 530a to the oxide 530b. Also, the oxide 530 has the oxide 530c on the oxide 530b, which can prevent impurities from diffusing from structures formed above the oxide 530c to the oxide 530b.

[0215] The oxide 530 preferably has a stacked structure of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. The atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. The atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxide 530a. The oxide 530c can be the same metal oxide as that used for the oxide 530a or the oxide 530b.

[0216] The oxides 530a and 530c preferably have a conduction band minimum energy higher than that of the oxide 530b, and the oxides 530a and 530c preferably have a lower electron affinity than that of the oxide 530b.

[0217] Here, the energy level of the conduction band minimum changes smoothly at the junction between the oxides 530a, 530b, and 530c. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a, 530b, and 530c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 530a and 530b and at the interface between the oxides 530b and 530c.

[0218] Specifically, when the oxides 530a and 530b, and the oxides 530b and 530c, contain a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxides 530a and 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0219] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 500 to obtain a high on-state current.

[0220] Conductor 542 (conductor 542a and conductor 542b) functioning as a source electrode and a drain electrode are provided on oxide 530b. Conductor 542 is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when they absorb oxygen.

[0221] 8A, a region 543 (regions 543a and 543b) may be formed as a low-resistance region at and near the interface between the oxide 530 and the conductor 542. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0222] Providing the conductor 542 so as to be in contact with the oxide 530 may reduce the oxygen concentration in the region 543. Also, a metal compound layer containing the metal contained in the conductor 542 and components of the oxide 530 may be formed in the region 543. In such a case, the carrier density in the region 543 increases, and the region 543 becomes a low-resistance region.

[0223] Insulator 544 is provided to cover conductor 542 and suppress oxidation of conductor 542. In this case, insulator 544 is provided to cover the side surfaces of oxide 530 and insulator 524 and to be in contact with insulator 522. Alternatively, insulator 544 does not have to be in contact with insulator 522, and insulator 524 may be provided between insulator 522 and insulator 544. In this case, insulator 544 is provided to cover the side surfaces of oxide 530 and to be in contact with insulator 524.

[0224] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride.

[0225] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later process. Note that if the conductor 542 is made of an oxidation-resistant material or a material whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.

[0226] The insulator 550 functions as a gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top and side surfaces) of the oxide 530c. The insulator 550 is preferably formed using an insulator that releases oxygen when heated. For example, in TDS analysis, the amount of released oxygen converted into oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower.

[0227] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0228] By providing the insulator 550, which releases oxygen upon heating, in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similarly to the insulator 524, the insulator 550 preferably has a low concentration of impurities such as water or hydrogen. The thickness of the insulator 550 is preferably 1 nm to 20 nm.

[0229] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0230] The conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 8A and 8B, but may be a single-layer structure or a stacked structure of three or more layers.

[0231] Conductor 560a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms. Alternatively, conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) is preferably used. Conductor 560a has the function of suppressing the diffusion of oxygen, which can suppress the oxidation of conductor 560b due to oxygen contained in insulator 550, thereby preventing a decrease in conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0232] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Because the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0233] The insulator 580 is provided on the conductor 542 with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of an excess oxygen region in a later step.

[0234] Furthermore, by providing the insulator 580, which releases oxygen when heated, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0235] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0236] When miniaturizing memory devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for this purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0237] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0238] For example, the insulator 574 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0239] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0240] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0241] Furthermore, conductors 540a and 540b are arranged in openings formed in insulators 581, 574, 580, and 544. Conductor 540a and 540b are arranged opposite each other with conductor 560 interposed therebetween. Conductor 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0242] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0243] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0244] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. Using a material with a relatively low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0245] Furthermore, conductors 546, 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0246] The conductor 546 and the conductor 548 function as plugs or wirings that connect to the capacitor 600 and the transistor 500. The conductor 546 and the conductor 548 can be formed using the same materials as the conductor 328 and the conductor 330.

[0247] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0248] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0249] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can also be used.

[0250] 7, the conductor 612 and the conductor 610 are shown as single-layer structures, but are not limited to this configuration and may be a stacked structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0251] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other structures such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0252] An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape underneath.

[0253] By using this structure, in a memory device including an OS transistor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, an OS transistor with a large on-state current can be provided. Alternatively, an OS transistor with a small off-state current can be provided. Alternatively, miniaturization or high integration of a memory device including an OS transistor can be achieved.

[0254] <Example of transistor structure> Note that the transistor 500 described in this embodiment is not limited to the above structure. Structural examples that can be used for the transistor 500 are described below.

[0255] <Transistor structure example 1> An example structure of a transistor 510A will be described using Figures 9A, 9B, and 9C. Figure 9A is a top view of the transistor 510A. Figure 9B is a cross-sectional view of the portion indicated by the dashed-dotted line L1-L2 in Figure 9A. Figure 9C is a cross-sectional view of the portion indicated by the dashed-dotted line W1-W2 in Figure 9A. Note that in the top view of Figure 9A, some elements are omitted for clarity.

[0256] 9A, 9B, and 9C show a transistor 510A and insulators 511, 512, 514, 516, 580, 582, and 584 which function as interlayer films. Also shown are a conductor 546 (conductor 546a and conductor 546b) which is electrically connected to the transistor 510A and functions as a contact plug, and a conductor 503 which functions as a wiring.

[0257] Transistor 510A has a conductor 560 (conductor 560a and conductor 560b) that functions as a first gate electrode, a conductor 505 (conductor 505a and conductor 505b) that functions as a second gate electrode, an insulator 550 that functions as a first gate insulating film, insulators 521, 522, and 524 that function as a second gate insulating film, an oxide 530 (oxide 530a, oxide 530b, and oxide 530c) that has a region where a channel is formed, a conductor 542a that functions as one of a source or a drain, a conductor 542b that functions as the other of the source or a drain, and an insulator 574.

[0258] 9B, in the transistor 510A, the oxide 530c, the insulator 550, and the conductor 560 are disposed in an opening in the insulator 580 with the insulator 574 interposed therebetween. The oxide 530c, the insulator 550, and the conductor 560 are also disposed between the conductor 542a and the conductor 542b.

[0259] The insulators 511 and 512 function as interlayer films.

[0260] The interlayer film can be formed of a single layer or a stack of insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO), or (Ba,Sr)TiO (BST). These insulators may also contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. These insulators may also be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may also be stacked on the above insulators.

[0261] For example, the insulator 511 preferably functions as a barrier film that prevents impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, the insulator 511 is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the impurities are less likely to permeate through the insulator). Alternatively, the insulator 511 is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate through the insulator). Furthermore, for example, aluminum oxide or silicon nitride may be used as the insulator 511. This structure can prevent impurities such as hydrogen and water from diffusing from the substrate side toward the transistor 510A through the insulator 511.

[0262] For example, the insulator 512 preferably has a lower dielectric constant than the insulator 511. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0263] The conductor 503 is formed so as to be embedded in the insulator 512. Here, the height of the top surface of the conductor 503 and the height of the top surface of the insulator 512 can be made approximately the same. Note that although the conductor 503 is shown as having a single layer structure, the present invention is not limited to this. For example, the conductor 503 may have a multilayer film structure of two or more layers. Note that the conductor 503 is preferably made of a highly conductive material containing tungsten, copper, or aluminum as a main component.

[0264] In the transistor 510A, the conductor 560 may function as a first gate electrode. The conductor 505 may function as a second gate electrode. In this case, the threshold voltage of the transistor 510A can be controlled by changing the potential applied to the conductor 505 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 505 can increase the threshold voltage of the transistor 510A above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 505 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 505.

[0265] Furthermore, for example, by overlapping the conductor 505 and the conductor 560, when a potential is applied to the conductor 560 and the conductor 505, the electric field generated from the conductor 560 and the electric field generated from the conductor 505 can be connected and can cover the channel formation region formed in the oxide 530.

[0266] That is, the channel formation region can be electrically surrounded by the electric field of the conductor 560 functioning as the first gate electrode and the electric field of the conductor 505 functioning as the second gate electrode. That is, like the transistor 500 described above, this has a surrounded channel (S-channel) structure.

[0267] The insulators 514 and 516 function as interlayer films, similar to the insulator 511 or 512. For example, the insulator 514 preferably functions as a barrier film that prevents impurities such as water or hydrogen from entering the transistor 510A from the substrate side. This structure can prevent impurities such as hydrogen or water from diffusing from the substrate side toward the transistor 510A through the insulator 514. Furthermore, for example, the insulator 516 preferably has a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings.

[0268] The conductor 505 functioning as the second gate has a conductor 505a formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 505b formed further inside. Here, the height of the top surfaces of the conductor 505a and the conductor 505b can be made approximately the same as the height of the top surface of the insulator 516. Note that although the transistor 510A has a structure in which the conductor 505a and the conductor 505b are stacked, the present invention is not limited to this. For example, the conductor 505 may have a single layer structure or a stacked structure of three or more layers.

[0269] Here, the conductor 505a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the impurities are less likely to permeate through it). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate through it). Note that in this specification and the like, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0270] For example, the conductor 505a has a function of suppressing the diffusion of oxygen, so that the conductor 505b can be prevented from being oxidized and its conductivity from decreasing.

[0271] Furthermore, when the conductor 505 also functions as a wiring, it is preferable that the conductor 505b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. In this case, the conductor 503 is not necessarily provided. Note that although the conductor 505b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the above-mentioned conductive material.

[0272] The insulators 521, 522, and 524 function as a second gate insulating film.

[0273] The insulator 522 preferably has a barrier property. When the insulator 522 has a barrier property, it functions as a layer that prevents impurities such as hydrogen from entering the transistor 510A from the periphery of the transistor 510A.

[0274] The insulator 522 is preferably a single-layer or multi-layer insulator containing aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), oxide nitride containing aluminum and hafnium, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0275] Furthermore, it is preferable that the insulator 521 be thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 521 having a thermally stable layered structure with a high dielectric constant.

[0276] 9B and 9C show a three-layer stacked structure as the second gate insulating film, but it may have a two-layer or less, or four-layer or more. In this case, it is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0277] The oxide 530 having a region functioning as a channel formation region includes an oxide 530a, an oxide 530b on the oxide 530a, and an oxide 530c on the oxide 530b. Having the oxide 530a below the oxide 530b can suppress impurity diffusion from structures formed below the oxide 530a to the oxide 530b. Having the oxide 530c on the oxide 530b can suppress impurity diffusion from structures formed above the oxide 530c to the oxide 530b. The oxide 530 can be made of an oxide semiconductor, which is one of the above-described metal oxides.

[0278] Note that the oxide 530c is preferably provided in an opening in the insulator 580 via the insulator 574. When the insulator 574 has a barrier property, it can prevent impurities from the insulator 580 from diffusing into the oxide 530.

[0279] One of the conductors 542 functions as a source electrode, and the other functions as a drain electrode.

[0280] The conductors 542a and 542b can be made of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing any of these as its main component. In particular, a metal nitride film such as tantalum nitride is preferable because it has barrier properties against hydrogen or oxygen and is highly resistant to oxidation.

[0281] Although a single-layer structure is shown in FIG. 9B, a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be laminated. Alternatively, a titanium film and an aluminum film may be laminated. Alternatively, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0282] Other examples include a three-layer structure in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0283] A barrier layer may be provided over the conductor 542. The barrier layer is preferably formed using a substance that has a barrier property against oxygen or hydrogen. With this structure, oxidation of the conductor 542 can be suppressed when the insulator 574 is formed.

[0284] The barrier layer can be made of, for example, a metal oxide. In particular, it is preferable to use an insulating film that has barrier properties against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide. Silicon nitride formed by CVD may also be used.

[0285] The presence of the barrier layer can broaden the range of material options for the conductor 542. For example, materials with low oxidation resistance but high conductivity, such as tungsten or aluminum, can be used for the conductor 542. Also, for example, a conductor that is easy to form or process can be used.

[0286] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably provided in the opening provided in the insulator 580 with the oxide 530c and the insulator 574 interposed therebetween.

[0287] As transistors become more miniaturized and highly integrated, thinning of the gate insulating film can cause problems such as leakage current. In this case, the insulator 550 may have a stacked structure, similar to the second gate insulating film. By using a stacked structure of a high-k material and a thermally stable material for the insulator functioning as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a stacked structure that is thermally stable and has a high dielectric constant can be achieved.

[0288] The conductor 560 functioning as the first gate electrode includes a conductor 560a and a conductor 560b on the conductor 560a. As with the conductor 505a, the conductor 560a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, the conductor 560a is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0289] The conductor 560a has the function of suppressing oxygen diffusion, which improves the material selectivity of the conductor 560b. In other words, the presence of the conductor 560a suppresses oxidation of the conductor 560b, preventing a decrease in conductivity.

[0290] As a conductive material capable of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Furthermore, an oxide semiconductor that can be used as the oxide 530 can be used as the conductor 560a. In this case, by forming the conductor 560b by a sputtering method, the electrical resistance of the conductor 560a can be reduced, making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0291] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 560 functions as wiring, it is preferable to use a conductor with high conductivity for the conductor 560b. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0292] An insulator 574 is disposed between the insulator 580 and the transistor 510A. The insulator 574 is preferably an insulating material that has a function of suppressing diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. Other examples of the insulator include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0293] The insulator 574 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 574 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0294] Insulators 580, 582, and 584 function as interlayer films.

[0295] Like the insulator 514, the insulator 582 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 510A from the outside.

[0296] Similarly to the insulator 516, the insulators 580 and 584 preferably have a lower dielectric constant than the insulator 582. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0297] Additionally, transistor 510A may be electrically connected to other structures through plugs or interconnects such as conductor 546 embedded in insulator 580, insulator 582, and insulator 584.

[0298] Similarly to the conductor 505, the conductor 546 can be made of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, either in a single layer or a stacked layer. For example, it is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity. Alternatively, it is preferable to form the conductor 546 from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance.

[0299] For example, by using a layered structure of tantalum nitride, a conductor that has barrier properties against hydrogen and oxygen, and tungsten, which has high conductivity, as the conductor 546, it is possible to suppress the diffusion of impurities from the outside while maintaining the conductivity as a wiring.

[0300] With the above structure, an OS transistor with a large on-state current or a small off-state current can be provided. Alternatively, a change in electrical characteristics of a memory device including an OS transistor can be suppressed and the reliability can be improved.

[0301] <Transistor structure example 2> An example structure of a transistor 510B will be described using Figures 10A, 10B, and 10C. Figure 10A is a top view of the transistor 510B. Figure 10B is a cross-sectional view of the portion indicated by the dashed-dotted line L1-L2 in Figure 10A. Figure 10C is a cross-sectional view of the portion indicated by the dashed-dotted line W1-W2 in Figure 10A. Note that in the top view of Figure 10A, some elements are omitted for clarity.

[0302] The transistor 510B is a modified example of the transistor 510A. Therefore, to avoid repetition of the description, the differences from the above transistor will be mainly described.

[0303] In transistor 510A, a portion of insulator 574 is provided in an opening provided in insulator 580 and is provided so as to cover the side surface of conductor 560. On the other hand, in transistor 510B, an opening is formed by removing a portion of insulator 580 and insulator 574.

[0304] Furthermore, an insulator 576 (insulators 576a and 576b) having barrier properties may be disposed between the conductor 546 and the insulator 580. By providing the insulator 576, it is possible to prevent oxygen in the insulator 580 from reacting with the conductor 546 and oxidizing the conductor 546.

[0305] When an oxide semiconductor is used for the oxide 530, the oxide 530 preferably has a stacked structure of multiple oxide layers with different atomic ratios of metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. The atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. The atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to M in the metal oxide used for the oxide 530a. The oxide 530c can be the same metal oxide as can be used for the oxide 530a or the oxide 530b.

[0306] The oxide 530a, the oxide 530b, and the oxide 530c preferably have crystallinity, and CAAC-OS is particularly preferable. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies) and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 530b. This can reduce the extraction of oxygen from the oxide 530b even during heat treatment, making the transistor 510B stable against high temperatures (or thermal budgets) during the manufacturing process.

[0307] One or both of the oxides 530a and 530c may be omitted. The oxide 530 may be a single layer of the oxide 530b. When the oxide 530 is a stack of the oxides 530a, 530b, and 530c, the conduction band minimum energies of the oxides 530a and 530c are preferably higher than the conduction band minimum energy of the oxide 530b. In other words, the electron affinity of the oxides 530a and 530c is preferably lower than the electron affinity of the oxide 530b. In this case, the oxide 530c is preferably a metal oxide that can be used for the oxide 530a. Specifically, the atomic ratio of the element M among the constituent elements of the metal oxide used for the oxide 530c is preferably higher than the atomic ratio of the element M among the constituent elements of the metal oxide used for the oxide 530b. In addition, the atomic ratio of the element M to In in the metal oxide used for oxide 530c is preferably greater than the atomic ratio of the element M to In in the metal oxide used for oxide 530b. In addition, the atomic ratio of In to M in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of In to M in the metal oxide used for oxide 530c.

[0308] Here, the energy level of the conduction band minimum changes smoothly at the junction between the oxides 530a, 530b, and 530c. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a, 530b, and 530c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 530a and 530b and at the interface between the oxides 530b and 530c.

[0309] Specifically, the oxides 530a and 530b, and the oxides 530b and 530c, may have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low density of defect states. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxides 530a and 530c may be made of In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like. The oxide 530c may also have a stacked structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide, may be used. In other words, the oxide 530c may have a stacked structure of In-Ga-Zn oxide and an oxide not containing In.

[0310] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. Oxide 530b may be a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or 3:1:2. Oxide 530c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0311] In this case, the oxide 530b serves as the main carrier path. The oxide 530a and the oxide 530c are configured as described above, thereby reducing the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 510B to achieve a high on-state current and high frequency characteristics. Note that when the oxide 530c has a stacked structure, in addition to reducing the defect state density at the interface between the oxide 530b and the oxide 530c, it is expected to prevent the constituent elements of the oxide 530c from diffusing toward the insulator 550. More specifically, the oxide 530c has a stacked structure, and an oxide not containing In is positioned above the stacked structure, thereby preventing In from diffusing toward the insulator 550. The insulator 550 functions as a gate insulator, and diffusion of In leads to poor transistor characteristics. Therefore, by forming the oxide 530c into a stacked structure, a highly reliable memory device can be provided.

[0312] The oxide 530 is preferably a metal oxide that functions as an oxide semiconductor. For example, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more, is preferably used as the metal oxide that forms the channel formation region of the oxide 530. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced. By using such a transistor, a memory device with low power consumption can be provided.

[0313] <Transistor structure example 3> 11A and 11B will be used to describe a structural example of a transistor 510C. The transistor 510C is a variation of the transistor 500. Therefore, to avoid repetition of description, differences from the above transistor will be mainly described. Note that the structures illustrated in FIGS. 11A and 11B can also be applied to other transistors, such as the transistor 300, included in a memory device according to one embodiment of the present invention.

[0314] 11A and 11B are cross-sectional views of the transistor 510C in the channel length direction and the channel width direction, respectively. The transistor 510C shown in FIGS. 11A and 11B differs from the transistor 500 shown in FIGS. 8A and 8B in that the transistor 510C includes the insulators 402 and 404 and that the insulator 550 includes the insulators 550a and 550b. The transistor 510C also differs from the transistor 500 shown in FIGS. 8A and 8B in that the insulator 551 is provided in contact with a side surface of the conductor 540a, the insulator 551 is provided in contact with a side surface of the conductor 540b, the conductor 572a is provided in contact with a top surface of the conductor 542a, the conductor 532a is provided in contact with a top surface of the region 543a, the conductor 572b is provided in contact with a top surface of the conductor 542b, and the conductor 532b is provided in contact with a top surface of the region 543b. Furthermore, the transistor 500 differs from the transistor 500 shown in FIGS. 8A and 8B in that it does not have the insulator 520 and the oxide 530c.

[0315] 11A and 11B, the insulator 402 is provided over the insulator 512. The insulator 404 is provided over the insulator 574 and the insulator 402.

[0316] 11A and 11B, the insulators 514, 516, 522, 544, 580, and 574 are patterned, and the insulator 404 covers them. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 402. As a result, the oxide 530 and the like are isolated from the outside by the insulators 404 and 402.

[0317] The insulators 402 and 404 preferably have a high function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules) or water molecules. For example, silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, are preferably used for the insulators 402 and 404. This can suppress the diffusion of hydrogen and other substances into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 510C. Therefore, the reliability of a memory device including an OS transistor can be improved.

[0318] Silicon oxide, silicon oxynitride, or the like can be used for insulator 550a, and hafnium oxide, for example, can be used for insulator 550b. This can suppress oxidation of conductor 560. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) can be used for conductors 572a and 572b, and the metal oxide used for oxide 530a, for example, can be used for conductors 532a and 532b. This can suppress oxidation of conductors 542a and 542b.

[0319] The insulator 551 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 551 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 551 is preferably made of a material with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 551 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 551 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductors 540a and 540b. Furthermore, oxygen contained in the insulator 580 can be suppressed from being absorbed by the conductors 540a and 540b. These features can improve the reliability of a memory device including an OS transistor.

[0320] <Transistor structure example 4> 12A and 12B will be used to describe a structural example of a transistor 510D. The transistor 510D is a variation of the transistor 500. Therefore, to avoid repetition of description, differences from the above transistor will be mainly described. Note that the structures illustrated in FIGS. 12A and 12B can also be applied to other transistors, such as the transistor 300, included in a memory device according to one embodiment of the present invention.

[0321] 12A and 12B illustrate modifications of the transistor illustrated in FIGS. 8A and 8B. FIG. 12A is a cross-sectional view of the transistor in the channel length direction, and FIG. 12B is a cross-sectional view of the transistor in the channel width direction. The transistor illustrated in FIGS. 12A and 12B differs from the transistor 500 illustrated in FIGS. 8A and 8B in that the transistor includes an insulator 402 and an insulator 404. The transistor also differs from the transistor 500 illustrated in FIGS. 8A and 8B in that the insulator 551 is provided in contact with a side surface of the conductor 540a and the insulator 551 is provided in contact with a side surface of the conductor 540b. The transistor also differs from the transistor 500 illustrated in FIGS. 8A and 8B in that the insulator 520 is not provided. The transistor also differs from the transistor illustrated in FIGS. 8A and 8B in that the oxide 530c has a two-layer structure of an oxide 530c1 and an oxide 530c2.

[0322] 12A and 12B, the insulator 402 is provided over the insulator 512. The insulator 404 is provided over the insulator 574 and the insulator 402.

[0323] 12A and 12B , the insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and the insulator 404 covers them. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 402. As a result, the oxide 530 and the like are isolated from the outside by the insulators 404 and 402.

[0324] The insulators 402 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules) or water molecules. For example, silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, are preferably used for the insulators 402 and 404. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 510D. Therefore, the reliability of a memory device including an OS transistor can be improved.

[0325] The insulator 551 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 551 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 551 is preferably made of a material with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 551 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 551 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductors 540a and 540b. Furthermore, oxygen contained in the insulator 580 can be suppressed from being absorbed by the conductors 540a and 540b. These features can improve the reliability of a memory device including an OS transistor.

[0326] The oxide 530c1 contacts the top surface of the insulator 522, the side surface of the insulator 524, the side surface of the oxide 530a, the top surface and side surfaces of the oxide 530b, the side surfaces of the conductors 542a and 542b, the side surface of the insulator 544, and the side surface of the insulator 580. The oxide 530c2 contacts the insulator 550.

[0327] Oxide 530c1 can be, for example, an In-Zn oxide. Oxide 530c2 can be made of the same material as that used for oxide 530c when oxide 530c has a single-layer structure. For example, oxide 530c2 can be made of a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5.

[0328] By forming the oxide 530c as a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-state current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be, for example, a power MOS transistor. The oxide 530c of the transistor shown in FIGS. 8A and 8B can also have a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0329] The transistors shown in FIGS. 12A and 12B can be applied to, for example, the transistor 500, the transistor 300, or both.

[0330] Note that the structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0331] (Embodiment 3) In this embodiment, an oxide semiconductor, which is a type of metal oxide, will be described.

[0332] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition to these, it is preferable that it contains one or more elements selected from aluminum, gallium, yttrium, tin, etc. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0333] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 13A. Fig. 13A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0334] As shown in FIG. 13A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0335] The structure within the bold frame in Figure 13A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "amorphous" and "crystal."

[0336] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 13B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 13B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 13B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 13B is 500 nm.

[0337] In Figure 13B, the horizontal axis is 2θ [deg.] and the vertical axis is intensity [au]. As shown in Figure 13B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 13B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0338] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 13C. Figure 13C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 13C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0339] As shown in FIG. 13C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0340] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 13A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0341] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0342] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0343] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0344] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0345] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0346] For example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0347] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0348] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0349] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is unlikely to occur in CAAC-OS. Furthermore, since the crystallinity of oxide semiconductors can be reduced by impurities or defects, CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable against high temperatures (or thermal budgets) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0350] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of these microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when electron diffraction (also known as selected-area electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0351] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0352] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0353] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0354] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into first and second regions, forming a mosaic structure in which the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure).

[0355] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0356] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0357] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0358] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0359] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0360] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0361] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0362] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0363] An oxide semiconductor with low carrier density is preferably used for the transistor (see Embodiment 2 for more details). Note that in order to reduce the carrier density of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor with low carrier density may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0364] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0365] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0366] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0367] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0368] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by SIMS) are calculated as follows: 18 atoms / cm3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0369] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0370] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier density increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0371] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible (more specifically, see Embodiment 2).

[0372] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0373] Note that the structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0374] (Fourth embodiment) In this embodiment mode, an example of a semiconductor wafer on which the memory device or the like described in the above embodiment mode is formed and an example of an electronic component in which the memory device is incorporated will be described.

[0375] <Semiconductor wafer> First, an example of a semiconductor wafer on which a memory device or the like is formed will be described with reference to FIG. 14A.

[0376] 14A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0377] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0378] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0379] By performing a dicing process, chips 4800a as shown in FIG. 14B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0380] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 14A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the apparatus for manufacturing the element.

[0381] <Electronic components> 14C is a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 14C includes a chip 4800a in a mold 4711. A memory device according to one embodiment of the present invention or the like can be used as the chip 4800a.

[0382] 14C omits some parts to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0383] 14D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple memory devices 4710 provided on interposer 4731.

[0384] The memory device 4710 may be, for example, a chip 4800a, the memory device described in the above embodiment, or a high bandwidth memory (HBM). The semiconductor device 4735 may be an integrated circuit such as a CPU, a GPU, an FPGA, or a memory device. In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0385] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0386] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0387] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0388] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0389] Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0390] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When the heat sink is provided, it is preferable to align the height of the integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the memory device 4710 and the height of the semiconductor device 4735.

[0391] Electrodes 4733 may be provided on the bottom of package substrate 4732 in order to mount electronic component 4730 on another substrate. Fig. 14D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0392] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0393] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0394] (Embodiment 5) In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0395] A storage device according to one embodiment of the present invention can be used, for example, as a storage device for various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, Internet of Things (IoT) terminal devices, healthcare, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0396] 15A to 15J and 16A to 16E illustrate examples of electronic devices including an electronic component 4700 or an electronic component 4730 including the memory device according to one embodiment of the present invention.

[0397] [mobile phone] 15A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0398] By applying a storage device according to one embodiment of the present invention, the information terminal 5500 can store temporary files (such as caches when using a web browser) generated when an application is executed.

[0399] [Wearable devices] 15B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0400] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0401] [Information terminal] 15C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0402] Like the information terminal 5500 described above, the desktop information terminal 5300 can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0403] 15A to 15C are taken as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0404] [electric appliances] 15D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. Electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0405] A storage device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the storage device.

[0406] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0407] [Game consoles] 15E illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0408] FIG. 15F further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 15F, the controller 7522 can include a display unit that displays game images, and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 15F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0409] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0410] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0411] Furthermore, by applying the storage device described in the above embodiments to the portable game console 5200 or the stationary game console 7500, temporary files and the like required for calculations that occur during game execution can be stored.

[0412] 15E shows a portable game machine and FIG. 15F shows a stationary game machine as examples of game machines, but the electronic device of one embodiment of the present invention is not limited to these. Examples of the electronic device of one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0413] [Moving object] The storage device described in the above embodiment can be applied to a vehicle, which is a moving object, and to the vicinity of the driver's seat of the vehicle.

[0414] FIG. 15G illustrates an automobile 5700 as an example of a moving object.

[0415] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0416] In particular, the display device can enhance safety by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby compensating for a field of view obstructed by a pillar or the like, a blind spot on the driver's seat, etc. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be enhanced.

[0417] The storage device described in the above embodiment can temporarily store information, and therefore, for example, the storage device can be used to store necessary temporary information in an automatic driving system for the automobile 5700, a system that provides road guidance, hazard prediction, or the like. The display device may be configured to display temporary information such as road guidance and hazard prediction. The display device may also be configured to store video images from a driving recorder installed in the automobile 5700.

[0418] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0419] [camera] The storage device described in the above embodiment can be applied to a camera.

[0420] 15H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0421] A low-power digital camera 6240 can be realized by applying the storage device described in the above embodiment to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0422] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0423] 15I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0424] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the storage device described above, the video camera 6300 can store temporary files generated during encoding.

[0425] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0426] 15J is a cross-sectional schematic diagram showing an example of an ICD. ICD main body 5400 has at least battery 5401, electronic components 4700, a regulator, a control circuit, antenna 5404, wire 5402 to the right atrium, and wire 5403 to the right ventricle.

[0427] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0428] The ICD main unit 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (such as in the case of rapid ventricular tachycardia or ventricular fibrillation), treatment with an electric shock is administered.

[0429] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 4700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration, and so on.

[0430] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 can also function as an auxiliary power source.

[0431] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0432] [PC expansion device] The storage device described in the above embodiment can be applied to computers such as PCs and expansion devices for information terminals.

[0433] Figure 16A shows an example of such an expansion device: a portable expansion device 6100 that is external to a PC and equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting it to a PC via USB, for example. While Figure 16A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may also be a relatively large expansion device equipped with a cooling fan, for example.

[0434] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with circuits that drive the storage devices and the like described in the above embodiments. For example, the board 6104 is equipped with an electronic component 4700 and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to an external device.

[0435] [SD card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0436] FIG. 16B is a schematic diagram of the external appearance of an SD card, and FIG. 16C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the circuit board 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, and the like provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0437] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.

[0438] [SSD] The storage device described in the above embodiment can be applied to an SSD that can be attached to electronic devices such as information terminals.

[0439] FIG. 16D is a schematic diagram of the external appearance of an SSD, and FIG. 16E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a storage device and a circuit for driving the storage device. For example, the circuit board 5153 is equipped with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the circuit board 5153. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0440] [Calculator] 17A is an example of a large-scale computer. The computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The computer 5600 may also be called a supercomputer.

[0441] Computer 5620 can have the configuration shown in the perspective view of Fig. 17B, for example. In Fig. 17B, computer 5620 has motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

[0442] PC card 5621 shown in FIG. 17C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 includes board 5622. Board 5622 includes connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 17C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0443] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0444] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0445] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0446] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0447] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. The semiconductor device 5628 can be, for example, a memory device. The electronic component 4700 can be used as the semiconductor device 5628.

[0448] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0449] By using a storage device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller, faster, or consume less power. Furthermore, the storage device of one embodiment of the present invention consumes less power, which can reduce heat generation from a circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using a storage device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0450] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0451] A1: circuit layer, A2: circuit layer, A3: wiring layer, BL: wiring, BLD: circuit, BSL: wiring, BTr: transistor, CA1: capacitance, CB1: capacitance, CL: wiring, CS: control signal, CTr: transistor, CTR: control circuit, CVC: circuit, DEC: decoder, DL: wiring, INV: inverter circuit, IT: terminal, IT1: terminal, IT2: terminal, M1: conductor, M2: conductor, M3: conductor, MC: memory cell, MCA: memory cell array, MCL: memory cell section, NA: NAND circuit, NFL: NAND flash layer, OIV: inverter circuit, OSC: Circuit, OT: Terminal, OUTP: Output circuit, PRPH: Circuit, RDATA: Data signal, SCL1: Scribe line, SCL2: Scribe line, SRG: String, SSL: Wiring, STr: Transistor, SUB: Substrate, TrA1: Transistor, TrA2: Transistor, TrA3: Transistor, TrA4: Transistor, TrB1: Transistor, TrB2: Transistor, TrB3: Transistor, TrB4: Transistor, TrB5: Transistor, TrB6: Transistor, VHL: Wiring, VLL: Wiring, WDATA: Data signal, W L: wiring, WLD: circuit, 100: memory device, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 500: transistor, 510A: transistor, 510B: transistor, 510C: transistor, 510D: transistor, 530: oxide, 530a: oxide, 530b: oxide, 530c: oxide, 530c1: oxide, 530c2: oxide, 543: region, 543a: region, 543b: region, 600: capacitor, 700: transistor, 800: transistor, 900: transistor , 4700: electronic component, 4702: printed circuit board, 4704: mounting board, 4710: storage device, 4711: mold, 4712: land, 4713: electrode pad, 4714: wire, 4730: electronic component, 4731: interposer, 4732: package substrate, 4733: electrode, 4735: semiconductor device, 4800: semiconductor wafer, 4800a: chip, 4801: wafer, 4801a: wafer, 4802: circuit unit, 4803: spacing, 4803a: spacing, 5110: SD card, 5111: housing, 5112: connector, 5113: substrate,5115: Controller chip, 5150: SSD, 5151: Housing, 5152: Connector, 5153: Board, 5155: Memory chip, 5156: Controller chip, 5200: Portable game console, 5201: Housing, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display unit, 5303: Keyboard, 5400: ICD main unit, 5401: Battery, 5402 : Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Housing, 5511: Display unit, 5600: Computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629 : Connection terminal, 5630: Motherboard, 5631: Slot, 5700: Automobile, 5800: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer door, 5900: Information terminal, 5901: Housing, 5902: Display unit, 5903: Operation switch, 5904: Operation switch, 5905: Band, 6100: Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 610 4: Circuit board, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: Housing, 6302: Housing, 6303: Display unit, 6304: Operation switch, 6305: Lens, 6306: Connection unit, 7500: Stationary game console, 7520: Main unit, 7522: Controller,

Claims

1. a first circuit layer, a second circuit layer, a wiring layer, and a NAND flash layer; a first conductor, a second conductor, and a third conductor; the NAND flash layer is provided above the second circuit layer; the wiring layer is provided above the NAND flash layer; the first circuit layer is provided above the wiring layer; the second circuit layer and the first circuit layer are electrically connected via the first conductor; the first circuit layer and the NAND flash layer are electrically connected via the second conductor and the third conductor; a decoder is provided on the first circuit layer; The NAND flash layer is provided with memory cells, a control circuit for controlling the decoder and the memory cells is provided in the second circuit layer; the decoder is located in a region overlapping the first conductor electrically connected to the second circuit layer and in a region overlapping the second conductor electrically connected to the NAND flash layer; When the control circuit selects one page from a plurality of pages included in the NAND flash layer, the control circuit outputs a selection signal to the decoder via a first wiring electrically connected to the second circuit layer; the first conductor is used for the first wiring, the selection signal sent from the second circuit layer to the decoder is a digital signal; the decoder has a function of selecting one page of the NAND flash layer in response to the selection signal; the decoder has a function of outputting a high-level potential to a selected page of the NAND flash layer via a second wiring, and outputting a low-level potential to a non-selected page of the NAND flash layer via the second wiring; the second wiring is a word line and is electrically connected to the memory cell; the second wiring includes the second conductor and the third conductor; The number of pages in the NAND flash layer is set to X (X is 2 ｋ where k is an integer satisfying the formula: Y + log ２ X number of memory devices (Y is an integer equal to or greater than 0, and Y includes the power supply line of the decoder and is the number of lines other than the selection signal line).

2. In claim 1, The decoder includes inverter circuits INV[1] to INV[Y+log ２ X], inverter circuits OIV[1] to OIV[X], and NAND circuits NA[1] to NA[X], The first wiring [t] (t is 1 or more and Y+log ２ X) is electrically connected to the input terminal of the inverter circuit INV[t], The first wiring [t] is electrically connected to one or more selected from the first input terminals of each of the NAND circuits NA[1] to NA[X], an output terminal of the inverter circuit INV[t] is electrically connected to one or more selected from the second input terminals of the NAND circuits NA[1] to NA[X]; an output terminal of the NAND circuit NA[s] (s is an integer of 1 or more and X or less) is electrically connected to input terminals of the inverter circuits OIV[1] to OIV[X]; A memory device in which output terminals of the inverter circuits OIV[1] to OIV[X] are electrically connected to the second wiring [s].

Images