Semiconductor device

Abstract

To provide a semiconductor storage device which does not require high voltage in writing, generates fewer defects, and requires shorter time in writing, and in which data cannot be rewritten without increasing cost.SOLUTION: The semiconductor storage device includes a first transistor connected to a diode, a second transistor with a gate connected to one terminal of a source electrode and a drain electrode of the first transistor connected to the diode, and a memory element with a capacitor connected to the gate of the second transistor and to the one terminal of the source electrode and the drain electrode of the first transistor connected to the diode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing the same. [Background technology]

[0002] In recent years, many electronic devices, such as computers, use various data to achieve desired results. These data are stored in a semiconductor memory device (also called a memory) It can be used temporarily or permanently by storing it in a suitable place.

[0003] Semiconductor memory devices are, in a broad sense, external memory devices such as hard disks and flexible disks. This includes devices (auxiliary storage devices), but also refers to semiconductor memory devices such as CPUs (central processing units). In most cases it means.

[0004] Semiconductor memory devices can be classified into volatile memory and nonvolatile memory. A memory is a semiconductor storage device in which data is lost when the power is turned off. It is a semiconductor memory device that continues to retain data even after the power is turned off, and after writing data This allows the data to be retained semi-permanently.

[0005] Volatile memory has the potential to lose data but has a short access time. Non-volatile memory can retain data but consumes less power. As such, each semiconductor memory device has its own unique characteristics. Each semiconductor memory device is used depending on the type of data to be handled or the purpose of use.

[0006] Among non-volatile memories, there is ROM (Read Only Memory) which cannot be written to. Flash memory, which can be written and erased multiple times, and EEPROM (Electronic cally Erasable and Programmable Read Onl There are various types of memory, such as RAM (RAM), which can be written only once. A one-time memory is preferable from the viewpoint of security, since data is difficult to tamper with.

[0007] As an example of write-once memory, a voltage is applied to both ends of an element made of amorphous silicon. There is also an anti-fuse type memory in which the electrodes are silicided to short out the memory. While using rewritable memory such as flash memory and EEPROM, erasure is not performed. By creating a memory area that does not have a write-once memory, it can be used logically as a write-once memory ( See Patent Document 1. ). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 7-297293 Summary of the Invention [Problem to be solved by the invention]

[0009] However, conventional write-once memory has the problem of requiring high voltage for writing. In write-once memory, the read operation is performed to permanently change the memory element. For example, when writing, a voltage higher than that used in the actual operation must be applied. For silicide-type write-once memory, which uses silicide as the memory element, the number of V voltage is required to operate flash memory or EEPROM as write-once memory. When using a ferroelectric capacitor, a voltage of 15 to 18 V is required. A voltage circuit is required, which increases the power consumption when writing. In order to apply a high voltage, a high potential voltage must also be applied to peripheral circuits such as decoders during writing. As a result, in order to increase the withstand voltage of the peripheral circuits so that they can withstand high voltages, In addition, it is necessary to increase the channel length and form an LDD region, which increases the number of manufacturing steps and This hinders high integration.

[0010] In addition, silicide-type write-once memory may not be fully functional due to insufficient write voltage. The resistance is high enough that it is not recognized as data 1 during the read operation (described later). A short circuit may occur, where the resistance is high. The child essentially becomes a defective element.

[0011] In addition, silicide-type write-once memory can write to multiple memory cells simultaneously. It is difficult to write to many memory elements in a short time. In the case of a memory cell or EEPROM, it is possible to write to multiple memory cells at the same time, The write time is about 100 μs, which is long.

[0012] Flash memory or ERAM that can be used as a write-once memory by logic circuit operation EPROM is a type of memory that can be used to store data stored in write-once memory due to a malfunction of the logic circuit. In particular, there is a risk that rewritable memory and writer data may be rewritten in semiconductor storage devices. This problem is likely to occur when multiple memory cells are fabricated using the same structure. In addition, malicious users may cause the logic circuit to malfunction, resulting in write-once memory. There is a risk that data in the memory may be tampered with.

[0013] In view of the above, one embodiment of the present invention is to provide a memory device that does not require a high voltage for writing without increasing costs. It is a semiconductor memory device that is not prone to defects, has a short write time, and cannot be rewritten. The objective is to provide a place for [Means for solving the problem]

[0014] One aspect of the present invention is a diode-connected first transistor and a diode-connected second transistor. A second transistor having a gate connected to one of the source and drain electrodes of the first transistor. The semiconductor memory device includes a memory element having a first transistor. One of the source and drain electrodes of the first transistor is connected to the diode-connected first transistor. A parasitic capacitance is formed between the source electrode of the transistor and one of the drain electrodes.

[0015] In one embodiment of the present invention, a diode-connected first transistor and a diode-connected second transistor are provided. a second transistor whose gate is connected to one of the source and drain electrodes of the first transistor; The second transistor and the source electrode and drain electrode of the diode-connected first transistor a memory element having a capacitance element connected to one terminal of the electrode and the gate of the second transistor; It is a semiconductor memory device including a child.

[0016] When the second transistor is in an on-state, that is, when a voltage higher than the threshold voltage is applied to the gate, When the gate is turned on, it is in the data write state, and when the gate is turned off, that is, when a voltage lower than the threshold voltage is applied, it is in the data write state. When voltage is applied to the gate, data is not written. One of the source and drain terminals of the first transistor functions as an anode. In addition, the channel region of the diode-connected first transistor is made of an oxide semiconductor. By forming it, 1×10 -19 A / μm or less, even 1×10 -20 A / μm or more Therefore, the second current that has risen due to the data writing can be reduced. The potential of the gate of the transistor or the second transistor increased by writing data The potential of the gate and the capacitance element leaks from the diode-connected first transistor. In other words, the potential of the gate of the second transistor can be maintained. The data can be retained.

[0017] Therefore, the write voltage is set to a voltage that can turn on the second transistor, i.e., It is possible to set the voltage to be equal to or higher than the threshold voltage of the transistor, and the write voltage can be reduced. In addition, there is no need to provide a boost circuit for the write voltage, and power consumption during writing can be reduced. It is possible to reduce the power consumption, and also to increase the channel length to increase the breakdown voltage and to reduce the LDD region shape. This eliminates the need for a separate memory device, making it possible to reduce the size of the memory device and achieve higher integration.

[0018] Also, unlike silicide-type write-once memory, the memory element is made of a transistor. Since it is possible to form the wiring, it is possible to reduce writing failures.

[0019] In the semiconductor memory device according to one aspect of the present invention, the write time is The on-state current of the first transistor is determined by the on-state current of the second transistor and the capacitance of the capacitor. Flow 10 -6 A: Even if the capacitance of the capacitive element is 1 pF, writing is completed in about 1 μs. It is also possible to write to multiple memory elements simultaneously. The reading time is significantly reduced.

[0020] In addition, the memory cell included in the semiconductor memory device according to one embodiment of the present invention is a write-once memory. Therefore, data rewriting due to malfunction of the logic circuit does not occur. By simply changing the wiring layout of the memory element of the memory, it is possible to form a rewritable memory. This allows for the development of semiconductors that incorporate rewritable memory and write-once memory. It is also possible to fabricate a memory device. This can improve safety. [Effects of the Invention]

[0021] It does not require high voltage for writing, is less likely to cause defects, has a short writing time, and is easy to rewrite data. Therefore, a semiconductor memory device that cannot be easily replaced can be manufactured without increasing costs. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 2] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 3] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 4] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 5] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 6]FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 7] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 8] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 9] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 10] FIG. 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 11] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 12] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 13] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a top view illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view illustrating a semiconductor memory device according to one embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a diagram illustrating an RFID tag. [Figure 18] FIG. 1 is a diagram illustrating an RFID tag. [Figure 19] FIG. 1 is a diagram illustrating an example of how an RFID tag is used. [Figure 20] FIG. 10 is a diagram showing an equivalent circuit diagram used in a simulation and the results thereof. [Figure 21] Characteristics of a transistor including an oxide semiconductor [Figure 22] FIG. 10 is a circuit diagram for evaluating characteristics of a transistor including an oxide semiconductor. [Figure 23] 10 is a timing chart for evaluating characteristics of a transistor including an oxide semiconductor; [Figure 24]10A and 10B are graphs showing characteristics of a transistor including an oxide semiconductor; [Figure 25] 10A and 10B are graphs showing characteristics of a transistor including an oxide semiconductor; [Figure 26] 10A and 10B are graphs showing characteristics of a transistor including an oxide semiconductor; DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to the above embodiments and details, and may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made thereto. The present invention is not limited to the following description of the embodiments. In describing the configuration of the present invention, the same reference numerals will be used in common among different drawings. do.

[0024] The size, layer thickness, or area of each component shown in the drawings of each embodiment is The figures may be exaggerated for clarity and are not necessarily limited to the scale. Not determined.

[0025] In this specification, terms using ordinal numbers such as first, second, and third are used to identify components. This is added for convenience of distinguishing between them and does not limit the number.

[0026] Voltage is the difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is possible to do this.

[0027] The source electrode and the drain electrode of the transistor are both connected to the semiconductor layer. When a voltage is applied to the gate electrode, the potential between the source electrode and the drain electrode The source and drain electrodes are switched depending on the operation, so that current flows according to the difference. Therefore, when explaining the structure of a transistor, In this case, they are called the source electrode and the drain electrode. These electrodes are also called the first electrode and the second electrode. There is no particular difference in meaning depending on how it is used.

[0028] (Embodiment 1) In this embodiment, a configuration of a semiconductor memory device according to one embodiment of the present invention will be described with reference to drawings. In this embodiment, an n-type transistor (n The following explains the case where a N-channel transistor is used instead of an N-type transistor. It goes without saying that a p-type transistor with holes as the majority carrier can be used. .

[0029] FIG. 1 illustrates a memory element according to one embodiment of the present invention. A memory element 101 illustrated in FIG. 1A includes: The transistor 102, the transistor 103, and the capacitor 104 are connected in diode connection. The gate of the transistor 103 is connected to the capacitor 104 and the first electrode of the transistor 102. The second electrode and the gate of the transistor 102 are connected together. The gate of the transistor 103, the first electrode of the capacitor 104, and the The connection region of the first electrode is node A, and the connection region of the second electrode and gate of the transistor 102 is node B. The next region is called node B.

[0030] In the memory element described in this embodiment, the first electrode of the diode-connected transistor 102 serves as the anode. The channel region is formed of an oxide semiconductor. The transistor 102 has a low off-state current. The gate and the second electrode of the transistor 102 are connected to each other. When the transistor is in the ON state, current flows from node B to node A, but when the transistor is in the OFF state, current flows from node A to node B. The current flowing to node B is extremely small.

[0031] Here, in the memory element 101, the potential of the node A is low (i.e., the potential of the transistor 103 The state where the potential of the node A is high (that is, the transistor 103 is turned on) is data 0. The state in which the

[0032] The diode-connected transistor 102 is turned on, and the transistor By charging the transistor 103 to a voltage higher than the threshold voltage, the transistor 103 is turned on. By applying a voltage to node A that results in a write state, data 1 is written to the memory element 101. This can be done.

[0033] On the other hand, after the data writing is completed, the transistor 102 is turned off. Even if the potential of the node B, to which the gate and the second electrode of the transistor 102 are connected, decreases, the transistor 102 Since the off-state current of the transistor 102 is extremely low and the transistor 102 is diode-connected, Current does not flow easily from the first electrode to the second electrode. Therefore, the voltage charged at node A is The voltage at node A can be maintained for a long period without being reduced. (Data 1) cannot be rewritten, and the memory element 101 operates essentially as a write-once memory. The capacitance of the capacitor 104 is set to a value that corresponds to the required data retention time. Design appropriately accordingly.

[0034] The first electrode or the second electrode of the transistor 103 and the diode-connected transistor When a parasitic capacitance is formed at the first electrode of the resistor 102, the capacitance element 1 In this case, the memory element is a diode as shown in FIG. The transistor 102 and the transistor 103 are gate-connected. The gate is connected to the first electrode of the transistor 102. The electrode and the gate are connected.

[0035] Next, a memory cell having the memory element shown in FIG. 1(A) arranged in a matrix is used. The configuration of the array is shown in FIGS.

[0036] FIG. 2A is a diagram showing one form of a NOR type memory cell array.

[0037] The memory cell 110 has a memory element 111, and a gate connected to a write word line WL1. The first electrode is connected to the memory element 111, and the second electrode is connected to the write bit line BL1. The gate of the transistor 115 is connected to the read word line WL2, and the first electrode of the transistor 115 is connected to the read word line WL3. A transistor 1 is connected to the read bit line BL2 and has a second electrode connected to the memory element 111. The transistor 115 functions as a select transistor for writing. The transistor 116 functions as a select transistor for reading.

[0038] The memory element 111 includes a diode-connected transistor 112, a transistor 113, and a and a capacitor 114. A second electrode of the transistor 112 is connected to the gate. The gate of transistor 113 is connected to the first electrode of transistor 115. A first electrode of the element 114 is connected to a first electrode of the transistor 112. The first electrode of transistor 113 is connected to the second electrode of transistor 116, and the second electrode of transistor 117 is connected to the first electrode of transistor 118. A second electrode of the capacitor 13 is at a fixed potential. A second electrode of the capacitor 114 is at a fixed potential.

[0039] FIG. 2(B) is a diagram showing a form of a NOR type memory cell array different from that shown in FIG. 2(A). be.

[0040] The memory cell 130 has a memory element 131, whose gate is connected to a write word line WL1, The first electrode is connected to the memory element 131, and the second electrode is connected to the write bit line BL1. The transistor 135 is a select transistor for writing. It functions as such.

[0041] The memory element 131 includes a diode-connected transistor 132, a transistor 133, and a and a capacitor 134. A second electrode of the transistor 132 is connected to the gate and The gate of transistor 133 is connected to the first electrode of transistor 135. A first electrode of the element 134 is connected to a first electrode of the transistor 132. The first electrode of the resistor 133 is connected to the read bit line BL2, and the second electrode is connected to a fixed voltage. A second electrode of the capacitor 134 is connected to a read word line WL2.

[0042] FIG. 3 is a diagram showing one form of a NAND type memory cell array.

[0043] The memory cell 120 has a memory element 121, a gate connected to a write word line WL, and a The first electrode is connected to the memory element 121, and the second electrode is connected to the write bit line BL. The transistor 125 functions as a selection transistor for writing. It works.

[0044] The memory element 121 includes a diode-connected transistor 122, a transistor 123, and a and a capacitor 124. A second electrode of the transistor 122 is connected to the gate and The gate of transistor 123 is connected to the first electrode of transistor 125. The first electrode of the element 124 is connected to the first electrode of the transistor 122. The first electrode of the transistor 123 is connected to the data line DL for reading, and the third electrode of the transistor 123 is connected to the data line DL for reading. The second electrode of the capacitor 124 is connected to the first electrode of the transistor 123 in the next column. The electrodes are at a fixed potential.

[0045] The channel regions of the diode-connected transistors 112, 122, and 132 are made of oxide semiconductor The transistors 112, 122, and 132 each having an oxide semiconductor in a channel region are formed of The transistors 112, 122, and 132 are diode-connected. The gate and the second electrode are connected. When 132 is in the ON state, current flows from node B to node A, but when it is in the OFF state, There is very little current flowing from node A to node B.

[0046] Channel regions of transistors 113, 115, 116, 123, 125, 133, and 135 an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single crystal silicon layer Also, diode-connected transistors 112, 122, and 13 As with 2, it may be formed of an oxide semiconductor.

[0047] In the semiconductor memory device described in this embodiment, the channel of the diode-connected first transistor By forming the insulating layer using an oxide semiconductor, -19 A / μm or less, and even 1×10 -20 This allows the off-state current to be reduced to less than A / μm. The potential of the gate of the second transistor and the capacitance element, which has risen due to the load, is The first transistor is less likely to leak current, and the gate potential of the second transistor is maintained. In other words, data that has been written once can be retained.

[0048] The data write voltage is a voltage that can turn on the second transistor, i.e., It is possible to set the threshold voltage of the transistor or higher, thereby reducing the write voltage. In addition, it is not necessary to provide a boost circuit for the write voltage, and the power consumption during writing is It is possible to reduce the stress, and also to increase the channel length to increase the breakdown voltage and to Since the formation of the region is not required, the memory element can be reduced in size and can be highly integrated.

[0049] The write time of the semiconductor memory device shown in this embodiment is The on-current of the first transistor is determined by the on-current of the second transistor and the capacitance of the capacitor. 0 -6A. Even if the capacitance of the capacitive element is 1 pF, writing is completed in about 1 μs. It is also possible to write to multiple memory elements simultaneously. can be significantly reduced.

[0050] The memory cells included in the semiconductor memory device shown in this embodiment are write-once memory cells. Therefore, data rewriting due to malfunction of the logic circuit does not occur. This can improve the security of data retention in the semiconductor memory device.

[0051] Note that the memory cell and the memory cell array described in this embodiment are just one example. This does not limit the composition.

[0052] (Embodiment 2) In this embodiment, the data writing and reading of the semiconductor memory device shown in the first embodiment is performed. This will be explained with reference to the drawings.

[0053] Regarding the writing of data into the NOR type memory cell 110 shown in FIG. 2(A), FIG. This will be used to explain.

[0054] First, the write bit line BL1 and the write bit line BL2 connected to the memory cell 110 to be written are A first potential is applied to the word line WL1, and a second potential is applied to the bit line BL2 for reading and the word line WL3 for reading. The first potential is used to turn on the transistors 113 and 115. This is a potential higher than the threshold voltage of the transistors 113 and 115, which is 2V in this case. Let's say.

[0055] When the potential of the write word line WL1 becomes the first potential, the write select transistor Transistor 115 acting as a diode and transistor 112 connected as a diode is turned on, and the potential of the node A, that is, the potential of the capacitor 114 and the gate of the transistor 113, is written. The potential rises to approximately the same as that of the reserved bit line BL1, and the transistor 113 turns on. Data 1 can be written by the above process.

[0056] In writing data 1, the node A is charged with enough charge to turn on the transistor 113. Since the write voltage is only required, a booster circuit for writing is not required. A voltage is supplied from the power supply to the logic circuit that drives the rechargeable cell 110. , the time is sufficient to charge the capacitor 104, so that the transistors 112 and 115 On-current of 10 -6 A, when the capacitance of the capacitance element 114 is 1 pF, a short time of about 1 μs The writing ends between them.

[0057] After the write operation is completed, the write bit line BL1 and the write word line BL2 are connected as shown in FIG. 4(B). The potential of WL1 is set to 0V. This allows the transistor to function as a select transistor for writing. The transistor 115 and the diode-connected transistor 112 are turned off, but the oxide The off-state current of the transistor 112 formed using a semiconductor is very small. Specifically, a transistor formed using an oxide semiconductor The off-state current of 112 is 1×10 -19 A / μm or less, even 1×10 -20 A / μm or less Therefore, if a capacitance of 1 pF is added to the capacitance element 114, data can be stored for 20 to 200 days. The memory element 111 can store data, and functions as a write-once memory. Here, "holding data" means that the potential of the capacitor 114 is the potential at the time of writing data 1. This refers to a state in which the voltage is 90% or more of the reference voltage, i.e., 1.8V or more.

[0058] Next, reading data from the memory cell 110 shown in FIG. 2(A) will be explained with reference to FIG. FIG. 5(A) shows how to read data 1, and FIG. 5(B) shows how to read data 0. To read data, the potential of the read word line WL2 is changed. The transistor 116 that functions as the selection transistor for the bit line B The output of the read circuit 117 is determined according to the voltage of L2. The bit line BL1 and the write word line WL1 are set to the ground potential, and the transistors 112 and 113 are set to the ground potential. 15 is in the off state.

[0059] When reading data 1, as shown in FIG. 5(A), the read word belonging to the column to be read is A second potential is applied to the read line WL2 to turn on the transistor 116. A third potential, which is a negative potential, is applied to the read word line WL2 belonging to the column for which no read operation is to be performed. The potential of the second transistor 116 is a potential that turns the transistor 116 on, and the threshold voltage of the transistor 116 is In this case, the potential is set to 2V. In the case of data 1, the transistor 113 is turned on. Therefore, the output of the read circuit 117 is determined by the on-resistance of the transistor 113 and the The ratio of the sum of the on-resistances of the transistors 116 to the resistance (denoted as R1) included in the readout circuit 117. Here, the resistor R1 in the read circuit is determined by the on-resistance of the transistor 113. By making the resistance larger than the sum of the on-resistance of the resistor and the transistor 116, The potential at node C of the read line BL2 is approximately 0V. The signal is inverted by an inverter 118 included in a circuit 117 and output as data 1.

[0060] When reading data 0, as shown in FIG. 5B, a second voltage is applied to the read word line WL2. When data is 0, transistor 113 is turned on. Since the transistor 113 is turned off, the output of the read circuit 117 is The sum of the on-resistances of the resistors 116 and R1 included in the readout circuit 117 is compared. Here, the resistor R1 included in the read circuit 117 is set to ON when the transistor 113 is turned OFF. By making it smaller than the sum of the resistance and the on-resistance of the transistor 116, The potential at node C of bit line BL2 is set to approximately 2V by the read circuit 117. The potential is inverted by an inverter 118 included in the read circuit 117, and is set as data 0. and output.

[0061] In the memory cells belonging to the columns where reading is not performed, the read word line WL2 is negative. The third potential is applied to the transistor 116, which is a potential of the transistor 116 in the off state. The potential is a negative potential lower than the threshold voltage of the transistor 116, which is −2 V in this example. The transistor 116 is turned off. Therefore, the data of the memory cells not selected for reading is There is no risk of data being read out.

[0062] Next, the data write operation of the NOR type memory cell 130 shown in FIG. 2(B) in the first embodiment will be described. The following describes the operation of reading and writing using the drawings.

[0063] First, the writing of data into the NOR type memory cell 130 shown in FIG. 2(B) will be described. 6 will be used to explain.

[0064] First, the write bit line BL1 and the write bit line BL2 belonging to the memory cell 130 to be written are A first potential is applied to the word line WL1, and the read word line WL2 is set to the ground potential. The first potential is a potential that turns on the transistors 133 and 135. The potential is set to be higher than the threshold voltage of 133 and 135, which is 2V in this example.

[0065] The write word line WL1 and the write bit line BL1 are set to the first potential. This turns on transistor 135, turns on diode-connected transistor 132, and turns on The charge is charged in the node A, that is, the capacitor element 134 and the gate of the transistor 133, and the write The potential rises to approximately the same as that of the bit line BL1, and the transistor 133 turns on. Data 1 can be written by this process.

[0066] After the write operation is completed, the potential of the write bit line BL1 and the write word line WL1 is set to 0V. This allows the transistor 135, which functions as a select transistor for writing, and The diode-connected transistor 132 is turned off. Since the off-state current of the transistor 132 is very small, the voltage of the node A is maintained for a long period of time. As a result, the memory element 131 functions as a write-once memory.

[0067] Next, the reading of data from the memory cell 130 shown in FIG. 2B will be described with reference to FIG. FIG. 7(A) shows how to read data 1, and FIG. 7(B) shows how to read data 0. To read data, the potential of the read word line WL2 is changed. Reading is performed according to the voltage on bit line BL2.

[0068] When reading data 1, as shown in FIG. 7(A), the read word belonging to the column to be read is The read word line WL2 is set to the ground potential, and the other read word lines WL2 are set to the third potential, which is a negative potential. Let the potential be

[0069] The memory cell 130 to be read stores data 1, that is, the capacitance element 134 of the memory cell 130 stores the first When the voltage of 1 is charged, the transistor 133 turns on and the read bit line BL The potential at node C of the read circuit 11 is approximately 0V. 7, and is output as data 1.

[0070] When reading data 0, as shown in FIG. 7(B), the read word belonging to the column to be read is The read word line WL2 is set to the ground potential, and the other read word lines WL2 are set to the third potential, which is a negative potential. Let the potential be

[0071] When the memory cell 130 to be read has data 0, that is, when the capacitance element 13 of the memory cell 130 If no charge is stored in the bit 4, the transistor 133 is turned off, and the bit 4 for reading is The potential at node C of the output line BL2 is set to approximately 2V by the read circuit 117. The value is inverted by an inverter included in the read circuit 117 and output as data 0. can be.

[0072] A negative potential is applied to the read word line WL2 of the memory cell belonging to the column where reading is not performed. The potential of the capacitor 134 of the memory cell is stored in the node A. The third potential is added to the potential stored in the memory. The potential of the capacitor 134 of the recell drops, and regardless of the data written to the memory cell, The transistor 133 is turned off. Therefore, the data of the unselected memory cells is read out. There is no risk of this happening.

[0073] Next, the data writing to the NAND type memory cell 120 shown in FIG. 3 in the first embodiment will be described. The reading and writing will be explained with reference to the drawings.

[0074] The writing of data into the NAND type memory cell 120 shown in FIG. 3 will be described with reference to FIG. 8. do.

[0075] First, the first bit line BL and the word line WL belonging to the memory cell 120 to be written are connected to the bit line BL and the word line WL. The first potential is a potential that turns on the transistors 123 and 125. In addition, in the capacitor 124, the second transistor not connected to the transistors 123 and 125 The electrode is at ground potential.

[0076] When the write word line WL is at a first potential, the transistor 125 is turned on. The diode-connected transistor 122 turns on, and the node A, i.e., the capacitor 124 and the transistor The potential of the gate of the transistor 123 rises to approximately the same potential as the write bit line BL, The transistor 123 is turned on. Data 1 can be written by the above steps.

[0077] After the write operation is completed, the potential of the write bit line BL is set to 0V. The transistor 125 acting as a select transistor and the diode-connected transistor The transistor 122 formed using an oxide semiconductor is turned off. Because the current is very small, the potential at node A is maintained for a long period of time. 21 functions as a write-once memory.

[0078] Next, reading data from the memory cell 120 shown in FIG. 3 will be described with reference to FIG. Figure 9(A) shows how to read data 1, and Figure 9(B) shows how to read data 0. The data is read from all memory cells connected to a certain bit line, that is, the area surrounded by the region 129. In the capacitor 124 included in the memory cell 120, the transistor 123 is connected to the This is done by applying a voltage to the second electrode of the memory cell belonging to the column to be read. A ground potential is applied to the second electrode of the capacitance element 124, and the other regions 129 A fourth potential is applied to the second electrode of the capacitance element 124 of the memory cell, and the read bit line BL The output of the read circuit 117 is determined according to the voltage of the fourth potential. The fourth potential is a potential higher than the threshold voltage of the first potential, and here, the fourth potential is set to 2V.

[0079] When reading data 1, as shown in FIG. 9A, the capacitance element of the memory cell from which data is read is A charge is stored in the capacitor 124, and a first potential is applied to the first electrode. By connecting the second electrode of the element 124 to the ground potential, the transistor 123 is turned on. In the region 129, the second electrode of the capacitance element 124 of the memory cell from which reading is not performed is connected to the first electrode. By applying the potential of the capacitor 124 to the capacitor 124, the potential of the first electrode of the capacitor 124 is increased. The transistor 123 is turned on. As a result, the transistor 123 connected to the data line DL All of them are turned on, and the potential of node C on the data line DL becomes 0V. The potential at is inverted by an inverter included in the read circuit 117 and is output as data 1. and output.

[0080] When reading data 0, as shown in FIG. 9B, the capacity of the memory cell 120 from which data is read is The first electrode of the capacitance element 124 is at 0V. On the other hand, the memory cells in the area 129 that are not being read are By applying a fourth potential to the second electrode of the capacitor 124, the first The potential of the electrode is boosted, turning on transistor 123. As a result, The potential at node C of DL is brought to approximately 2V by the read circuit 117 .

[0081] According to this embodiment, a high voltage is not required for writing, defects are unlikely to occur, and writing Therefore, it is possible to provide a semiconductor memory device in which the time is short and data cannot be rewritten.

[0082] (Embodiment 3) In this embodiment, one mode of the semiconductor memory device shown in Embodiment 1 and Embodiment 2 will be described. The following description will be given with reference to the drawings.

[0083] FIG. 10A is an example of a semiconductor memory device having the memory cell array shown in the first embodiment. The semiconductor memory device 300 includes a memory cell array 301, a column decoder 302, a row decoder 303, and a The memory cell array 301 includes a matrix memory cell 303 and an interface circuit 304. It has a plurality of memory cells 305 arranged in a square shape.

[0084] The interface circuit 304 receives an external signal from the column decoder 302 and the row decoder 303. 03 and transmits the data read from the memory cell 305 to an external device. Output to.

[0085] The column decoder 302 drives the memory cells 305 from the interface circuit 304. and generates a signal to be sent to the bit line for writing or reading. The row decoder 303 drives the memory cells 305 from the interface circuit 304. and generates a signal to send to the word line for writing or reading. The column decoder 302 outputs a signal to the bit line, and the row decoder 303 outputs a signal to the word line. The memory cell array 301 is accessed by a signal output to the corresponding line. The cell is uniquely determined.

[0086] As shown in FIG. 10B, the write-once method shown in the first and second embodiments A semiconductor memory device having a memory cell array in which a rewritable memory and a non-rewritable memory are mixed is provided. The semiconductor memory device 310 shown in FIG. array 311, second memory cell array 312, column decoder 302, row decoder 3 03, an interface circuit 304, and the first memory cell array 311 includes The memory cell 313 having the write-once memory element shown in the first and second embodiments is a matrix. The second memory cell array 312 is arranged in a row, and a rewritable memory element is Memory cells 314 having the same structure are arranged in a matrix.

[0087] The rewritable memory element is a write-once memory shown in the first and second embodiments. It is possible to fabricate the rewritable memory element using the same process. This will be explained with reference to FIG. 11(A) and FIG. 11(B).

[0088] FIG. 11(A) shows a memory cell and a memory cell having a NOR type rewritable memory element. The memory cell 400 has a memory element 401 and a gate for writing data. The first electrode is connected to the write word line WL1, the second electrode is connected to the memory element 401, and the third electrode is connected to the write word line WL2. A transistor 402 connected to a read bit line BL1 and a transistor 403 connected to a read word line WL2 , the first electrode is connected to the read bit line BL2, and the second electrode is connected to the memory element 40 The transistor 406 is connected to the select transistor for reading. It functions as a transistor.

[0089] The memory element 401 includes a transistor 403 and a capacitor 404. The gate of the transistor 403 is connected to a first electrode of the capacitor 404 and a first electrode of the transistor 402. The first electrode of the transistor 403 is connected to the second electrode of the transistor 406. The second electrode of the capacitor 404 is connected to a fixed potential. The poles are at a fixed potential.

[0090] The transistor 402 includes an oxide semiconductor, similar to the transistor 102 described in Embodiment 1. The transistors 403 and 406 are manufactured using the same transistor 10 described in Embodiment 1. It can be prepared in the same manner as in 3.

[0091] Regarding the writing of data into the NOR type memory cell 400 shown in FIG. 11(A), FIG. 12 is used. FIG. 12(A) shows how to write data 1, and FIG. 12(B) shows how to write data 0. This shows how to do it.

[0092] When writing data 1, as shown in FIG. 12(A), A first potential is applied to the connected write bit line BL1 and write word line WL1. The first potential is applied to the transistor 402, and the read word line WL2 is set to the ground potential. 403 is turned on, and is higher than the threshold voltage of the transistors 402 and 403. Here, let's assume it's 2V.

[0093] When the potential of the write word line WL1 becomes the first potential, the transistor 402 is turned on, and the potential of the node A, that is, the potential of the capacitor 404 and the gate of the transistor 403, is written. The potential rises to approximately the same as that of the reserved bit line BL1, and the transistor 403 turns on. Data 1 can be written by the above process.

[0094] When writing data 0, as shown in FIG. 12(B), The connected write bit line BL1 is set to the ground potential, and the write word line WL1 is set to the first potential. The first potential is applied to the word line WL2 for reading, and the second potential is applied to the word line WL3 for reading. This potential is higher than the threshold voltage of the transistor 402. Here we will use 2V.

[0095] When the potential of the write word line WL1 becomes the first potential, the transistor 402 is turned on, and the potential of the node A, that is, the capacitance element 404 and the gate of the transistor 403, is set to the ground potential. The potential of the write bit line BL1 drops to the potential of the write bit line BL1. The data is turned off and data 0 can be written. Therefore, during the write period, the read word line WL2 is set to the ground potential, and the transistor 406 Turn off the.

[0096] Next, the data read from the memory cell 400 shown in FIG. 11(A) will be explained using FIG. FIG. 13(A) shows how to read data 1, and FIG. 13(B) shows how to read data 0. The data is read by changing the potential of the read word line WL2. The transistor 406, which functions as a select transistor for reading, is turned on, and the read bias The output of the read circuit 117 is determined according to the voltage of the bit line BL2.

[0097] When reading data 1, as shown in FIG. 13(A), the readout data belonging to the column to be read out is A second potential is applied to the word line WL2, turning on the transistor 406. In this case, the transistor 403 is turned on, and therefore the NOR type transistor shown in FIG. 2A of Embodiment 2 is turned on. As in the read method of (1), the node C of the read bit line BL2 is at the ground potential. The potential at is inverted by an inverter included in the read circuit 117, and the data 1 and and output.

[0098] When reading data 0, as shown in FIG. 13(B), the second When data is 0, a potential is applied to turn on transistor 406. Since the read circuit 117 is turned off, the read bit line BL2 is set to approximately 2V. The potential is inverted by an inverter included in the read circuit 117, and is set to data 0. and output.

[0099] In the memory cells of the column where reading is not performed, a negative potential is applied to the read word line WL2. The third potential is applied to the transistor 406. The potential is a negative potential lower than the threshold voltage of the transistor 406, which is −2 V in this example. The transistor 406 is turned off. Therefore, the data of the memory cells that are not selected for reading is read. There is no risk of it being leaked.

[0100] FIG. 11(B) has a NOR type rewritable memory element different from that of FIG. 11(A). 11(B) is a diagram showing a memory cell. The memory cell shown in FIG. 11(B) is the same as the memory cell shown in FIG. The transistor 405 is arranged between the transistor 402 and the write bit line BL1. This configuration is the same as that of the first embodiment except that the gate connection of the transistor 112 is changed. The gate is simply connected to the write word line WL1. A slight change in the lines can transform a write-once memory into a rewritable memory or vice versa. The data writing and reading methods are shown in FIG. ) and therefore omitted.

[0101] In this embodiment, the write-once memory element and the rewritable memory element are NOR Although the type is shown, the NAND type can be used as appropriate.

[0102] In this way, write-once memory and rewritable memory are mounted on the same semiconductor storage device. The rewritable memory can be the same as that shown in the first and second embodiments. It can be fabricated using the same process as write-once memory and is compatible with logic signals. Regardless of the operation, the write-once memory is a rewritable memory. The memory can be treated as a rewritable memory. It is possible to provide a semiconductor memory device in which data rewriting does not occur in principle due to operation. This becomes:

[0103] (Fourth embodiment) In this embodiment mode, the configuration of the semiconductor memory device shown in any of Embodiments 1 to 3 and its The manufacturing method will be described with reference to FIGS.

[0104] In this embodiment mode, a top view and a cross-sectional view of the structure of the semiconductor memory device shown in Embodiment 1 are shown. The following description will be given using the drawings, but it can be applied to the second and third embodiments as appropriate.

[0105] FIG. 14 is one mode of a top view of the memory cell 110 in the semiconductor memory device described in Embodiment 1. 15 shows cross-sectional views taken along lines AB, CD, and EF in FIG.

[0106] The transistor 502 illustrated in FIG. 14 corresponds to the transistor 113 illustrated in FIG. The transistor 503 corresponds to the transistor 116 shown in FIG. 2A and is diode-connected. The transistor 505 corresponds to the diode-connected transistor 112 shown in FIG. The transistor 506 corresponds to the transistor 115 shown in FIG. The capacitor 504 corresponds to the capacitor 114 shown in FIG.

[0107] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can also be used. The technical essence of the present invention is that the channel region of the diode-connected transistor 505 is made of an oxide. Since the semiconductor memory device is formed of a nitride semiconductor layer, the specific configuration of the semiconductor memory device is not shown here. However, there is no need to limit it to this.

[0108] As shown in FIG. 15, a transistor is formed on an insulating layer 510 and an insulating layer 512 stacked on a substrate 508. A transistor 502 and a capacitor 504 are provided, and insulating layers 510 and 512 are stacked. The transistor 505 is provided over the insulating layer 536 , the insulating layer 538 , and the insulating layer 540 .

[0109] The semiconductor memory device shown in this embodiment has a transistor 502 and a transistor 503 in the lower part. (not shown), a capacitor 504, and a transistor 506 (not shown), The upper part of the transistor 505 is connected to a diode. It may be provided on the upper part instead of on the lower part.

[0110] The transistor 502 includes a semiconductor layer 519 formed over the insulating layer 512 and a semiconductor layer 519 a gate insulating layer 522 formed on the gate electrode 521; 26 and wirings 534a and 534b electrically connected to the semiconductor layer 519. The layer 519 is a low concentration layer provided to sandwich the channel region 514. The impurity region 516 and the high-concentration impurity region 518 (collectively referred to simply as the impurity region) It consists of:

[0111] Here, a sidewall insulating layer 530 is provided on the side surface of the gate electrode 526. In addition, the low-concentration impurity region 516 overlaps with the sidewall insulating layer 530 .

[0112] The capacitor element 504 is a semiconductor layer formed on an insulating layer 512 and configured as a high-concentration impurity region. 520, a gate insulating layer 524 provided on the semiconductor layer 520, and a gate insulating layer 524 a capacitor electrode 528 provided on the semiconductor layer 520; a wiring 534c electrically connected to the semiconductor layer 520; The capacitor electrode 528 has a wiring 534b connected to it. A sidewall insulating layer 532 is provided.

[0113] The insulating layer 536, the insulating layer 538, and the insulating layer 539 are formed to cover the transistor 502 and the capacitor 504. An insulating layer 540 is provided.

[0114] The diode-connected transistor 505 is connected to the wiring 534c and the and an oxide semiconductor layer 542 electrically connected to the wiring 534c and the wiring 534d. 534d, and a gate insulating layer 544 covering the oxide semiconductor layer 542; a gate electrode 546a provided over the oxide semiconductor layer 542 so as to overlap with the oxide semiconductor layer 542; The gate electrode 546a seals the opening formed in the gate insulating layer 544. By electrically connecting to the line 534d, it is diode-connected.

[0115] An insulating layer 552 and an insulating layer 554 are provided to cover the transistor 505 .

[0116] 14, the wiring 546b functioning as the ground wiring is formed on the gate insulating layer 54 4, the wiring 534a of the transistor 502 is electrically connected to the wiring 534a. Since the capacitor electrode 528 is electrically connected to the wiring 534a, the capacitance of the capacitor 504 The electrode 528 is electrically connected to the wiring 546b.

[0117] The wiring 534a is connected through openings formed in the insulating layers 536, 538, and 540. 518 and the capacitor electrode 528 of the capacitor element 504. The wiring 534b is formed through openings formed in the insulating layers 536, 538, and 540. The wiring 534c is electrically connected to the high concentration impurity region 518 through the insulating layer 536, the insulating layer 538, and the insulating layer 540 through the openings formed in the insulating layer 540. The semiconductor layer 520 and the gate electrode 526 of the transistor 502 (see FIG. 14) are connected to each other. are electrically connected.

[0118] 14, the wiring 534d is formed by insulating layers 536, 538 and 539. 40 is electrically connected to the high concentration impurity region of the transistor 506 through the opening formed in the and is electrically connected to the oxide semiconductor layer 542 of the transistor 505. The wire 534e is connected through openings formed in the insulating layers 536, 538 and 540. , is electrically connected to the high-concentration impurity region of the transistor 506. Through openings formed in insulating layers 536, 538, and 540, a transistor It is electrically connected to the high concentration impurity region 503.

[0119] The substrate 508 is a substrate that has at least a heat resistance sufficient to withstand the subsequent heat treatment. When a glass substrate is used as the substrate 508, the strain point is 730° C. or higher. For the glass substrate, for example, aluminosilicate glass, Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. It is preferable to use a glass substrate containing more BaO than B2O3.

[0120] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material can be used. Alternatively, a substrate made of crystallized glass can be used. In addition, the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material may be insulated. A substrate having an insulating layer formed thereon can also be used. A plastic substrate can also be used. When a plastic substrate is used as the substrate 508, the substrate 508 and the insulating layer 51 An adhesive may be provided between the 0.

[0121] The insulating layer 510 is preferably formed of a nitride insulating layer, and the insulating layer 512 is preferably formed of an oxide insulating layer. The nitride insulating layer is preferably formed of a silicon nitride layer, a silicon nitride oxide layer, a nitride Examples of oxide insulating layers include a silicon oxide layer and a silicon oxynitride layer. , aluminum oxide layer, etc.

[0122] The semiconductor layer 519 of the transistor 502 and the high-concentration impurity semiconductor of the capacitor 504 The semiconductor layer 520 may be an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a monocrystalline silicon layer. It is possible to form the gate insulating film by using a single crystal silicon layer for the channel region. Examples of such transistors include a transistor using a single crystal semiconductor substrate for a channel region, A single-crystal silicon layer that becomes the channel region is formed on an insulating region, so-called SOI (Si A transistor using a silicon-on-insulator (SiC) substrate can be used. In addition, a diode-connected transistor 502 is connected to the semiconductor layer 519 of the transistor 502. An oxide semiconductor layer similar to the oxide semiconductor layer described in 05 may be formed.

[0123] The gate insulating layer 522 and the gate insulating layer 524 may be a silicon oxide layer, a silicon nitride layer, an oxide layer, or the like. A silicon nitride layer, a silicon nitride oxide layer, or an aluminum oxide layer may be formed as a single layer or a stacked layer. It can be formed as follows.

[0124] The gate insulating layer 522 and the gate insulating layer 524 are made of hafnium silicate (HfSi O x ), nitrogen-doped hafnium silicate (HfSi x O y N z ), nitrogen added Hafnium aluminate (HfAl x O y N z ), hafnium oxide, yttrium oxide By using high-k materials such as silicon, gate leakage current can be reduced. High-k materials and silicon oxide layers, silicon nitride layers, silicon oxynitride layers, and silicon nitride oxide layers It can have a laminated structure with one or more of a silicon layer or an aluminum oxide layer. The thickness of the gate insulating layer 522 and the gate insulating layer 524 is 10 nm or more and 300 nm or less. It can be said that:

[0125] The gate electrode 526 and the capacitor electrode 528 are made of aluminum, chromium, copper, tantalum, or titanium. a metal element selected from the group consisting of molybdenum, tungsten, and the like, or a material containing the above-mentioned metal element as a component. The metal layer can be formed by using an alloy of the above metal elements or an alloy combining the above metal elements. Also, one or more of manganese, magnesium, zirconium, and beryllium may be selected. The gate electrode 526 and the capacitor electrode 528 may be formed of a single layer. For example, a silicon-containing aluminum layer may be formed. Single layer structure, double layer structure with titanium layer laminated on aluminum layer, titanium layer on titanium nitride layer a two-layer structure in which a tungsten layer is laminated on a titanium nitride layer; Two-layer structure with a tungsten layer on a titanium layer, and an aluminum layer on the titanium layer. There are also three-layer structures, such as a laminated aluminum layer and a titanium layer on top of that. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium A layer of an element selected from the group consisting of fluorine, an alloy layer made up of multiple elements, or a nitride layer may be used. good.

[0126] The gate electrode 526 and the capacitor electrode 528 are made of indium tin oxide and tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide, titanium oxide, indium tin oxide, indium zinc oxide, By using a conductive material with light transmission, such as indium tin oxide with added silicon oxide, Furthermore, it is possible to form a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element. It can also be done as follows.

[0127] The sidewall insulating layer 530 and the sidewall insulating layer 532 are formed on the gate insulating layer 522 and the The insulating layer 524 can be formed using a material similar to that of the gate insulating layer 524. In addition, there are cases where the sidewall insulating layer is not formed due to the integration of capacitance elements.

[0128] The insulating layer 536 and the insulating layer 540 are formed in the same manner as the gate insulating layer 522 and the gate insulating layer 524. The insulating layer 538 can be formed using an organic resin layer. Examples of the organic resin layer include acrylic, epoxy, polyimide, polyamide, and polyvinyl fluoride. Also, siloxane polymers such as phenol and benzocyclobutene can be used. It can be used.

[0129] The wirings 534a to 534f are made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or the like. a metal element selected from the group consisting of buten and tungsten, an alloy containing the above-mentioned metal element, or The metal layer can be formed by using an alloy that combines the above-mentioned metal elements. One or more selected from the group consisting of gun, magnesium, zirconium, and beryllium A metal element may be used. The wirings 534a to 534f may have a single-layer structure or a double-layer structure. For example, a single layer structure of an aluminum layer containing silicon, Two-layer structure with titanium layer laminated on aluminum layer, two-layer structure with titanium layer laminated on titanium nitride layer Two-layer structure: a tungsten layer on a titanium nitride layer; a tungsten layer on a tantalum nitride layer A two-layer structure with a stainless steel layer, a titanium layer, and an aluminum layer on top of that titanium layer. There are also three-layer structures, such as aluminum with a titanium layer on top. , selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium A layer of an element, an alloy layer of a combination of elements, or a nitride layer may be used.

[0130] The wirings 534a to 534f contain indium tin oxide or tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, ketone oxide It is also possible to use a conductive material with light transmission, such as indium tin oxide doped with indium. Furthermore, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element may also be used. Cut.

[0131] The transistor 505 and the transistor 506 have the same configuration as the transistor 502. It can be said that:

[0132] The oxide semiconductor layer 542 is an In—Sn—Ga—Zn—O-based metal oxide, which is a quaternary metal oxide. oxides, and ternary metal oxides such as In-Ga-Zn-O and In-Sn-Zn -O metal oxides, In-Al-Zn-O metal oxides, Sn-Ga-Zn-O metal acids oxides, Al-Ga-Zn-O metal oxides, Sn-Al-Zn-O metal oxides, and binary In-Zn-O based metal oxides, Sn-Zn-O based metal oxides, Al- Zn-O metal oxide, Zn-Mg-O metal oxide, Sn-Mg-O metal oxide, I n-Mg-O based metal oxides can be used. Here, n-based metal oxides are n The oxide semiconductor layer is made of metal oxides of various kinds. Elements other than the metal oxides may be contained in an amount of 1% or less, preferably 0.1% or less.

[0133] The oxide semiconductor layer 542 is a ternary metal oxide, and is made of InM X Zn Y O Z (Y=0 Metal oxides expressed by the formula (1.5-5) may also be used, where M is gallium (Ga) or One or more elements selected from Group 13 elements such as aluminum (Al) and boron (B) The contents of In, M, Zn, and O are optional, and the content of M is zero. (i.e., x=0). On the other hand, the contents of In and Zn are not zero. The above notation includes In-Ga-Zn-O based metal oxides and In-Zn-O based metal oxides. This includes:

[0134] The metal oxide forming the oxide semiconductor layer 542 has an energy gap of 2 eV or more. , preferably 2.5 eV or more, and more preferably 3 eV or more.

[0135] The oxide semiconductor layer 542 has an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a single-crystalline structure. In addition, a crystal with its c-axis nearly parallel to the direction perpendicular to the surface can be used. An oxide semiconductor having the following structure can be used.

[0136] The oxide semiconductor layer 542 is formed of an i-type or substantially i-type oxide semiconductor layer. The i-type or substantially i-type oxide semiconductor layer has a carrier density of 5×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / c m 3 In addition, it is preferable that there are few hydrogen or oxygen vacancies that serve as donors. Hydrogen concentration is 1×10 16 / cm 3 The carrier density is preferably determined by Hall effect measurement. Furthermore, the carrier density at lower concentrations can be measured by CV measurement (Capacitance-Vehicle Response Measurement). It is obtained from the measurement results of the tance-voltage measurement. The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). It is obtained by Daily Ion Mass Spectroscopy.

[0137] The transistor uses the i-type or substantially i-type oxide semiconductor layer 542 as a channel region. The resistor 505 has an off-state current of 1×10 -19 A / μm or less, even 1×10 -20 A / This means that the thickness can be reduced to below 1 μm, i-type or substantially i-type oxide semiconductor. The conductor layer has a wide band gap and requires a large amount of thermal energy to excite electrons. Therefore, direct and indirect recombination are unlikely to occur. In the off state, the number of holes, which are minority carriers, is essentially zero. Direct and indirect recombination are unlikely to occur, and the current is extremely low. When the capacitor is in a non-conducting (off) state, the oxide semiconductor layer can be regarded as an insulator. On the other hand, i-type or substantially i-type oxide semiconductors When the transistor is in a conducting state, the semiconductor layer is made of amorphous silicon. Therefore, the transistor 505 is in the off state. In this state, the device is in a normally-off state with extremely low leakage current, and has excellent switching characteristics. do.

[0138] The gate insulating layer 544 is formed by appropriately using the materials shown in the gate insulating layer 522 and the gate insulating layer 524. When the gate insulating layer 544 has a stacked structure, the oxide semiconductor layer 542 By forming the layer in contact with the oxide semiconductor layer 542 as an oxide insulating layer, oxygen vacancies in the oxide semiconductor layer 542 can be reduced. Oxygen can be supplied to the oxide semiconductor layer 542, and the oxide semiconductor layer 542 can be made i-type or substantially i-type. It can be made into a type.

[0139] The insulating layer 552 and the insulating layer 554 are the same as the insulating layer 536, the insulating layer 538, or the insulating layer 540. It can be formed in the same way.

[0140] In this embodiment, the channel region of the diode-connected transistor 505 is made into an i-type or Since the semiconductor layer is formed of an oxide semiconductor layer that is substantially i-type, the off-state current can be significantly reduced. Therefore, the voltage applied to the capacitor 504 can be held for a long time. .

[0141] Next, in the semiconductor memory device shown in FIG. 15, a manufacturing process of the transistor 505 will be described. 16. Note that the transistors 502, 503, and The transistor 506 may be manufactured using a known transistor manufacturing process as appropriate.

[0142] As shown in FIG. 16A, the source electrode and the drain electrode of the transistor 505 are formed on the insulating layer 540. Wiring 534c and wiring 534d that function as drain electrodes are formed.

[0143] The insulating layer 540 can be formed by a sputtering method, a CVD method, a printing method, a coating method, or the like. Alternatively, high density plasma CVD using microwaves (for example, frequency 2.45 GHz) can be used. This allows the formation of a high-quality insulating layer 540 that is dense and has a high withstand voltage. The intimate contact with the high-quality insulating layer 540 reduces the interface state and improves the interface characteristics. In addition, the insulating layer 540 obtained by high density plasma CVD has a constant thickness. It can be formed by high-density plasma CVD, so it has excellent step coverage. The thickness of the insulating layer 540 can be precisely controlled. The doped oxide semiconductor layer is extremely sensitive to the interface states and interface charges, so it is necessary to The layer 540 is formed by high density plasma CVD using microwaves, thereby reducing the interface state. The interface characteristics can be improved.

[0144] When the insulating layer 540 is formed, the substrate 508 is heated to remove the impurities contained in the insulating layer 540. This can reduce the amount of hydrogen, water, hydroxyl groups, hydrides, etc. that are produced.

[0145] In addition, in order to reduce hydrogen, water, hydroxyl groups, hydrides, etc. contained in the insulating layer 540, When the insulating layer 540 is formed by a deposition method, hydrogen, water, a hydroxyl group, or the like remaining in the treatment chamber is removed. In this case, it is preferable to form the insulating layer 540 while removing hydrides or the like. To remove hydrogen, water, hydroxyl radicals, hydrides, etc., an adsorption type vacuum pump is used. Representative examples of adsorption type vacuum pumps include cryopumps, ion pumps, and titanium The pump is a sublimation pump. The exhaust means is a turbo pump with a cold transistor. It is possible to use a mixture containing a top coat.

[0146] The purity of the sputtering gas used in forming the insulating layer 540 is set to 6N (99.9%). 999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration is 1p pm or less, preferably 0.1 ppm or less), hydrogen contained in the insulating layer 540, Water, hydroxyl groups, hydrides, etc. can be reduced.

[0147] The wiring 534c and the wiring 534d are formed by using a printing method, an inkjet method, or the like. Alternatively, the insulating layer 540 may be formed by a sputtering method, a CV method, or the like. After forming a conductive layer by the D method, evaporation method, etc., a resist is formed by the photolithography process. The conductive layer is etched using the mask to form wiring 534c and wiring 534d. It is possible.

[0148] Next, as shown in FIG. 16(B), the following is formed on the insulating layer 540, the wiring 534c, and the wiring 534d: An oxide semiconductor layer 541 is formed. The oxide semiconductor layer 541 is formed by a printing method or an inkjet method. Alternatively, the insulating layer 540 can be formed by a sputtering method, a CV method, or the like. An oxide semiconductor layer is formed by the D method, coating method, pulsed laser deposition method, etc., and then photolithography is performed. the oxide semiconductor layer is etched using the resist formed in the etching process as a mask, An island-shaped oxide semiconductor layer 541 can be formed.

[0149] The carrier density of the oxide semiconductor layer is determined by the hydrogen concentration of the source gas and the target under the film formation conditions. The oxide semiconductor depends on the concentration of oxygen, the material and composition of the film, and the heat treatment conditions. or increasing the oxygen concentration in the oxide semiconductor layer to reduce oxygen vacancies. By this, the oxide semiconductor layer becomes i-type or substantially i-type. The oxide semiconductor layer 5 is then subjected to a process for making the oxide semiconductor layer i-type or substantially i-type. 41 may be either i-type or n-type.

[0150] Note that in the case where the oxide semiconductor layer is formed by a sputtering method, the oxide semiconductor layer is oxidized by heating the substrate. Impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the compound semiconductor layer can be reduced. Furthermore, the first heat treatment can promote crystal growth.

[0151] In addition, when the oxide semiconductor layer is formed by a sputtering method, the metal in the metal oxide target The relative density of the metal oxide is 80% or more, preferably 95% or more, and more preferably 99.9%. By setting the above, the impurity concentration in the oxide semiconductor layer can be reduced, and the electrical characteristics and This makes it possible to obtain a highly reliable transistor.

[0152] In addition, by performing preheating treatment before forming the oxide semiconductor layer, Hydrogen, water, hydroxyl groups, and hydrides remaining on the inner wall, target surface, and target material Therefore, impurities such as hydrogen, water, a hydroxyl group, and hydride contained in the oxide semiconductor layer can be removed. It is possible to reduce the amount of

[0153] In addition, similarly to the insulating layer 540, before, during, or after forming the oxide semiconductor layer, Afterwards, hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the sputtering device are removed. Therefore, it is preferable to use an adsorption type vacuum pump. Since the hydrides and the like are exhausted, hydrogen, water, hydroxyl groups, hydrides, and the like contained in the oxide semiconductor layer are Which concentrations can be reduced?

[0154] Next, first heat treatment is performed to remove hydrogen, water, a hydroxyl group, and hydrogen contained in the oxide semiconductor layer 541. In other words, it is possible to perform at least one of dehydration and dehydrogenation. Note that oxygen vacancies are formed in the oxide semiconductor layer 541 during the first heat treatment. .

[0155] The temperature of the first heat treatment is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. The heat treatment device used for the first heat treatment is not particularly limited, and may be a resistance heating element or the like. The apparatus may be provided with a device for heating the object to be treated by heat conduction or heat radiation from the heating element. For example, electric furnaces and GRTA (Gas Rapid Thermal Atomic Energy thermal annealing) equipment, LRTA (Lamp Rapid Thermal An Use an RTA (Rapid Thermal Anneal) device such as a LRTA devices can be used with halogen lamps, metal halide lamps, and xenon lamps. Lamps such as clamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps The GRTA device heats the object to be treated by radiating light (electromagnetic waves) emitted from the It is a device that performs heat treatment using high-temperature gas.

[0156] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that hydrogen, water, hydroxyl groups, hydrides, etc. are not contained. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the treatment equipment must be 6N or less. (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurities It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0157] In the first heat treatment, the inside of the furnace is in a nitrogen atmosphere during the temperature rise, and the inside of the furnace is in a nitrogen atmosphere during the cooling. The atmosphere may be switched to an oxygen atmosphere inside, and dehydration or dehydrogenation may be performed in a nitrogen atmosphere. After this, the atmosphere is changed to an oxygen atmosphere to supply oxygen to the inside of the oxide semiconductor layer. As a result, the hydrogen concentration is reduced and oxygen is introduced into the oxygen vacancies in the oxide semiconductor layer in which oxygen vacancies are formed. It is possible to supply an element, and form an i-type or substantially i-type oxide semiconductor layer. It can be achieved.

[0158] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer For example, when the crystallization rate is 90% or more, the oxide semiconductor layer may be crystallized. In some cases, the oxide semiconductor layer has crystallinity of 80% or more.

[0159] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide Oxide semiconductors in which crystals with their c-axes nearly parallel to the surface are formed in the surface layer of the semiconductor layer. It may also be a body layer.

[0160] Here, the substrate is introduced into an electric furnace and heated at 450 Heat treatment is carried out at ℃ for 1 hour.

[0161] Next, as shown in FIG. 16(C), a gate insulating layer 544 is formed.

[0162] The gate insulating layer 544 can be formed in the same manner as the insulating layer 540. When a silicon oxide layer is formed as the layer 544 by a sputtering method, the silicon oxide layer The oxide semiconductor layer 541 is then heated to a temperature of 1000° C. for 1 hour. It is possible to reduce oxygen vacancies that contribute as donors and achieve a composition that satisfies the stoichiometric ratio. As a result, an i-type or substantially i-type oxide semiconductor layer can be obtained. In addition, the oxide semiconductor layer and the high-quality insulating layer 540 can be closely contacted with each other. By doing so, the interface state density can be reduced and the interface characteristics can be improved.

[0163] Note that the i-type or substantially i-type oxide semiconductor layer has a low interface state and interface charge. Because it is extremely sensitive, the insulating layer 540 is formed by high density plasma CVD using microwaves. This reduces the interface state density and improves the interface characteristics.

[0164] Next, a second heat treatment (preferably 200 The second heat treatment is carried out at a temperature of 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. This may be performed after forming a protective insulating layer or a planarizing insulating layer on the base insulating layer 544. The oxide insulating layer of the gate insulating layer 544 is converted into the oxide semiconductor generated by the first heat treatment. It is possible to supply oxygen to oxygen vacancies in the cellular layer, and oxygen that contributes as a donor It is possible to reduce defects and achieve a structure that satisfies the stoichiometric ratio. As a result, it is possible to achieve a more i-type structure. Alternatively, a substantially i-type oxide semiconductor layer 542 can be formed.

[0165] In this embodiment mode, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour.

[0166] Next, as shown in FIG. 16(D), an opening is formed in the gate insulating layer 544, and then the gate insulating layer 544 is A gate electrode 546a is formed on the layer 544 and the wiring 534d. Therefore, a transistor in which the output electrode 546a and the wiring 534d are diode-connected can be fabricated. The gate electrode 546a can be formed in the same manner as the wirings 534c and 534d. Cut.

[0167] Next, as shown in FIG. 16(E), an insulating film is formed on the gate insulating layer 544 and the gate electrode 546a. A layer 552 and an insulating layer 554 are formed.

[0168] Furthermore, heat treatment was carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. The heat treatment can improve the reliability of the transistor.

[0169] Note that in FIG. 16, after the wirings 534c and 534d are formed, the oxide semiconductor layer After the oxide semiconductor layer 541 was formed on the insulating layer 540, the wiring 534 c and wiring 534d may be formed.

[0170] 16, a gate electrode 546a is formed on the insulating layer 540, and the gate electrode 546b is formed on the insulating layer 540. A gate insulating layer 544 is formed over the gate insulating layer 544, and an oxide semiconductor layer 541 is formed over the gate insulating layer 544. and wirings serving as source and drain electrodes are formed over the oxide semiconductor layer 541. In this case, one of the wirings functioning as a source electrode and a drain electrode, The wiring 534c is electrically connected to the source electrode and the drain electrode. The other of the wirings is electrically connected to gate electrode 546a.

[0171] By the above steps, the i-type or substantially i-type oxide semiconductor layer is formed in the channel region. Thus, the transistor 505 with extremely low off-state current can be manufactured.

[0172] (Embodiment 5) In this embodiment mode, an RFI having the semiconductor memory device described in any of Embodiment Modes 1 to 4 is used. The form of the D tag will be explained using drawings.

[0173] The circuit shown in Figure 17 is an RFID tag. Radio frequency contactless automatic identification technology) is a contactless recording It has features such as being able to read recorded information, operating without batteries, and being highly durable and weather resistant. The RFID tag can operate in the pond because it receives radio waves (which contain operational instructions) from its antenna. This is because electricity can be generated by rectifying the current (which includes current, etc.) in a circuit. RFID tags can be written or rewritten by users to improve their functionality. It is often the case that memory is installed.

[0174] The RFID tag 1520 includes an antenna circuit 1521 and a signal processing circuit 1522. The signal processing circuit 1522 includes a rectifier circuit 1523, a power supply circuit 1524, a demodulation circuit 1525, an oscillator circuit 1526, and an oscillator circuit 1528. circuit 1526, logic circuit 1527, memory control circuit 1528, memory circuit 152 9, a logic circuit 1530, an amplifier 1531, and a modulation circuit 1532. 9 has the semiconductor memory device of the above embodiment.

[0175] The communication signal received by the antenna circuit 1521 is input to the demodulation circuit 1525. The communication signal transmitted between the antenna circuit 1521 and the reader / writer is The frequencies of the signals in the ultra-high frequency band are 13.56MHz, 915MHz, 2.45GHz, etc. Of course, there are antenna circuits 1521 and relays. The frequency of the signal transmitted and received between the reader / writer is not limited to this, and may be, for example, a submillimeter wave. 300GHz to 3THz, millimeter waves 30GHz to 300GHz, microwaves 3GHz to 30GHz, ultra-high frequency 300MHz to 3GHz, ultra-high frequency 30MHz Any frequency between 100 MHz and 300 MHz can be used. The signal transmitted between the and the reader / writer is a modulated carrier wave. The modulation method can be analog or digital, and can be amplitude modulation, phase modulation, frequency modulation, and It may be either spread spectrum, preferably amplitude modulation or frequency modulation.

[0176] The oscillation signal output from the oscillation circuit 1526 is supplied to the logic circuit 1527 as a clock signal. The modulated carrier wave is demodulated by a demodulation circuit 1525. The demodulated signal is also The signal analyzed by the logic circuit 1527 is sent to the memory controller 1528. The memory control circuit 1528 sends the data to the memory circuit 1529. , retrieves the data stored in the memory circuit 1529, and sends it to the logic circuit 1530. The signal sent to the logic circuit 1530 is encoded by the logic circuit 1530 and then output to the The signal amplified by the amplifier 1531 is input to the modulation circuit 153 2 modulates the carrier wave. This modulated carrier wave allows the reader / writer to read the RFID tag. The signal from the tag 1520 is recognized.

[0177] The carrier wave that enters the rectifier circuit 1523 is rectified and then input to the power supply circuit 1524. The power supply voltage thus obtained is transmitted from the power supply circuit 1524 to the demodulation circuit 1525 and the oscillator circuit 15 26, logic circuit 1527, memory control circuit 1528, memory circuit 1529, logic The signal is supplied to a circuit 1530, an amplifier 1531, a modulation circuit 1532, and the like.

[0178] Regarding the connection between the signal processing circuit 1522 and the antenna in the antenna circuit 1521, For example, the antenna and the signal processing circuit 1522 are connected by wire bonding or band bonding. Alternatively, one side of the chip-shaped signal processing circuit 1522 is connected as an electrode. The signal processing circuit 1522 is attached to the antenna using an ACF (a Using anisotropic conductive film You can be there.

[0179] The antenna may be laminated on the same substrate as the signal processing circuit 1522, or may be an external antenna. Of course, the antenna is provided above or below the signal processing circuit.

[0180] The rectifier circuit 1523 converts an AC signal induced by a carrier wave received by the antenna circuit 1521 into a is converted into a DC signal.

[0181] The RFID tag 1520 may have a battery 1581 as shown in FIG. The power supply voltage output from the current circuit 1523 is sufficient to operate the signal processing circuit 1522. When the battery 1581 is not in operation, the power is supplied to each circuit constituting the signal processing circuit 1522, e.g. For example, a demodulation circuit 1525, an oscillation circuit 1526, a logic circuit 1527, a memory control circuit 1528, memory circuit 1529, logic circuit 1530, amplifier 1531, modulation circuit 1532 It supplies power voltage to the following:

[0182] In addition, the surplus of the power supply voltage output from the rectifier circuit 1523 is supplied to the battery 1581. The RFID tag can be charged. By providing an antenna circuit and a rectifier circuit, randomly generated electromagnetic waves, etc. Energy can be obtained from this to store in the battery 1581.

[0183] The RFID tag can be used continuously by charging the battery. For example, a lithium battery using a gel electrolyte can be used. If polymer batteries, lithium ion batteries, or lithium secondary batteries are used, the battery size will be In addition, nickel-metal hydride batteries and nickel-cadmium batteries can be used as batteries. A battery or a large-capacity capacitor can be used.

[0184] (Embodiment 6) In this embodiment, the RFID tag 1520 shown in the fifth embodiment is used as an example. This will be used to explain.

[0185] The RFID tag 1520 can be used for a wide range of purposes, such as bills, coins, securities, and unregistered Bonds, certificates (driver's licenses, resident cards, etc. (See Figure 19(A))), recording media (DVD Software, video tapes, etc. (See Figure 19(B)), packaging containers (wrapping paper, bottles, etc. ( See Figure 19(C). )), vehicles (bicycles, etc. (See Figure 19(D). )), personal belongings ( bags, glasses, etc.), food, plants, animals, the human body, clothing, household items, or electronic devices (liquid LCD display devices, EL display devices, television devices, or mobile phones) or other items It should be attached to tags attached to goods (see Figure 19(E) and Figure 19(F)). can be done.

[0186] The RFID tag 1520 can be mounted on a printed circuit board, attached to a surface, or embedded in For example, they can be embedded in the paper of a book, or in a package made of organic resin. If it is a package, it is embedded in the organic resin and fixed to each item. To achieve a small, thin, and lightweight design, the product itself remains intact even after it is attached to the product. In addition, RFIs are not used on banknotes, coins, securities, bearer bonds, or certificates. By providing the D tag 1520, an authentication function can be provided. This will help prevent counterfeiting. By attaching the RFID tag of the present invention to goods, clothing, household items, electronic devices, etc. This will improve the efficiency of systems such as inspection systems. However, by attaching the RFID tag 1520, security against theft etc. can be improved. It can be increased. [Example]

[0187] In this embodiment, the data retention time of the memory element shown in any of Embodiments 1 to 3 is The results of verification by simulation are shown below.

[0188] The circuit diagram for the simulation and the results are shown in Figure 20. The circuit shown in Figure 20(A) is 6. A memory element according to one embodiment of the present invention includes a diode-connected transistor 601 and a transistor The circuit has a transistor 602 and a capacitor 603. The circuit shown in FIG. 20B includes a resistor 611 and a transistor 612. , a capacitor 613, a resistor 614, and a resistor 615. The resistor 611 is a diode connection in the off state. The resistor 614 is equivalent to the gate of the transistor 612. The resistor 615 represents the inter-electrode leakage component of the capacitor 613 .

[0189] Assuming the state immediately after writing, the simulation was performed with the initial voltage of node A set to 2V. The simulation software used was SIMUCAD DESIGN AUTOMATIC. ON's Gateway, Version 2.6.12.R was used. The potential of node A is , a resistor 611 assuming an off-current of a diode-connected transistor 601, The resistor 614 is assumed to be a gate leakage component of the capacitor 612, and the inter-electrode leakage component of the capacitor 613 is assumed to be a gate leakage component of the capacitor 612. The potential decreases monotonically over time due to the resistance 615. The time until the transistor 612 can no longer be kept in the OFF state is the time during which data can be retained. In this example, data 1 can be held until the voltage drops by 10%, i.e., until it drops to 1.8V. This is defined as the period during which data 1 is retained.

[0190] Conditions 1 and 2 are set so that the resistance value of the resistor 611 is set to the value of the diode-connected transistor 601. The value of the off-state current of a transistor whose channel region is formed using an oxide semiconductor layer is used as the condition 3. The resistance value of the resistor 611 is set by oxidizing the channel region of the diode-connected transistor 601. The value of the off-state current of a transistor not formed with a compound semiconductor layer was used. Condition 1: 2 × 10 20 Ω (off current equivalent: 10 -20 A), Condition 2: 2 × 10 19 Ω (off current equivalent: 10 -1 9 A), Condition 3: 2 × 10 9 Ω (off current equivalent: 10 -9 A) Resistor 614 and resistor 615 The resistance value of resistor 611 is assumed to be 10 times that of resistor 611.

[0191] The simulation results are shown in Figure 20(C). Figure 20(C) shows the relationship between nodes and elapsed time on the horizontal axis. The graph shows the voltage of A on the vertical axis. Under condition 3, the data 1 retention time was 176.3 μs. In contrast, under condition 1, the data 1 retention time was 17.63 × 10 6s (approximately 200 days) , and under condition 2, the data 1 retention time is 1.763 × 10 6 s (about 20 days). As a result, the channel region of the diode-connected transistor 601 is formed of an oxide semiconductor layer. By doing so, it was found that it was possible to retain data1 for a significantly longer period of time. [Example]

[0192] In this example, an i-type or substantially i-type oxide semiconductor layer is used for the channel region. The results of determining the off-state current of the transistor will be described.

[0193] First, a transistor using an i-type or substantially i-type oxide semiconductor layer as a channel region was fabricated. Considering that the off-state current of the transistor is sufficiently small, the channel width W is set to 1 m, which is sufficiently large. The off-state current of a transistor with a channel width W of 1 m was measured. The results of measuring the gate current are shown in Figure 21. In Figure 21, the horizontal axis is the gate voltage VG and the vertical axis is When the drain voltage VD is +1V or +10V, the gate voltage When VG is in the range of -5V to -20V, the off-state current of the transistor is 1×10 -12 After A In addition, the off-state current of the transistor (here, per unit channel width ( The value per 1μm is 1aA / μm (1×10 -18 A / μm) or less. It was.

[0194] Next, an off-state current of a transistor using an i-type or substantially i-type oxide semiconductor layer is measured. As mentioned above, the flow is calculated more accurately. The off-state current of a transistor using an i-type oxide semiconductor layer for a channel region is 1×1 0 -12 Therefore, we fabricated a device for characteristic evaluation and obtained a more accurate The results of the measurement of the current (a value below the detection limit of the measuring instrument in the above measurement) are explained below. do.

[0195] First, the characteristic evaluation element used in the current measurement method will be described with reference to FIG.

[0196] The characteristic evaluation element shown in FIG. 22 has three measurement systems 800 connected in parallel. 0 represents the capacitor element 802, the transistor 804, the transistor 805, and the transistor 806. , and transistor 808. The capacitor 806 uses an i-type or substantially i-type oxide semiconductor layer for a channel region. A transistor with this structure was applied.

[0197] In the measurement system 800, one of the source terminal and the drain terminal of the transistor 804, One of the terminals of the capacitor 802 and the source terminal and drain terminal of the transistor 805 One end is connected to a power supply (the power supply that provides V2). the other of the source and drain terminals of the transistor 808 One of the terminals of the capacitor 802, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 are connected to each other. The other of the source terminal and the drain terminal of the transistor 808 is connected to the One of the source terminal and the drain terminal of the transistor 806 and the gate of the transistor 806 The output terminal of the transistor 805 is connected to a power supply (the power supply that provides V1). the other of the source and drain terminals of the transistor 806 The other terminal is connected to form an output terminal Vout.

[0198] The gate terminal of the transistor 804 is connected to a resistor R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R A potential Vext_b2 that controls the state of the transistor 808 is supplied to the gate terminal of the transistor 808. A potential Vext_b1 that controls the on and off states of the transistor 808 is supplied. Furthermore, the potential Vout is output from the output terminal.

[0199] Next, a current measurement method using the above characteristic evaluation element will be described.

[0200] First, an outline of the initialization period during which a potential difference is applied to measure the off-state current will be described. During the initialization period, the gate terminal of the transistor 808 is connected to the transistor 808. A potential Vext_b1 is input to the source terminal or drain of the transistor 804. a node connected to the other of the input terminals (i.e., the source terminal and the drain terminal of the transistor 808) One of the drain terminals, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 A potential V1 is applied to node A, which is a node connected to a child. In addition, the transistor 804 is kept in an off state.

[0201] Then, a potential that turns off the transistor 808 is applied to the gate terminal of the transistor 808. Vext_b1 is input to turn off the transistor 808. After turning off the transistor 804, the potential V1 is set to a low potential. The potential V2 is set to the same potential as the potential V1. When the initialization period is over, the node A and the source terminal of the transistor 804 A potential difference is generated between the node A and one of the drain terminals of the transistor 808. A potential difference occurs between the source terminal and the drain terminal of the transistor. A small amount of charge flows through the transistor 804 and the transistor 808. In other words, an off-current occurs. do.

[0202] Next, an outline of the measurement period of the off-state current will be described. The potential of one of the source terminal or drain terminal of 804 (i.e., V2) and The potential of the other terminal of the source terminal or the drain terminal of the transistor 808 (i.e., V1) is On the other hand, during the measurement period, the potential of the node A is not fixed (floor As a result, charge flows through the transistor 804, and over time, The amount of charge held at node A changes. In other words, the output potential Vout of the output terminal also fluctuates. do.

[0203] The details of the relationship between the potentials during the initialization period in which the above potential difference is applied and the subsequent measurement period are as follows: The timing chart is shown in FIG.

[0204] In the initialization period, first, the potential Vext_b2 is applied when the transistor 804 is turned on. This sets the potential of node A to V2, that is, a low potential ( VSS). After that, the potential Vext_b2 is set to Vext_b1 when the transistor 804 is turned off. The transistor 804 is turned off by applying a voltage (low potential) to the transistor 804. The potential Vext_b1 is set to a potential (high potential) that turns on the transistor 808. This causes the potential of node A to become V1, i.e., the high potential (VDD). The potential Vext_b1 is set to a potential that turns off the transistor 808. As a result, node A goes into a floating state, and the initialization period ends.

[0205] In the subsequent measurement period, charges flow into node A, causing potentials V1 and V2 to Or, the potential is set so that charge flows out from node A. Here, the potential V1 and the potential V 2 is the low potential (VSS). However, at the timing when the output potential Vout is measured, In this case, it is necessary to operate the output circuit, so V1 is temporarily set to a high potential (VDD). The period when V1 is at a high potential (VDD) should be short enough so as not to affect the measurement. The period.

[0206] As described above, when a potential difference is applied and the measurement period begins, the voltage at node A increases over time. The amount of charge held changes, and the potential at node A changes accordingly. This means that the potential of the gate terminal of the transistor 805 fluctuates, so over time, the output The potential of the output potential Vout of the terminal also changes.

[0207] A method for calculating the off-state current from the obtained output potential Vout will be described below.

[0208] Before calculating the off-state current, the relationship between the potential VA of node A and the output potential Vout is calculated. This allows the potential VA of node A to be calculated from the output potential Vout. From the above relationship, the potential VA of node A can be expressed as a function of the output potential Vout as follows: It is possible.

[0209]

number

[0210] The charge QA at node A is calculated by the potential VA of node A, the capacitance CA connected to node A, and the constant Using a constant, it is expressed as follows: CA is the sum of the capacitance of the capacitive element 802 and other capacitances.

[0211]

number

[0212] The current IA at node A is the sum of the charge flowing into (or out of) node A. Since it is a time derivative, the current IA at node A can be expressed as follows:

[0213]

number

[0214] In this way, the capacitance CA connected to node A and the output potential Vout of the output terminal The current IA of the diode A can be calculated.

[0215] By using the method described above, the leakage current flowing between the source and drain of the transistor in the off state can be reduced. The off-state current (off current) can be measured.

[0216] In this example, a highly purified oxide film having a channel length L=10 μm and a channel width W=50 μm was used. A transistor 804, a transistor 805, a transistor 806, and a transistor 807 are formed using a compound semiconductor. In each of the paralleled measurement systems 800, a capacitance element 802 The capacitance values of the capacitive element 802a, 802b, and 802c are respectively set to 100 fF and 100 fF. The capacitance of the capacitance element 802c was set to 1 pF, and the capacitance of the capacitance element 802b was set to 3 pF.

[0217] In the measurement according to this embodiment, VDD=5V and VSS=0V. In this case, the potential V1 is set to VSS as a rule, and the voltage is increased by 100 msec every 10 to 300 sec. Vout was measured as VDD for the period c. The Δt was set to approximately 30,000 seconds.

[0218] FIG. 24 shows the relationship between the elapsed time Time in the current measurement and the output potential Vout. From FIG. 24, it can be seen that the potential changes over time.

[0219] FIG. 25 shows the off-state current at room temperature (25° C.) calculated from the above current measurement. FIG. 25 shows the relationship between the source-drain voltage V and the off-state current I. 25, the off-current is about 40zA / μm when the source-drain voltage is 4V. In addition, under the condition of a source-drain voltage of 3.1 V, the off-current It was found that the current density was 10zA / μm or less. -21 Represents A.

[0220] Furthermore, the off-state current calculated from the above current measurement in a temperature environment of 85°C was The figure shows the relationship between the source-drain voltage V and the off-state voltage V under a temperature environment of 85°C. This shows the relationship between the current I and the source-drain voltage of 3.1 V. It was found that the off-state current was 100 zA / μm or less.

[0221] As described above, according to this embodiment, the i-type or substantially i-type oxide semiconductor layer is formed in the channel region. It was confirmed that the off-state current of the transistor used in the above region was sufficiently small. As shown in the first to third embodiments, the i-type or substantially i-type oxide semiconductor The conductor layer is used as a channel region, and the transistors 102, 112, and 113 are diode-connected. It can be seen that the off-state current is also sufficiently small in 22 and 132. [Explanation of symbols]

[0222] 101 Memory element 102 transistor 103 Transistor 104 Capacitive element 110 memory cells 111 Memory element 112 transistors 113 Transistor 114 Capacitor element 115 transistors 116 transistors 117 circuits 118 Inverter 120 memory cells 121 Memory element 122 transistors 123 Transistor 124 Capacitor element 125 transistors 129 areas 130 memory cells 131 Memory element 132 transistors 133 Transistor 134 Capacitor element 135 transistors 300 Semiconductor memory device 301 Memory Cell Array 302 Column Decoder 303 Low Decoder 304 Interface Circuit 305 memory cells 310 Semiconductor memory device 311 Memory Cell Array 312 Memory Cell Array 313 memory cells 314 memory cells 400 memory cells 401 Memory element 402 transistor 403 Transistor 404 Capacitor element 405 Transistor 406 Transistor 502 transistor 503 Transistor 504 Capacitive element 505 Transistor 506 Transistor 508 PCB 510 Insulating layer 512 Insulation layer 514 Channel Region 516 Low concentration impurity region 518 High concentration impurity region 519 Semiconductor Layer 520 Semiconductor layer 522 Gate insulating layer 524 Gate insulating layer 526 Gate electrode 528 Capacitive electrode 530 Sidewall insulating layer 532 Sidewall insulating layer 534a Wiring 534b Wiring 534c wiring 534d Wiring 534e wiring 534f wiring 536 Insulating Layer 538 Insulating Layer 540 Insulating Layer 541 Oxide semiconductor layer 542 Oxide semiconductor layer 544 Gate insulating layer 546a Gate electrode 546b wiring 552 Insulation layer 554 Insulating layer 601 Transistor 602 Transistor 603 Capacitor element 611 Resistance 612 Transistor 613 capacity 614 Resistance 615 Resistance 800 measurement system 802 Capacitor element 802a Capacitive element 802b Capacitive element 802c Capacitive Element 804 transistor 805 transistor 806 Transistor 808 Transistor 1520 RFID tags 1521 Antenna Circuit 1522 Signal Processing Circuit 1523 Rectifier circuit 1524 Power supply circuit 1525 Demodulation Circuit 1526 Oscillator Circuit 1527 Logic Circuit 1528 Memory control circuit 1529 Memory Circuit 1530 Logic Circuit 1531 Amplifier 1532 Modulation circuit 1581 Battery

Claims

1. a first transistor, a second transistor, a third transistor, and a fourth transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the first transistor is electrically connected to the one of the source and the drain of the third transistor; the other of the source and the drain of the first transistor is electrically connected to the gate of the first transistor; one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor; the other of the source and the drain of the third transistor is electrically connected to a first wiring; the other of the source and the drain of the second transistor is electrically connected to a second wiring; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the gate of the third transistor is electrically connected to a fourth wiring; the gate of the fourth transistor is electrically connected to a fifth wiring; a channel formation region of the first transistor having a region through which carriers flow in a first direction; a channel formation region of the second transistor having a region through which carriers flow in a direction along the first direction; a channel formation region of the third transistor having a region through which carriers flow in a direction along the first direction; a channel formation region of the fourth transistor has a region in which carriers flow in a direction along the first direction; In a plan view, the first wiring, the second wiring, and the third wiring have regions extending in a direction intersecting the first direction, In a plan view, the fourth wiring and the fifth wiring have a region extending in the first direction, the first transistor has an oxide semiconductor in a channel formation region; the fourth wiring and the fifth wiring are provided in contact with an insulating surface; an insulating layer is provided on the fourth wiring and the fifth wiring; The semiconductor device, wherein the first wiring and the third wiring are provided in contact with an upper surface of the insulating layer.

2. In claim 1, the second transistor has an oxide semiconductor in a channel formation region; the third transistor has an oxide semiconductor in a channel formation region; The fourth transistor is a semiconductor device including an oxide semiconductor in a channel formation region.

Images