Circuit arrangement and electronic apparatus

Abstract

To provide a circuit arrangement and the like that can detect and control a current flowing in an N-type transistor regardless of transistor characteristics.SOLUTION: A circuit arrangement 20 controls an N-type transistor 11 provided between a node of a load 90 and a power supply node, and includes: a charge pump circuit 50 that performs a charge pump operation to output gate control voltage DRV higher than a source voltage VCO of the N-type transistor 11 to a gate of the N-type transistor; a detection circuit 30 that detects the value of change of the source voltage VCO of the N-type transistor 11, and outputs a detection signal DT that becomes active when the value of change is determined to be equal to or more than a reference value; and a charge pump control circuit 40 that, when the detection signal DT becomes active, stops the charge pump operation performed by the charge pump circuit 50.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit device, an electronic device, and the like. [Background technology]

[0002] Power supply circuits for supplying power to a load have been known for some time. In such power supply circuits, when a transistor is turned on while power is being supplied to the drain, a potential difference occurs between the drain and source of the transistor, causing an overcurrent to flow. This necessitates an overcurrent detection circuit. One possible method for detecting overcurrent is to measure the voltage across a sense resistor connected in series with the transistor. However, this method suffers from a problem of significant energy loss when a large current flows through the sense resistor. Patent Document 1, on the other hand, discloses an overcurrent detection circuit that does not use such a sense resistor. Patent Document 1 detects whether the voltage of a drive signal output to the transistor's gate exceeds a reference value. If the drive voltage exceeds the reference value, it is determined that an overcurrent has been detected. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-147411 Summary of the Invention [Problem to be solved by the invention]

[0004] As described above, the conventional technology of Patent Document 1 detects overcurrent based on the voltage value of the drive signal, but even if the drive voltage is the same, the value of the current flowing through the transistor changes depending on the transistor characteristics. As a result, the current value when detecting overcurrent, etc., does not remain constant due to the transistor characteristics, which poses a problem that overcurrent, etc. cannot be detected accurately. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device for controlling an N-type transistor provided between a load node and a power supply node, the circuit device including: a charge pump circuit that performs a charge pump operation to output to the gate of the N-type transistor a gate control voltage that is higher than the source voltage of the N-type transistor; a detection circuit that detects a change in the source voltage of the N-type transistor and outputs a detection signal that becomes active when it determines that the change is equal to or greater than a reference value; and a charge pump control circuit that stops the charge pump operation of the charge pump circuit when the detection signal becomes active.

[0006] Another aspect of the present disclosure relates to an electronic device including the circuit device described above and the N-type transistor. [Brief explanation of the drawings]

[0007] [Figure 1] 1 shows an example of the configuration of a circuit device and electronic equipment according to an embodiment of the present invention. [Figure 2] 3 shows a detailed configuration example of the circuit device of the present embodiment. [Figure 3] 1 shows an example of the configuration of a control clock signal generation circuit. [Figure 4] FIG. 4 is a signal waveform diagram illustrating the operation of the present embodiment. [Figure 5] FIG. 4 is a signal waveform diagram illustrating the operation of the present embodiment. [Figure 6] FIG. 4 is a signal waveform diagram illustrating the operation of the present embodiment. [Figure 7] 3 shows a detailed configuration example of the circuit device of the present embodiment. [Figure 8] FIG. 4 is a signal waveform diagram illustrating the operation of the charge pump circuit. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0009] 1. Circuit devices and electronic devices 1 shows an example of the configuration of a circuit device 20 and an electronic device 10 according to this embodiment. The electronic device 10 includes an N-type transistor 11, a load 90, and the circuit device 20.

[0010] The electronic device 10 may be, for example, a printing device, a video projection device, a wearable device, an information processing device, a display device, a television receiver, or a portable information terminal. However, the electronic device 10 is not limited to these devices and may be various devices that use a DC power supply voltage VCC. In addition to the circuit device 20 shown in FIG. 1 , the electronic device 10 may include a processing unit implemented by a CPU or MPU, a storage unit implemented by a semiconductor memory, an output unit that outputs images or sounds, an input unit through which a user inputs information, or a communication unit for communicating with the outside. In this case, the processing unit may operate by, for example, executing a program stored in the storage unit. The processing unit is a processor, and performs, for example, control processing and management processing for each unit of the electronic device 10. The storage unit stores programs executed by the processing unit and various data. The output unit is implemented by a display unit such as a display or an audio output unit such as a speaker. The input unit is implemented by an input interface such as various input controllers. The communication unit is implemented by a communication IC, for example.

[0011] N-type transistor 11 is provided between power supply node NV and node NL of load 90. Specifically, the drain of N-type transistor 11 is connected to power supply node NV, and the source is connected to node NL of load 90. Power supply node NV is a node to which power supply voltage VCC is supplied, and node NL is a node to which load 90 is provided. N-type transistor 11 is a so-called power transistor, which supplies power supply voltage VCC to load 90 when on and cuts off the supply of power supply voltage VCC to load 90 when off.

[0012] A power supply voltage VCC is supplied to the power supply node NV from a DC power supply. The DC power supply may be, for example, an AC-DC converter, a DC-DC converter, or a battery. Although not shown in FIG. 1, these DC power supplies may also be included in the electronic device 10.

[0013] The load 90 is, for example, a capacitive load. A capacitive load is a load having capacitance. The capacitive load 90 is charged by a current IB flowing from a power supply node NV via an N-type transistor 11, causing the voltage at a node NL of the load 90 to rise. For example, the load 90 includes a circuit that operates on a power supply voltage VCC supplied to the node NL via the N-type transistor 11, and circuit elements such as a capacitor. Specifically, the load 90 may include, for example, a capacitor for stabilizing the power supply, a processing device that executes processing in the electronic device 10, or a motor driver that drives a motor. However, the load 90 is not limited to these and may include circuits for implementing various functions in the electronic device 10.

[0014] The circuit device 20 is a device that controls an N-type transistor provided between a node NL of the load 90 and a power supply node NV. For example, the circuit device 20 controls the supply of a power supply voltage VCC to the load 90 by outputting a gate control voltage DRV to the gate of the N-type transistor 11. The circuit device 20 includes a detection circuit 30, a charge pump control circuit 40, and a charge pump circuit 50.

[0015] The charge pump circuit 50 is a circuit that performs a charge pump operation. For example, the charge pump circuit 50 performs a charge pump operation to output a gate control voltage DRV that is higher than the source voltage VCO of the N-type transistor 11 to the gate of the N-type transistor 11. The source voltage VCO of the N-type transistor 11 is, for example, the voltage of a node NL of the load 90. Specifically, the charge pump circuit 50 performs a charge pump operation using a boost capacitor (not shown) to generate a gate control voltage DRV that is higher than the source voltage VCO and output it to the gate of the N-type transistor 11. As a result, when the charge pump circuit 50 is operating, the N-type transistor 11 is turned on, and the power supply voltage VCC is supplied to the load 90 via the N-type transistor 11.

[0016] The detection circuit 30 outputs a detection signal DT based on the detection result of the source voltage VCO of the N-type transistor 11. For example, the detection circuit 30 detects a change in the source voltage VCO of the N-type transistor 11 and outputs a detection signal DT that becomes active when it determines that the change is equal to or greater than a reference value. The detection circuit 30 can also be called a current detection circuit or an overcurrent detection circuit. The change in the source voltage VCO corresponds to the difference between the source voltage VCO at the i-th timing and the source voltage VCO at the i+1-th timing following the i-th timing. The time interval between the i-th timing and the i+1-th timing is, for example, a constant interval, where i is an integer greater than or equal to 1. The reference value is a value prepared in advance as a comparison value for the change in the source voltage VCO. For example, the reference value is stored in a register included in the circuit device 20. The register is a storage unit. The detection signal DT is, for example, a signal that indicates an active state when it is at a first voltage level and an inactive state when it is at a second voltage level. The first voltage level is either a high level or a low level, and the second voltage level is the other of the high level and the low level.

[0017] The charge pump control circuit 40 controls the charge pump circuit 50, for example, by controlling the charge pump operation of the charge pump circuit 50. For example, the charge pump control circuit 40 controls the charge pump circuit 50 to perform or stop the charge pump operation. When the detection signal DT from the detection circuit 30 is active, the charge pump control circuit 40 stops the charge pump operation of the charge pump circuit 50. For example, the charge pump control circuit 40 outputs a control clock signal CK that controls the charge pump operation to the charge pump circuit 50, causing the charge pump circuit 50 to perform the charge pump operation. When the detection signal DT becomes active, the charge pump control circuit 40 stops the charge pump operation by not outputting the control clock signal CK for the charge pump operation. Note that modifications are also possible, such as lowering the operating frequency of the charge pump when the detection signal DT is active.

[0018] Specifically, when the detection signal DT of the detection circuit 30 is inactive, the charge pump control circuit 40 outputs a control clock signal CK to the charge pump circuit 50, whose voltage level alternates between a first voltage level and a second voltage level and then from the second voltage level to the first voltage level. This allows the charge pump circuit 50 to perform charge pump operation based on this control clock signal CK and output a gate control voltage DRV higher than the source voltage VCO to the gate of the N-type transistor 11. On the other hand, when the detection signal DT of the detection circuit 30 is active, the charge pump control circuit 40 stops outputting the control clock signal CK to the charge pump circuit 50. For example, the charge pump control circuit 40 fixes the control clock signal CK to a predetermined voltage level. This stops the charge pump operation of the charge pump circuit 50, preventing the gate control voltage DRV from being boosted by the charge pump operation.

[0019] As described above, in this embodiment, the charge pump circuit 50 performs a charge pump operation, outputting a gate control voltage DRV higher than the source voltage VCO to the gate of the N-type transistor 11. By inputting a gate control voltage DRV higher than the source voltage VCO to the gate, the N-type transistor 11 turns on, and the power supply voltage VCC is supplied to the load 90. The detection circuit 30 then detects the change in the source voltage VCO of the N-type transistor 11, and when the change exceeds a reference value, the detection signal DT becomes active. This stops the charge pump operation of the charge pump circuit 50, and the charge pump circuit 50 no longer boosts the gate control voltage DRV. For example, the capacitance of the load 90 is charged by the current IB flowing through the N-type transistor 11, which is turned on by the charge pump operation of the charge pump circuit 50. In this case, the charge charged to the load 90 is expressed as Q = CV, and therefore the change in the source voltage VCO corresponds to the current IB flowing through the N-type transistor 11. Therefore, by detecting the change in source voltage VCO and comparing it with a reference value, detection circuit 30 can determine whether a current such as an overcurrent has flowed through N-type transistor 11. When the change in source voltage VCO exceeds the reference value, detection signal DT becomes active, and charge pump control circuit 40 stops the charging operation of charge pump circuit 50. This stops the boosting operation of gate control voltage DRV, making it possible to prevent a current such as an overcurrent from flowing through N-type transistor 11. In this embodiment, the change in source voltage VCO is detected rather than the gate voltage of N-type transistor 11 as in the above-mentioned conventional technology, making it possible to detect an overcurrent or the like independently of transistor characteristics, etc.

[0020] Fig. 2 shows a detailed configuration example of the circuit device 20. Note that the circuit device 20 of this embodiment is not limited to the configuration shown in Fig. 2, and various modifications are possible, such as omitting some of the components, adding other components, or replacing the components with other types of components.

[0021] 2, the detection circuit 30 includes an A / D conversion circuit 32, a subtraction circuit 33, and a comparison circuit 34. The detection circuit 30 may also include a register 35. The A / D conversion circuit 32 performs A / D conversion on the source voltage VCO. The A / D conversion circuit 32 then outputs the A / D converted value of the source voltage VCO to the subtraction circuit 33. The A / D conversion circuit 32 may be of various types, such as a successive approximation type, a delta-sigma type, a double integral type, or a flash type.

[0022] The subtraction circuit 33 determines the change value CHV of the source voltage VCO based on the A / D converted value of the source voltage from the A / D conversion circuit 32. For example, the subtraction circuit 33 performs a process of subtracting the A / D converted value of the source voltage VCO at the i-th timing, which is before the i+1th timing, from the A / D converted value of the source voltage VCO at the i+1th timing, to determine the change value CHV of the source voltage VCO. The time interval between the i+1th timing and the i-th timing is, for example, the clock interval of the measurement clock signal MSCK.

[0023] The comparator circuit 34 compares the change value CHV of the source voltage VCO with a reference value RFV and outputs a detection signal DT. For example, the comparator circuit 34 compares the change value CHV of the source voltage VCO with the reference value RFV, and outputs an active detection signal DT when it determines that the change value CHV is equal to or greater than the reference value RFV. For example, when the active level is high, the comparator circuit 34 outputs a detection signal DT that goes high when CHV≧RFV. The register 35 stores the reference value RFV. The register 35 can be realized by a storage circuit such as a flip-flop circuit or RAM. For example, the reference value RFV stored in a nonvolatile memory may be transferred to and stored in the register 35. The reference value RFV is set to a different value depending on, for example, the electronic device 10 or the circuit device 20. For example, the reference value RFV is set to a value corresponding to the capacitance of the load 90. For example, the reference value RFV is set to a smaller value as the capacitance of the load 90 increases.

[0024] When the charge pump control circuit 40 determines that the change value CHV of the source voltage VCO is equal to or greater than the reference value RFV and the detection signal DT becomes active, the charge pump control circuit 40 stops the charge pump operation of the charge pump circuit 50. For example, the charge pump control circuit 40 stops the charge pump operation of the charge pump circuit 50 by stopping the control clock signal CK. For example, the charge pump control circuit 40 stops the control clock signal CK, which alternately changes voltage level, by fixing the control clock signal CK at a predetermined voltage level.

[0025] For example, the detection circuit 30 detects the source voltage VCO of the N-type transistor 11 at a detection interval based on the measurement clock signal MSCK. The detection circuit 30 then detects a change value CHV based on the difference between the detected source voltage VCO and the source voltage VCO detected immediately before during the detection interval. For example, the A / D conversion circuit 32 samples the source voltage VCO at a sampling interval corresponding to the detection interval based on the measurement clock signal MSCK and performs A / D conversion. The subtraction circuit 33 then calculates the change value CHV by calculating the difference between the A / D-converted value of the source voltage VCO from the A / D conversion circuit 32 and the A / D-converted value of the source voltage VCO immediately before during the detection interval (sampling interval) of the measurement clock signal MSCK. The comparison circuit 34 then compares the change value CHV with a reference value RFV. If the change value CHV is equal to or greater than the reference value RFV, the detection signal DT becomes active, and the charge pump operation of the charge pump circuit 50 stops.

[0026] The charge pump control circuit 40 outputs a control clock signal CK, which controls the charge pump operation, to the charge pump circuit 50 based on the charge pump clock signal CPCK. When the detection signal DT is active, the charge pump control circuit 40 stops the control clock signal CK. Specifically, the charge pump control circuit 40 includes a control clock signal generation circuit 42. The control clock signal generation circuit 42 receives the charge pump clock signal CPCK and the detection signal DT. When the detection signal DT is inactive, the control clock signal generation circuit 42 outputs the charge pump clock signal CPCK to the charge pump circuit 50 as the control clock signal CK. On the other hand, when the detection signal DT is active, the control clock signal generation circuit 42 stops the charge pump operation of the charge pump circuit 50 by preventing the charge pump clock signal CPCK from being output to the charge pump circuit 50 as the control clock signal CK.

[0027] FIG. 3 shows an example configuration of the control clock signal generation circuit 42. The control clock signal generation circuit 42 includes a logical product circuit AN and an inverter circuit IV. The inverter circuit IV inverts the signal level of the detection signal DT and outputs the inverted signal of the detection signal DT to the logical product circuit AN. The logical product circuit AN generates and outputs the control clock signal CK by logically producting the charge pump clock signal CPCK and the inverted signal of the detection signal DT. For example, when the detection signal DT is at a low level (inactive), the logical product circuit AN outputs the charge pump clock signal CPCK as the control clock signal CK. On the other hand, when the detection signal DT is at a high level (active), the logical product circuit AN inputs an inverted signal of a low level, causing the output of the logical product circuit AN to go low. As a result, the charge pump clock signal CPCK is no longer output to the charge pump circuit 50 as the control clock signal CK, and the charge pump operation of the charge pump circuit 50 stops.

[0028] FIG. 4 is a signal waveform diagram illustrating the operation of the circuit device 20 of this embodiment. This illustrates, for example, the operation after the power supply voltage VCC to the circuit device 20 is turned on. The A / D conversion circuit 32 in FIG. 2 samples the source voltage VCO at, for example, the edge timing of the measurement clock signal MSCK and performs A / D conversion. The subtraction circuit 33 determines, as a change value CHV, the difference between the A / D converted value of the source voltage VCO at, for example, the (i+1)th time point and the A / D converted value of the source voltage VCO at the i-th time point. The comparison circuit 34 compares this change value CHV with a reference value RFV. When the change value CHV is equal to or greater than the reference value RFV, the comparison circuit 34 outputs an active detection signal DT, which stops the charge pump operation of the charge pump circuit 50.

[0029] 4, since the change value CHV of the source voltage VCO exceeds the reference value RFV, the detection signal DT goes to the active high level as shown at A2. As a result, the control clock signal CK is fixed to the low level as shown at A3 and stops, and the charge pump operation of the charge pump circuit 50 stops.

[0030] 4, because the change value CHV of the source voltage VCO is lower than the reference value RFV, the detection signal DT becomes the inactive low level as shown at A5. Therefore, as shown at A6, the charge pump clock signal CPCK is input to the charge pump circuit 50 as the control clock signal CK, and the charge pump circuit 50 performs a charge pump operation. This charge pump operation boosts the gate control voltage DRV, and the current IB flowing through the N-type transistor 11 increases as shown at A8.

[0031] As current IB increases in this way, the change value CHV of source voltage VCO exceeds reference value RFV, as shown at A9, and detection signal DT goes high, as shown at A10. This stops control clock signal CK, as shown at A11, and charge pump operation stops. Subsequently, the change value CHV, which rose due to the increase in current IB, gradually decreases, as shown at A12. For example, the charge at the gate node of N-type transistor 11 is discharged via the discharge path, causing the gate control voltage DRV to decrease. This decreases the gate-source voltage of N-type transistor 11, reducing current IB and decreasing the change value CHV corresponding to current IB.

[0032] For example, if the capacitance of the load 90 is C and the charge at the node NL of the load 90 is Q, the following equation (1) holds between the charge Q and the source voltage VCO.

[0033] Q = C × VCO (1)

[0034] The current flowing through N-type transistor 11 is expressed as IB=ΔQ / Δt, and the change in source voltage VCO is expressed as CHV=ΔVCO / Δt, so the following equation (2) holds.

[0035] IB=ΔQ / Δt=C×(ΔVCO / Δt)=C×CHV (2)

[0036] Therefore, by detecting the change CHV of the source voltage VCO of N-type transistor 11, it is possible to detect current IB, such as an overcurrent, flowing through N-type transistor 11. Because the change CHV, which is the amount of change in source voltage VCO, corresponds to the current IB flowing through N-type transistor 11, overcurrents and the like can be detected regardless of the transistor characteristics. For example, in this embodiment, reference value RFV is set to a value corresponding to the allowable current that can flow through N-type transistor 11. Then, as shown in FIG. 4 , when the change CHV of source voltage VCO becomes equal to or greater than reference value RFV corresponding to the allowable current, the charge pump operation of charge pump circuit 50 is stopped, and the boosting of gate control voltage DRV of N-type transistor 11 is stopped. This makes it possible to prevent overcurrents and the like exceeding the allowable current corresponding to reference value RFV from flowing through N-type transistor 11.

[0037] FIG. 5 is also a signal waveform diagram illustrating the operation of the circuit device 20 of this embodiment. At B1 in FIG. 5, the change value CHV of the source voltage VCO exceeds the reference value RFV. Therefore, the detection signal DT goes high (active level) as shown at B2. The control clock signal CK stops as shown at B3, and the charge pump operation of the charge pump circuit 50 stops. At B4, the change value CHV is below the reference value RFV. Therefore, the detection signal DT goes low (inactive level) as shown at B5. The control clock signal CK is input to the charge pump circuit 50 as shown at B6, and the charge pump operation begins. This charge pump operation boosts the gate control voltage DRV, increasing the current IB flowing through the N-type transistor 11. As the current IB increases, the change value CHV of the source voltage VCO exceeds the reference value RFV. Therefore, the detection signal DT goes high (high level) as shown at B7. The control clock signal CK stops as shown at B8, and the charge pump operation stops. The change value CHV, which increased due to the increase in current IB, then gradually decreases as shown at B9.

[0038] The operations of B1, B2, B3, B4, B5, B6, B7, B8, and B9 in Fig. 5 described above correspond to the operations of A1, A2, A3, A4, A5, A6, A10, A11, and A12 in Fig. 4. And, operations similar to those of B1, B2, B3, B4, B5, B6, B7, B8, and B9 are performed in C1, C2, C3, C4, C5, C6, C7, C8, and C9 in Fig. 5.

[0039] FIG. 6 illustrates the changes in the source voltage VCO and current IB of N-type transistor 11 until the power supply voltage VCC is charged to load 90. In this embodiment, the current flowing through N-type transistor 11 is controlled by monitoring the source voltage VCO. Specifically, power is applied at D1 in FIG. 6, and the current IB flowing through N-type transistor 11 changes as shown at D2. That is, as explained in the above equation (2), the current flowing through N-type transistor 11 is expressed as IB = C × CHV. Therefore, at D2 in FIG. 6, the current IB changes with the same change characteristics as the change value CHV shown at B9 and C9 in FIG. 5. In this case, in this embodiment, when the change value CHV exceeds the reference value RFV, the detection signal DT becomes active, the control clock signal CK stops, and the charge pump operation stops, as shown at B7, B8, C7, and C8 in FIG. 5. Therefore, as shown at D2 in FIG. 6, the current IB flowing through N-type transistor 11 is prevented from exceeding the allowable current corresponding to the reference value RFV, thereby preventing overcurrent and other problems. Then, as shown by B6 and C6 in Fig. 5, the charge pump operation using the control clock signal CK charges the node NL of the load 90, causing the source voltage VCO of the N-type transistor 11 to gradually rise as shown by D3 in Fig. 6. Then, as shown by D4, the node NL of the load 90 begins to be charged to the power supply voltage VCC.

[0040] As described above, the circuit device 20 of this embodiment includes a charge pump circuit 50, a detection circuit 30, and a charge pump control circuit 40, as shown in FIGS. 1 and 2. The charge pump circuit 50 performs a charge pump operation to output a gate control voltage DRV higher than the source voltage VCO to the gate of the N-type transistor 11. That is, the charge pump circuit 50 outputs the gate control voltage DRV, boosted by the charge pump operation, to the gate of the N-type transistor 11. This turns on the N-type transistor 11, allowing current IB to flow from the power supply node NV through the N-type transistor 11 to charge the node NL of the load 90. The detection circuit 30 then detects the change CHV in the source voltage VCO and outputs a detection signal DT that becomes active when it determines that the change CHV is equal to or greater than the reference value RFV. For example, since the change CHV exceeds the reference value RFV at A1 and A9 in FIG. 4, the detection signal DT becomes high and active, as shown at A2 and A10. When the detection signal DT becomes active, the charge pump control circuit 40 stops the charge pump operation of the charge pump circuit 50. For example, as shown at A3 and A11 in FIG. 4 , the charge pump operation of the charge pump circuit 50 stops when the control clock signal CK stops. In this embodiment, the current IB flowing through the N-type transistor 11 is detected using the change CHV in the source voltage VCO of the N-type transistor 11, enabling current detection independent of transistor characteristics. When the change CHV in the source voltage VCO becomes equal to or greater than the reference value RFV, the detection signal DT becomes active, stopping the charge pump operation of the charge pump circuit 50. Therefore, when a current corresponding to the reference value RFV flows through the N-type transistor 11, the charge pump operation of the charge pump circuit 50 stops, and the boosting of the gate control voltage DRV of the N-type transistor 11 stops. This prevents a current corresponding to the reference value RFV from flowing through the N-type transistor 11, thereby preventing overcurrent and other problems.

[0041] 2 and 4, detection circuit 30 detects source voltage VCO of N-type transistor 11 at detection intervals based on measurement clock signal MSCK and detects a change value CHV of source voltage VCO based on the difference between the detected source voltage VCO and the source voltage VCO detected immediately before in the detection interval. For example, a difference (subtraction value) is calculated between source voltage VCO detected at (i+1)th time point and source voltage VCO detected at i-th time point, which is the detection interval based on measurement clock signal MSCK before the i+1th time point, and the change value CHV is calculated based on this difference. In this way, the change value CHV is calculated from the difference between the detected source voltage VCO and the source voltage VCO detected immediately before in the detection interval, making it possible to calculate the change value CHV of source voltage VCO with the detection interval based on measurement clock signal MSCK as the unit time. When the change value CHV with the detection interval as the unit time becomes equal to or greater than reference value RFV, detection signal DT becomes active, charge pump operation is stopped, and a current exceeding the current value corresponding to reference value RFV is prevented from flowing through N-type transistor 11.

[0042] In this case, the detection interval based on the measurement clock signal MSCK is shorter than the clock interval of the charge pump clock signal CPCK used for charge pump operation. For example, as shown in FIG. 4, the measurement clock signal MSCK has a faster clock speed than the charge pump clock signal CPCK, and the detection interval based on the measurement clock signal MSCK is shorter than the clock interval of the charge pump clock signal CPCK. In this way, the source voltage VCO is detected at a detection interval shorter than the clock interval of the charge pump clock signal CPCK, and the change value CHV of the source voltage VCO can be detected based on the difference between the detected source voltage VCO and the source voltage VCO detected immediately before in the detection interval. This makes it possible to realize charge pump control such that, when the detection signal DT is inactive, the charge pump operation is performed to boost the gate control voltage DRV, and when the detection signal DT is active, the charge pump operation is stopped to stop boosting the gate control voltage DRV.

[0043] 2, detection circuit 30 includes an A / D conversion circuit 32 that performs A / D conversion on the source voltage VCO, a subtraction circuit 33 that determines a change value CHV based on the A / D-converted value of the source voltage VCO, and a comparison circuit 34 that compares the change value CHV with a reference value RFV and outputs an active detection signal DT when it is determined that the change value CHV is equal to or greater than the reference value RFV. In this manner, the change value CHV of the source voltage VCO can be determined by subtraction circuit 33 based on the value obtained by A / D conversion of the source voltage VCO by A / D conversion circuit 32. Then, comparison circuit 34 compares the change value CHV with the reference value RFV and outputs an active detection signal DT, thereby enabling control such as stopping the charge pump operation of charge pump circuit 50.

[0044] As shown in FIG. 2, the circuit device 20 also includes a register 35 that stores a reference value RFV. For example, the comparator circuit 34 compares the reference value RFV stored in the register 35 with the change value CHV of the source voltage VCO calculated by the subtractor circuit 33, and outputs an active detection signal DT when the change value CHV is equal to or greater than the reference value RFV. In this manner, an appropriate reference value RFV according to the capacitance of the load 90 is stored in the register 35, and based on the comparison result between this reference value RFV and the change value CHV of the source voltage VCO, the detection signal DT is made active to stop the charge pump operation. Therefore, the charge pump operation can be controlled by setting an appropriate reference value RFV according to the capacitance of the load 90.

[0045] The charge pump control circuit 40 also outputs a control clock signal CK to the charge pump circuit 50 based on the charge pump clock signal CPCK, which controls the charge pump operation. When the detection signal DT is active, the control clock signal CK is stopped. As described with reference to FIGS. 2 and 3, this configuration allows the charge pump circuit 50 to perform charge pump operation by outputting a control clock signal CK based on the charge pump clock signal CPCK to the charge pump circuit 50 when the detection signal DT is inactive. When the detection signal DT becomes active, the control clock signal CK is stopped, and the charge pump operation is stopped. For example, when the detection signal DT is inactive as shown at A5 in FIG. 4, the control clock signal CK is output to the charge pump circuit 50 as shown at A6, and the gate control voltage DRV is boosted by the charge pump operation as shown at A7. When the detection signal DT becomes active as shown at A10, the control clock signal CK is stopped as shown at A11, and the charge pump operation is stopped, and the boosting of the gate control voltage DRV is stopped.

[0046] The charge pump control circuit 40 stops the charge pump operation when the detection signal DT becomes active. The detection circuit 30 outputs an inactive detection signal DT when it determines that the change value CHV, which decreased during the period when the charge pump operation was stopped, falls below the reference value RFV. The charge pump control circuit 40 then resumes the charge pump operation when the detection signal becomes inactive. For example, when the detection signal DT becomes active as shown at B7 in FIG. 5, the control clock signal CK stops as shown at B8, and the charge pump operation stops. During this charge pump operation stop period, the change value CHV of the source voltage VCO decreases as shown at B9. For example, if the gate control voltage DRV of the N-type transistor 11 decreases or the source voltage VCO increases, the gate-to-source voltage of the N-type transistor 11 decreases, and the change value CHV corresponding to the current IB flowing through the N-type transistor 11 decreases. When it is determined that the decreased change value CHV, as shown at B9, falls below the reference value RFV as shown at C4 in FIG. 5, the detection signal DT becomes inactive as shown at C5. When the detection signal DT becomes inactive in this way, the control clock signal CK is output as shown at C6, and the charge pump operation is resumed. In this way, when the change value CHV of the source voltage VCO decreases due to the stop of the charge pump operation and falls below the reference value RFV, the detection signal DT becomes inactive, and the charge pump operation is resumed. This increases the gate control voltage DRV of the N-type transistor 11, and the current IB flowing through the N-type transistor 11 increases. Therefore, as shown at D2 in Figure 6, it is possible to gradually increase the source voltage VCO, which is the voltage at node NL of the load 90, while controlling the current IB flowing through the N-type transistor 11 so that it does not exceed the current value corresponding to the reference value RFV.

[0047] Furthermore, when the detection circuit 30 determines that the increased change value CHV is equal to or greater than the reference value RFV during the period after the charge pump operation is resumed, it outputs an active detection signal DT. The charge pump control circuit 40 stops the charge pump operation when the detection signal DT becomes active. For example, as shown at C6 in FIG. 5 , when the control clock signal CK is output and the charge pump operation resumes, the gate control voltage DRV of the N-type transistor 11 is boosted, the current IB flowing through the N-type transistor 11 increases, and the change value CHV of the source voltage VCO increases. When the increased change value CHV becomes equal to or greater than the reference value RFV, the detection signal DT becomes active as shown at C7, and the control clock signal CK stops as shown at C8, stopping the charge pump operation. In this way, when the charge pump operation is resumed and the change value CHV of the source voltage VCO increases and becomes equal to or greater than the reference value RFV, the detection signal DT becomes active and the charge pump operation is again stopped. This allows the source voltage VCO to be increased by repeatedly restarting and stopping the charge pump operation, for example, and the node NL of the load 90 to be charged with the power supply voltage VCC.

[0048] 2. Charge pump operation based on regulated voltage FIG. 7 shows a more detailed configuration example of the circuit device 20 of this embodiment. In FIG. 7, the circuit device 20 includes a regulator 60 in addition to the detection circuit 30, charge pump control circuit 40, and charge pump circuit 50 described above. The circuit device 20 also includes terminals TVVCC, TDRV, TCHP1, and TCHP2 and a source voltage input terminal TVCO. The circuit device 20 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate. Each terminal is, for example, a pad on the integrated circuit device or a terminal on a package that houses the integrated circuit device. The circuit device 20 of this embodiment is not limited to the configuration shown in FIG. 7 , and various modifications are possible, such as omitting some of its components, adding other components, or replacing some components with other types of components.

[0049] The regulator 60 outputs a regulated voltage VRG by regulating the power supply voltage VCC from the power supply node NV. A terminal TVCC is connected to the power supply node NV, and the power supply voltage VCC is supplied to the regulator 60 via the terminal TVCC. The regulator 60 is a step-down regulator that outputs a regulated voltage VRG that is lower than the power supply voltage VCC. The regulator 60 is, for example, a linear regulator, but is not limited to this and may be any of various types of DC-DC converters.

[0050] The charge pump circuit 50 performs a charge pump operation based on the regulated voltage VRG, thereby outputting a gate control voltage DRV to the gate of the N-type transistor 11. One end of a boost capacitor 12 is connected to a terminal TCHP1, and the other end of the boost capacitor 12 is connected to a terminal TCHP2. The boost capacitor 12 is a so-called flying capacitor, and the charge pump circuit 50 performs a charge pump operation using the boost capacitor 12. A terminal TDRV is connected to the gate of the N-type transistor 11, and the charge pump circuit 50 outputs a gate control voltage DRV to the gate of the N-type transistor 11 via the terminal TDRV. The charge pump circuit 50 uses the regulated voltage VRG to generate a gate control voltage DRV that is higher than the source voltage VCO of the N-type transistor 11. As a result, when the charge pump circuit 50 is operating, the N-type transistor 11 is turned on, and the power supply voltage VCC is supplied to the load 90 via the N-type transistor 11.

[0051] Specifically, the charge pump circuit 50 outputs the gate control voltage DRV by boosting the source voltage VCO of the N-type transistor 11 based on the regulated voltage VRG. The circuit device 20 includes a source voltage input terminal TVCO to which the source voltage VCO is input. The charge pump circuit 50 boosts the source voltage VCO input to the source voltage input terminal TVCO based on the source voltage VCO. In this manner, a voltage boosted based on the regulated voltage VRG is applied as the gate-source voltage of the N-type transistor 11. This turns on the N-type transistor 11, allowing the power supply voltage VCC to be supplied to the load 90 via the N-type transistor 11.

[0052] 7, the charge pump circuit 50 includes a drive circuit 52 and a gate control circuit 54. The drive circuit 52 receives a control clock signal CK from the charge pump control circuit 40. Specifically, when the change value CHV of the source voltage VCO falls below the reference value RFV and the detection signal DT from the detection circuit 30 becomes inactive, the charge pump control circuit 40 outputs the charge pump clock signal CPCK to the drive circuit 52 as the control clock signal CK. On the other hand, when the change value CHV of the source voltage VCO exceeds the reference value RFV and the detection signal DT from the detection circuit 30 becomes active, the charge pump control circuit 40 stops outputting the control clock signal CK. Based on the control clock signal CK, the drive circuit 52 outputs a drive signal CHP1 based on the regulated voltage VRG to one end of the boost capacitor 12. The gate control circuit 54 receives a signal CHP2 from the other end of the boost capacitor 12. The gate control circuit 54 outputs a gate control voltage DRV based on the signal CHP2 and the source voltage VCO of the N-type transistor 11.

[0053] Specifically, the drive circuit 52 includes a first transistor TRA1, a second transistor TRA2, and a control circuit 53. The gate control circuit 54 includes a first diode DI1, a second diode DI2, a resistor RB, and a switch circuit TRB.

[0054] The first transistor TRA1 is provided between the output node NVRG of the regulator 60 and one end of the boost capacitor 12. Specifically, the first transistor TRA1 is a P-type transistor, and the source of the first transistor TRA1 is connected to the output node NVRG of the regulator 60 and the drain of the first transistor TRA1 is connected to the terminal TCHP1.

[0055] The second transistor TRA2 is provided between one end of the boost capacitor 12 and the ground node. Specifically, the second transistor TRA2 is an N-type transistor, and has a source connected to the ground node and a drain connected to the terminal TCHP1.

[0056] The first diode DI1 is provided between the other end of the boost capacitor 12 and the gate of the N-type transistor 11. The forward direction of the first diode DI1 is the direction from the other end of the boost capacitor 12 to the gate. That is, the anode of the first diode DI1 is connected to the terminal TCHP2, and the cathode is connected to the terminal TDRV. The first diode DI1 is, for example, a Schottky barrier diode.

[0057] The second diode DI2 is provided between the source of the N-type transistor 11 and the other end of the boost capacitor 12. The forward direction of the second diode DI2 is from the source of the N-type transistor 11 to the other end of the boost capacitor 12. That is, the anode of the second diode DI2 is connected to the source voltage input terminal TVCO, and the cathode is connected to the terminal TCHP2. The second diode DI2 is, for example, a Schottky barrier diode.

[0058] Resistor RB is provided between the gate and source of N-type transistor 11. Specifically, one end of resistor RB is connected to the cathode of first diode DI1 and terminal TDRV, and the other end is connected to the anode of second diode DI2 and source voltage input terminal TVCO. Resistor RB serves as a discharge path for the charge at the gate node of N-type transistor 11.

[0059] The switch circuit TRB is provided between the gate and source of the N-type transistor 11. Specifically, the switch circuit TRB is a P-type transistor. The source of the P-type transistor is connected to the cathode of the first diode DI1 and the terminal TDRV, and the drain is connected to the anode of the second diode DI2 and the source voltage input terminal TVCO. A signal that controls the switch circuit TRB to turn on or off is input to the gate of the P-type transistor from the charge pump control circuit 40.

[0060] The charge pump control circuit 40 turns on the switch circuit TRB to fix the N-type transistor 11 to the off state. For example, when the circuit device 20 is in the shutdown state, the charge pump control circuit 40 turns on the switch circuit TRB to reliably cut off the power supply to the load 90.

[0061] 8 is a waveform diagram showing the operation of the charge pump circuit 50. The following description will be given ignoring the forward voltages of the first diode DI1 and the second diode DI2.

[0062] When the detection signal DT of the detection circuit 30 becomes inactive and the charge pump operation is enabled, the control circuit 53 alternately turns on the first transistor TRA1 and the second transistor TRA2 based on the control clock signal CK. When the first transistor TRA1 is off and the second transistor TRA2 is on, the drive signal CHP1 is 0 V. At this time, the signal CHP2 is at the same voltage as the source voltage VCO due to the second diode DI2. When the first transistor TRA1 changes from off to on and the second transistor TRA2 changes from on to off, the drive signal CHP1 rises from 0 V to the regulated voltage VRG. As a result, the signal CHP2 becomes a voltage higher than the source voltage VCO by the regulated voltage VRG.

[0063] This voltage VCO+VRG is the gate control voltage DRV, and is output via the first diode DI1 to the gate of the N-type transistor 11. The gate of the N-type transistor 11 is charged by the charge supplied by the drive circuit 52, and in a steady state, the gate control voltage DRV is maintained at VCO+VRG.

[0064] On the other hand, when the detection signal DT of the detection circuit 30 becomes inactive and the control clock signal CK stops, the control circuit 53 does not drive the first transistor TRA1 and the second transistor TRA2, thereby stopping the charge pump circuit 50. For example, the control circuit 53 keeps the first transistor TRA1 on and the second transistor TRA2 off. After the charge pump circuit 50 stops, the gate-source voltage of the N-type transistor 11 drops due to the discharge path of the resistor RB.

[0065] As described above, the circuit device of this embodiment controls an N-type transistor provided between a load node and a power supply node. The circuit device includes a charge pump circuit that performs a charge pump operation to output a gate control voltage to the gate of the N-type transistor that is higher than the source voltage of the N-type transistor, and a detection circuit that detects a change in the source voltage of the N-type transistor and outputs a detection signal that becomes active when it determines that the change is equal to or greater than a reference value. The circuit device also includes a charge pump control circuit that stops the charge pump operation of the charge pump circuit when the detection signal becomes active.

[0066] In this embodiment, the current flowing through the N-type transistor is detected using the change in the source voltage of the N-type transistor, making it possible to detect the current without depending on the transistor characteristics. When the change in the source voltage exceeds a reference value, the detection signal becomes active and the charge pump operation of the charge pump circuit stops. Therefore, when a current corresponding to the reference value flows through the N-type transistor, the charge pump operation of the charge pump circuit stops and the boosting of the gate control voltage of the N-type transistor stops. This makes it possible to prevent a current corresponding to the reference value from flowing through the N-type transistor. Therefore, it becomes possible to detect and control the current flowing through the N-type transistor without depending on the transistor characteristics.

[0067] In addition, in this embodiment, the detection circuit may detect the source voltage of the N-type transistor at a detection interval based on the measurement clock signal, and detect a change value based on the difference between the detected source voltage and the source voltage detected immediately before in the detection interval.

[0068] In this way, the change value can be calculated from the difference between the detected source voltage and the source voltage detected immediately before in the detection interval, making it possible to calculate the change value of the source voltage with the detection interval based on the measurement clock signal as the unit time.

[0069] In this embodiment, the detection interval may be shorter than the clock interval of the charge pump clock signal used for the charge pump operation.

[0070] In this way, the source voltage is detected at a detection interval shorter than the clock interval of the charge pump clock signal, and the change in the source voltage can be detected based on the difference between the detected source voltage and the source voltage detected immediately before in the detection interval.

[0071] In addition, in this embodiment, the detection circuit may include an A / D conversion circuit that performs A / D conversion on the source voltage, a subtraction circuit that determines a change value in the source voltage based on the A / D converted value of the source voltage from the A / D conversion circuit, and a comparison circuit that compares the change value with a reference value and outputs an active detection signal when it determines that the change value is equal to or greater than the reference value.

[0072] In this way, it becomes possible to obtain the change value of the source voltage by the subtraction circuit based on the value obtained by A / D converting the source voltage by the A / D conversion circuit.

[0073] This embodiment may also include a register for storing a reference value.

[0074] In this way, an appropriate reference value corresponding to the load capacitance can be stored in a register, and based on the comparison result between this reference value and the change in the source voltage, the detection signal can be made active and the charge pump operation can be stopped.

[0075] In this embodiment, the charge pump control circuit may output a control clock signal to the charge pump circuit that controls the charge pump operation based on the charge pump clock signal, and may stop the control clock signal when the detection signal is active.

[0076] In this way, for example, when the detection signal is inactive, a control clock signal based on the charge pump clock signal is output to the charge pump circuit to perform charge pump operation, and when the detection signal becomes active, the control clock signal stops and the charge pump operation stops.

[0077] In this embodiment, the charge pump control circuit may stop the charge pump operation when the detection signal becomes active, and the detection circuit may output an inactive detection signal when it determines that the change value that decreased during the period when the charge pump operation was stopped has fallen below a reference value.The charge pump control circuit may then resume the charge pump operation when the detection signal becomes inactive.

[0078] In this way, when the change in the source voltage decreases due to the stop of the charge pump operation and falls below the reference value, the detection signal becomes inactive and the charge pump operation is resumed.

[0079] In addition, in this embodiment, the detection circuit may output an active detection signal when it determines that the increased change value during the period after the charge pump operation is resumed is equal to or greater than a reference value, and the charge pump control circuit may stop the charge pump operation when the detection signal becomes active.

[0080] In this way, when the charge pump operation is resumed and the change in the source voltage increases and reaches or exceeds the reference value, the detection signal becomes active and the charge pump operation is stopped again.

[0081] In addition, this embodiment may include a regulator that outputs a regulated voltage by regulating the power supply voltage of the power supply node, and the charge pump circuit may output a gate control voltage to the gate node of the N-type transistor by performing a charge pump operation based on the regulated voltage.

[0082] In this way, the boosted voltage based on the regulated voltage is applied as the gate-source voltage of the N-type transistor, turning it on and allowing the power supply voltage to be supplied to the load via the N-type transistor.

[0083] The electronic device of this embodiment may include the circuit device described above and an N-type transistor.

[0084] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the circuit device, electronic device, detection circuit, charge pump control circuit, charge pump circuit, load, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0085] 10...electronic device, 11...N-type transistor, 12...boosting capacitor, 20...circuit device, 30...detection circuit, 32...A / D conversion circuit, 33...subtraction circuit, 34...comparison circuit, 35...register, 40...charge pump control circuit, 42...control clock signal generation circuit, 50...charge pump circuit, 52...drive circuit, 53...control circuit, 54...gate control circuit, 60...regulator, 90...load, CHV...change value, CK...control clock signal, CPCK...charge pump clock signal, DRV...gate control voltage, DT...detection signal, IB...current, MSCK...measurement clock signal, NL...node, NV...power supply node, RFV...reference value, VCC...power supply voltage, VCO...source voltage, VRG...regulated voltage

Claims

1. A circuit device for controlling an N-type transistor provided between a load node and a power supply node, a charge pump circuit that performs a charge pump operation to output a gate control voltage to the gate of the N-type transistor that is higher than a source voltage of the N-type transistor; a detection circuit that detects a change in the source voltage of the N-type transistor and outputs a detection signal that becomes active when it is determined that the change is equal to or greater than a reference value; a charge pump control circuit that stops the charge pump operation of the charge pump circuit when the detection signal becomes active; A circuit device comprising:

2. 2. The circuit device according to claim 1, The detection circuit detecting the source voltage of the N-type transistor at a detection interval based on a measurement clock signal; The circuit device detects the change value based on a difference between the detected source voltage and the source voltage detected immediately before in the detection interval.

3. 3. The circuit device according to claim 2, The circuit device is characterized in that the detection interval is shorter than the clock interval of a charge pump clock signal used for the charge pump operation.

4. 2. The circuit device according to claim 1, The detection circuit an A / D conversion circuit for A / D converting the source voltage; a subtraction circuit that determines the change in the source voltage based on the A / D converted value of the source voltage from the A / D conversion circuit; a comparison circuit that compares the change value with the reference value and outputs the detection signal in an active state when it is determined that the change value is equal to or greater than the reference value; A circuit device comprising:

5. 2. The circuit device according to claim 1, A circuit device comprising a register for storing the reference value.

6. 2. The circuit device according to claim 1, The charge pump control circuit outputting a control clock signal to the charge pump circuit to control the charge pump operation based on the charge pump clock signal; A circuit device, characterized in that when the detection signal is active, the control clock signal is stopped.

7. 2. The circuit device according to claim 1, The charge pump control circuit When the detection signal becomes active, the charge pump operation is stopped; The detection circuit outputting an inactive detection signal when it is determined that the change value that has decreased during the period in which the charge pump operation is stopped has fallen below the reference value; The charge pump control circuit When the detection signal becomes inactive, the circuit device resumes the charge pump operation.

8. In claim 7, The detection circuit outputting an active detection signal when it is determined that the increased change value during the period after the charge pump operation is resumed is equal to or greater than the reference value; The charge pump control circuit When the detection signal becomes active, the circuit device stops the charge pump operation.

9. 2. The circuit device according to claim 1, a regulator that outputs a regulated voltage by regulating a power supply voltage of the power supply node; The charge pump circuit A circuit device characterized in that the charge pump operation is performed based on the regulated voltage, thereby outputting the gate control voltage to the gate node of the N-type transistor.

10. A circuit arrangement according to any one of claims 1 to 9; the N-type transistor; 1. An electronic device comprising:

Images