Semiconductor device

Abstract

To provide a semiconductor device with a novel structure, in which a storage content can be held even under no power supply situations, and writing is possible without limitation on the number of times.SOLUTION: A semiconductor device is formed of a material that can sufficiently reduce an off current of a transistor, for example, an oxide semiconductor material that is a wide-gap semiconductor. By the use of the semiconductor material that can sufficiently reduce the off current of the transistor, the information can be held for a long time. Moreover, timing of changing a potential of a signal line is delayed from timing of changing a potential of a writing word line. Thus, wrong data writing can be prevented.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a method for driving the same. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. and non-volatile memory, which retains its contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] According to the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Every time information is read, a write operation is required again. In transistors, leakage current (off-state current) between the source and drain in the off state Therefore, even when the transistor is not selected, charge flows in and out, causing data Therefore, the write operation (refresh operation) is performed again at a predetermined interval. It is difficult to reduce power consumption sufficiently. Therefore, for long-term memory retention, other methods using magnetic or optical materials are required. This requires a storage device.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem in that the memory element will stop functioning after a certain number of writes. To mitigate the effect of this problem, for example, the number of writes to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to inject or remove charge from the floating gate. This requires a high voltage and a circuit for it. It takes a relatively long time to write or erase data, and it is not easy to speed up writing or erasing. There is also the problem that: [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization. [Means for solving the problem]

[0011] In the disclosed invention, a material that can sufficiently reduce the off-state current of a transistor, such as For example, a semiconductor device is constructed using an oxide semiconductor material, which is a wide-gap semiconductor. By using semiconductor materials that can sufficiently reduce the off-state current of the transistor, It is possible to retain information for a long period of time.

[0012] In addition, the timing of the potential change of the signal line is set to be shorter than the timing of the potential change of the write word line. This makes it possible to prevent errors in writing data.

[0013] One aspect of the present invention is a semiconductor memory device including a write word line, a read word line, a bit line, and a source line. a signal line, a memory cell array including a plurality of memory cells, a first driving circuit, and a second driving circuit. and an operating circuit, and each of the memory cells has a first gate electrode, a first source electrode, a first drain electrode, a a first transistor including a drain electrode and a first channel forming region; a second electrode, a second source electrode, a second drain electrode, and a second channel forming region; a first channel forming region and a second channel forming region; a first gate electrode and a second drain electrode, the first gate electrode and the second drain electrode being configured to include a semiconductor material different from the semiconductor material of the first region; and one of the electrodes of the capacitor are electrically connected to form a node where a charge is held, The first driving circuit is electrically connected to the first drain electrode via a bit line, and The second drive circuit is electrically connected to the second source electrode through a signal line. The other electrode of the capacitor element is electrically connected to the other electrode of the capacitor element via a write word line. The second gate electrode is electrically connected to the second drive circuit. The semiconductor device has a function of delaying a signal input to a signal line relative to a signal input to a signal line.

[0014] Furthermore, one aspect of the present invention is a semiconductor memory device including a write word line, a read word line, a bit line, and a source line. a first drive circuit; a second drive circuit; a second signal line; a memory cell array including a plurality of memory cells; The memory cell has a first gate electrode, a first storage capacitor, a second drive circuit, and a delay circuit. a first transistor including a source electrode, a first drain electrode, and a first channel forming region; a second gate electrode, a second source electrode, a second drain electrode, and a second channel-type a second transistor including a first channel formation region and a capacitor element, a first gate electrode including a semiconductor material different from that of the second channel formation region; The second drain electrode and one of the electrodes of the capacitance element are electrically connected to each other and hold electric charges. The first driving circuit is electrically connected to the first drain electrode via the bit line. and is electrically connected to the second source electrode via a signal line, and The circuit is electrically connected to the other electrode of the capacitor element via a read word line, and The delay circuit is electrically connected to the signal line and the second gate electrode through the write word line. It is a semiconductor device that is electrically connected.

[0015] Furthermore, one aspect of the present invention is a semiconductor memory device including a write word line, a read word line, a bit line, and a source line. a first drive circuit; a second drive circuit; a second signal line; a memory cell array including a plurality of memory cells; and two driving circuits, and each of the memory cells has a first gate electrode, a first source electrode, and a second a first transistor including a first drain electrode and a first channel forming region; a second source electrode, a second drain electrode, and a second channel forming region. The second transistor and the capacitor element are included, and the first channel forming region is The first gate electrode and the second drain electrode are formed of a semiconductor material different from that of the drain electrode. The gate electrode and one of the electrodes of the capacitance element are electrically connected to form a node where charge is held. the first driving circuit is electrically connected to the first drain electrode via a bit line; The second driving circuit is electrically connected to the second source electrode through a signal line. The other electrode of the capacitor element is electrically connected to the other electrode of the capacitor element through the output word line. The first gate electrode is electrically connected to the second gate electrode through a line, and the first buffer circuit is connected to the signal line. A second buffer circuit is connected to the write word line, and a first buffer circuit is connected to the write word line. The channel length of the transistor constituting the second buffer circuit is It is a semiconductor device that is longer than the channel length.

[0016] In the above configuration, a potential converter that outputs a potential higher than the power supply potential to the second driver circuit is provided. The configuration may include a circuit.

[0017] In the above configuration, the plurality of memory cells are connected in series between a bit line and a source line. is connected to.

[0018] In the above configuration, a wiring is provided between the bit line and the plurality of memory cells connected in series. The wires are electrically connected.

[0019] In the above configuration, a switch for controlling the connection between the bit line and the signal line and the output terminal is provided. a switch for controlling the connection between the bit line and the signal line and the input terminal; and wiring. The bit lines and signal lines are electrically connected.

[0020] In the above structure, the second channel formation region of the second transistor is formed of an oxide semiconductor. It is configured to include a conductor.

[0021] In the above configuration, the second driving circuit includes a potential conversion circuit and a write word The level shift circuit is electrically connected to the line or the read word line.

[0022] Note that in the above description, a transistor may be formed using an oxide semiconductor. The present invention is not limited to this. For example, wide-gap materials such as silicon carbide (more specifically, e.g., A semiconductor material having an energy gap Eg of greater than 3 eV may also be used.

[0023] In this specification, the terms "above" and "below" refer to the positional relationship of a component "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly below." " excludes those that include other components between the gate insulating layer and the gate electrode. do not have.

[0024] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0025] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It shall be possible.

[0026] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0027] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0028] Since a transistor using an oxide semiconductor has an extremely small off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced sufficiently. It is desirable that the potential is fixed) but the memory contents are retained for a long period of time. It is possible.

[0029] In addition, the semiconductor device according to the disclosed invention does not require a high voltage for writing information. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high-speed operation can be easily realized. Another advantage is that no action is required.

[0030] Furthermore, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. Therefore, by using this in combination with a transistor using an oxide semiconductor, This makes it possible to ensure sufficient high speed of the operation of the device (for example, the operation of reading information). In addition, transistors using materials other than oxide semiconductors are being developed for various applications requiring high-speed operation. Circuits (logic circuits, driver circuits, etc.) can be suitably realized.

[0031] In this way, transistors using materials other than oxide semiconductors (more broadly speaking, transistors that can operate satisfactorily) and transistors that use oxide semiconductors (or, more broadly, transistors that can operate satisfactorily) By integrating a transistor with a particularly low off-state current, It is possible to realize a semiconductor device that [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 2] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 3] Timing chart. [Figure 4] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 5] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 6] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 7] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 8] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 9] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device; [Figure 10] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 14] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 15] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 16]FIG. 10 is a circuit diagram for evaluating the characteristics of a transistor including an oxide semiconductor. [Figure 17] FIG. 10 is a timing chart for evaluating characteristics of a transistor including an oxide semiconductor. [Figure 18] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 19] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 20] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 21] A diagram showing the results of a memory window width survey. [Figure 22] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 23] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 24] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 25] Circuit diagram of semiconductor device [Figure 26] Cross-sectional and plan views of a semiconductor device [Figure 27] Circuit diagram of semiconductor device DETAILED DESCRIPTION OF THE INVENTION

[0033] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0034] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0035] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0036] (Embodiment 1) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the disclosed invention will be described. 1 to 3. Note that in the circuit diagrams, To indicate that it is a transistor, the symbol OS may also be added.

[0037] <Basic circuit> First, the basic circuit configuration and its operation will be explained with reference to FIG. In the semiconductor device shown in A-1), a first wiring (1st Line) and a transistor 1 The drain electrode (or source electrode) of 60 is electrically connected to the second wiring (2nd Line) and the source electrode (or drain electrode) of the transistor 160 are electrically Also, the third line (3rd Line) and the source of the transistor 162 are connected The electrode (or drain electrode) is electrically connected to the fourth line (4th Line). and the gate electrode of the transistor 162 are electrically connected. The gate electrode of transistor 160 and the drain electrode (or source electrode) of transistor 162 are , electrically connected to one of the electrodes of the capacitor element 164 and connected to the fifth line (5th Line). The other electrode of the capacitor 164 is electrically connected to the first electrode.

[0038] Here, the transistor 162 is, for example, a transistor including an oxide semiconductor. A transistor including an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 162 is turned off, the transistor 160 The potential of the gate electrode can be maintained for an extremely long period of time. By having the electrode 164, the charge applied to the gate electrode of the transistor 160 can be retained. This makes it easier to read the stored information.

[0039] The transistor 160 is not particularly limited. From the viewpoint of this, for example, transistors using single crystal silicon, which are switching It is preferable to use high speed transistors.

[0040] As shown in FIG. 1B, a structure without the capacitor 164 is also possible. .

[0041] In the semiconductor device illustrated in FIG. 1A-1, the potential of the gate electrode of the transistor 160 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0042] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The transistor 162 is set to a potential that turns it on, thereby turning it on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 1 That is, a predetermined charge is applied to the gate electrode of the transistor 160. Here, two different potentials are applied to the charge (hereinafter, the low potential is applied). Charge Q L , the charge that gives the high potential is the charge Q H (The following two terms are considered to be given: It is also possible to apply charges that give three or more different potentials to improve the storage capacity. After that, the potential of the fourth wiring may be set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate of the transistor 160 The charge applied to the electrode is retained (retention).

[0043] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long time.

[0044] Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the second wiring, In this state, when an appropriate potential (read potential) is applied to the fifth wire, the gate of the transistor 160 The first wiring has a different potential depending on the amount of charge held in the transistor electrode. If the transistor 160 is an n-channel type, then the gate electrode of the transistor 160 is connected to Q H is given The apparent threshold V th_H is connected to the gate electrode of transistor 160. L but The apparent threshold V for a given th_L This is because the The threshold voltage is the fifth wire required to turn on transistor 160. Therefore, the potential of the fifth wiring is V th_H and V th_L Inside By setting the potential V0 between the gate electrodes of the transistors 160, the charge applied to the gate electrodes of the transistors 160 can be determined. For example, in writing, H is given, the potential of the fifth wire is V 0(>V th_H ), transistor 160 is in the "ON state." Q L is given When this happens, the potential of the fifth wiring becomes V0( <V th_L ) even if transistor 16 0 remains in the "off state." Therefore, by looking at the potential of the first wiring, The information stored in the memory can be read.

[0045] When memory cells are arranged in an array, only the information of the desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and When the information of the other memory cells is not read, the transistor 160 is connected between the memory cells. When they are connected in parallel, the fifth array of memory cells that are not the object of reading is line so that transistor 160 is in the "off state" regardless of the state of its gate electrode. Such a potential, that is, V th_H A smaller potential can be applied between the memory cells. When the transistors 160 are connected in series, they are not the target of reading. The transistor 160 is connected to the fifth wiring of the memory cell regardless of the state of the gate electrode. The potential at which the "on state" is reached, i.e., V th_L Apply a larger potential to the fifth wire. That's fine.

[0046] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held when the transistor 162 is turned on. This turns on the transistor 162. (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off the transistor 162, the gate voltage of the transistor 160 is The poles are given a charge related to the new information.

[0047] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need to extract charge from the floating gate using a high voltage, and the erase operation In other words, it is possible to suppress the decrease in operating speed caused by the above. It will be revealed.

[0048] The drain electrode (or source electrode) of the transistor 162 is connected to the transistor 160 By electrically connecting the gate electrode of the It has the same effect as the floating gate of a floating gate type transistor. In this case, the drain electrode (or source electrode) of the transistor 162 and the transistor 16 The part where the gate electrode of transistor 0 is electrically connected is sometimes called the node FG. When 162 is off, the node FG can be seen as buried in an insulator, and the node Charge is held in the FG. The off-state current of the transistor 162 including an oxide semiconductor is The transistor is less than 1 / 100,000th of the size of a transistor formed by silicon semiconductors, etc. It is possible to ignore the loss of charge stored in node FG due to leakage of capacitor 162. In other words, the transistor 162 including an oxide semiconductor can generate information without power supply. It is possible to realize a non-volatile memory device capable of holding information.

[0049] For example, if the off-state current of the transistor 162 at room temperature (25° C.) is 10 zA (1 zA (zepto)), ampere) is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 164 is about 10 fF. In some cases, at least 10 4 It is possible to hold data for more than 10 seconds. However, it goes without saying that this will vary depending on the transistor characteristics and capacitance value.

[0050] In addition, in the semiconductor device of the disclosed invention, the conventional floating gate type transistor There is no problem of deterioration of the gate insulating film (tunnel insulating film) that has been pointed out in In other words, the problem of the gate when injecting electrons into the floating gate, which was previously considered This solves the problem of deterioration of the insulating film. This means that there is no The high voltage required for writing and erasing data in a memory cell is also unnecessary.

[0051] The semiconductor device shown in FIG. 1(A-1) includes elements such as transistors that constitute the semiconductor device. It can be thought of as including resistance and capacitance as shown in Figure 1(A-2). That is, in FIG. 1(A-2), the transistor 160 and the capacitor 164 are respectively It is considered to be composed of resistance and capacitance. R1 and C1 are The resistance value R1 is the resistance value and capacitance value of the capacitance element 164. R2 and C2 correspond to the resistance of the insulating layer. The resistance and capacitance of the transistor 160 are shown in FIG. The capacitance C2 corresponds to the resistance value of the gate insulating layer, and the capacitance C2 is the so-called gate capacitance (the capacitance between the gate electrode and The capacitance formed between the source electrode or drain electrode, and the gate electrode and the channel type This corresponds to the capacitance value of the capacitance formed between the gate and gate regions.

[0052] The resistance between the source and drain electrodes when the transistor 162 is in the off state (actual If the gate leakage current of the transistor 162 is sufficiently small, then Under the small condition, R1 and R2 are R1 ≥ ROS (R1 is greater than or equal to ROS), R2 ≥ R If S (R2 is greater than or equal to ROS) is satisfied, the charge retention period (information retention period) The off-state current of the transistor 162 is primarily determined by the off-state current of the transistor 162.

[0053] On the other hand, if this condition is not satisfied, the off-state current of the transistor 162 is not sufficiently small. In addition, it becomes difficult to secure a sufficient retention period. Leakage current (e.g., between the source and gate electrodes of transistor 160) This is because the leakage current that occurs is large. The semiconductor device is such that R1 ≥ ROS (R1 is equal to or greater than ROS) and R2 ≥ ROS (R2 is equal to or greater than ROS). It is desirable that the relationship be such that

[0054] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1≧C2 (C1 is equal to or greater than C2). By increasing C1, when the potential of the node FG is controlled by the fifth wiring, The potential of the wiring can be efficiently applied to the node FG, and the potential of the fifth wiring can be applied to the node FG. The potential difference between potentials (for example, the read potential and the non-read potential) can be kept low. This is because

[0055] In this way, by satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are the gate insulating layer of the transistor 160 and the capacitance element 164. The same applies to C1 and C2. Therefore, the gate insulating layer It is desirable to appropriately set the materials and thicknesses of the layers so as to satisfy the above-mentioned relationship.

[0056] In the semiconductor device shown in this embodiment, the node FG is connected to a flow The floating gate of the present embodiment functions in the same way as the floating gate of a floating gate transistor. The node FG has characteristics that are essentially different from the floating gate of flash memory, etc. It has the following characteristics.

[0057] In flash memory, the potential applied to the control gate is high, so that The cells are spaced apart to avoid affecting the floating gates of adjacent cells. This is one of the factors that hinders the high integration of semiconductor devices. This is due to the flash memory technology that generates a tunnel current by applying a high electric field. This is due to the fundamental principles of the harpoon.

[0058] On the other hand, the semiconductor device according to this embodiment is a switch of a transistor using an oxide semiconductor. It operates by tunneling and does not use the principle of charge injection by tunnel current as described above. In other words, unlike flash memory, a high electric field for injecting charges is not required. Therefore, there is no need to consider the influence of the high electric field caused by the control gate on the adjacent cells. This makes it easier to achieve high integration.

[0059] In addition, the fact that a high electric field is not required and large peripheral circuits (such as a boost circuit) are not required is also an advantage of flash memory. For example, when the voltage applied to the memory cell according to this embodiment is The maximum and minimum voltages applied simultaneously to each terminal of the memory cell The maximum value of the difference) is the maximum value of the difference in one memory cell when writing two-level (1-bit) information. , 5V or less, preferably 3V or less.

[0060] Furthermore, the relative dielectric constant εr1 of the insulating layer constituting the capacitance element 164 and the dielectric constant εr2 of the insulating layer constituting the transistor 160 are When the relative dielectric constant εr2 of the gate insulating layer is made different from that of the capacitance element 164, the area S 1 and the area S2 of the region having the gate capacitance of the transistor 160, and 2·S2≧S 1 (2·S2 is greater than or equal to S1), preferably S2≧S1 (S2 is greater than or equal to S1), while C It is easy to realize 1≧C2 (C1 is equal to or greater than C2). The insulating layer constituting the element 164 is a film made of a high-k material such as hafnium oxide. or the product of a film made of a high-k material such as hafnium oxide and a film made of an oxide semiconductor. The layer structure is used to set εr1 to 10 or more, preferably 15 or more, and the transistor 160 is constructed. The gate insulating layer is made of silicon oxide, and the range of 3≦εr2≦4 (εr2 is 3 (4 or less).

[0061] By using such a configuration in combination, the semiconductor device according to the disclosed invention can be further improved. Integration is possible.

[0062] In order to increase the memory capacity of a semiconductor device, in addition to increasing the integration density, a method of multi-level data storage is also being adopted. For example, it is possible to write three or more levels of information into one memory cell. This allows for a larger memory capacity than when writing two-level (1-bit) information. For example, the charge Q L , a charge Q that gives a high potential H In addition , By applying a charge Q that gives another potential to the gate electrode of the transistor 160, multi-values are realized. In this case, a relatively large circuit configuration (for example, 15F 2 ~50 F 2 Even if F is used (e.g., F is the minimum processing dimension), sufficient storage capacity can be ensured.

[0063] <Application Example 1> Next, a more specific circuit configuration and operation using the circuit shown in Figure 1 will be described in Figures 2 and 3. This will be explained with reference to FIG.

[0064] FIG. 2A is an example of a circuit diagram of a semiconductor device having (m×n) memory cells 170. The configuration of the memory cell 170 in FIG. 2 is the same as that in FIG. 1(A-1). As shown in (B), the first wiring in FIG. 1(A-1) corresponds to the bit line in FIG. 2(B). BL, and the second wiring in FIG. 1(A-1) corresponds to the source line SL in FIG. 2(B). The third wiring in FIG. 1(A-1) corresponds to the signal line S in FIG. 2(B), and The fourth wiring in FIG. 1(A-1) corresponds to the write word line WWL in FIG. 2(B). The fifth wiring in FIG. 1(A-1) corresponds to the read word line RWL in FIG. 2(B). However, in FIG. 2A, the memory cells 170(1,1) to (1,n) in the first row Only the memory cells 170(m,1) to (m,n) in the mth row are directly connected to the bit line BL. Only the memory cells 170 in the other rows are directly connected to the source line SL. The cell 170 is electrically connected to the bit line BL and the source line SL.

[0065] The semiconductor device shown in FIG. 2 has m (m is an integer of 2 or more) write word lines WWL and m n read word lines RWL, n source lines SL (n is an integer of 2 or more), and n bit lines The memory cells 170 are arranged in a matrix of m rows by n columns. The memory cell array is arranged in a rectangular shape, and n bit lines BL and n signal lines S are connected. The first drive circuit 190 connected to the m write word lines WWL and the m read word lines and a second drive circuit 192 connected to the word line RWL. The second drive circuit 192 is connected by a wiring WRITE and a wiring READ. .

[0066] In addition, an address selection signal line A is connected to the second drive circuit 192. The selection signal line A is a wiring that transmits a signal for selecting an address in the row direction of the memory cells.

[0067] Regarding the first driving circuit 190 and the second driving circuit 192 shown in FIG. 2(A), FIG. The first drive circuit 190 and the second drive circuit 192 are connected to the wiring WRITE and are connected by a wire READ.

[0068] The first driving circuit 190 includes a read circuit 211, a control circuit 212, and a delay circuit 213. , and a buffer circuit 214. The input terminal IN is connected to a control circuit 212, a delay The signal line S is connected to the bit line 213 and the buffer circuit 214. The read circuit 211 connected to the line BL is connected to the output terminal OUT.

[0069] The second driving circuit 192 includes a decoder circuit 221, a control circuit 222, and a buffer circuit 22 3, and a buffer circuit 224. The address selection signal line A is connected to a decoder circuit The decoder circuit 221 is connected to a control circuit 222. The control circuit 222 is connected to the write word line WWL via a buffer circuit 223. The control circuit 222 also supplies the read word line RWL via a buffer circuit 224. is connected to.

[0070] Data writing, storage, and reading are basically the same as in Figure 1. The specific write operation is as follows. As an example, the write operation shown in FIG. 2(B) is used here. 23, the node FG is supplied with a potential V1 (a potential lower than the power supply potential VDD) or a base potential V2. The following explains the case where either the potential applied to node FG or the potential applied to node GND is applied. The relationship is not limited to this. In addition, when the potential V1 is applied to the node FG, the data held is Data "1" is the data that is retained when the reference potential GND is applied to node FG. 0”.

[0071] First, data is written to the memory cell 170 to be written. The potential of the write word line RWL is set to GND, and the potential of the write word line WWL is set to V2 (a voltage higher than V1). A memory cell 170 to be written is selected as a potential (eg, VDD).

[0072] When writing data "0" to the memory cell 170, GND is applied to the signal line S, and When writing data "1" to the reseller 170, V2 is applied to the signal line S. Since the potential of the write word line WWL is V2, V1 can be applied to the node FG. It is possible.

[0073] Data is retained by setting the potential of the read word line RWL and the potential of the write word line WWL. , GND.

[0074] When the potential of the read word line RWL is fixed to GND, the potential of the node FG becomes In other words, when V1, which is data "1", is applied to node FG, The potential of the node FG becomes V1, and GND, which is data "0", is applied to the node FG. If the potential of the node FG is GND,

[0075] Since GND is applied to the write word line WWL, data "1" and data "0" are When either of the above is written, the transistor 162 is turned off. Since the off-state current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is is maintained for

[0076] Data is read from the read word line R connected to the memory cell 170 to be read. The potential of the WL and the write word line WWL is set to GND. The potential of the read word line RWL connected to the memory cell 170 that is not written is set to V2. This is done by setting the potential of the write word line WWL to GND.

[0077] The potential of the read word line RWL connected to the memory cell 170 to be read is set to GND. Then, V1, which is data "1", is applied to the node FG of the memory cell 170 to be read. On the other hand, when the data is applied to the node FG, the transistor 160 is turned on. If GND is 0", transistor 160 is in an off state.

[0078] Also, the voltage of the read word line RWL connected to the memory cell 170 that is not the target for reading is When the potential of the write word line WWL is V2 and the potential of the write word line WWL is GND, If data "1" is written to the memory cell 170 that does not have data "0", is written, transistor 160 is turned on.

[0079] That is, the above-described read operation stores data "1" in the memory cell 170 to be read. If it has been written, the transistor 160 is turned on, and the potential of the bit line BL When data "0" is written, the transistor 160 is turned on. The potential of the bit line BL at the start of reading is maintained or increased.

[0080] When the above-described configuration is adopted, the data holding operation and the data reading operation are The potential of the read word line RWL and the potential of the write word line WWL are GND. In other words, data "1" is written to all memory cells 170 in the target column. In this case, the transistor 160 is turned on, and the signal is stored in the storage device regardless of whether it is being held or read. Therefore, the source line SL and the bit line BL are electrically connected. In order to sufficiently suppress the power consumption caused by such a situation, It is preferable to provide a selection transistor between 70 and the source line SL or the bit line BL. Alternatively, the potentials of the source line SL and the bit line BL may be made equal except during the read operation. stomach.

[0081] FIG. 3 shows an example of a timing chart showing a more detailed operation of the semiconductor device shown in FIG. The names such as READ and A in the timing chart indicate the current If there are multiple wires with the same function, the wire They are distinguished by adding _1, _2, etc. to the end of the name. Therefore, the semiconductor device in which the memory cells 170 are arranged in 2 (rows) x 2 (columns) will be described as an example. However, the disclosed invention is not limited thereto.

[0082] The timing chart shown in FIG. 3 shows the timing when data “1” is written to all memory cells (write Write 1), then read all the written data (Read 1), then read the first row Data "1" is written to the memory cell in the first column and the memory cell in the second row and second column. Write data "0" to the memory cell at row 1, column 2 and the memory cell at row 2, column 1 (write Write 2), and then read all the written data (Read 2). It indicates the relationship of rank.

[0083] In write 1, WRITE is set to high potential and READ is set to low potential to write to the memory cell. The second driving circuit 192 drives the row corresponding to the potentials of A_1 and A_2. A selection signal is output to RWL and WWL. Here, when A_1 is at a high potential, the first row When A_2 is at a high potential, the second row is selected. The WWL of the selected row is at high potential, and the RWL is at low potential regardless of whether it is selected or not. .

[0084] In write 1, data “1” is written to all memory cells, so the row selection type is In accordance with the timing, S_1 and S_2 are set to high potential. The signal input period of S_1 and S_2 should be longer than the signal input period of WWL. The signal input of S_2 is delayed from the signal input of WWL. Signal input period of S_1 and S_2 is short, or the signal inputs of S_1 and S_2 are earlier than the signal input of WWL, This is because there is a possibility that the writing to the memory cell will be insufficient. For example, a delay circuit 213 is connected to S_1 or S_2 to delay the signal input of S_1 or S_2. The output can be delayed from the signal input of WWL. The size (for example, channel length) of the transistors constituting the FA circuit 214 is connected to WWL. The size (for example, channel length) of the transistor constituting the buffer circuit 223 to be connected is larger than that of the transistor. By increasing the driving power, the signal inputs of S_1 and S_2 can be connected to the signal input of WWL. Alternatively, a buffer circuit 214 connected to S_1 or S_2 may be configured. The size (e.g., channel width) of the transistor to be connected to the WWL is determined by the buffer circuit 2 The size (e.g., channel width) of the transistor constituting 23 is made smaller, and the driving capacity is By dropping the signal input of S_1 and S_2, the signal input of WWL can be delayed. The potentials of BL_1 and BL_2 do not pose a significant problem during writing (high voltage (It may be at a high or low potential).

[0085] In read 1, WRITE is set to low potential and READ is set to high potential, and data is read from the memory cell. The second driving circuit 192 selects rows corresponding to A_1 and A_2. A signal is output to RWL and WWL. Here, when A_1 is high, the first row When A_2 is at a high potential, the second row is selected. L is at low potential, RWL of the unselected row is at high potential, and WWL is at high potential. The voltage will be low regardless of the selection.

[0086] By the above operation, BL_1 and BL_2 store the data stored in the memory cells of the selected row. The potentials of S_1 and S_2 are given according to the data being read. Sometimes it's not a problem.

[0087] The relationship of the potentials of the wirings in write 2 is the same as in write 1. Data "1" is written to the memory cell at row 1, column 1 and the memory cell at row 2, column 2. Then, data "0" is written to the memory cell at the first row, second column and the memory cell at the second row, first column. To achieve this, S_1 and S_2 are set to low or high potential according to the row selection timing. do.

[0088] The relationship of the potentials of the wirings in readout 2 is the same as that in readout 1. A potential corresponding to the data stored in the memory cells of the selected row is applied to BL_1 and BL_2. You can see that this can be achieved.

[0089] In the above-mentioned write operation, the signal input to the write word line WWL is higher than the signal input to the write word line WWL. In order to delay the signal input to the signal line S, for example, the delay circuit shown in FIG. It is preferable to provide it in the circuit 190 and connect it to the signal line S. Connecting the delay circuit to the signal line S Therefore, the change in the potential of the signal line S can be delayed from the change in the potential of the write word line WWL. This makes it possible to suppress errors in writing to the memory cell 170.

[0090] Next, the delay circuit 213 provided in the first driving circuit 190 shown in FIG. 23 will be described with reference to FIG. This will be explained with reference to Figures 22A, 22B, 22C, 22D, and 22C.

[0091] The delay circuit 213 is a circuit in which an even number of inverters are connected in series as shown in FIG. As shown in Figure 4(B), an even number of interconnections can be used. As shown in Figure 4(C), an even number of capacitors are connected in series. A resistor may be added to the inverter. A resistor and a capacitor may be added to an even number of inverter circuits connected to the .

[0092] Alternatively, in the above-described write operation, the signal input to the write word line WWL is In order to delay the signal input to the signal line S, the first driving circuit 190 and the second driving circuit In the buffer circuit provided in the circuit 192, the buffer circuit The size (e.g., channel length) of the transistor of the circuit 214 is controlled by the second driving circuit 192. The size of the transistor of the buffer circuit 223 may be larger than that of the transistor of the first The size of the transistor of the buffer circuit 214 included in the driving circuit 190 (for example, the channel width) is determined by the size (e.g., For example, it may be smaller than the channel width. The change in the potential of the signal line S can be delayed by the change in the potential of the memory cell 170. This can reduce input errors.

[0093] Next, the readout circuit 211 provided in the second drive circuit 192 shown in FIG. 22 for further explanation.

[0094] FIG. 22(A) shows a schematic diagram of a readout circuit. The readout circuit is composed of a transistor and a sensor. It has a amplifier circuit.

[0095] When reading, terminal A is connected to the bit line BL to which the memory cell to be read is connected. A bias potential Vbias is applied to the gate electrode of the transistor, and The potential of the electrode is controlled.

[0096] The memory cell 170 exhibits different resistance values depending on the data stored therein. When the transistor 160 of the selected memory cell 170 is in an on state, it is in a low resistance state. When the transistor 160 of the selected memory cell 170 is in an off state, it is in a high resistance state. .

[0097] When the memory cell is in a high resistance state, the potential at terminal A becomes higher than the reference potential Vref, and the sense The amplifier circuit outputs a potential (data "0") corresponding to the potential of terminal A. When the resistor is in a low resistance state, the potential at terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit The path outputs a potential (data "1") corresponding to the potential of terminal A.

[0098] In this way, data can be read from the memory cell by using the read circuit. Note that the read circuit of this embodiment is an example. Other known circuits may be used. Also, the read circuit may have a precharge circuit. Instead of the reference potential Vref a reference bit line may be connected.

[0099] FIG. 22(B) shows a differential sense amplifier which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin( + ) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output and becomes so.

[0100] FIG. 22(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the signal Sp is set to High and the signal Sn is set to Low to cut off the power supply potential (Vdd). Then, the potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low and the signal S n is set to High to supply the power supply potential (Vdd), if the potentials for comparison V1in and V2 in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is Hig h and becomes so. By using such a relationship, the difference between V1in and V2in can be amplified.

[0101] <Application Example 2> Next, a circuit configuration different from the circuit configuration shown in FIG. 2 will be described with reference to FIG. 5.

[0102] FIG. 5A is an example of a circuit diagram of a semiconductor device having (m×n) memory cells 170. The configuration of the memory cell 170 in FIG. 5(A) is the same as that in FIG. 2(B), so a detailed description will not be given. The literal meaning is omitted.

[0103] The semiconductor device shown in FIG. 5A has m (m is an integer of 2 or more) write word lines WWL and , m read word lines RWL, n source lines SL (n is an integer of 2 or more), and n The bit lines BL, n signal lines S, and memory cells 170 are arranged vertically (m rows) by horizontally (n columns). a memory cell array arranged in a matrix, a potential conversion circuit 180, and n bit a first driver circuit 190 connected to the line BL and n signal lines S; a second driver circuit 192 connected to the line WWL and the m read word lines RWL; Here, the potential conversion circuit 180 is connected to the second driving circuit 192 by a wiring VHL. and outputs a potential (high potential: VH) higher than the power supply potential VDD to the second drive circuit 192. In this embodiment, the wiring WRITE and the wiring READ are connected to a potential conversion circuit 180, the potential is converted to match the output of the first drive circuit 190. However, the disclosed invention is not limited to this. 190 and the second driver circuit 192 are connected by a wiring WRITE and a wiring READ. It may also be configured not to be continuous.

[0104] In addition, an address selection signal line A is connected to the second drive circuit 192. The selection signal line A is a wiring that transmits a signal for selecting an address in the row direction of the memory cells.

[0105] Regarding the first driving circuit 190 and the second driving circuit 192 shown in FIG. 5(A), FIG. The first drive circuit 190 and the second drive circuit 192 are connected to the wiring WRITE and READ are connected by the wiring WRITE and wiring READ. are each connected to a potential conversion circuit 180.

[0106] The first driving circuit 190 includes a read circuit 211, a control circuit 212, and a delay circuit 213. , and a buffer circuit 214. The input terminal IN is connected to a control circuit 212, a delay The signal line S is connected to the bit line 213 and the buffer circuit 214. The read circuit 211 connected to the line BL is connected to the output terminal OUT.

[0107] The second driving circuit 192 includes a decoder circuit 221, a control circuit 222, and a buffer circuit 22 3, a buffer circuit 224, and a level shift circuit 225. The select signal line A is connected to the decoder circuit 221. , and is connected to a control circuit 222, which includes a level shift circuit 225 and a buffer circuit. The control circuit 22 is connected to the write word line WWL via a write circuit 223. 2 is connected to the read word line RWL via a buffer circuit 224. The read circuit 211 can be seen in FIG. 22, and the delay circuit 213 can be seen in FIG. 4. Here, GND or VH is output to the write word line WWL.

[0108] Data writing, storage, and reading are the same as in FIG. 2. However, in this configuration In this configuration, when writing, the potential of the write word line WWL is set to a potential higher than the power supply potential. Therefore, a sufficiently high potential can be applied to the node FG. This allows for longer data retention and improves data discrimination.

[0109] As an example of the potential conversion circuit 180, an example of a booster circuit that performs four-stage boosting is shown in FIG. In this case, the input terminal (here, the source terminal or the drain terminal) of the first transistor 1300 is The power supply potential VDD is supplied to the gate terminal (the terminal connected to the gate terminal). The output terminal of the first transistor 1300 (here, the source terminal or the drain terminal) The second transistor 131 is connected to the gate terminal (which is a terminal that is not connected to the gate terminal). The input terminal of the first capacitor 1350 is connected to one terminal of the second capacitor 1350. The output terminal of the transistor 1310 is connected to the input terminal of the third transistor 1320 and the second One terminal of the capacitance element 1360 is connected to the Although omitted, one terminal of the nth capacitance element is connected to the output terminal of the nth transistor. In Figure 6, the output of the final stage transistor The output terminal is connected to a transistor 1390 connected to a power supply VDD. For example, a configuration in which a capacitance connected to the ground potential GND is further added may be used. In FIG. 6, the output of the fifth transistor 1340 is the output VH of the boost circuit. This becomes:

[0110] Furthermore, the other terminal of the second capacitor 1360 and the other terminal of the fourth capacitor 1380 A clock signal CP_CLK is input to the other terminal of the first capacitance element 1350. The other terminal of the third capacitor element 1370 is connected to an inverted clock signal CP_CLK. That is, the clock signal CP_CLKB is input to the other end of the 2k-th capacitive element. A clock signal CP_CLK is input to one terminal of the (2k-1)th capacitive element, and the other terminal of the (2k-1)th capacitive element receives the clock signal CP_CLK. It can be said that the inverted clock signal CP_CLKB is input (k: natural number). The clock signal CP_CLK and the inverted clock signal CP_CLKB can be used interchangeably. can be done.

[0111] When the clock signal CP_CLK is low, that is, when the inverted clock signal CP_CLKB When is High, the second capacitance element 1360 and the fourth capacitance element 1380 are charged. The nodes N1 and N3 are electrically connected to the inverted clock signal CP_CLKB. The potential is a predetermined voltage (corresponding to the potential difference between High and Low of the clock signal CP_CLK). On the other hand, the node that is capacitively coupled with the clock signal CP_CLK is The potentials at N2 and node N4 are pulled down by a predetermined voltage.

[0112] As a result, the charge flows through the second transistor 1310 and the fourth transistor 1330. The potentials of the nodes N2 and N4 are raised to a predetermined value.

[0113] Next, when the clock signal CP_CLK goes high and the inverted clock signal goes low, The potentials of the nodes N2 and N4 are further increased. The potential of N3 is pulled down by a predetermined voltage.

[0114] This allows the first transistor 1300, the third transistor 1320, and the fifth transistor Charge moves through the resistor 1340, resulting in the nodes N1, N3 and N The potential of 5 is raised to a predetermined potential. The potential at V N5 =V N4(CP_CLK=High) >V N3(CP_CLK=Lo w) >V N2(CP_CLK=High) >V N1(CP_CLK=Low) >Vdd and The boost circuit configuration is limited to four-stage boosting. The number of stages in the booster circuit can be changed as needed.

[0115] Note that a transistor used in a booster circuit includes an oxide semiconductor having good off-state current characteristics. By using a transistor, the voltage holding time of each node can be increased.

[0116] Next, the level shift circuit 225 (level shifter) provided in the second drive circuit 192 will be described. and explain.

[0117] 7 and 8 show examples of boost level shift circuit diagrams. The configuration of the level shifter shown in FIG. The source terminal of the first p-type transistor 1200 and the source terminal of the third p-type transistor 1201 are as follows: The source terminals of the transistor 1230 are both electrically connected to a power supply that provides a potential VH. The drain terminal of the first p-type transistor 1200 is connected to the drain terminal of the second p-type transistor 1210. and the drain terminal of the third p-type transistor 1230 is electrically connected to the source terminal of The second p-type transistor 1240 is electrically connected to the source terminal of the fourth p-type transistor 1240. The drain terminal of the transistor 1210 is connected to the drain terminal of the first n-type transistor 1220. and a fourth p-type transistor 1230 electrically connected to the gate terminal of the third p-type transistor 1230. The drain terminal of the second n-type transistor 1240 is connected to the drain terminal of the second n-type transistor 1250. and the gate terminal of the first p-type transistor 1200. The source terminal of the first n-type transistor 1220 and the source terminal of the second n-type transistor 1250 Both children are given GND (=0[V]).

[0118] In FIG. 7, an input signal (I) is input to the gate terminal of the second p-type transistor 1210 and the The inverted signal (IB) of the input signal is input to the gate terminal of the n-type transistor 1220 of is connected to the gate terminal of the fourth p-type transistor 1240 and the gate terminal of the second n-type transistor 1250 The output signal (O) is input to the gate terminal of the fourth p-type transistor 1240. The power is taken out from the drain terminal of the second p-type transistor 1210. It is also possible to extract the inverted signal (OB) of the output signal from the output terminal.

[0119] The basic operation of the level shifter shown in Figure 7 will be explained. When a high level is input to the input signal (I), When the first n-type transistor 1220 is turned on, the third p-type transistor A potential GND is input to the gate terminal of the third p-type transistor 1230, and the third p-type transistor 1230 is turned on. At the same time, the inverted output signal (OB) is set to Low. The potential is GND. On the other hand, the inverted input signal (IB) is Low at this time, so the fourth The first p-type transistor 1240 is conductive and the second n-type transistor 1250 is non-conductive. Here, the third p-type transistor 1230 and the fourth p-type transistor 12 40 are both in a conducting state, the output signal (O) is High. The place will be VH.

[0120] When the potential of the input signal (I) is low, the transistor of the level shifter shown in Figure 7 The output signal (O) is low, and the potential at this time is equal to GND. become.

[0121] In this way, an output signal (O) with amplitude converted from the input signal can be obtained. That is, the level shifter shown in FIG. 7 shifts the High and Low voltages of the input signal (I). The potential difference can be converted into the potential difference between High and Low of the output signal (O).

[0122] FIG. 8 shows an example of a boost level shift circuit diagram different from that shown in FIG. 7. The level shifter shown in FIG. The configuration of the first p-type transistor 1260 is as follows: The source terminals of the transistor 1280 are both electrically connected to a power supply that provides a potential VH. The drain terminal of the first n-type transistor 1270 is connected to the drain terminal of the first p-type transistor 1270. 260 and the gate terminal of the second p-type transistor 1280. The drain terminal of the second n-type transistor 1290 is connected to the drain terminal of the second p-type transistor 12 80 and the gate terminal of the first p-type transistor 1260. The source terminal of the first n-type transistor 1270 and the source terminal of the second n-type transistor The source terminals of the capacitors 1290 are both supplied with GND (=0[V]).

[0123] In FIG. 8, an input signal (I) is input to the gate terminal of a first n-type transistor 1270. The inverted signal (IB) of the input signal is input to the gate terminal of the second n-type transistor 1290. The output signal (O) is taken from the drain terminal of the second n-type transistor 1290. The drain terminal of the first n-type transistor 1270 outputs the inverted output signal. It is also possible to extract a signal (OB).

[0124] The basic operation of the level shifter shown in Figure 8 will be explained. When a high level is input to the input signal (I), When the first n-type transistor 1270 is turned on, the second p-type transistor A potential GND is input to the gate terminal of the second p-type transistor 1280, and the second p-type transistor 1280 is turned on. At the same time, the inverted output signal (OB) is set to Low. On the other hand, the inverted input signal (IB) is low at this time, so the second The first n-type transistor 1290 is in a non-conducting state. Since 80 is in a conductive state, the output signal (O) is High, and the potential at this time is It becomes VH.

[0125] When the potential of the input signal (I) is low, the transistor of the level shifter shown in Figure 8 The output signal (O) is low, and the potential at this time is equal to GND. become.

[0126] In this way, an output signal (O) with amplitude converted from the input signal can be obtained. That is, the level shifter shown in FIG. 8 shifts the High and Low voltages of the input signal (I). The potential difference can be converted into the potential difference between High and Low of the output signal (O).

[0127] The potential converted to a high potential by the potential conversion circuit 180 shown in FIG. 7 and 8, which are included in the The potential is then converted to a high potential by the potential conversion circuit 180. The level of the signal is transferred from the signal line S to each memory cell by using a boost level shifter included in the first drive circuit 190. Alternatively, the signal may be output to memory cell 170.

[0128] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0129] (Embodiment 2) In this embodiment, a structure of a semiconductor device according to one embodiment of the disclosed invention and a manufacturing method thereof will be described. This will be described with reference to FIGS.

[0130] <Cross-sectional and planar configurations of semiconductor device> FIG. 9 shows an example of the configuration of a semiconductor device. FIG. 9(A) shows a cross section of the semiconductor device, and FIG. 9(B) shows a plan view of the semiconductor device. Here, FIG. 9(A) shows the A of FIG. 9(B). 9(A) and 9(B) correspond to the cross sections taken along lines 1-A2 and B1-B2. The semiconductor device has a transistor 160 using a first semiconductor material in the lower part and a The transistor 162 is made of a second semiconductor material. It is desirable that the first semiconductor material and the second semiconductor material are different materials. The material is a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material is an oxide A transistor using a material other than an oxide semiconductor can operate at high speed. On the other hand, transistors using oxide semiconductors can be used for a long time due to their characteristics. It allows charge retention.

[0131] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can also be used. The technical essence of the invention is to develop a semiconductor device that can sufficiently reduce the off-state current, such as an oxide semiconductor, to retain data. The advantage of this method is that the transistor 162 is made of a semiconductor material that can be reduced to The specific configuration of the semiconductor device, such as the materials used in the device and the structure of the semiconductor device, is shown here. There is no need to limit it to anything.

[0132] The transistor 160 in FIG. 9 is formed on a substrate 100 that includes a semiconductor material (e.g., silicon). 00 and the channel forming region 116 provided in between. The impurity region 120 is formed by the metal compound region 124 in contact with the impurity region 120, and the channel A gate insulating layer 108 is provided on the gate forming region 116, and a The figure does not explicitly show the source electrode or the drain electrode. However, for convenience, this state is also referred to as a transistor. In this case, the source region and the drain region are not shown in order to explain the connection relationship of the transistor. The source electrode and the drain electrode may include the drain region. In the above, the term "source electrode" may include the source region.

[0133] In addition, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. The transistor 160 is covered with an insulating layer 128 and an insulating layer 130. In order to achieve high integration, the transistor 160 is It is preferable that the transistor 160 does not have a sidewall insulating layer. When the above characteristics are important, a sidewall insulating layer is provided on the side surface of the gate electrode 110, and The impurity region 120 may include regions with different impurity concentrations.

[0134] The transistor 162 in FIG. 9 has a source electrode or drain electrode provided on the insulating layer 130. a source or drain electrode 142a, and a source or drain electrode 142b. The drain electrode 142a and the source or drain electrode 142b are electrically connected to each other. The oxide semiconductor layer 144 is connected to the source electrode or drain electrode 142a. Alternatively, the drain electrode 142b and the gate insulating layer 146 covering the oxide semiconductor layer 144 and the gate insulating layer 146 are A gate electrode 148 is provided on the oxide insulating layer 146 so as to overlap with the oxide semiconductor layer 144. a, and a gate electrode between the source electrode or drain electrode 142a and the oxide semiconductor layer 144. The insulating layer 143a in the region overlapping with the electrode 148a and the source or drain electrode 142 The insulating layer 143 in the region overlapping with the gate electrode 148a between the oxide semiconductor layer 144 and the insulating layer 143 b. In addition, the capacitance between the source electrode or the drain electrode and the gate electrode is reduced. To reduce the heat loss, it is desirable to provide insulating layers 143a and 143b. It is also possible to employ a structure in which the layer 143a and the insulating layer 143b are not provided.

[0135] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 144. It is desirable that the gas be highly purified by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 a toms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 144 is determined as follows: Secondary Ion Mass Spectrometry (SIMS) In this way, the hydrogen concentration is sufficiently reduced and high purity is obtained. The defect level in the energy gap caused by oxygen deficiency is In the oxide semiconductor layer 144, the carrier concentration is reduced to 1×10 12 / cm 3 Less than desired Or 1×10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 Less than and For example, the off-state current (here, per unit channel width (1 μm)) at room temperature (25°C) The value of 100zA (1zA (zeptoampere) is 1 x 10 -21 A) The following are desirable: In this way, the oxide that has become i-type (intrinsic) or substantially i-type is By using a compound semiconductor, it is possible to obtain a transistor 162 with excellent off-state current characteristics. can.

[0136] In the transistor 162 of FIG. 9, leakage current occurring between elements due to miniaturization is suppressed. In order to achieve this, the oxide semiconductor layer 144 is processed into an island shape. In the case where the oxide semiconductor layer is not processed into an island shape, the oxide semiconductor layer may be processed without any etching. This can prevent contamination of the oxide semiconductor layer 144 due to etching.

[0137] The capacitor 164 in FIG. 9 includes a source electrode or a drain electrode 142a, an oxide semiconductor layer 144, a gate insulating layer 146, and an electrode 148b. The electrode or drain electrode 142a functions as one electrode of the capacitor 164. The electrode 48 b functions as the other electrode of the capacitor 164 .

[0138] In the capacitor 164 of FIG. 9, the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked. By doing so, the insulation between the source electrode or drain electrode 142a and the electrode 148b is reduced. Of course, in order to ensure sufficient capacity, oxide semiconductor The capacitor element 164 may be configured without the insulating layer 143a. A capacitor element 164 having an insulating layer formed in the same manner may be used. If the capacitor 164 is not required, the capacitor 164 may not be provided.

[0139] Note that in the transistor 162 and the capacitor 164, the source electrode or the drain electrode The ends of the electrode 142a and the source or drain electrode 142b are tapered. It is preferable that the source electrode or drain electrode 142a, the source electrode or drain electrode The tapered end of the electrode 142b improves the coverage of the oxide semiconductor layer 144. This is because the taper angle can be improved and step disconnection can be prevented. The taper angle is 0° or more and 60° or less. The source electrode or drain electrode 142a) is perpendicular to the cross section (plane perpendicular to the surface of the substrate). This indicates the inclination angle between the side and bottom surfaces of the layer when observed from a perpendicular direction.

[0140] In this embodiment, the transistor 162 and the capacitor 164 are By adopting such a planar layout, For example, if the minimum processing dimension is F and the area occupied by the memory cell is 15 F 2 ~25F 2 It is possible to do so.

[0141] An insulating layer 150 is provided over the transistor 162 and the capacitor 164. An insulating layer 152 is provided on the edge layer 150. The gate insulating layer 146 and the insulating layer An electrode 154 is provided in an opening formed in the insulating layer 152. On the top of the electrode 154, a wiring 156 is formed to connect to the electrode 154. The source electrode or drain electrode 142b is connected to the wiring 156. For example, the present invention is not limited to this. The wiring 156 may be directly connected to the source electrode or the metal compound region 124. may be in contact with the drain electrode 142b.

[0142] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. A method for fabricating the transistor 160 will be described with reference to FIGS. 10 and 11. A method for manufacturing the transistor 162 and the capacitor 164 will be described with reference to FIGS. 12 and 13. Please refer to the following for explanation.

[0143] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 10(A)). The substrate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Substrates such as silicon germanium, compound semiconductor substrates, and SOI substrates can be used. Here, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. Generally, an "SOI substrate" is a substrate in which silicon is deposited on an insulating surface. The term "substrate" refers to a substrate having a structure in which a semiconductor layer is provided, but in this specification, it refers to a substrate having a silicon layer on an insulating surface. The term "substrate" is used to include a substrate having a semiconductor layer made of a material other than silicon. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate is configured such that a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This includes:

[0144] In particular, when a single crystal semiconductor substrate such as silicon is used as the substrate 100 containing a semiconductor material, In this case, it is preferable because the read operation of the semiconductor device can be performed at high speed.

[0145] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 10(A)). The protective layer 102 is made of, for example, silicon oxide or silicon nitride. For example, an insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of the transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or a metal element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity include phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Sodium, gallium, etc. can be used.

[0146] Next, etching is performed using the protective layer 102 as a mask, and the This removes a portion of the substrate 100 from the exposed area. A semiconductor region 104 separated from the region is formed (see FIG. 10(B)). For this purpose, dry etching is preferably used, but wet etching may also be used. The etching gas and etching solution should be selected appropriately depending on the material to be etched. can be done.

[0147] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see FIG. 10(C)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. The insulating layer can be removed by polishing such as CMP (chemical mechanical polishing) or etching. After the semiconductor region 104 is formed, Alternatively, after the element isolation insulating layer 106 is formed, the protective layer 102 is removed.

[0148] Next, an insulating layer is formed on the surface of the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. Complete.

[0149] The insulating layer will later become a gate insulating layer, and is formed by, for example, heat treatment ( Instead of heat treatment, high density Plasma treatment may be applied. High density plasma treatment may be performed using, for example, helium (He), argon (Ar), or the like. Rare gases such as argon (Ar), krypton (Kr), and xenon (Xe), oxygen, and nitrogen oxide It can be done using a mixture of gases such as ammonia, nitrogen, and hydrogen. The insulating layer may be formed by a deposition method, a sputtering method, or the like. , silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, Yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen Hafnium silicate (HfSi x O y N z (x>0, y>0, z>0) , nitrogen-doped hafnium aluminate (HfAl x O y N z (x>0, y>0, z It is desirable to have a single layer structure or a laminated structure including the insulating layer. For example, the thickness is 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. can be done.

[0150] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, a conductive material such as polycrystalline silicon can be used to form the conductive layer. The method for forming the layer is not particularly limited, and may be a vapor deposition method, a CVD method, a sputtering method, or the like. Various film forming methods such as talc coating and spin coating can be used. In this embodiment, an example in which a layer containing a conductive material is formed using a metal material is shown. Let's say.

[0151] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, the gate electrode 110 is formed (see FIG. 10(C)).

[0152] Next, phosphorus (P) or arsenic (As) is added to the semiconductor region 104 to form a channel forming region. 116 and impurity region 120 are formed (see FIG. 10(D)). Phosphorus and arsenic are added to form p-type transistors. In this case, impurity elements such as boron (B) and aluminum (Al) may be added. The concentration of the added impurities can be set appropriately, but as semiconductor elements become highly miniaturized, If so, it is desirable to increase the concentration.

[0153] A sidewall insulating layer is formed around the gate electrode 110 to form a gate insulating film containing different impurity elements. An impurity region doped with a certain concentration may be formed.

[0154] Next, a metal layer 122 is formed so as to cover the gate electrode 110, the impurity region 120, etc. (FIG. The metal layer 122 can be formed by vacuum deposition, sputtering, spin coating, or the like. The metal layer 122 can be formed by various film forming methods such as a metal deposition method. The metal material used is one that reacts with the semiconductor material that makes up the semiconductor 4 to form a low-resistance metal compound. Such metal materials are preferably titanium and tantalum. , tungsten, nickel, cobalt, platinum, etc.

[0155] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the pure region 120 (see FIG. 11(A)). When polycrystalline silicon or the like is used as the gate electrode 110, the gold of the gate electrode 110 A metal compound region is also formed in the portion in contact with the metal layer 122.

[0156] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize heat treatment in a very short time. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0157] Next, insulating layers 128 and 130 are formed to cover the respective components formed by the above-described steps. The insulating layer 128 and the insulating layer 130 are formed using silicon oxide, oxynitride, or the like. It is formed using a material containing an inorganic insulating material such as silicon, silicon nitride, or aluminum oxide. In particular, the insulating layer 128 and the insulating layer 130 may be made of a low-k material. By using this, it is possible to sufficiently reduce the capacitance caused by overlapping of various electrodes and wiring. The insulating layer 128 and the insulating layer 130 are preferably made of porous materials. A porous insulating layer may be applied. A porous insulating layer has a lower dielectric constant than a dense insulating layer. This reduces the capacitance caused by the electrodes and wiring, making it possible to further reduce the capacitance. The insulating layer 128 and the insulating layer 130 are formed using an organic insulating material such as polyimide or acrylic. In this example, the insulating layer 128 and the insulating layer 130 are stacked. However, one embodiment of the disclosed invention is not limited to this. A layer structure may also be used.

[0158] As a result of the above, a transistor 160 using the substrate 100 containing a semiconductor material is formed (see FIG. 11(B)). Such a transistor 160 has the advantage of being capable of high-speed operation. Therefore, by using the transistor as a readout transistor, Therefore, information can be read out at high speed.

[0159] Then, as a process before forming the transistor 162 and the capacitor element 164, the insulating layer 128 The insulating layer 130 is subjected to CMP processing to expose the upper surface of the gate electrode 110 (FIG. 11( As a process for exposing the upper surface of the gate electrode 110, in addition to the CMP process, etching Although it is possible to apply a chipping process or the like, it is possible to improve the characteristics of the transistor 162. Therefore, it is desirable to make the surfaces of the insulating layer 128 and the insulating layer 130 as flat as possible. .

[0160] Before and after each of the above steps, further steps may be performed to form electrodes, wiring, semiconductor layers, insulating layers, etc. For example, the wiring structure may be a laminated structure of an insulating layer and a conductive layer. It is also possible to realize a highly integrated semiconductor device by adopting a multi-layer wiring structure.

[0161] <Method of manufacturing the upper transistor> Next, a conductive layer is formed on the gate electrode 110, the insulating layer 128, the insulating layer 130, etc. The conductive layer is selectively etched to form the source or drain electrode 142a, the source or drain electrode 142b, and the Alternatively, a drain electrode 142b is formed (see FIG. 12(A)).

[0162] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the above elements Alloys containing manganese, magnesium, zirconium, beryllium, etc. can be used. Using either aluminum, neodymium, or scandium, or a combination of these materials Good too.

[0163] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The source or drain electrode 142a and the source or drain electrode 142 It has the advantage of being easy to process into b.

[0164] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or a combination of these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0165] The etching of the conductive layer is performed to form the source or drain electrode 142a and the source It is preferable to perform this process so that the end of the source or drain electrode 142b has a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The ends of the source or drain electrodes 142a and 142b are By etching to form a tapered shape, the gate insulating layer 14 to be formed later can be This improves the covering property of 6 and prevents breakage.

[0166] The channel length (L) of the upper transistor is determined by the source or drain electrode 142a and and the distance between the bottom ends of the source electrode or drain electrode 142b. Exposure for forming a mask used when forming a transistor with a channel length (L) of less than 25 nm When using light, extreme ultraviolet rays with a wavelength of several nanometers to several tens of nanometers are used. It is preferable to use ultraviolet light. Extreme ultraviolet light exposure provides high resolution and a wide depth of focus. Therefore, the channel length (L) of the transistor to be formed later should be set to 10 nm or more. It is possible to make it 000nm (1μm) or less, which enables the operating speed of the circuit to be increased. Furthermore, miniaturization also makes it possible to reduce the power consumption of semiconductor devices.

[0167] An insulating layer that functions as a base may be provided on the insulating layer 128 or the insulating layer 130. The insulating layer can be formed by using a PVD method, a CVD method, or the like.

[0168] Next, an insulating layer 143a is formed on the source or drain electrode 142a. An insulating layer 143b is formed on each of the drain electrodes 142b (see FIG. 12(B)). The insulating layer 143a and the insulating layer 143b are formed on the source electrode or the drain electrode 142a. After forming an insulating layer covering the source electrode or the drain electrode 142b, the insulating layer is selected. The insulating layer 143a and the insulating layer 143b can be formed by selectively etching the insulating layer 143a. The insulating layer is formed so as to overlap a part of the gate electrode to be formed later. By providing the gate electrode with a dielectric layer, the capacitance between the gate electrode and the source electrode or the drain electrode is reduced. It is possible.

[0169] The insulating layer 143a and the insulating layer 143b are made of silicon oxide, silicon oxynitride, silicon nitride, or silicon oxide. The insulating layer can be formed using a material containing an inorganic insulating material such as aluminum chloride. By using a low-k material for the layer 143a and the insulating layer 143b, It becomes possible to sufficiently reduce the capacitance between the electrode and the source electrode or the drain electrode. It is preferable that the insulating layer 143a and the insulating layer 143b are made of porous materials. A porous insulating layer may be applied. A porous insulating layer has a lower dielectric constant than a dense insulating layer. This reduces the capacitance between the gate electrode and the source or drain electrode. It is possible to reduce it.

[0170] In addition, in order to reduce the capacitance between the gate electrode and the source electrode or the drain electrode, In this case, it is preferable to form the insulating layer 143a and the insulating layer 143b. It is also possible to configure it without providing it.

[0171] Next, the source or drain electrode 142a and the source or drain electrode 1 After forming an oxide semiconductor layer so as to cover 42b, the oxide semiconductor layer is selectively etched. The oxide semiconductor layer 144 is formed by etching (see FIG. 12C).

[0172] The oxide semiconductor layer is made of quaternary metal oxides such as In-Sn-Ga-Zn-O and ternary metal oxides. Metal oxides such as In-Ga-Zn-O, In-Sn-Zn-O, and In-Al-Zn- O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, Binary metal oxides such as In-Zn-O, In-Ga-O, Sn-Zn-O, and Al -Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, and other single-component metals It can be formed using oxides such as In-O, Sn-O, and Zn-O.

[0173] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0174] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0, m: non-natural number). Also, M is used instead of Ga, and I nMO3(ZnO) m (m>0, m: non-natural number) Here, M is gallium (Ga), aluminum (Al), iron (Fe), or nickel. (Ni), manganese (Mn), cobalt (Co), etc. For example, M can be Ga, Ga and Al, Ga and Fe, or G Ga and Ni, Ga and Mn, Ga and Co, etc. can be applied. Please note that the above composition is derived from the crystal structure and is merely an example. do.

[0175] The target for forming the oxide semiconductor layer by sputtering is In:Ga:Zn= It is preferable to use a material having a composition ratio of 1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, the composition of In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] A metal oxide target having a ratio of In2O3:Ga2 can also be used. Metal oxide targets with a composition ratio of O3:ZnO=1:1:1 [molar ratio] and I Metal oxide with a composition ratio of n2O3:Ga2O3:ZnO=1:1:4 [molar ratio] The target and the composition ratio of In2O3:Ga2O3:ZnO=1:0:2 [molar ratio] A metal oxide target having a metal oxide layer may also be used.

[0176] In this embodiment, the amorphous oxide semiconductor layer is formed by using an In—Ga—Zn—O-based metal oxide. The film is formed by sputtering using a metal target.

[0177] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more; More preferably, it is 99.9% or more. A metal oxide target with a high relative density is used. This makes it possible to form an oxide semiconductor layer with a dense structure.

[0178] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of rare gas (typically argon) and oxygen. In practice, impurities such as hydrogen, water, hydroxyl groups, and hydrides are preferably at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the concentration has been reduced to 10 ppb or less. .

[0179] When forming the oxide semiconductor layer, for example, the object to be processed is kept in a processing chamber maintained in a reduced pressure state. The temperature of the workpiece is maintained at 100°C or higher and lower than 550°C, preferably 200°C or higher and 400°C or higher. Alternatively, the temperature of the object to be treated is adjusted to the temperature of the object to be treated when the oxide semiconductor layer is formed. The temperature may be room temperature (25°C ± 10°C). Then, while removing moisture from the processing chamber, hydrogen A sputtering gas from which silicon dioxide and water have been removed is introduced, and an oxide semiconductor layer is formed using the target. The oxide semiconductor layer is formed while heating the object to be treated. It is possible to reduce impurities contained in the material. It is also possible to reduce damage caused by sputtering. To remove moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, titanium sublimation pumps, etc. It is also possible to use a turbo molecular pump with a cold trap added. Hydrogen and water can be removed from the processing chamber by evacuating it using a cryopump or similar. Therefore, the impurity concentration in the oxide semiconductor layer can be reduced.

[0180] The oxide semiconductor layer is formed under the conditions, for example, when the distance between the object to be treated and the target is 17 0 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen 100 %) atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon In addition, a pulsed direct current (DC) power supply is used. This reduces the amount of powdery material (also called particles or dust) that is generated during film formation, and improves film thickness distribution. The thickness of the oxide semiconductor layer is preferably 1 nm or more and 50 nm or less. The thickness is set to 1 nm or more and 30 nm or less, and more preferably 1 nm or more and 10 nm or less. By using an oxide semiconductor layer with a thickness of 1000 nm, it is possible to suppress the short channel effect that accompanies miniaturization. However, the appropriate thickness depends on the oxide semiconductor material used and the application of the semiconductor device. Since thicknesses vary, the thickness can be selected depending on the material used and the intended use.

[0181] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and deposits on the formation surface (for example, the surface of the insulating layer 130) are removed. Here, the reverse sputtering is a method of removing the sputtered material. Instead of bombarding the target with ions, the ions are bombarded onto the surface to be treated. This refers to a method of modifying the surface by bombarding the surface with ions. In this case, a high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the object to be treated. In addition, nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. An atmosphere according to the above may be applied.

[0182] After that, the oxide semiconductor layer is preferably subjected to heat treatment (first heat treatment). Excess hydrogen (including water and a hydroxyl group) in the oxide semiconductor layer is removed by first heat treatment; The structure of the oxide semiconductor layer can be adjusted to reduce defect levels in the energy gap. The temperature of the first heat treatment is, for example, 300°C or higher and lower than 550°C, or 400°C or higher and lower than 50°C. Keep below 0℃.

[0183] The heat treatment is carried out by, for example, placing the object to be treated in an electric furnace using a resistance heating element, and heating the object in a nitrogen atmosphere. The process can be carried out under the conditions of 450°C for 1 hour. During this time, the oxide semiconductor layer is not exposed to the air. Ensure that water and hydrogen do not get mixed in.

[0184] Heat treatment equipment is not limited to electric furnaces, and may be heat conduction or heat radiation from a medium such as heated gas. For example, a device for heating the object to be treated may be used. pid Thermal Anneal equipment, GRTA (Gas Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. or an inert gas such as nitrogen that does not react with the material to be treated by heat treatment. It is used.

[0185] For example, in the first heat treatment, the workpiece is placed in a heated inert gas atmosphere and heated for several minutes. After the heating, the object to be treated may be taken out of the inert gas atmosphere and subjected to GRTA treatment. GRTA treatment allows high-temperature heat treatment in a short time. It is possible to apply this method even under temperature conditions exceeding 100°C. During the treatment, an inert gas is used instead of oxygen. By performing the first heat treatment in an atmosphere containing oxygen, This is because the defect level in the energy gap caused by oxygen vacancies can be reduced. .

[0186] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0187] In either case, the first heat treatment reduces impurities and produces an i-type (intrinsic semiconductor) or i-type By forming an oxide semiconductor layer that is as close to the original thickness as possible, a transistor with extremely excellent characteristics can be realized. It can be realized.

[0188] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. The dehydrogenation treatment is performed after the formation of an oxide semiconductor layer, after the formation of a gate insulating layer, or after the formation of a gate electrode. It is also possible to carry out the dehydration treatment at a timing such as after the dehydration treatment. The hydrogenation treatment may be carried out not only once but also multiple times.

[0189] The oxide semiconductor layer may be etched either before or after the heat treatment. From the viewpoint of miniaturization of elements, it is preferable to use dry etching. However, wet etching may also be used. The thickness can be appropriately selected depending on the material to be etched. If this does not pose a problem, the oxide semiconductor layer may be used without being processed into an island shape.

[0190] Next, a gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144, and then a gate insulating layer 146 is formed. A gate electrode 148a is formed over the layer 146 in a region overlapping with the oxide semiconductor layer 144. Then, an electrode 148b is formed in a region overlapping with the source or drain electrode 142a (FIG. 12(D)).

[0191] The gate insulating layer 146 can be formed by using a CVD method, a sputtering method, or the like. The gate insulating layer 146 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. tantalum oxide, hafnium oxide, yttrium oxide, gallium oxide, hafnium silicon Gate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0)), nitrogen-doped hafnium aluminium Laminate (HfAl x O y N z (x>0, y>0, z>0) The gate insulating layer 146 may have a single layer structure or a stacked layer structure. Although there is no particular limitation on the thickness, when miniaturizing semiconductor devices, For example, when silicon oxide is used, In this case, the thickness is set to 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. can.

[0192] As mentioned above, when the gate insulating layer is made thin, the gate leakage caused by the tunnel effect etc. To solve the gate leakage problem, the gate insulating layer 146 is doped with hafnium oxide. tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0 , y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0), nitrogen-doped hafnium aluminate (HfAl x O y N z ( It is recommended to use high-k materials such as x>0, y>0, z>0. By using an igh-k material for the gate insulating layer 146, the electrical characteristics can be maintained while the gate It is possible to increase the film thickness to suppress leakage. and a film containing silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon oxide It may also have a laminated structure with a film containing either aluminum or the like.

[0193] After the gate insulating layer 146 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. When the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 Oxygen is supplied to the oxide semiconductor layer 144 to compensate for oxygen vacancies in the oxide semiconductor layer 144, thereby forming an i-type (intrinsic) or Alternatively, the oxide semiconductor layer 144 can be formed to be as close to i-type as possible.

[0194] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. A heat treatment may be performed. In addition, a second heat treatment may be performed after the first heat treatment, or The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It's okay to do that.

[0195] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide The semiconductor layer 144 is highly purified so that it contains as few impurities as possible other than its main components. can.

[0196] The gate electrode 148a and the electrode 148b are formed by forming a conductive layer on the gate insulating layer 146. The gate electrode can be formed by selectively etching the conductive layer. The conductive layers that become the electrodes 148a and 148b can be formed by PVD methods such as sputtering, It can be formed by using a CVD method such as a plasma CVD method. The same applies to the case of the drain electrode 142a, etc., and the descriptions therefor can be taken into consideration.

[0197] Next, an insulating layer 15 is formed on the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. 13A, the insulating layer 150 and the insulating layer 152 are formed. 2 can be formed by using a PVD method, a CVD method, etc. Also, silicon oxide, an oxide Contains inorganic insulating materials such as silicon nitride, silicon nitride, hafnium oxide, and aluminum oxide. The material can be used to form the substrate.

[0198] The insulating layer 150 and the insulating layer 152 may be made of a material with a low dielectric constant or a structure with a low dielectric constant (porous It is desirable to use a structure with low dielectric constants for the insulating layer 150 and the insulating layer 152. This reduces the capacitance that occurs between wiring and electrodes, making it possible to speed up operation. This is because

[0199] In this embodiment, the insulating layer 150 and the insulating layer 152 are stacked. The present invention is not limited to this embodiment. It may be a single layer or a laminated structure of three or more layers. It is also possible to have a configuration in which no insulating layer is provided.

[0200] It is desirable that the insulating layer 152 be formed so that its surface is flat. By forming the insulating layer 152 so that the surface is flat, it is possible to This is because electrodes, wiring, and the like can be suitably formed on the insulating layer 152. The insulating layer 152 is planarized using a method such as CMP (chemical mechanical polishing). It is possible.

[0201] Next, a source electrode or a drain electrode is formed on the gate insulating layer 146, the insulating layer 150, and the insulating layer 152. An opening is formed that reaches the electrode 142b (see FIG. 13(B)). This is done by selective etching using a mask or the like.

[0202] Thereafter, an electrode 154 is formed in the opening, and a wiring 15 in contact with the electrode 154 is formed on the insulating layer 152. 6 is formed (see FIG. 13(C)).

[0203] The electrode 154 is formed by forming a conductive layer in the region including the opening using, for example, a PVD method or a CVD method. Then, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by the following.

[0204] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (such as the native oxide film) on the surface is reduced, and the lower electrode (here, the source electrode or It has the function of reducing the contact resistance with the drain electrode 142b. The titanium nitride film has a barrier function to suppress the diffusion of conductive materials. After forming a barrier film made of titanium nitride or the like, a copper film may be formed by plating.

[0205] When forming an electrode by removing a part of the conductive layer, the surface is made flat. For example, a thin titanium film or titanium nitride film is formed in the area including the opening. If a tungsten film is formed to fill the opening after the etching, the subsequent CMP process By this process, unnecessary tungsten, titanium, titanium nitride, etc. are removed and the surface In this way, the flatness of the surface including the electrode 154 can be improved. As a result, in the subsequent steps, good electrodes, wiring, insulating layers, semiconductor layers, etc. can be formed. This becomes possible.

[0206] The wiring 156 is formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. After forming a conductive layer using the above, the conductive layer is patterned to form the conductive layer. The conductive layer may be made of aluminum, chromium, copper, tantalum, titanium, or molybdenum. It is possible to use an element selected from the group consisting of tungsten and tungsten, or an alloy containing the above-mentioned elements. Manganese, magnesium, zirconium, beryllium, neodymium, scandium The source electrode may be made of any one of the following materials or a combination of these materials. Or it is similar to the drain electrode 142a.

[0207] As a result of the above, the transistor 162 including the highly purified oxide semiconductor layer 144 and The capacitor element 164 is completed (see FIG. 13(C)).

[0208] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 below The carrier density of the oxide semiconductor layer 144 is 1 / 2 times that of a general silicon wafer. The carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., 1 x10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than) In addition, the off-state current of the transistor 162 is also sufficiently small. The off-state current (here, the value per unit channel width (1 μm)) of 2 at room temperature (25°C) is 100zA (1zA (zeptoampere) is 1 x 10 -21 A) Less than 10zA, preferably The following is the result.

[0209] By using the oxide semiconductor layer 144 that has been highly purified and made intrinsic, It is easy to sufficiently reduce the off-state current of such a transistor. By using this, a semiconductor device capable of retaining memory contents for an extremely long period of time can be obtained. do.

[0210] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0211] (Embodiment 3) In this embodiment, semiconductor devices having different structures from those shown in FIGS. 2 and 5 will be described with reference to FIGS. 25 to 27. This will be explained with reference to the following.

[0212] FIG. 25A is an example of a circuit diagram of a semiconductor device having (m×n) memory cells 170. The configuration of the memory cell 170 in FIG. 25(A) is the same as that in FIG. 2(B), so the details are Detailed explanations will be omitted.

[0213] The semiconductor device shown in FIG. 25A has a structure similar to that of the semiconductor device shown in FIG. The difference between the semiconductor device shown in FIG. 2A and the semiconductor device shown in FIG. 25A is the bit line The difference is whether or not a wiring 195 electrically connected to BL is provided. The semiconductor device shown in A) has a wiring 195 electrically connected to the bit line BL. The wiring 195 has a function of keeping the potential of the bit line applied to the memory cell at an appropriate value. In the disclosed invention, in which a large number of memory cells are connected in series, This is because a voltage drop in the memory cell can make it difficult to read information.

[0214] For example, a unit is made up of 64 memory cells connected in series, and each unit is assigned an appropriate Wiring 195 is connected to each unit so that a suitable potential can be applied. Even in a configuration having a large number of memory cells, information can be read out favorably. The number of memory cells in each unit is not limited to 64. It can be 32, 128, etc. The value can be set appropriately within a range that does not affect the read operation.

[0215] 26A and 26B are diagrams showing an example of the configuration of the semiconductor device shown in FIG. 25. In FIG. 26A, 26(A) shows a cross section of the semiconductor device, and FIG. 26(B) shows a plan view of the semiconductor device. ) corresponds to the cross section taken along lines C1-C2 and D1-D2 in FIG. 26(B). A characteristic feature of this configuration is that the source electrode or the drain electrode 142a is electrically connected to the The wiring 156a is included in addition to the wiring 156b. This corresponds to the wiring 195 electrically connected to the bit line BL in FIG. Although not shown in FIG. 26(B), the wiring 156a and the wiring 156b are parallel to each other. It exists in a form that extends vertically.

[0216] The operation of the semiconductor device is the same as that of FIG. Please refer to the corresponding description of the form.

[0217] Even when the configuration of FIG. 2(A) or FIG. 5(A) is adopted, the signal line S is Instead, it is possible to obtain the same effect. In this case, for example, As shown in FIG. 1, the bit line BL and the signal line S are electrically connected, and then the bit line BL and A switch 231 controls the connection between the signal line S and the output terminal OUT, and a bit line BL and a signal A switch 232 that controls the connection between the line S and the input terminal IN, and a wiring SW. In this case, the signal supplied to the wiring SW is used to read out the When writing, switch 231 should be turned on, and when writing, switch 232 should be turned on. The signal supplied to the wiring SW is the signal from the wiring WRITE and wiring READ. The signal is generated by the signal generating circuit 233 based on the above. When such a configuration is adopted, Since there is no need to provide the wiring 195 shown in FIG. 25, it is possible to maintain a suitable read operation while The integration density of semiconductor devices can be further increased.

[0218] Other configurations in Fig. 27 are the same as those in Fig. 23. For details, see the explanation of Fig. 23. This can be taken into consideration.

[0219] Note that the structure shown in this embodiment is a modified example of the semiconductor device shown in FIG. A modified example of the semiconductor device shown in (A) may also be used.

[0220] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0221] (Fourth embodiment) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 14. In this embodiment, telephones, mobile phone devices), portable information terminals (including portable game consoles and audio playback devices) digital cameras, digital video cameras, electronic paper, television equipment (television The semiconductor device described above is applied to electronic devices such as a television receiver. This section explains the case where

[0222] FIG. 14A shows a notebook personal computer, which includes a housing 701, a housing 702, The display unit 703, the keyboard 704, etc. At least one of the semiconductor devices is provided with the semiconductor device described in the above embodiment. It has high speed writing and reading of information, long-term storage, and low power consumption. This realizes a notebook-type personal computer with reduced processing power.

[0223] FIG. 14B shows a personal digital assistant (PDA), and a main body 711 includes a display unit 713 and an external An external interface 715, operation buttons 714, etc. are provided. The main body 711 is provided with a stylus 712 for operating the terminal. Therefore, writing and reading of information can be performed at high speed. A portable information terminal capable of long-term memory retention and sufficiently reduced power consumption is realized. .

[0224] FIG. 14C shows an electronic book 720 that uses electronic paper. The electronic book 720 has a housing 721 and a housing 722. The display unit 721 and the display unit 723 are configured as two housings. 25 and a display unit 727 are provided. The housing 721 and the housing 723 are connected by a shaft portion 737. The housing 7 is connected to the shaft 737, and can be opened and closed around the shaft 737. 21 includes a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housings 723 is provided with the semiconductor device described in the above embodiment. Therefore, information can be written and read at high speed, can be stored for a long period of time, and can be erased. This allows for the realization of an electronic book with significantly reduced power consumption.

[0225] FIG. 14D shows a mobile phone that is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 slide and unfold as shown in FIG. 14(D). The two can be folded into an overlapping state, making them compact and suitable for portability. The housing 741 also includes a display panel 742, a speaker 743, a microphone 744, an operation panel 745, and a keyboard 746. Key 745, pointing device 746, camera lens 747, external connection terminal 74 The housing 740 also includes a solar cell 749 for charging the mobile phone. , an external memory slot 750, etc. The antenna is built into the housing 741. At least one of the housing 740 and the housing 741 is provided with the semiconductor device shown in the previous embodiment. This allows for high speed writing and reading of information and long-term storage. Thus, a portable telephone that can be held and consumes a sufficient amount of power is realized.

[0226] FIG. 14(E) shows a digital camera, which includes a main body 761, a display unit 767, an eyepiece unit 763, and an operation unit. It is composed of an operation switch 764, a display unit 765, a battery 766, etc. The semiconductor device described in the above embodiment is provided in the memory 761. High speed writing and reading, long-term memory retention, and low power consumption A digital camera having such a configuration is realized.

[0227] FIG. 14F shows a television device 770, which includes a housing 771, a display portion 773, a stand, and the like. The television device 770 is operated by a switch provided in the housing 771. This can be done using a switch or a remote control 780. The semiconductor device described in the above embodiment is mounted on the device 780. High speed writing and reading, long-term memory retention, and low power consumption A reduced television set is realized.

[0228] As described above, the electronic device described in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for the realization of electronic devices with reduced power consumption. [Example]

[0229] In this example, the off-state current of a transistor including a highly purified oxide semiconductor was measured. Explain the results.

[0230] First, the off-state current of a transistor using a highly purified oxide semiconductor must be sufficiently small. Considering this, we prepared a transistor with a sufficiently large channel width W of 1 m and measured the off-state current. The results of measuring the off-state current of a transistor with a channel width W of 1 m are shown in Figure 15. In FIG. 15, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. When the voltage VD is +1V or +10V, if the gate voltage VG is in the range of -5V to -20V, , the off-current of the transistor is 1 × 10, which is the detection limit. -12 It turns out that it is below A. In addition, the off-state current of the transistor (here, the value per unit channel width (1 μm)) is 1aA / μm (1×10 -18 A / μm or less.

[0231] Next, we aimed to more accurately determine the off-state current of a transistor using a highly purified oxide semiconductor. As described above, the transistor using the highly purified oxide semiconductor The off-state current of the transistor is 1×10, which is the detection limit of the measuring instrument. -12 It turns out that it is below A. Therefore, we fabricated a device for characteristic evaluation to obtain a more accurate value of the off-state current (measured in the above measurement). The results of the calculation (values below the detection limit of the detector) are explained below.

[0232] First, the characteristic evaluation element used in the current measurement method will be described with reference to FIG.

[0233] The characteristic evaluation element shown in FIG. 16 has three measurement systems 800 connected in parallel. 0 represents the capacitor element 802, the transistor 804, the transistor 805, and the transistor 806. , and transistor 808. The capacitor 806 and the transistor 808 are transistors using a highly purified oxide semiconductor. Sta was applied.

[0234] In the measurement system 800, one of the source terminal and the drain terminal of the transistor 804, One of the terminals of the capacitor 802 and the source terminal and drain terminal of the transistor 805 One end is connected to a power supply (the power supply that provides V2). the other of the source and drain terminals of the transistor 808 One of the terminals of the capacitor 802, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 are connected to each other. The other of the source terminal and the drain terminal of the transistor 808 is connected to the One of the source terminal and the drain terminal of the transistor 806 and the gate of the transistor 806 The output terminal of the transistor 805 is connected to a power supply (the power supply that provides V1). the other of the source and drain terminals of the transistor 806 The other terminal is connected to serve as an output terminal.

[0235] The gate terminal of the transistor 804 is connected to a resistor R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R A potential Vext_b2 that controls the state of the transistor 808 is supplied to the gate terminal of the transistor 808. A potential Vext_b1 that controls the on and off states of the transistor 808 is supplied. Furthermore, the potential Vout is output from the output terminal.

[0236] Next, a current measurement method using the above characteristic evaluation element will be described.

[0237] First, an outline of the initialization period during which a potential difference is applied to measure the off-state current will be described. During the initialization period, the gate terminal of the transistor 808 is connected to the transistor 808. The potential Vext_b1 is input to the source terminal of the transistor 804. a node connected to the other of the input or drain terminals of the transistor 808 (i.e., the source of the transistor 808) one of the terminal and the drain terminal of the capacitor 802, the other terminal of the capacitor 802, and the transistor 80 A potential V1 is applied to node A, which is the node connected to the gate terminal of transistor 5. The potential V1 is, for example, a high potential. A potential that turns the transistor 804 to the off state is applied to the transistor 804.

[0238] Then, a potential that turns off the transistor 808 is applied to the gate terminal of the transistor 808. Vext_b1 is input to turn off the transistor 808. After turning off the transistor 804, the potential V1 is set to a low potential. The potential V2 is set to the same potential as the potential V1. When the initialization period is over, the node A and the source terminal of the transistor 804 A potential difference is generated between the node A and one of the drain terminals of the transistor 808. A potential difference occurs between the source terminal and the drain terminal of the transistor. A small amount of charge flows through the transistor 804 and the transistor 808. In other words, an off-current occurs. do.

[0239] Next, an outline of the measurement period of the off-state current will be described. The potential of one of the source terminal or drain terminal of 804 (i.e., V2) and The potential of the other terminal of the source terminal or the drain terminal of the transistor 808 (i.e., V1) is On the other hand, during the measurement period, the potential of the node A is not fixed (floor As a result, charge flows through the transistor 804, and over time, The amount of charge held at node A changes. In other words, the output potential Vout of the output terminal also fluctuates. do.

[0240] The details of the relationship between the potentials during the initialization period in which the above potential difference is applied and the subsequent measurement period are as follows: The timing chart is shown in FIG.

[0241] In the initialization period, first, the potential Vext_b2 is set to the ON state by the transistor 804. This sets the potential of node A to V2, that is, a low potential ( Note that it is not necessary to apply a low voltage (VSS) to node A. The potential Vext_b2 is set to a potential (low potential) that turns off the transistor 804. Then, the potential Vext_b1 is applied to the transistor 804. The potential (high potential) is set so that the transistor 808 is turned on. The potential of A becomes V1, that is, the high potential (VDD). This sets the node A to a potential that turns off the resistor 808. The initialization period ends.

[0242] In the subsequent measurement period, charges flow into node A, causing potentials V1 and V2 to Or, the potential is set so that charge flows out from node A. Here, the potential V1 and the potential V 2 is the low potential (VSS). However, at the timing when the output potential Vout is measured, In this case, it is necessary to operate the output circuit, so V1 is temporarily set to a high potential (VDD). The period when V1 is at a high potential (VDD) should be short enough so as not to affect the measurement. The period.

[0243] As described above, when a potential difference is applied and the measurement period begins, the voltage at node A increases over time. The amount of charge held changes, and the potential at node A changes accordingly. This means that the potential of the gate terminal of the transistor 805 fluctuates, so over time, the output The potential of the output potential Vout of the terminal also changes.

[0244] A method for calculating the off-state current from the obtained output potential Vout will be described below.

[0245] Before calculating the off-state current, the potential V of node A A and the output voltage Vout. This causes the output potential Vout to change to the potential V at node A. A can be obtained. From the above relationship, the potential of node A, V A is expressed as a function of the output potential Vout as follows: It is possible.

[0246]

number

[0247] Also, the charge Q at node A A is the potential V of node A A , capacitance C connected to node A A , fixed Using a constant, it is expressed as follows: C A is the sum of the capacitance of the capacitive element 802 and other capacitances.

[0248]

number

[0249] Current I at node A A is the charge flowing into (or out of) node A. Since it is a time derivative, the current I at node A A is expressed as follows:

[0250]

number

[0251] In this way, the capacitance C connected to node A A The output potential Vout of the output terminal is Current I A can be obtained.

[0252] By using the method described above, the leakage current flowing between the source and drain of the transistor in the off state can be reduced. The off-state current (off current) can be measured.

[0253] In this example, a highly purified oxide film having a channel length L=10 μm and a channel width W=50 μm was used. A transistor 804, a transistor 805, a transistor 806, and a transistor 807 are formed using a compound semiconductor. In each of the paralleled measurement systems 800, a capacitance element 802 The capacitance values were set to 100fF, 1pF, and 3pF.

[0254] In the measurement according to this embodiment, VDD=5V and VSS=0V. In this case, the potential V1 is set to VSS as a rule, and the voltage is increased by 100 msec every 10 to 300 sec. Vout was measured as VDD for the period c. The Δt was set to approximately 30,000 seconds.

[0255] FIG. 18 shows the relationship between the elapsed time Time in the current measurement and the output potential Vout. From FIG. 18, it can be seen that the potential changes over time.

[0256] FIG. 19 shows the off-state current at room temperature (25° C.) calculated from the above current measurement. FIG. 19 shows the relationship between the source-drain voltage V and the off-state current I. From 19, when the source-drain voltage is 4 V, the off-current is about 40 zA / μm. In addition, under the condition of a source-drain voltage of 3.1 V, the off-current It was found that the current density was 10zA / μm or less. -21 Represents A.

[0257] Furthermore, the off-state current calculated from the above current measurement in a temperature environment of 85°C was The figure shows the source-drain voltage V and the off-state voltage V under a temperature environment of 85°C. It shows the relationship between the current I and the source-drain voltage of 3.1 V. It was found that the off-state current was 100 zA / μm or less.

[0258] As described above, in this example, in a transistor using a highly purified oxide semiconductor, It was confirmed that the flow was sufficiently small. [Example]

[0259] The number of times that a memory cell according to one embodiment of the disclosed invention can be rewritten was investigated. The survey results will be explained with reference to FIG.

[0260] The semiconductor device used in the investigation has a circuit configuration shown in FIG. An oxide semiconductor was used for a transistor corresponding to the transistor 162. The capacitance element corresponding to 4 has a capacitance value of 0.33 pF.

[0261] The investigation involves setting the initial memory window width and repeating the retention and writing of information a predetermined number of times. This was done by comparing the memory window width after the data was written. The third wiring in FIG. 1(A-1) is connected to 0V, and the third wiring in FIG. 1(A-2) is connected to 0V. or 5V, and the wire corresponding to the fourth wire is set to either 0V or 5V. When the potential of the wiring corresponding to the fourth wiring is 0V, Is the transistor (write transistor) corresponding to the transistor 162 in the off state? Therefore, the potential applied to the node FG is maintained. In this case, the transistor corresponding to the transistor 162 is in the ON state, so the third The potential of the wiring corresponding to the wiring is applied to the node FG.

[0262] The memory window width is one of the indicators that show the characteristics of a memory device. Between the states, the potential Vcg of the wiring corresponding to the fifth wiring and the potential Vcg of the wiring corresponding to the transistor 160 The curve (V The difference between the memory states is the shift amount ΔVcg of the memory state (cg-Id curve). The state where 0V is applied to FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG are In other words, the memory window width is This can be confirmed by sweeping the potential Vcg in the low and high states.

[0263] Figure 21(A) shows the memory window width in the initial state and the 9 Write times The horizontal axis in Figure 21(A) represents the V The vertical axis indicates cg(V), and the vertical axis indicates Id(A).

[0264] As shown in Figure 21(A), 1 × 10 9 Before and after writing many times, The Vcg-Id curves for writing in the High state and the Vcg-Id curves for writing in the Low state are almost No change is observed. Also, the Vcg-Id curve for writing in the High state and the Vcg-Id curve for writing in the Low state The shift (ΔVcg) from the Vcg-Id curve is also 1×10 9 Posted times There is almost no change before and after.

[0265] FIG. 21(B) shows the transistor in writing a high state or writing a low state. The potential of the wiring corresponding to the fifth wiring required to turn on 160 and the number of rewrites In FIG. 21B, the horizontal axis indicates the number of rewrites, and the vertical axis indicates the number of rewrites to the fifth wiring. The potential of the corresponding wiring, i.e., the apparent threshold voltage V of the transistor 160 th (V) vinegar.

[0266] The threshold value can generally be calculated by the tangent method. The slope of the curve is the square root of the drain current Id, and the vertical axis is the gate voltage Vg. The tangent line at the point where the voltage is maximum is found. The intercept is the threshold value. In Figure 21(B), the apparent threshold value V th of Calculated.

[0267] Table 1 shows the memory window width calculated from Figure 21(B). The width of the apparent threshold voltage V of the transistor 160 when writing a high state th_ H and the apparent threshold voltage V of the transistor 160 when writing the low state. th_L and The difference was calculated.

[0268] [Table 1]

[0269] From Table 1, the memory cell of this embodiment has a write speed of 1×10 9 Before and after the The change in window width was within 2%, specifically 1.68%. Tomo1×109 It was shown that the semiconductor device did not deteriorate before and after the write operation.

[0270] FIG. 21(C) shows the relationship between the number of rewrites and the mutual conductance (gm) of the memory cell. In Figure 21(C), the horizontal axis represents the number of rewrites, and the vertical axis represents the mutual conductance (g m) values are shown.

[0271] When the transconductance (gm) of the memory cell decreases, it becomes difficult to distinguish between the written and erased states. However, as shown in FIG. 21(C), the memory cell of this embodiment is 10 9 It can be seen that there is almost no change in the gm value even after rewriting. The semiconductor device according to this embodiment is 9 Extremely reliable, with no deterioration even after multiple rewrites It can be said that this is a semiconductor device.

[0272] As described above, the memory cell according to one embodiment of the disclosed invention can perform data storage and writing in one step. 0 9 Even after repeated rewriting, the characteristics do not change and the rewriting durability is extremely high. According to one aspect of the present invention, a highly reliable memory cell and an extremely reliable memory cell having the same are provided. It can be said that a highly reliable semiconductor device can be realized. [Explanation of symbols]

[0273] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 116 Channel formation region 120 Impurity region 122 Metal layer 124 Metal compound area 128 Insulating Layer 130 Insulating layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 146 Gate insulating layer 148a Gate electrode 148b Electrode 150 insulating layer 152 Insulating layer 154 Electrode 156 Wiring 156a Wiring 156b Wiring 160 transistors 162 transistors 164 Capacitor 170 memory cells 180 Potential conversion circuit 190 first drive circuit 192 Second driving circuit 195 Wiring 211 Readout circuit 212 control circuit 213 Delay Circuit 214 Buffer Circuit 221 Decoder Circuit 222 control circuit 223 Buffer Circuit 224 Buffer Circuit 225 Level Shift Circuit 231 Switch 232 Switch 233 Signal generation circuit 701 Case 702 Case 703 Display section 704 keyboard 711 Main Unit 712 Stylus 713 Display section 714 Operation Button 715 external interface 720 e-books 721 Case 723 Case 725 Display section 727 Display section 731 Power supply 733 Operation Key 735 Speaker 737 Shaft 740 chassis 741 Case 742 Display Panel 743 Speaker 744 microphone 745 Operation Key 746 Pointing Device 747 Camera Lens 748 External connection terminal 749 Solar Cells 750 external memory slot 761 Main Unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television Equipment 771 Case 773 Display section 775 Stand 780 Remote Controlled Machine 800 measurement system 802 Capacitor element 804 transistor 805 transistor 806 Transistor 808 Transistor 1200 p-type transistors 1210 p-type transistor 1220 n-type transistor 1230 p-type transistor 1240 p-type transistor 1250 n-type transistor 1260 p-type transistor 1270 n-type transistor 1280 p-type transistor 1290 n-type transistor 1300 transistors 1310 transistor 1320 transistor 1330 transistor 1340 transistor 1350 Capacitor 1360 Capacitor 1370 Capacitive element 1380 Capacitive element 1390 transistor

Claims

1. a first transistor having silicon in a channel formation region, a second transistor having an oxide semiconductor in a channel formation region, and a capacitor; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive layer having a region overlapping with the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having the same material as the second conductive layer and functioning as the other electrode of the capacitor; a second insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; a third insulating layer having a region located above the second insulating layer; a sixth conductive layer having a region in contact with an upper surface of the third insulating layer and electrically connected to the second conductive layer through an opening in the third insulating layer; a seventh conductive layer having a region in contact with the upper surface of the third insulating layer and having the same material as the sixth conductive layer; the seventh conductive layer has a function of supplying a potential to the first transistor, the opening in the third insulating layer does not have a region overlapping with the oxide semiconductor layer.

2. a first transistor having silicon in a channel formation region, a second transistor having an oxide semiconductor in a channel formation region, and a capacitor; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive layer having a region overlapping with the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having the same material as the second conductive layer and functioning as the other electrode of the capacitor; a second insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; a third insulating layer having a region located above the second insulating layer; a sixth conductive layer having a region in contact with an upper surface of the third insulating layer and electrically connected to the second conductive layer through an opening in the third insulating layer; a seventh conductive layer having a region in contact with the upper surface of the third insulating layer and having the same material as the sixth conductive layer; the seventh conductive layer has a function of supplying a potential to the first transistor, the opening of the third insulating layer does not have a region overlapping with the oxide semiconductor layer, the seventh conductive layer has a region overlapping with a channel formation region of the first transistor and a region overlapping with a channel formation region of the second transistor.

3. 3. The semiconductor device according to claim 1, wherein the third insulating layer has a thickness greater than that of the second insulating layer.

Images