Integrated circuit including vertical capacitor

Abstract

SOLUTION: In some examples, an integrated circuit comprises: a first plate (167); a second plate (168); and a dielectric layer (262) disposed between the first plate (167) and second plate (168). The first plate (167), the second plate (168), and the dielectric layer (262) are disposed on an isolation region (250) of the integrated circuit to form a vertical capacitor (252).SELECTED DRAWING: Figure 1(d)

Description

[Technical Field]

[0001] A nonvolatile memory (NVM) bitcell is an electronic device element configured to store information. The electrical state (e.g., threshold voltage) of the bitcell can be used to define a logic level, such as a logic low level (representing a digital low or 0) or a logic high level (representing a digital high or 1). This defined logic level is sometimes referred to as the information (or bit) stored in the bitcell. Summary of the Invention

[0002] According to at least one example, an integrated circuit includes a first plate, a second plate, and a dielectric layer disposed between the first plate and the second plate, the first plate and the second plate forming a vertical capacitor, and the first plate, the second plate, and the dielectric layer of the vertical capacitor are disposed over an isolation region of the integrated circuit.

[0003] According to another example, an integrated circuit includes a floating gate flash bitcell including at least a control gate layer, a word line gate layer, and a dielectric layer, and the integrated circuit also includes a vertical capacitor disposed on a shallow trench isolation (STI) region, the vertical capacitor including the control gate layer, the word line gate layer, and the dielectric layer, the dielectric layer disposed between the control gate layer and the word line gate layer.

[0004] According to yet another example, a method for fabricating an integrated circuit having at least one vertical capacitor over a shallow trench isolation (STI) region on a substrate includes depositing a first dielectric layer over the STI region, depositing a first polysilicon layer over the first dielectric layer, patterning the first polysilicon layer to form a first plate of the vertical capacitor having a sidewall, depositing a second dielectric layer such that the second dielectric layer abuts the sidewall, and depositing a second polysilicon layer such that the second polysilicon layer abuts the second dielectric layer and forms a second plate of the vertical capacitor. [Brief explanation of the drawings]

[0005] [Figure 1A] 1 illustrates a portion of an exemplary layout of a floating gate flash bit cell memory array, in accordance with various examples.

[0006] [Figure 1B] 1 illustrates a side view cross section of an exemplary bitcell pair, according to various examples.

[0007] [Figure 1C] 1 illustrates an exemplary layout of an array of vertical capacitors, in accordance with various examples.

[0008] [Figure 1D] 1 illustrates a side view cross section of an exemplary vertical capacitor, according to various examples.

[0009] [Figure 2] 1 illustrates an exemplary method performed to fabricate a vertical capacitor, according to various examples.

[0010] [Figure 3A] 1 illustrates the fabrication of an exemplary bitcell, in accordance with various examples. [Figure 3B] 1 illustrates the fabrication of an exemplary bitcell, in accordance with various examples. [Figure 3C] 1 illustrates the fabrication of an exemplary bitcell, in accordance with various examples. [Figure 3D] 1 illustrates the fabrication of an exemplary bitcell, in accordance with various examples. [Figure 3E] 1 illustrates the fabrication of an exemplary bitcell, in accordance with various examples. [Figure 3F] 1 illustrates the fabrication of an exemplary bitcell, in accordance with various examples. [Figure 3G] 1 illustrates the fabrication of an exemplary bitcell, in accordance with various examples.

[0011] [Figure 4A]1 illustrates the fabrication of at least one vertical capacitor, according to various embodiments. [Figure 4B] 1 illustrates the fabrication of at least one vertical capacitor, according to various embodiments. [Figure 4C] 1 illustrates the fabrication of at least one vertical capacitor, according to various embodiments. [Figure 4D] 1 illustrates the fabrication of at least one vertical capacitor, according to various embodiments. [Figure 4E] 1 illustrates the fabrication of at least one vertical capacitor, according to various embodiments. [Figure 4F] 1 illustrates the fabrication of at least one vertical capacitor, according to various embodiments. [Figure 4G] 1 illustrates the fabrication of at least one vertical capacitor, according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0012] Flash memory is a non-volatile storage medium that can store information in an array of bit cells. This stored information (or "bits") can be electrically erased, programmed, and read. In some cases, an array of floating gate transistor bit cells can be used in flash memory. A floating gate transistor bit cell resembles a standard metal-oxide field-effect transistor (MOSFET), except that it includes multiple gates, such as a control gate and a floating gate. As described above, the electrical state of the bit cell can be used to define a logic level, which can be referred to as a bit, stored in the bit cell. This can be done using a change in the threshold voltage of the bit cell. The threshold voltage of a floating gate type transistor bit cell can change due to the presence or absence of trapped charge in its floating gate, which further changes the threshold voltage of the floating gate transistor bit cell (relative to its previous threshold voltage). When electrons are trapped in the floating gate type transistor bit cell, the threshold voltage (or electrical state of the floating gate transistor bit cell) can be characterized as a digital low or "0," which is stored as a bit in the bit cell. Conversely, when the floating gate is depleted of electrons, the electrical state may be referred to as a digital high or "1" that is stored as a bit in the bit cell.

[0013] As discussed above, the character of the bit stored in a floating gate bit cell (e.g., a digital high or low) depends on the presence or absence of charge at the floating gate. In some cases, charge is stored / depleted in the floating gate by applying a voltage potential (e.g., 10 V or higher) at the control gate of the floating gate transistor bit cell. In some cases, a charge pump circuit is used to apply the voltage potential. An exemplary charge pump circuit boosts the input charge to provide a higher voltage than the voltage supplied to the charge pump circuit. In some cases, the charge pump circuit is capacitor-based, and capacitor-based charge pump circuits typically employ capacitors such as metal-over-semiconductor (MOS) capacitors.

[0014] MOS capacitors typically include a layer of metal (e.g., metal contacts), a layer of insulating material (e.g., silicon dioxide), and a layer of semiconductor material (e.g., silicon). These layers are typically fabricated laterally, and the fabrication design of these capacitors results in parasitic capacitance being generated between the substrate (e.g., a p-type silicon substrate) and the capacitor's plate (e.g., an n-well), which interferes with the capacitance of the MOS capacitor and degrades its performance. To avoid the parasitic capacitance interference, planar poly-to-poly capacitors or metal-to-poly capacitors are used in charge pumps. However, fabricating such capacitors requires extra masks, increasing overall manufacturing costs. Therefore, an alternative capacitor design that can be used in charge pump circuits and alleviates the above-mentioned concerns is desirable.

[0015] Accordingly, at least some of the examples in this description are directed to systems and methods for fabricating vertical capacitors that can be used in floating gate flash bitcell technology. In at least some examples, the vertical capacitors described herein are fabricated on the same die as the floating gate flash bitcell without the use of additional masks. The vertical capacitors in this description are located in isolation regions, such as shallow trench isolation (STI) regions. Locating the vertical capacitors on STI regions prevents interference from the parasitic capacitances mentioned above (e.g., n-well to p-substrate). In at least some examples, the vertical capacitors utilize the word line gate layer and control gate layer of the flash bitcell as their capacitor plates. In at least some examples, the control gate layer and word line gate layer are separated by a dielectric layer, which may include a multi-layer structure.

[0016] FIG. 1( a) illustrates a portion of an exemplary layout 100 of a floating gate flash bit cell memory array (or floating gate bit cells) according to various examples. The layout 100 shows at least some of the layers that form the array of floating gate bit cells. The layout 100 includes bit line (BL) layers 106, 108, 110, 112, 114, and 116 and a source line (SL) layer 124. The layout 100 also includes word line (WL) gate layers 118 and 122, an erase gate (EG) layer 120, and control gate (CG) layers 102 and 104. The area occupied by the BL layers 106, 108, 110, 112, 114, and 116 is sometimes referred to as the active area. The layout 100 also illustrates at least some of the layers (e.g., the WL gate layers 118 and 122 and the CG layers 102 and 104) that form vertical capacitors used in charge pump circuits. This description is not limited to floating gate bitcell arrays that include the aforementioned gate layers, and the following vertical capacitor description is valid for other types of floating gate bitcells, including floating gate bitcells that do not use an erase gate layer.

[0017] 1(a) also illustrates a coordinate system 1, whose X and Y axes are respectively within the page of the drawing and whose Z axis is away from the page of the drawing. For example, from a layout 100 perspective (as shown in FIG. 1(a)), one or more bit cells are positioned on a line 50 aligned with the Y axis, while from a manufacturing perspective (as shown in FIG. 1(b)), a cross-sectional side view of one or more bit cells can be seen in the YZ plane along line 50.

[0018] Layout 100 is used, at least in part, as a layout (or blueprint) for fabricating an array of vertical capacitors (not explicitly depicted) that are implemented with an array of floating gate bit cells and a CMOS logic array. In some examples, layout 100 may be used to fabricate an array of bit cells that are implemented as a standalone memory device (e.g., implemented on its own semiconductor die, enclosed within its own chip package, etc.). In some examples, layout 100 may be used to fabricate an array of bit cells that are implemented in an integrated circuit (IC) (e.g., implemented on a semiconductor die that includes additional circuitry).

[0019] 1(b), a side view cross section of an exemplary pair of bit cells 70, 80 can be seen in the Y-Z plane along line 50 (FIG. 1(a)) through bit line 112. Other bit cells can be seen in the Y-Z plane along other bit lines 106, 108, 110, 114, and 116, which lie on the Y axis.

[0020] Bitcells 70 and 80 are substantially similar in structure. Bitcell 70 includes a bitline layer 112 disposed on a substrate 126. Bitcell 70 also includes a wordline (WL) gate layer 118, a control gate layer 102, a floating gate layer 132, and an erase gate layer 120 (which is also shared by bitcell 80). Bitcell 70 further includes dielectric layers 138 and 140. These dielectric layers are fabricated to provide isolation between the wordline gate layer 118, the control gate layer 102, the floating gate layer 132, and the erase gate 120. In some examples, substrate 126 may include silicon. In such examples, dielectric layer 140 may include silicon dioxide, and dielectric layer 138 may include silicon nitride. Bitcell 70 also includes a dielectric layer 111, which acts as a floating gate dielectric and provides isolation between the floating gate 132 and the substrate 126. The bitcell 70 forms a WL transistor including a WL gate layer 118 (similar to the gate of a MOSFET), a bitline layer 112 (similar to the drain of a MOSFET), and a sourceline layer 124 (similar to the source of a MOSFET). The bitcell 70 also includes an implanted layer 128 disposed in a substrate 126 below the wordline gate layer 118. In some examples, the implanted layer 128 can be used to modify the threshold voltage of the WL transistor. In some examples, the substrate 126 also includes an additional implanted layer, such as an anti-punchthrough layer 136 formed by implanting a dopant (e.g., boron) into the substrate 126. While the bitcell 70 (or an array of such bitcells) shown in FIG. 1(b) includes an erase gate layer 120, a control gate layer 102, a wordline gate layer 118, and a floating gate layer 132, this description is not limited to floating gate bitcells 70 including the aforementioned gate layers. This description is valid for floating gate bitcell arrays. Here, each floating gate bitcell includes a word line gate layer 118, a control gate layer 102, and a floating gate layer 132.

[0021] Similar to bit cell 70, bit cell 80 includes a bit line 112, a source line layer 124, an erase gate layer 120, a floating gate layer 134, a control gate layer 104, and a word line gate layer 122. Bit cell 80 also includes dielectric layers 146, 148, which separate word line gate layer 122, control gate layer 104, floating gate layer 134, and erase gate 120 from one another. Bit cell 80 also includes a dielectric layer 111, which serves as a floating gate 134 dielectric and provides isolation between the floating gate 132 and a substrate 126. In some examples, substrate 126 may include silicon. In such examples, dielectric layer 146 may include silicon dioxide, and dielectric layer 148 may include silicon nitride. In some examples, word line gate layers 118, 122 and control gate layers 102, 104 include polysilicon.

[0022] In some examples, the bitcells 70, 80 may be fabricated within an integrated circuit (IC) (eg, implemented on a semiconductor die that includes additional circuitry).

[0023] As described above, the vertical capacitors are formed using the wordline gate layer and control gate layer on the same die as the array of floating gate bit cells. Unlike the bit cells 70, 80, which are fabricated on the substrate 126, the vertical capacitors are fabricated on isolation regions (e.g., STI regions) to prevent parasitic capacitance interference. While this description generally describes a vertical capacitor on a single STI region, in some examples, multiple vertical capacitors are distributed among multiple isolation regions (e.g., STI regions).

[0024] 1(c) shows an example layout 160 of an array of vertical capacitors formed using control gate layers 167, 169, 171, ..., 237 and word line gate layers 166, 168, 170, ..., 236 of bit cells (not explicitly shown) located on the same die as the vertical capacitors. Layout 160 includes a contact layer 162 that couples with each of the control gate layers 167, 169, 171, ..., 237. Layout 160 also includes a contact layer 164 that couples with each of the word line gate layers 166, 168, 170, ..., 236. In some examples, word line gate layers 166, 168, 170, ..., 236 and control gate layers 167, 169, 171, ..., 237 comprise polysilicon.

[0025] In some examples, layout 160 may be used in conjunction with layout 100 to fabricate an array of vertical capacitors and bit cells that are implemented in an integrated circuit (IC) (e.g., implemented on a semiconductor die that includes additional circuitry).

[0026] FIG. 1(d) shows a side view cross section of a vertical capacitor disposed along a portion of line 165 (FIG. 1(c)). FIG. 1(d) shows vertical capacitors 251-260 disposed on an STI region 250 disposed on a substrate 126. The capacitor shown in FIG. 1(d) includes word line gate layers 166, 168, 170, 172, 174, and 176 and control gate layers 167, 169, 171, 173, and 175. For example, word line gate layer 166 serves as one plate, and control gate layer 167 serves as the other plate of vertical capacitor 251. In some examples, a dielectric layer 261 is disposed between word line gate layer 166 and control gate layer 167. In some examples, this dielectric layer 261 may include a three-layer structure. In some examples, this three-layer structure includes two dielectric layers 271 that are oxide layers and dielectric layer 272 that is a nitride layer. In examples where the substrate includes silicon, dielectric layer 271 includes silicon dioxide and dielectric layer 272 includes silicon nitride. Other materials may also be used.

[0027] Similar to vertical capacitor 251 formed between word line gate 166 and control gate 167, vertical capacitor 252 is formed between control gate layer 167 and word line gate layer 168, with dielectric layer 262 disposed therebetween. Similar to vertical capacitor 251, vertical capacitor 252 is also disposed over STI region 250. In some examples, dielectric layer 262 includes a three-layer structure. In some examples, this three-layer structure includes two dielectric layers 296 that are oxide layers and dielectric layer 297 that is a nitride layer. In embodiments where the substrate includes silicon, dielectric layer 296 includes silicon dioxide and dielectric layer 297 includes silicon nitride. Similar to the vertical capacitors 251 and 252, vertical capacitors 253-260 are formed on the STI region 250 between the word line gate layers 168, 170, 172, 174, and 176 and the control gate layers 169, 171, 173, and 175, and each vertical capacitor 253-260 includes a dielectric layer, which may include a three-layer structure.

[0028] Referring to Figure 2, an exemplary method 300 may be performed to fabricate a vertical capacitor disposed over an STI region. Method 300 will be described in conjunction with the exemplary fabrication flow charts shown in Figures 3(a)-3(g) and 4(a)-4(g). Figures 3(a)-3(g) illustrate the fabrication of an exemplary bit cell including at least a control gate layer and a word line gate layer, and Figures 4(a)-4(g) illustrate the fabrication of at least one vertical capacitor using the control gate layer and word line gate layer of the above-referenced bit cell to form parallel plates.

[0029] The steps shown in Figures 3(a) to 3(g) can be seen along line 50 (Figure 1(a)), and the steps shown in Figures 4(a) to 4(g) can be seen along line 165 (Figure 1(c)).

[0030] For simplicity, the fabrication steps shown in Figures 3(a)-3(g) are for a single bitcell, and the steps shown in Figures 4(a)-4(g) are for at least one vertical capacitor formed using the bitcell's control gate layer and wordline gate layer. However, in other examples, these descriptions can be adapted for fabricating multiple bitcells and vertical capacitors.

[0031] Method 300 begins by obtaining substrate 126 (step 310) that includes an STI region, such as STI region 401 (FIG. 4(a)) that includes silicon dioxide. The STI region is created early in the semiconductor device fabrication process, before other electronic elements (e.g., transistors, bit cells) are formed. In some examples, fabricating the STI region involves etching a pattern of trenches (not explicitly shown in FIGS. 3(a)-3(g) and 4(a)-4(g)) in a substrate, such as substrate 126. Further steps in fabricating the STI region include depositing one or more dielectric materials (e.g., silicon dioxide) to fill the trenches, and then removing excess dielectric material using a planarization technique (e.g., chemical-mechanical planarization).

[0032] In some examples, additional steps (not explicitly included in method 300) can be performed following step 310. The additional steps can include depositing a floating dielectric layer 405 and a floating gate layer 410 to form a portion of the bitcell (FIGS. 3(a) and 3(b) , respectively). The deposition of the gate layer 410 can be seen in FIG. 4(b), but the deposition of the dielectric layer 405 is masked to include it in the fabrication of the bitcell. In some examples, the dielectric layer 405 can be fabricated such that the dielectric layer 405 is disposed over the STI region 410 (not explicitly shown in FIG. 4(b)). In some examples, the floating gate layer 410 comprises polysilicon. In some examples, the aforementioned deposition steps can be performed using chemical vapor deposition.

[0033] In some examples, from a vertical capacitor perspective, the method 300 may also include removing the floating gate layer 410 from the STI regions 401 (FIG. 4(c)). Masking and dry / wet etching techniques can be used to remove the floating gate layer 410 so that the gate layer 410 is removed from the STI regions 401 (FIG. 4(c)), but not from the dielectric layer 405 of FIG. 3(c). In some examples, chemical mechanical polishing techniques can be used to remove the floating gate layer 410 from the STI regions 401.

[0034] After removing the floating gate layer 410 from the STI region 401, the method 300 may proceed to step 320, which may include depositing a dielectric layer 413. From the perspective of a vertical capacitor, the dielectric layer 413 is deposited on the STI region 401 (FIG. 4(c)), and from the perspective of a bitcell, the dielectric layer 413 is deposited on the floating gate layer 410 (FIG. 3(c)). In some examples, the dielectric layer 413 may include a three-layer structure. In some examples, this three-layer structure includes two dielectric layers 412, 416 comprising silicon dioxide and a dielectric layer 414 comprising silicon nitride. In some examples, step 320 may also include implanting a dopant (e.g., boron) into the substrate 126 to form an anti-punchthrough layer 136 (FIG. 3(c)).

[0035] The method 300 then moves to step 330, which includes depositing a control gate layer 420 on the dielectric layer 413. The control layer 420 may be seen from the perspective of both the vertical capacitor (FIG. 4(c)) and the bitcell (FIG. 3(c)). In some examples, step 330 may also include depositing a dielectric layer 430 on the control gate layer 420. Again, the dielectric layer 430 may be seen from the perspective of both the vertical capacitor (FIG. 4(c)) and the bitcell (FIG. 3(c)). In some examples, deposition of both the control gate layer 420 and the dielectric layer 430 may be performed using chemical vapor deposition. In some examples, the control gate layer 420 includes polysilicon and the dielectric layer 430 includes silicon nitride.

[0036] Next, method 300 may move to step 340, which includes patterning control gate layer 430 (FIGS. 3(d) and 4(d)). Patterning may be performed using photolithography and dry plasma etching. From the perspective of a vertical capacitor, control gate 420, or at least a portion of control gate layer 420, following step 340, forms the first plate of the vertical capacitor. As noted above, for brevity, method 300, FIGS. 3(a)-3(g), and 4(a)-4(g) describe the formation of a single bit cell and at least one vertical capacitor. In other examples, patterning may be performed such that multiple bit cells and vertical capacitors may be formed. FIG. 4(d) shows sidewalls 2, 3 of patterned control gate layer 420.

[0037] The method 300 may proceed to step 350, which includes depositing a dielectric layer 417 on the sidewalls 2, 3 of the control gate layer 420 (FIG. 4(e)). The deposition of the dielectric layer 417 can also be seen in FIG. 3(e). While FIG. 4(e) shows the dielectric layer 417 in contact with the control gate layer 420 and the dielectric layer 430 (e.g., the deposition of the dielectric layer 417 may extend from the top of the dielectric layer 416 to the top of the dielectric layer 430), in some examples, the dielectric layer 417 only contacts the control gate layer 420. In some examples, following the deposition of the dielectric layer 417, a portion of the floating gate layer 410 may be etched / removed, and then a dopant (such as boron) may be implanted into the substrate 126. In some examples, the dielectric layer 417 assumes a three-layer structure including dielectric layers 418, 420, and 422. In some examples, the dielectric layers 418, 422 include silicon dioxide and the dielectric layer 420 includes silicon nitride.

[0038] Next, method 300 may proceed to step 360, which includes depositing polysilicon layer 421 such that polysilicon layer 421 is disposed on top of dielectric layer 416, dielectric layers 418, 420, 422, and 430 (FIGS. 3(f), 3(g), 4(f), and 4(g)). Step 360 may also include etching a portion of polysilicon layer 421 to form two separate polysilicon layers 413 and 415, referred to as the word line gate layer and the erase gate layer, respectively (FIGS. 3(g) and 4(g)).

[0039] Modifications may be made to the exemplary embodiments described and other embodiments may be made within the scope of the claims of the present invention. It is possible.

Claims

1. 1. An integrated circuit comprising: A first plate, a second plate, and a dielectric layer disposed between the first and second plates; Including, the first and second plates and the dielectric layer form a vertical capacitor, the first and second plates and the dielectric layer of the vertical capacitor being disposed over an isolation region of the integrated circuit.

2. 10. The integrated circuit of claim 1, further comprising a second vertical capacitor; the second vertical capacitor a second plate; and a third plate; and a second dielectric layer disposed between the second and third plates over the isolation region; , an integrated circuit.

3. 10. The integrated circuit of claim 1, The integrated circuit further comprises a flash bit cell including at least the first plate and the second plate.

4. 10. The integrated circuit of claim 1, The integrated circuit, wherein the dielectric layer comprises a first silicon dioxide layer, a second silicon dioxide layer, and a silicon nitride layer.

5. 10. The integrated circuit of claim 1, The integrated circuit, wherein the isolation region is disposed on a silicon substrate.

6. 10. The integrated circuit of claim 1, The integrated circuit, wherein the isolation region comprises a shallow trench isolation (STI) region.

7. 10. The integrated circuit of claim 1, the isolation regions comprising silicon dioxide.

8. 1. An integrated circuit comprising: a floating gate flash bitcell including at least a control gate layer, a word line gate layer, and a dielectric layer; a vertical capacitor disposed on a shallow trench isolation (STI) region; Including, the vertical capacitor includes the control gate layer, the word line gate layer, and the dielectric layer, the dielectric layer being disposed between the control gate layer and the word line gate layer.

9. 9. An integrated circuit according to claim 8, the control gate layer and the word line gate layer comprise polysilicon.

10. 9. An integrated circuit according to claim 8, The integrated circuit, wherein the STI regions comprise silicon dioxide.

11. 9. An integrated circuit according to claim 8, The integrated circuit wherein the STI region is disposed on a silicon substrate.

12. 9. An integrated circuit according to claim 8, The integrated circuit further includes a floating gate layer, the dielectric layer being located between the control gate layer and the floating gate layer.

13. 9. An integrated circuit according to claim 8, The integrated circuit wherein the dielectric layer comprises at least one silicon dioxide layer.

14. 9. An integrated circuit according to claim 8, The integrated circuit, wherein the dielectric layer comprises a first silicon dioxide layer, a second silicon dioxide layer, and a silicon nitride layer.

15. 1. A method for manufacturing an integrated circuit having at least one vertical capacitor on a shallow trench isolation (STI) region on a substrate, comprising: depositing a first dielectric layer over the STI region; depositing a first polysilicon layer over the first dielectric layer; patterning the first polysilicon layer to form a first plate of the vertical capacitor having sidewalls; depositing a second dielectric layer such that the second dielectric layer contacts the sidewall; and depositing a second polysilicon layer such that the second polysilicon layer contacts the second dielectric layer and forms a second plate of the vertical capacitor; A method comprising:

16. 16. The method of claim 15, The method, wherein the first dielectric layer comprises a first silicon dioxide layer, a second silicon dioxide layer, and a silicon nitride layer.

17. 16. The method of claim 15, The method, wherein the second dielectric layer comprises a first silicon dioxide layer, a second silicon dioxide layer, and a silicon nitride layer.

18. 16. The method of claim 15, The method wherein the STI regions comprise silicon dioxide.

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