Display device

Abstract

To provide a display device capable of improving the yield or improving the reliability.SOLUTION: A display device in an embodiment includes: a substrate including a display region that displays an image and a peripheral region around the display region; a plurality of display elements disposed in the display region and each including a lower electrode, an upper electrode existing over the lower electrode, and an organic layer positioned between the lower electrode and the upper electrode and emitting light according to the voltage application; a first partition wall disposed in the display region and between the adjacent display elements; and a second partition wall disposed in the peripheral region and connected to the first partition wall. The first partition wall and the second partition wall include a conductive lower part and an upper part including an end part protruding from a side surface of the lower part. In addition, the second partition wall includes a plurality of rectangular openings.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. For these types of display devices, technology that can improve yield and reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device that can achieve an improvement in yield or reliability. [Means for solving the problem]

[0005] A display device according to one embodiment includes a substrate having a display region for displaying an image and a peripheral region surrounding the display region; a plurality of display elements arranged in the display region, each of which includes a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition wall arranged in the display region and between adjacent display elements; and a second partition wall arranged in the peripheral region and connected to the first partition wall. The first partition wall and the second partition wall each include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. Furthermore, the second partition wall has a plurality of elongated openings. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of the display device for explaining the structure of the peripheral region. [Figure 5] FIG. 5 is a schematic cross-sectional view of a part of the peripheral region taken along line VV in FIG. [Figure 6] FIG. 6 is a schematic enlarged cross-sectional view of a portion of the partition wall disposed in the peripheral region. [Figure 7] FIG. 7 is a schematic enlarged plan view of region VII in FIG. [Figure 8] FIG. 8 is a schematic enlarged plan view of region VIII in FIG. [Figure 9A] FIG. 9A is a schematic cross-sectional view showing an example of a manufacturing process of a display device. [Figure 9B] FIG. 9B is a schematic cross-sectional view showing a step subsequent to FIG. 9A. [Figure 9C] FIG. 9C is a schematic cross-sectional view showing a step subsequent to FIG. 9B. [Figure 9D] FIG. 9D is a schematic cross-sectional view showing a step subsequent to FIG. 9C. [Figure 9E] FIG. 9E is a schematic cross-sectional view showing a step subsequent to FIG. 9D. [Figure 9F] FIG. 9F is a schematic cross-sectional view showing a step subsequent to FIG. 9E. [Figure 9G] FIG. 9G is a schematic cross-sectional view showing a step subsequent to FIG. 9F. [Figure 9H] FIG. 9H is a schematic cross-sectional view showing a step subsequent to FIG. 9G. [Figure 9I] FIG. 9I is a schematic cross-sectional view showing a step subsequent to FIG. 9H. [Figure 10] FIG. 10 is a schematic plan view of a peripheral region according to a comparative example. [Figure 11] FIG. 11 is a schematic cross-sectional view of the peripheral region according to the comparative example. [Figure 12] FIG. 12 is a schematic enlarged plan view of the peripheral region according to the second embodiment. [Figure 13] FIG. 13 is another schematic enlarged plan view of the peripheral region according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0008] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0009] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is rectangular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to a rectangle and may be other shapes such as a square, a perfect circle, or an ellipse.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0013] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] In the display area DA, a plurality of scanning lines G that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines S that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL are arranged. In the example of Fig. 1, the scanning lines G and the power supply lines PL extend in the X direction, and the signal lines S extend in the Y direction, but this is not limiting.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line G. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0020] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP51, AP52, and AP53 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel opening AP51 is larger than the pixel opening AP52, which is larger than the pixel opening AP53. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio and the subpixel SP3 has the smallest aperture ratio.

[0021] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP51. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP52. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP53.

[0022] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with pixel opening AP51 constitute the display element DE1 of subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with pixel opening AP52 constitute the display element DE2 of subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with pixel opening AP53 constitute the display element DE3 of subpixel SP3. Display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. A rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0023] Conductive partition walls 6A (first partition walls) are disposed on the rib layer 5. The partition walls 6A entirely overlap the rib layer 5 and have the same planar shape as the rib layer 5. That is, the partition walls 6A have pixel openings AP61, AP62, and AP63 in the subpixels SP1, SP2, and SP3, respectively. From another perspective, the rib layer 5 and the partition walls 6A have a lattice shape in a planar view and surround each of the subpixels SP1, SP2, and SP3. The partition walls 6A serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0024] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines G, signal lines S, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0025] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0026] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. This shape of the partition wall 6A is called an overhanging shape.

[0027] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Also, in the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0028] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP51. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP52. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP53. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6A.

[0029] Display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. Display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. Display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. The cap layers CP1, CP2, and CP3 function as optical adjustment layers that improve the extraction efficiency of light emitted from organic layers OR1, OR2, and OR3, respectively.

[0030] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0031] A portion of the laminated film FL1 is located on the upper portion 62. This portion is separated from a portion of the laminated film FL1 that is located around the partition wall 6A (a portion that constitutes the display element DE1). Similarly, a portion of the laminated film FL2 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL2 that is located around the partition wall 6A (a portion that constitutes the display element DE2). Furthermore, a portion of the laminated film FL3 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL3 that is located around the partition wall 6A (a portion that constitutes the display element DE3).

[0032] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6A around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6A around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6A around the subpixel SP3.

[0033] 3, the stacked film FL1 and the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE12 on the partition wall 6A. Also, the stacked film FL1 and the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE13 on the partition wall 6A.

[0034] The sealing layers SE11, SE12, and SE13 (first sealing layers) are covered with a resin layer RS1 (first resin layer). The resin layer RS1 is covered with a sealing layer SE2 (second sealing layer). The sealing layer SE2 is covered with a resin layer RS2 (second resin layer). The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with portions of them extending into the peripheral area SA.

[0035] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0036] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0037] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0038] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0039] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0040] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0041] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0042] For example, the upper portion 62 of the partition wall 6A has a laminated structure of a lower layer made of a metal material and an upper layer made of a conductive oxide. Examples of the metal material that can be used to form the lower layer include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the upper layer include ITO and IZO. The upper portion 62 may also have a single-layer structure made of a metal material. Furthermore, the upper portion 62 may also include a layer made of an insulating material.

[0043] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal on the signal line S is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0044] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0045] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0046] 4 is a schematic plan view of the display device DSP for explaining the structure of the peripheral area SA. The display device DSP further includes partition walls 6B (second partition walls) arranged in the peripheral area SA. The partition walls 6B are formed by the same process as the partition walls 6A shown in FIGS. 2 and 3, and have the same structure as the partition walls 6A. In FIG. 4, a dot pattern is applied to the area corresponding to the partition walls 6B. The partition walls 6B surround the display area DA.

[0047] The partition wall 6B has ends E1a, E1b, E1c, and E1d (first to fourth ends). The end E1a is located between the display area DA and the terminal portion T and extends parallel to the X direction. The end E1b is located on the opposite side of the display area DA from the end E1a and extends parallel to the X direction. The end E1c connects the left ends of the ends E1a and E1b in the figure and extends parallel to the Y direction. The end E1d connects the right ends of the ends E1a and E1b in the figure and extends parallel to the Y direction.

[0048] The display device DSP includes a dam structure DS arranged in the peripheral area SA. In the example of Fig. 4, the dam structure DS includes rectangular dam portions DM1 and DM2.

[0049] The dam portion DM1 surrounds the partition wall 6B. The dam portion DM2 surrounds the dam portion DM1. Parts of the dam portions DM1 and DM2 pass between the terminal portion T and the partition wall 6B.

[0050] The shapes of the dam portions DM1 and DM2 are not limited to the example shown in Fig. 4. The number of dam portions provided in the dam structure DS may be one, or three or more.

[0051] Fig. 5 is a schematic cross-sectional view of a part of the peripheral area SA taken along line VV in Fig. 4. The cross-sectional structure shown in this figure can be applied to any position in the peripheral area SA. The circuit layer 11 shown in FIG. 3 includes inorganic insulating layers 31, 32, and 33 formed of an inorganic insulating material, an organic insulating layer 34 formed of an organic insulating material, and metal layers 41, 42, and 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is disposed on the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is disposed on the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is disposed on the organic insulating layer 34 and is covered by the organic insulating layer 12.

[0052] Both dam portions DM1 and DM2 protrude above the substrate 10. In the example of FIG. 5, dam portion DM1 is formed of organic insulating layers 12 and 34. Dam portion DM2 is also formed of organic insulating layers 12 and 34. That is, in this embodiment, dam portions DM1 and DM2 are formed of the same material as organic insulating layers 12 and 34 by the same process as organic insulating layers 12 and 34.

[0053] The circuit layer 11 includes a power supply line PW to which a common voltage is applied. The power supply line PW is connected to the terminal portion T shown in FIG. 4. In the example of FIG. 5, the power supply line PW has a first wiring W1 formed by a metal layer 42 and a second wiring W2 formed by a metal layer 43. The first wiring W1 and the second wiring W2 are in contact with each other at a contact portion CN0 located between an end E0 of the organic insulating layer 12 and a dam portion DM1.

[0054] The peripheral area SA is further provided with a conductive relay layer RL that connects the partition wall 6B and the power supply line PW, and a rib layer 5. The relay layer RL is formed, for example, from the same material and by the same process as the above-described lower electrodes LE1, LE2, and LE3.

[0055] The relay layer RL is located closer to the display area DA (left side in the figure) than the dam portion DM1, and covers the organic insulating layer 12. The rib layer 5 continuously covers the relay layer RL and the dam portions DM1 and DM2. The end of the rib layer 5 is located outside the dam portion DM2.

[0056] The partition wall 6B is disposed on the rib layer 5. The rib layer 5 is open at a contact portion CN1 that overlaps the organic insulating layer 12 in a plan view. The partition wall 6B is in contact with the relay layer RL at the contact portion CN1.

[0057] The relay layer RL is in contact with the second wiring W2 of the power supply line PW at the contact portion CN2, which is located between the end E0 of the organic insulating layer 12 and the dam portion DM1 in plan view.

[0058] The partition wall 6B is covered with a laminated film FL. The laminated film FL is covered with a sealing layer SE1. The laminated film FL is one of the laminated films FL1, FL2, and FL3 shown in FIG. 3. The sealing layer SE1 is one of the sealing layers SE11, SE12, and SE13 shown in FIG. 3.

[0059] In the example of Figure 5, the end E2 of the stacked film FL and the sealing layer SE1 is located between the end E1a of the partition wall 6B and the dam portion DM1. The stacked film FL is divided by the end E1a. The sealing layer SE1 continuously covers each divided portion of the stacked film FL1. By dividing the stacked film FL in this way, it is possible to block the path of moisture penetration through the stacked film FL.

[0060] 3 are arranged above the sealing layer SE1. The resin layer RS1, sealing layer SE2, and resin layer RS2 cover the sealing layer SE1 and the rib layer 5. The laminated film FL and the end E2 of the sealing layer SE1 are covered by the resin layer RS1. The dam portion DM1 serves to block the resin layer RS1 before it hardens during the manufacture of the display device DSP.

[0061] 5, the end portion Er1 of the resin layer RS1 is located above the dam portion DM1, but the position of the end portion Er1 is not limited to this example.

[0062] The sealing layer SE2 covers the end Er1 of the resin layer RS1. The sealing layer SE2 is in contact with the rib layer 5 in an area outside the end Er1 (to the right in the figure). In the example of FIG. 5, the end Es of the sealing layer SE2 is located above the dam portion DM2. The resin layer RS1 is surrounded by the sealing layer SE1, the rib layer 5, and the sealing layer SE2. This prevents moisture from penetrating the resin layer RS1.

[0063] The resin layer RS2 covers the sealing layer SE2. The dam portion DM2 serves to block the resin layer RS2 before hardening during the manufacturing of the display device DSP. In this embodiment, the end Er2 of the resin layer RS2 is located between the end Er1 of the resin layer RS1 and the end Es of the sealing layer SE2. More specifically, the end Er2 is located above the dam portion DM2. Note that the position of the end Er2 is not limited to the example of FIG. 5.

[0064] 6 is a schematic enlarged cross-sectional view of a portion of the partition wall 6B. The partition wall 6B includes a lower portion 61 and an upper portion 62 similar to those of the partition wall 6A. The lower portion 61 of the partition wall 6B also includes a bottom layer 63 and an axial layer 64.

[0065] In this embodiment, the partition wall 6B has a plurality of openings APx. At the edge portions Ex of the openings APx, the upper portions 62 protrude from the side surfaces of the axial layer 64. That is, the edge portions Ex have an overhanging shape similar to the partition wall 6A shown in Fig. 3. The ends E1a, E1b, E1c, and E1d of the partition wall 6B shown in Fig. 4 also have an overhanging shape.

[0066] The laminated film FL is divided by edges Ex. The sealing layer SE1 continuously covers each divided portion of the laminated film FL.

[0067] Next, the planar shape and arrangement of the aperture APx will be described with attention focused on regions VII and VIII enclosed by dashed lines in FIG.

[0068] Fig. 7 is a schematic enlarged plan view of region VII. Fig. 8 is a schematic enlarged plan view of region VIII. These figures show partition walls 6A and 6B, dam portions DM1 and DM2, relay layer RL, and contact portion CN1, but omit other elements.

[0069] 7 and 8, the dotted portions correspond to the partition walls 6A and 6B. The partition walls 6A and 6B are integrally formed. The partition wall 6A has the above-mentioned multiple pixel openings AP61, AP62, and AP63. The partition wall 6B has the above-mentioned multiple openings APx.

[0070] The opening APx has an elongated shape. Specifically, the opening APx has a rectangular shape that is elongated in the Y direction with rounded corners. For example, the width of the opening APx in the Y direction is two to three times the width of the opening APx in the X direction. Note that the shape of the opening APx is not limited to this example. For example, the opening APx may have a shape that is elongated in the X direction.

[0071] In the examples of Figures 7 and 8, two openings APx are arranged close to each other in the X direction. Furthermore, pairs of such openings APx are arranged in the X and Y directions. For example, the spacing between the pair of openings APx in the X and Y directions is the same as the spacing between the pixels PX in the X and Y directions. With this configuration, the density of the openings in the partitions 6A and 6B is made uniform in the display area DA and the peripheral area SA. This makes it possible to suppress variations in the progress of erosion in the XY plane when etching the layer that forms the partitions 6A and 6B during manufacturing of the display device DSP.

[0072] The partition wall 6B further has a plurality of slits SL1 (first slits) that reach any of the ends E1a, E1b, E1c, and E1d. These slits SL1 have a width that is smaller than the width of the opening APx in the short-side direction (the X direction in the example of FIGS. 7 and 8).

[0073] Each slit SL1 is connected to at least one aperture APx. In the following description, the aperture APx connected to the slit SL1 is called an aperture APx1 (first aperture). Also, an independent aperture APx not connected to the slit SL1 is called an aperture APx2 (second aperture).

[0074] For example, the slit SL1 opening at the end E1a in Fig. 7 and the slit SL1 opening at the end E1b in Fig. 8 have a trunk ST extending parallel to the Y direction and two branch portions BR extending in the X direction and intersecting the trunk ST. Furthermore, both ends of each branch portion BR are connected to the long sides of the aperture APx1. That is, each of these slits SL1 is connected to four apertures APx1.

[0075] 7 and 8 extend in the X direction, and most of them are connected to the long sides of the four apertures APx1. However, among the slits SL1 opening at the end E1c, the slits SL located at the corner between the end E1a and the end E1c and the corner between the end E1b and the end E1d are connected to the long side of one aperture APx1.

[0076] The relationship between the slits SL1 and the apertures APx1 is not limited to that exemplified here. For example, there may be a slit SL1 connected to two apertures APx1, a slit SL1 connected to three apertures APx1, or a slit SL1 connected to five or more apertures APx1.

[0077] 7 and 8, a first region A1 and a second region A2 of the partition wall 6B are defined. The first region A1 is a portion along the ends E1a, E1b, E1c, and E1d of the partition wall 6B, and includes a plurality of slits SL1 and a plurality of openings APx1 connected to these slits SL1. The second region A2 is a portion located between the first region A1 and the display region DA, and includes a plurality of openings APx2 not connected to the slits SL1. The second region A2 surrounds the display region DA.

[0078] The boundary between the first region A1 and the second region A2 is located within a range of a distance D from the dam portion DM1, for example. The distance D can be set within a range of 100 to 300 μm, for example. In one example, the distance D is 200 μm.

[0079] The second region A2 overlaps with the relay layer RL shown in FIG. 5 in plan view. The relay layer RL surrounds, for example, the display region DA. The partition walls 6B and the contact portions CN1 of the relay layer RL are dispersedly disposed in various locations in the second region A2. In the examples of FIGS. 7 and 8, the contact portions CN1 are provided at positions that do not overlap with the openings APx2 between the end E1a and the display region DA, between the end E1b and the display region DA, between the end E1c and the display region DA, and between the end E1d and the display region DA.

[0080] Next, an example of a manufacturing method of the display device DSP will be described. Figures 9A to 9I are schematic cross-sectional views showing the manufacturing process of the display device DSP. Figures 9A to 9I mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0081] In forming the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Next, as shown in Fig. 9A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12.

[0082] 9B, a rib layer 5 is formed to cover the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The rib layer 5 can be formed by, for example, CVD (Chemical Vapor Deposition).

[0083] Furthermore, as shown in Fig. 9C, the partition wall 6A is formed on the rib layer 5. Specifically, first, layers that will become the bases of the bottom layer 63, the axis layer 64, and the upper portion 62 are formed, and these layers are patterned by etching. Note that the partition wall 6B shown in Figs. 4 to 8 is formed in the same process as the partition wall 6A.

[0084] After the partition walls 6A and 6B are formed, pixel openings AP51, AP52, and AP53 are formed in the rib layer 5 by dry etching, as shown in Fig. 9D. In addition to this process, the rib layer 5 is subjected to dry etching multiple times. For example, these dry etching processes include etching for forming openings for the contact portions CN1 in the rib layer 5 in the peripheral region SA.

[0085] After the rib layer 5 and the partition walls 6A and 6B are formed, a process for forming the display elements DE1, DE2, and DE3 is carried out. In this embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order in which the display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0086] To form the display element DE1, first, as shown in FIG. 9E, a laminated film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP51, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition. The sealing layer SE11 is formed by CVD.

[0087] The stacked film FL1 and the sealing layer SE11 are formed not only in the display area DA but also in the peripheral area SA. The stacked film FL1 is divided into multiple parts by overhanging partition walls 6A and 6B. The sealing layer SE11 continuously covers each divided part of the stacked film FL1 and the partition walls 6A and 6B.

[0088] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R is disposed on the sealing layer SE11, as shown in Fig. 9F. The resist R covers the subpixel SP1 and part of the partition wall 6A around it.

[0089] Then, as shown in FIG. 9G, etching is performed using the resist R as a mask to remove the portions of the stacked film FL1 and the sealing layer SE11 that are exposed by the resist R. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 in the subpixel SP1. The etching may include wet etching or dry etching that is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R is removed.

[0090] The display element DE2 is formed in the same manner as the display element DE1. That is, when forming the display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire display area DA and the peripheral area SA. As shown in FIG. 3, the stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP52, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0091] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by vapor deposition. The sealing layer SE12 is formed by CVD. The stacked film FL2 is divided into multiple parts by overhanging partition walls 6A and 6B. The sealing layer SE12 continuously covers each divided part of the stacked film FL2 and the partition walls 6A and 6B. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 9H.

[0092] The display element DE3 is formed in the same manner as the display elements DE1 and DE2. That is, when forming the display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire display area DA and the peripheral area SA. As shown in FIG. 3 , the stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP53, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0093] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by vapor deposition. The sealing layer SE13 is formed by CVD. The stacked film FL3 is divided into multiple parts by overhanging partition walls 6A and 6B. The sealing layer SE13 continuously covers each divided part of the stacked film FL3 and the partition walls 6A and 6B. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 9I.

[0094] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in FIG. 3 are formed in this order.

[0095] 5 and 6 is, for example, the laminated film FL1, which is formed first among the laminated films FL1, FL2, and FL3. Similarly, the sealing layer SE1 is the sealing layer SE11, which is formed first among the sealing layers SE11, SE12, and SE13. In this way, if the sealing layer SE11, which is formed first, is left in the peripheral region SA, the peripheral region SA can be protected from etching when forming the display elements DE2 and DE3.

[0096] As another example, the stacked film FL may be the stacked film FL3 formed last among the stacked films FL1, FL2, and FL3. Similarly, the sealing layer SE1 may be the sealing layer SE13 formed last among the sealing layers SE11, SE12, and SE13.

[0097] The laminated films FL1, FL2, and FL3 formed by vapor deposition may have poor adhesion to the substrate, which may cause the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them to peel off from the substrate during the manufacturing of the display device DSP.

[0098] The peeling is likely to occur when the stacked films FL1, FL2, and FL3 are formed continuously over a wide area. In the display area DA, the stacked films FL1, FL2, and FL3 are finely divided by the partition walls 6A, which prevents the peeling.

[0099] In this embodiment, the partition wall 6B having a plurality of openings APx is disposed in the peripheral area SA, whereby the stacked films FL1, FL2, FL3 are finely divided in the peripheral area SA as well, thereby suppressing the peeling.

[0100] Furthermore, with the configurations shown in FIGS. 7 and 8, it is possible to obtain the effects described below, for example.

[0101] Fig. 10 is a schematic plan view of the peripheral area SA according to a comparative example of the present embodiment. Fig. 11 is a schematic cross-sectional view of the peripheral area SA according to the comparative example. As shown in Fig. 10, in the comparative example, a large number of openings APc smaller than the openings APx shown in Figs. 7 and 8 are provided in the partition wall 6B. These openings APc have a square shape with rounded corners. That is, the width of the openings APc in the X direction is the same as the width of the openings APc in the Y direction.

[0102] When such a small opening APc is provided in the partition wall 6B, during the formation of the resin layer RS1, the resin layer RS1 may be repelled before hardening due to the unevenness of the sealing layer SE1 caused by the opening APc. Fig. 11 shows the state in which the resin layer RS1 is repelled near the opening APc on the far left side of the figure and hardens in that state.

[0103] The resin layer RS1 has the role of flattening the base of the sealing layer SE2. If the resin layer RS1 hardens in a repelled state, an abnormal shape will occur in the sealing layer SE2 above it, which may create a path for moisture to penetrate into the interior of the display device DSP.

[0104] 7 and 8, the opening APx has a shape that is elongated in the Y direction. In this case, assuming that the opening APx and the opening APc have approximately the same width in the X direction, the opening APx has a larger width in the Y direction. Therefore, the opening APx is less likely to repel the resin layer RS1.

[0105] The resin layer RS1 is applied, for example, by an inkjet method. In this case, if the direction of movement (application direction) of the head that ejects the resin layer RS1 relative to the substrate coincides with the longitudinal direction of the opening APx, the repelling of the resin layer RS1 caused by the opening APx is more suitably suppressed. Therefore, when the opening APx is elongated in the Y direction as shown in Figures 7 and 8, it is preferable that the application direction is also parallel to the Y direction. As another example, the opening APx may have a shape that is elongated in the X direction, and the application direction may be parallel to the X direction.

[0106] The resin layer RS1 is thin near the ends E1a, E1b, E1c, and E1d, making the above-mentioned repelling more likely to occur. In contrast, in the example shown in FIGS. 7 and 8, multiple slits SL1 are provided in the first region A1 along the ends E1a, E1b, E1c, and E1d of the partition wall 6B, and openings APx1 are connected to these slits SL1. With this configuration, the uncured resin layer RS1 can easily fill the recesses in the sealing layer SE1 formed by the openings APx through the slits SL1. This makes it possible to effectively suppress the above-mentioned repelling.

[0107] For example, the resin layer RS1 tends to become thin when the distance D shown in Figure 7 is in the range of 100 μm. Furthermore, if the slits SL1 are formed close to the display area DA, the resistance of the second area A2, which is responsible for feeding power from the relay layer RL, may increase. Therefore, it is preferable to set the distance D in the range of 100 to 300 μm as described above.

[0108] [Second embodiment] A second embodiment will be described below. The configuration of the display device DSP not mentioned in this embodiment is the same as that of the first embodiment.

[0109] Figures 12 and 13 are schematic enlarged plan views of the peripheral area SA according to this embodiment, showing the same areas as those in Figures 7 and 8, respectively.

[0110] In this embodiment, the partition walls 6A formed in the display area DA are divided into a plurality of segments SG by a plurality of slits SL2 (second slits). Each slit SL2 extends in the Y direction. In the example of FIGS. 12 and 13, each segment SG is made up of one column of pixels PX aligned in the Y direction. However, this example is not limiting, and each segment SG may be made up of multiple columns of pixels PX.

[0111] As in the first embodiment, the partition wall 6B has a plurality of slits SL1. Hereinafter, the slits SL1 that reach the end E1a as shown in Fig. 12 will be referred to as slits SL1a (third slits). Also, the slits SL1 that reach the end E1b as shown in Fig. 13 will be referred to as slits SL1b (fourth slits).

[0112] As shown in Fig. 12, each slit SL1a is provided in the first region A1 and is separated from the slit SL2. On the other hand, as shown in Fig. 13, some of the multiple slits SL1b cross the first region A1 and the second region A2 and are connected to the slit SL2 in the display region DA. The slits SL1b and SL2 that are connected to each other form a continuous slit provided in the conductive layer including the partition walls 6A and 6B.

[0113] 12 and 13, the relay layer RL and the contact portion CN1 are provided between the display area DA and the edge E1a, whereas the relay layer RL and the contact portion CN1 are not provided between the display area DA and the edges E1b, E1c, and E1d.

[0114] In an electronic device equipped with a display device DSP, an antenna for near field communication (NFC) may be disposed on the rear side of the display device DSP. In this case, if the display device DSP has a structure in which the lattice-shaped partitions 6A are provided in the display area DA and are further surrounded by the second area of ​​the partitions 6B as in the first embodiment, the conductive layer formed by the partitions 6A and 6B may cause a decrease in the sensitivity of wireless communication by the antenna.

[0115] Specifically, the magnetic field generated by the antenna generates eddy currents in the conductive layer. These eddy currents create a magnetic field that counteracts the magnetic field, attenuating signal strength. This can reduce communication sensitivity when wireless communication is performed via the display device DSP.

[0116] In contrast, in this embodiment, the conductive layer is divided from the end E1b by slits SL1b and SL2. This suppresses the generation of the eddy current and improves the communication sensitivity of near-field wireless communication. In addition, the display device DSP according to this embodiment has the same effects as the first embodiment.

[0117] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0118] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of each of the above-described embodiments, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0119] Furthermore, with regard to other effects brought about by the aspects described in each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0120] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, DE1, DE2, DE3...display element, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE1, SE11, SE12, SE13, SE2...sealing layer, DM1, DM2...dam portion, RS1, RS2...resin layer, APx...opening, SL1, SL2...slit, 5...rib layer, 6A, 6B...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer.

Claims

1. a substrate having a display area for displaying an image and a peripheral area surrounding the display area; a plurality of display elements arranged in the display region, each of which includes a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition disposed in the display region and between adjacent display elements; a second partition wall disposed in the peripheral region and connected to the first partition wall; Equipped with the first and second partition walls each include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; The second partition wall has a plurality of elongated openings. Display device.

2. The second partition surrounds the display area. The display device according to claim 1 .

3. the second partition wall has a plurality of first slits extending to an end of the second partition wall, the plurality of openings include a plurality of first openings each connected to any one of the plurality of first slits, The display device according to claim 2 .

4. The plurality of first slits are connected to the long sides of the plurality of first openings, respectively. The display device according to claim 3 .

5. the plurality of openings further includes a plurality of second openings that are independent of each other and are not connected to the plurality of first slits; The display device according to claim 3 .

6. the second partition wall has a first region along the end portion of the second partition wall and a second region located between the first region and the display region; the plurality of first openings and the plurality of first slits are provided in the first region, The plurality of second openings are provided in the second region. The display device according to claim 5 .

7. a terminal portion provided in the peripheral region; a power supply line connected to the terminal portion; a relay layer connected to the power supply line and the second partition wall; Furthermore, the relay layer is made of the same material as the lower electrode and is formed in the same layer as the lower electrode; The display device according to claim 6.

8. the relay layer and the second partition wall are connected via a contact portion located in the second region. The display device according to claim 7 .

9. the second region and the relay layer surround the display region; The display device according to claim 8 .

10. the first partition is divided into a plurality of segments by second slits located in the display area; The display device according to claim 3.

11. the second partition wall has a first end and a second end located on the opposite side of the first end across the display area; the plurality of first slits include a third slit reaching the first end and a fourth slit reaching the second end, The second slit is spaced apart from the third slit and connected to the fourth slit. The display device according to claim 10.

12. a dam portion disposed in the peripheral region and surrounding the second partition wall, 12. A display device according to any one of claims 1 to 11.

13. a rib layer formed of an inorganic insulating material and positioned below the first partition wall and the second partition wall; The rib layer covers the dam portion. The display device according to claim 12.

14. a first sealing layer covering a laminated film including the organic layer and the upper electrode; a portion of the stacked film and the first sealing layer being disposed in the peripheral region; The display device according to claim 13.

15. the stacked film is divided by edges of the plurality of openings; The display device according to claim 14.

16. an end portion of the stacked film and an end portion of the first sealing layer are located between an end portion of the second partition wall and the dam portion; The display device according to claim 14.

17. the stacked film is divided by the end portion of the second partition wall. The display device according to claim 16.

18. Further comprising a first resin layer covering the first sealing layer. The display device according to claim 14.

19. a second sealing layer covering the first resin layer; the second sealing layer is in contact with the rib layer in a region outside an end of the first resin layer; 19. The display device according to claim 18.

20. Further comprising a second resin layer covering the second sealing layer.

20. The display device according to claim 19.

Images