Electronic circuit

Abstract

To shorten a time required for detecting abnormality of a charge pump.SOLUTION: An electronic circuit includes: a first comparator for comparing a target voltage corresponding to an output voltage of a charge pump and a reference voltage; a hold circuit for holding an output signal of the first comparator in synchronization with a clock signal; and a detection circuit for detecting abnormality of the charge pump based on an output signal of the holding circuit. The detection circuit includes: a capacitor to be charged / discharged according to the output signal of the holding circuit; and an output part for outputting a detection signal indicating a result of comparison between a charge voltage of the capacitor and a threshold voltage.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The disclosed technology relates to electronic circuits. [Background technology]

[0002] The following techniques are known as techniques for detecting abnormalities in charge pumps. For example, Patent Document 1 describes a charge pump circuit that includes a charge pump, a voltage detector that detects the output voltage of the charge pump, a control circuit that controls the charge pump based on the output of the voltage detector so that the output voltage reaches a target voltage, and an abnormality detection counter that determines that the charge pump is abnormal if the state in which the output voltage does not reach the target voltage continues for more than a predetermined time.

[0003] Patent Document 2 describes a charge pump circuit having a charge pump main body that generates a boosted voltage by boosting an input voltage by charging and discharging a capacitor using a clock signal, and a level detection circuit that outputs a detection voltage when the boosted voltage output from the charge pump main body exceeds a predetermined value, characterized in that the charge pump circuit is equipped with a sample-and-hold circuit that samples and holds the detection voltage output from the level detection circuit using a clock signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-117045 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-60318 Summary of the Invention [Problem to be solved by the invention]

[0005] A display driver IC (Integrated Circuit) called a TED (TCON-Embedded Driver) has a built-in charge pump and also a built-in detection circuit for detecting abnormalities in the charge pump. When the output voltage of the charge pump falls below a threshold, the detection circuit outputs a signal indicating that an abnormality has occurred in the charge pump. However, with conventional configurations, it takes a relatively long time to detect an abnormality in the charge pump.

[0006] The disclosed technology has been made in consideration of the above points, and aims to reduce the time required to detect an abnormality in a charge pump. [Means for solving the problem]

[0007] The electronic circuit according to the disclosed technology includes a first comparator that compares a target voltage corresponding to the output voltage of a charge pump with a reference voltage, a holding circuit that holds the output signal of the first comparator in synchronization with a clock signal, and a detection circuit that detects an abnormality in the charge pump based on the output signal of the holding circuit. The detection circuit includes a capacitor that is charged and discharged in response to the output signal of the holding circuit, and an output unit that outputs a detection signal indicating the result of comparing the charging voltage of the capacitor with a threshold voltage. [Effects of the Invention]

[0008] According to the disclosed technique, it is possible to reduce the time required to detect an abnormality in a charge pump. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a circuit block diagram showing an example of the configuration of an electronic circuit 1 according to an embodiment of the disclosed technique. [Figure 2] FIG. 1 is a circuit diagram illustrating an example of a configuration of a detection circuit according to an embodiment of the disclosed technology. [Figure 3A] 10 is a timing chart showing the operation of a detection circuit according to an embodiment of the disclosed technique. [Figure 3B]10 is a timing chart showing the operation of a detection circuit according to an embodiment of the disclosed technique. [Figure 4] FIG. 10 is a circuit block diagram showing the configuration of an electronic circuit according to a comparative example. [Figure 5] FIG. 10 is a diagram illustrating an example of a configuration of a detection circuit according to another embodiment of the disclosed technology. [Figure 6A] 10 is a timing chart showing the operation of a detection circuit according to another embodiment of the disclosed technique. [Figure 6B] 10 is a timing chart showing the operation of a detection circuit according to another embodiment of the disclosed technique. [Figure 7] FIG. 10 is a diagram illustrating an example of a configuration of a detection circuit according to another embodiment of the disclosed technology. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals.

[0011] [First embodiment] FIG. 1 is a circuit block diagram showing an example of the configuration of an electronic circuit 1 according to an embodiment of the disclosed technique. The electronic circuit 1 may constitute a part of a display driver IC (Integrated Circuit). The electronic circuit 1 includes a charge pump 2 and a detection circuit 30. The charge pump 2 detects a power supply voltage V DD is boosted and output as output voltage V GH The charge pump 2 includes a comparator 10, a flip-flop 11, a NAND circuit 12, buffers 13 and 15, an inverter 14, diodes 16, 17 and 18, capacitors 19, 20 and 21, and resistor elements 22 and 23.

[0012] The input terminal of the buffer 15 is connected to the power supply voltage V DDis input to the buffer 15. The output terminal of the buffer 15 is connected to the anode of the diode 16, and the cathode of the diode 16 is connected to the anode of the diode 17. The cathode of the diode 16 is connected to the anode of the diode 18. One end of the capacitor 19 is connected to the cathode of the diode 16 (anode of the diode 17) and the other end is connected to the output terminal of the buffer 13. One end of the capacitor 20 is connected to the cathode of the diode 17 (anode of the diode 18) and the other end is connected to the output terminal of the inverter 14. One end of the capacitor 21 is connected to the cathode of the diode 18 and the other end is connected to ground. The output voltage V GH will be output.

[0013] One end of the resistor element 22 is connected to the cathode of the diode 18, and the other end is connected to one end of the resistor element 23. The other end of the resistor element 23 is connected to ground. GH is divided by the resistor elements 22 and 23. That is, a voltage V expressed by the following equation (1) is output from the connection point of the resistor elements 22 and 23. FB In equation (1), R1 is the resistance value of the resistor element 22, and R2 is the resistance value of the resistor element 23. The voltage V FB is an example of a "target voltage" in the disclosed technology. V FB =V GH ×R2 / (R1+R2) (1)

[0014] Voltage V FB is input to the inverting input terminal of the comparator 10. The non-inverting input terminal of the comparator 10 is supplied with a reference voltage V REF The comparator 10 receives the voltage V FB and the reference voltage V REF and outputs an output signal S comp Outputs V FB >V REF In this case, a low-level output signal S comp is output, and V FB ≦V REF In this case, a high-level output signal Scomp The output signal S of the comparator 10 is comp is input to the data input terminal of the flip-flop 11. The comparator 10 is an example of a "first comparator" in the disclosed technology.

[0015] The flip-flop 11 outputs the comparator output signal S in synchronization with the clock signal CLK input to the clock input terminal. comp and the output signal S comp Output signal S indicating the state of Q and S QN The output signal S Q and S QN have the inverse relationship of logic. The flip-flop 11 is an example of a "holding circuit" in the disclosed technology.

[0016] The clock signal CLK is input to one input terminal of the NAND circuit 12, and the output signal S of the flip-flop 11 is input to the other input terminal. Q The NAND circuit 12 receives the clock signal CLK and the output signal S Q The output terminal of the NAND circuit 12 is connected to the input terminal of the buffer 13 and the input terminal of the inverter 14.

[0017] The operation of the charge pump 2 will be explained below. The output voltage V GH When is relatively low (V FB ≦V REF ), the comparator 10 outputs a high level output signal S comp and the output signal S of the flip-flop 11 Q In this case, the NAND circuit 12 outputs a pulse signal in which high and low levels alternate in synchronization with the clock signal CLK. This drives the capacitors 19 and 20, and the output voltage V GH increases.

[0018] The boost operation described above causes V FB >V REFThen, the comparator 10 outputs a low-level output signal S comp and the output signal S of the flip-flop 11 Q In this case, the output signal of the NAND circuit 12 is fixed to a high level, and the boosting operation is stopped. GH The output voltage V is driven by the load current flowing through the load. GH The level of V FB ≦V REF When this happens, the boost operation is restarted. If the charge pump 2 is normal, the above operation is repeated.

[0019] The detection circuit 30 detects the output signal S of the flip-flop 11. Q and S QN 2 is a circuit diagram showing an example of the configuration of the detection circuit 30. The detection circuit 30 includes inverters 31 and 32, capacitors 37 and 38, a current supply circuit 40, comparators 45 and 46, and resistor elements 47 and 48. The inverter 31 includes a P-MOS 33 and an N-MOS 34, and the inverter 32 includes a P-MOS 35 and an N-MOS 36. The P-MOS is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the N-MOS is an N-channel MOSFET. The current supply circuit 40 includes P-MOSs 41, 42, and 43 and a current source 44.

[0020] The gate of the P-MOS 33 is connected to the gate of the N-MOS 34 and the output terminal Q of the flip-flop 11, the source is connected to the drain of the P-MOS 42, and the drain is connected to the drain of the N-MOS 34 and one end of the capacitor 37. The source of the N-MOS 34 is connected to the ground. The gates of the P-MOS 33 and N-MOS 34, which are the input terminals of the inverter 31, receive the output signal S of the flip-flop 11. Q is input, and the capacitor 37 is charged according to the output of the inverter 31. The capacitor 37 is charged by the voltage V FB is the reference voltage V REFThe capacitor 37 is an example of a "first capacitor" in the disclosed technology.

[0021] The gate of the P-MOS 35 is connected to the gate of the N-MOS 36 and the output terminal QN of the flip-flop 11, the source is connected to the drain of the P-MOS 43, and the drain is connected to the drain of the N-MOS 36 and one end of the capacitor 38. The source of the N-MOS 36 is connected to the ground. The gates of the P-MOS 35 and N-MOS 36, which are the input terminals of the inverter 32, receive the output signal S of the flip-flop 11. QN is input, and the capacitor 38 is charged according to the output of the inverter 32. The capacitor 38 is charged by the voltage V FB is the reference voltage V REF The capacitor 38 is an example of a "second capacitor" in the disclosed technology.

[0022] The source of P-MOS 41 is connected to the power supply line, the gate is connected to the gates of P-MOSs 42 and 43 and its own drain, and the drain is connected to current source 44. The sources of P-MOSs 42 and 43 are each connected to the power supply line. A current mirror is formed by P-MOSs 41, 42, and 43, and a constant current I1 proportional to the current generated by current source 44 is output from each of P-MOSs 42 and 43. Capacitors 37 and 38 are each charged by current I1 supplied from current supply circuit 40.

[0023] One end of the resistor element 47 is connected to the power supply line, and the other end is connected to one end of the resistor element 48. The other end of the resistor element 48 is connected to the ground. DD A voltage dividing circuit is configured to divide the voltage V , which is expressed by the following equation (2), from the connection point of the resistor element 47 and the resistor element 48. th In equation (2), R3 is the resistance value of the resistive element 47, and R4 is the resistance value of the resistive element 48. V th =VDD ×R4 / (R3+R4) (2)

[0024] The comparator 45 has a non-inverting input terminal connected to one end of the capacitor 37, and an inverting input terminal connected to the connection point between the resistor element 47 and the resistor element 48. That is, the comparator 45 detects the charging voltage V of the capacitor 37. C1 and threshold voltage V th and a detection signal S indicating the comparison result of these voltages is generated. ldet The comparator 45 is an example of the "output unit" in the disclosed technology and also an example of the "second comparator" in the disclosed technology.

[0025] The comparator 46 has a non-inverting input terminal connected to one end of the capacitor 38, and an inverting input terminal connected to the connection point between the resistor element 47 and the resistor element 48. That is, the comparator 46 detects the charging voltage V of the capacitor 38 as C2 and threshold voltage V th and a detection signal S indicating the comparison result of these voltages is generated. hdet The comparator 46 is an example of the "output unit" in the disclosed technology and an example of the "third comparator" in the disclosed technology.

[0026] The operation of the detection circuit 30 will be described below. When the charge pump 2 is normal, the comparator 10 outputs an output signal S comp The output signal S of the comparator 10 is comp When the output signal S is at a high level, the flip-flop 11 outputs a high-level output signal S Q As a result, the P-MOS 33 of the inverter 31 is turned off and the N-MOS 34 is turned on, thereby discharging the capacitor 37. Also, the output signal S of the comparator 10 comp When the signal is at a high level, the flip-flop 11 outputs a low-level output signal S QN This causes the P-MOS 35 of the inverter 32 to be turned on and the N-MOS 36 to be turned off, thereby charging the capacitor 38.

[0027] On the other hand, the output signal S of the comparator 10 comp When the signal is at a low level, the flip-flop 11 outputs a low-level output signal S Q As a result, the P-MOS 33 of the inverter 31 is turned on and the N-MOS 34 is turned off, thereby charging the capacitor 37. Also, the output signal S of the comparator 10 comp When the output signal S is low, the flip-flop 11 outputs a high-level output signal S QN This causes the P-MOS 35 of the inverter 32 to be turned off and the N-MOS 36 to be turned on, thereby discharging the capacitor 38.

[0028] That is, when the charge pump 2 is normal, the charging and discharging of the capacitors 37 and 38 is repeated. As a result, the charging voltages V C1 and V C2 are the threshold voltages V th and the output signals S of the comparators 45 and 46 are maintained lower than ldet and S hdet are each maintained at a low level.

[0029] On the other hand, due to an abnormality in charge pump 2, V FB ≦V REF When the output signal S of the comparator 10 is fixed to the state comp 3A is a timing chart showing the operation of the detection circuit 30 in this case. In this case, the output signal S of the flip-flop 11 is fixed to a high level. QN is fixed at a low level, and the capacitor 38 is continuously charged by the current I1. As a result, the charging voltage V of the capacitor 38 C2 is the threshold voltage V th and the output signal S of the comparator 46 becomes higher than hdet becomes high level. A high level output signal S hdet This notifies the host system that an abnormality has occurred in the charge pump 2.

[0030] Charge pump 2 malfunctioned, causing V FB >V REF When the output signal S of the comparator 10 is fixed to the state comp 3B is a timing chart showing the operation of the detection circuit 30 in this case. In this case, the output signal S of the flip-flop 11 is fixed to a low level. Q is fixed at a low level, and the capacitor 37 continues to be charged by the current I1. As a result, the charging voltage V of the capacitor 37 C1 is the threshold voltage V th becomes higher than the output signal S ldet becomes high level. A high level output signal S ldet This notifies the host system that an abnormality has occurred in the charge pump 2.

[0031] When the clock signal CLK stops, the output signal S of the comparator 10 held in the flip-flop 11 immediately before the clock stops comp The capacitor 37 or 38 is continuously charged by the current I1 depending on the state of the capacitor. As a result, the charging voltage V C1 or V C2 is the threshold voltage V th becomes higher than the output signal S ldet Or the output signal S of the comparator 46 ldet becomes high level. A high level output signal S hdet or S ldet This notifies the host system that an abnormality has occurred in the charge pump 2.

[0032] According to the detection circuit 30, after an abnormality occurs in the charge pump 2, the output signal S hdet or S ldet The detection time T det is determined by the capacitance of the capacitors 37 and 38 and the current I1 (charging current of the capacitors 37 and 38) supplied from the current supply circuit 40. In other words, the detection time T det can be set to any length.

[0033] 4 is a circuit block diagram showing the configuration of an electronic circuit 1X according to a comparative example. The electronic circuit 1X according to the comparative example uses a comparator 80 to detect an abnormality in the charge pump 2. The output voltage V GH The divided voltage V FB is input to the non-inverting input terminal of the comparator 80. The inverting input terminal of the comparator 10 is supplied with a threshold voltage V thx The comparator 80 receives the voltage V FB and threshold voltage V thx and outputs an output signal S ldet The output signal S ldet This notifies the host system that an abnormality has occurred in the charge pump 2.

[0034] In the electronic circuit 1X according to the comparative example, the output voltage V GH In the electronic circuit 1X according to the comparative example, after an abnormality occurs in the charge pump 2, the output signal S of the comparator 80 ldet The detection time T until an abnormality is detected by det is determined by the capacitance of the capacitor 21 and the average load current. For example, the output voltage V GH is 15V, and the output voltage V GH When it is determined that an abnormality has occurred when the voltage drops to 5V, if the capacitance of the capacitor 21 is 2.2 μF and the average load current is 4 mA, the detection time T det As described above, with the configuration of the electronic circuit 1X according to the comparative example, it takes a relatively long time to detect an abnormality in the charge pump 2.

[0035] On the other hand, the electronic circuit 1 according to the embodiment of the disclosed technique has an output voltage V GH Voltage V according to FB and the reference voltage V REF and a comparator 10 that compares the output signal S compA flip-flop 11 holds the output signal S in synchronization with the clock signal CLK. Q , S QN The detection circuit 30 detects an abnormality in the charge pump 2 based on the output signal S of the flip-flop 11. Q , S QN The capacitors 37 and 38 are charged and discharged according to the charge voltage V C1 , V C2 and the threshold voltage V th The detection signal S indicates the result of the comparison with ldet or S hdet and an output unit that outputs the signal.

[0036] According to the electronic circuit 1 according to the embodiment of the disclosed technique, as described above, after an abnormality occurs in the charge pump 2, the output signal S hdet or S ldet The detection time T det is determined by the capacitance of the capacitors 37 and 38 and the current I1 (the charging current of the capacitors 37 and 38). In other words, the detection time T det can be set to any length, and the detection time T det In particular, in a display driver IC, the circuit operation is cyclical, and the load current of the load driven by the output voltage of the charge pump is regular, so the detection time T det It is possible to set it to a shorter value.

[0037] [Second embodiment] 5 is a diagram showing an example of the configuration of a detection circuit 30A according to the second embodiment. The detection circuit 30A differs from the detection circuit 30 according to the first embodiment (see FIG. 2) in that the detection circuit 30A does not include an inverter 32 and a capacitor 38 and that the discharge current of the capacitor 37 is controlled by a current supply circuit 60.

[0038] The current supply circuit 50 has P-MOSs 51 and 52 and a current source 53. The configuration of the current supply circuit 50 is the same as that of the current supply circuit 40 according to the first embodiment (see FIG. 2) described above, except that the P-MOS 43 is omitted, and outputs a current I1.

[0039] The current supply circuit 60 has N-MOSs 61 and 62 and a current source 63. The source of the N-MOS 61 is connected to ground, the gate is connected to the N-MOS 62 and its own drain, and the drain is connected to the current source 63. The source of the N-MOS 62 is connected to ground, and the drain is connected to the source of the N-MOS 34 that constitutes the inverter 31. The N-MOSs 61 and 62 form a current mirror, and a constant current I2 proportional to the current generated by the current source 63 is output from the N-MOS 62, and the capacitor 37 is discharged by the current I2. Note that the magnitudes of the currents I1 and I2 may be the same.

[0040] The detection circuit 30A includes a resistor element 49 provided between resistor elements 47 and 48. A threshold voltage V th1 The connection point between the resistor element 49 and the resistor element 48 outputs the threshold voltage V th2 will be output.

[0041] The comparator 45 has a non-inverting input terminal connected to one end of the capacitor 37, and an inverting input terminal connected to the connection point between the resistor element 47 and the resistor element 49. That is, the comparator 45 detects the charging voltage V C1 and threshold voltage V th1 and a detection signal S indicating the comparison result of these voltages is generated. ldet Output.

[0042] The inverting input terminal of the comparator 46 is connected to one end of the capacitor 37, and the non-inverting input terminal is connected to the connection point between the resistor element 49 and the resistor element 48. That is, the comparator 46 detects the charging voltage V of the capacitor 37 as C1 and threshold voltage V th2and a detection signal S indicating the comparison result of these voltages is generated. hdet Output.

[0043] The operation of the detection circuit 30A will be described below. When the charge pump 2 is normal, the comparator 10 outputs an output signal S comp The output signal S of the comparator 10 is comp When the output signal S is at a high level, the flip-flop 11 outputs a high-level output signal S Q As a result, the P-MOS 33 of the inverter 31 is turned off and the N-MOS 34 is turned on, thereby discharging the capacitor 37. On the other hand, the output signal S of the comparator 10 comp When the signal is at a low level, the flip-flop 11 outputs a low-level output signal S Q As a result, the P-MOS 33 of the inverter 31 is turned on and the N-MOS 34 is turned off. This causes the capacitor 37 to be charged. That is, when the charge pump 2 is normal, the capacitor 37 is repeatedly charged and discharged. This causes the charging voltage V of the capacitor 37 to be C1 is the threshold voltage V th1 and the threshold voltage V th2 and the output signals S of the comparators 45 and 46 are maintained higher than ldet and S hdet are each maintained at a low level.

[0044] On the other hand, due to an abnormality in charge pump 2, V FB ≦V REF When the output signal S of the comparator 10 is fixed to the state comp 6A is a timing chart showing the operation of the detection circuit 30A in this case. In this case, the output signal S of the flip-flop 11 is fixed to a high level. Q is fixed at a high level, and the capacitor 37 is continuously discharged by the current I2. As a result, the charging voltage V of the capacitor 37 C1 is the threshold voltage V th2 and the output signal S of the comparator 46 becomes lower than hdetbecomes high level. A high level output signal S hdet This notifies the host system that an abnormality has occurred in the charge pump 2.

[0045] Charge pump 2 malfunctioned, causing V FB >V REF When the output signal S of the comparator 10 is fixed to the state comp 6B is a timing chart showing the operation of the detection circuit 30A in this case. In this case, the output signal S of the flip-flop 11 is fixed to a low level. Q is fixed at a low level, and the capacitor 37 continues to be charged by the current I1. As a result, the charging voltage V of the capacitor 37 C1 is the threshold voltage V th1 becomes higher than the output signal S ldet becomes high level. A high level output signal S ldet This notifies the host system that an abnormality has occurred in the charge pump 2.

[0046] When the clock signal CLK stops, the output signal S of the comparator 10 held in the flip-flop 11 immediately before the clock stops comp The capacitor 37 is continuously charged by the current I1 or discharged by the current I2 depending on the state of the capacitor 37. As a result, the charging voltage V C1 is the threshold voltage V th1 or threshold voltage V th2 and the output signal S of the comparator 45 becomes lower than ldet Or the output signal S of the comparator 46 ldet becomes high level. A high level output signal S hdet or S ldet This notifies the host system that an abnormality has occurred in the charge pump 2.

[0047] According to the detection circuit 30A of this embodiment, after an abnormality occurs in the charge pump 2, the output signal S hdet or S ldet The detection time Tdet is determined by the capacitance of the capacitor 37, the current I1 (charging current), and the current I2 (discharging current). In other words, the detection time T det can be set to any length, and the detection time T det It is possible to shorten the

[0048] Furthermore, the detection circuit 30A uses a single capacitor 37 to generate the output signal S hdet and S ldet Therefore, the circuit area can be made smaller than that of the detection circuit 30 according to the first embodiment, which includes the two capacitors 37 and 38.

[0049] [Third embodiment] 7 is a diagram showing an example of the configuration of a detection circuit 30B according to a third embodiment of the disclosed technology. The detection circuit 30B differs from the detection circuit 30A according to the second embodiment in that it further includes a stop circuit 70. The stop circuit 70 is configured to stop a detection circuit 30B according to a control signal S blank Based on this, the charging and discharging of the capacitor 37 is stopped. The stopping circuit 70 is configured to include a P-MOS 71, an N-MOS 72, and an inverter 73.

[0050] The P-MOS 71 is provided between the current supply circuit 50 and the inverter 31, and the N-MOS 72 is provided between the current supply circuit 60 and the inverter 31. blank is input to the gate of the N-MOS 72 and also input to the gate of the P-MOS 71 via the inverter 73.

[0051] Control signal S blank is at a high level, the P-MOS 71 and the N-MOS 72 are both turned off, thereby cutting off the connection between the inverter 31 and the current supply circuits 50 and 60, and stopping the charging and discharging of the capacitor 37.

[0052] According to the detection circuit 30B of the third embodiment, similarly to the detection circuits 30 and 30A of the first and second embodiments described above, the detection time T det It is possible to shorten the time.

[0053] During the vertical blanking period of the display driver IC, the output voltage V of charge pump 2 GH The load on the control signal S blank By making it correspond to the vertical blanking period, the charging voltage V C1 This allows the fluctuation of the detection time T det In setting the detection time T det can be set to a shorter value. [Explanation of symbols]

[0054] 1 Electronic circuit 2 Charge Pump 10 Comparator 11. Flip-Flop 30, 30B, 30C detection circuit 37, 38 Capacitor 45, 46 Comparator 70 Stop circuit

Claims

1. a first comparator that compares a target voltage corresponding to an output voltage of the charge pump with a reference voltage; a holding circuit that holds the output signal of the first comparator in synchronization with a clock signal; a detection circuit that detects an abnormality in the charge pump based on an output signal of the holding circuit; The detection circuit a capacitor that is charged and discharged in response to an output signal from the holding circuit; an output unit that outputs a detection signal indicating a result of comparing the charging voltage of the capacitor with a threshold voltage; An electronic circuit comprising:

2. The capacitor is a first capacitor that is charged when the target voltage is lower than the reference voltage; a second capacitor that is charged when the target voltage is greater than the reference voltage; Including, The output unit a second comparator that outputs a first detection signal indicating a result of comparing the charging voltage of the first capacitor with a first threshold voltage; a third comparator that outputs a second detection signal indicating a result of comparing the charging voltage of the second capacitor with the first threshold voltage; 10. The electronic circuit of claim 1, comprising:

3. The capacitor is a first capacitor that is charged when the target voltage is lower than the reference voltage and that is discharged when the target voltage is higher than the reference voltage; a second comparator that outputs a first detection signal indicating a result of comparing the charging voltage of the first capacitor with a first threshold voltage; a third comparator that outputs a second detection signal indicating a result of comparing the charging voltage of the first capacitor with a second threshold voltage; 10. The electronic circuit of claim 1, comprising:

4. The detection circuit further includes a stop circuit that stops charging and discharging the first capacitor based on a control signal.

4. The electronic circuit of claim 3.

Images