Imaging apparatus and electronic apparatus

Abstract

To provide an imaging apparatus for facilitating pooling processing.SOLUTION: The pixel area of the imaging apparatus includes a plurality of pooling modules and an output circuit. The pooling module includes a pooling circuit and a comparison module. The pooling circuit includes a plurality of pixels and an arithmetic circuit. The comparison module includes a plurality of comparison circuits and a determination circuit. The pixel acquires a first signal by photoelectric conversion and multiplies the first signal by an arbitrary magnification, to generate a second signal. The pooling circuit adds a plurality of second signals by the arithmetic circuit, to generate a third signal. The comparison module compares a plurality of third signals and outputs the largest third signal to the determination circuit. The determination circuit determines the largest third signal and binarizes it, to generate a fourth signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. In particular, one aspect of the present invention relates to Semiconductor device, display device, light-emitting device, power storage device, memory device, driving method thereof, or This relates to a method for producing the above.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. It refers to a semiconductor element, circuit, or device, etc. Examples include a transistor, a diode, and other semiconductor elements. In another example, a circuit having a semiconductor element is a semiconductor device. As another example, a device including a circuit having a semiconductor element is a semiconductor device. do. [Background technology]

[0004] IoT (Internet of things), AI (Artificial I) With the development of information technology such as intelligence, the amount of data handled is on the rise In order for electronic devices to utilize information technologies such as IoT and AI, large amounts of data are required. There is a demand for decentralized management of data.

[0005] Image processing system for in-vehicle electronic devices and image processing system for monitoring moving objects In these cases, the use of AI is attracting attention for its potential to improve image recognition processing speed. Patent Document 1 discloses a technique for adding a calculation function to a device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-123087 Summary of the Invention [Problem to be solved by the invention]

[0007] With the advancement of technology, imaging devices equipped with solid-state imaging elements such as CMOS image sensors have become increasingly sophisticated. In the next generation, imaging devices will be equipped with even more advanced features. There is a demand for intelligent functionality.

[0008] To recognize an object from image data, advanced image processing is required. In the image processing, various analytical processes such as filtering and comparison processing are used to analyze images. The amount of calculation required for image analysis increases according to the number of pixels to be processed. For example, in an in-vehicle image processing system, the processing time increases accordingly. In addition, the increase in the amount of calculations in image processing systems can cause problems that affect safety. This raises the issue of increased power consumption.

[0009] In view of the above problems, one aspect of the present invention has an object to provide an imaging device with a novel configuration. Alternatively, one aspect of the present invention is a neural network having a pooling processing function. Another object of the present invention is to provide an imaging device that can reduce the amount of calculation. One of the objectives is to provide an imaging device with a novel configuration that can shorten processing time. Another embodiment of the present invention provides an imaging device with a novel structure that can reduce power consumption. One of our goals is to provide

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc.

[0011] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least the above-listed and / or other objects. It solves one problem. [Means for solving the problem]

[0012] One embodiment of the present invention is an imaging device including a pixel region and a first circuit, The pooling module includes a plurality of pools and an output circuit. a pooling circuit and a comparison module, and the pooling circuit includes a plurality of pixels and an arithmetic circuit The comparison module includes a plurality of comparison circuits and a determination circuit, and the pixel includes a photoelectric conversion The pixel has a function of multiplying the first signal by an arbitrary magnification to obtain a first signal. The pooling circuit has a function of generating a second signal, and the pooling circuit generates a plurality of second signals by an arithmetic circuit. and a comparison module for comparing the plurality of third signals to generate a third signal. and a function of comparing the third signal and the third signal, selecting the largest third signal, and outputting the selected signal to a determination circuit. The first circuit has a function of determining the largest third signal, binarizing it, and generating a fourth signal. The fourth signal is output to the output circuit. The pooling module controls the timing of the fourth signal. The pooling process is performed according to the prime number, and the pooling module is generated by the pooling process. The imaging device outputs a fourth signal obtained by the above method.

[0013] In the above configuration, the imaging device further includes a second circuit, a third circuit, a first wiring, and , a second wiring, and a third wiring; the pixel has a first output terminal; and the arithmetic circuit has A second circuit includes a first transistor, a second transistor, and a third transistor. The circuit is electrically connected to a plurality of pixels extending in the row direction via the first wiring, and the third circuit are electrically connected to a plurality of pixels extending in the column direction via second wirings, and the third wirings are , one of the source or drain of the first transistor and the source or drain of the second transistor One of the drains of the first transistor and one of the source and drain of the second transistor are electrically connected to each other. The gate of the first transistor is connected to the other of the source and drain of the first transistor. , the gate of the second transistor, the gate of the third transistor, and a pooling circuit are The third circuit is electrically connected to the first output terminal of the pixel, and the second wiring is connected to the selection signal The second circuit has a function of outputting a desired magnification to the pixel via the first wiring. The first transistor has a function of The second transistor has the same channel length as the first transistor, and the second transistor has the same channel width as the first transistor. By having a width, it has a function of outputting a third signal obtained by adding a plurality of second signals, and the third The channel width of the first transistor is determined by the number of pixels that the pooling circuit has. The fifth signal is the size of the third signal divided by the number of pixels. An imaging device having a function of outputting the above is preferred.

[0014] In the above configuration, the comparison module includes a first comparison circuit, a second comparison circuit, and a current a first comparison circuit including a fourth transistor to a ninth transistor; a first input terminal, a second input terminal, a second output terminal, and a fourth wiring; The second output terminal of the comparator is connected to the first input terminal of the second comparator via a current mirror circuit. The first input terminal is electrically connected to the source or drain of the fifth transistor. one of the source and drain of the seventh transistor and the gate of the fourth transistor The gate of the fifth transistor is electrically connected to the gate of the sixth transistor. The second input terminal is connected to one of the source and drain of the eighth transistor and the sixth transistor. One of the source or drain of the transistor, the gate of the seventh transistor, and the eighth transistor a second output connected to the gate of the first transistor and the gate of the ninth transistor; The terminal is connected to one of the source and drain of the fourth transistor and the source of the ninth transistor. The fourth to ninth transistors are electrically connected to either the source or the drain of the first transistor. The fourth transistor has a channel length equal to that of the fifth transistor. The channel width of the sixth transistor is preferably the same as that of the sixth transistor. The width is preferably twice the channel width of the fifth transistor, and the fourth to the fifth transistors The sixth transistor forms a first current mirror circuit, and the ninth transistor The channel width of the eighth transistor is preferably the same as the channel width of the seventh transistor. The channel width of the seventh transistor is preferably twice that of the eighth transistor. The first to ninth transistors form a second current mirror circuit, and the second to ninth transistors form a first comparison circuit. A sixth signal is applied to a first input terminal of the first comparator circuit, and a sixth signal is applied to a second input terminal of the first comparator circuit. , a seventh signal is given, and the second output terminal of the first comparison circuit outputs the sixth signal or the seventh signal. The larger of the two signals is output as the eighth signal and input to the first input terminal of the second comparator. The eighth signal is applied to the second input terminal of the second comparator, and the ninth signal is applied to the second input terminal of the second comparator. The second output terminal of the second comparator outputs the eighth signal or the ninth signal, whichever is larger. The signal is output to the decision circuit as the tenth signal, and the decision circuit decides the tenth signal and binarizes it. and the first circuit outputs the fourth signal to the output circuit. It is preferable that the imaging device has a function for controlling the timing of the exposure.

[0015] In the above configuration, the plurality of pixels are arranged in a matrix, and there is no shielding between adjacent pixels. An imaging device with an illuminated area is preferred.

[0016] In the above structure, the pixel further includes a photoelectric conversion element, a tenth transistor, and a first The first transistor, the twelfth transistor, the thirteenth transistor, and the first capacitor element and one electrode of the photoelectric conversion element is connected to the source or drain of the tenth transistor. The other of the source and drain of the tenth transistor is electrically connected to the eleventh transistor. an eleventh transistor electrically connected to one of the source and drain of the first transistor; One of the source and drain of the 12th transistor is electrically connected to the gate of the 13th transistor, The gate of the 12th transistor is electrically connected to one electrode of the first capacitor element. One of the source and the drain of the transistor is electrically connected to the first output terminal, The other electrode of the capacitor element 1 is electrically connected to one of the source and drain of the thirteenth transistor. The other of the source and the drain of the thirteenth transistor is electrically connected to the first wiring. The gate of the thirteenth transistor is electrically connected to the second wiring, and the gate of the thirteenth transistor is electrically connected to the first wiring. The transistors 0 and 12 each have a metal oxide in a channel formation region. An imaging device is preferred.

[0017] In the above structure, the metal oxide is In, Zn, and M (M is Al, Ti, Ga, Sn , Y, Zr, La, Ce, Nd or Hf) is preferred.

[0018] In the above structure, the photoelectric conversion element includes selenium or a compound containing selenium. is preferred. [Effects of the Invention]

[0019] In view of the above problem, one embodiment of the present invention can provide an imaging device with a novel configuration. Another aspect of the present invention is an imaging device having a neural network pooling processing function. Alternatively, one embodiment of the present invention can provide a device that reduces the amount of calculation and shortens the processing time. Alternatively, one embodiment of the present invention can provide an imaging device having a novel structure. It is possible to provide an imaging device with a novel configuration that can reduce power consumption.

[0020] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention has at least the above-listed effects and / or other effects. Therefore, one aspect of the present invention is to provide the above-mentioned series of In some cases, it may not have the effect described. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram illustrating an imaging apparatus. [Figure 2] FIG. 1 is a block diagram illustrating an imaging apparatus. [Figure 3] 1A is a block diagram illustrating an imaging device, and FIG. 1B is a circuit diagram illustrating an imaging device. [Figure 4] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 5] 1A is a block diagram illustrating an imaging device, and FIG. 1B is a timing chart illustrating the operation of the imaging device. [Figure 6] FIG. 1 is a block diagram illustrating an imaging apparatus. [Figure 7] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 8] FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 9] FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 10] FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 11] 1A is a diagram illustrating the configuration of an imaging device, and FIG. 1B is a cross-sectional view illustrating the configuration of an imaging device. [Figure 12] FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 13]FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 14] FIG. 1 is a perspective view of a package and module that houses an imaging device. [Figure 15] 1A and 1B are diagrams illustrating examples of the configuration of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0022] (Embodiment 1) In this embodiment, an imaging device that efficiently performs neural network pooling processing is This will be explained with reference to FIGS. 1 to 7.

[0023] First, a block diagram of the imaging device 10 will be described with reference to FIG. 0 is a pixel region, a driver 11, a driver 12, a driver 13, a plurality of wirings 111, a plurality of The pixel region has a wiring 112 (not shown) and a plurality of wirings 113a (not shown). The area includes a plurality of pooling modules 200, a plurality of analog-to-digital conversion circuits 250, and and an output circuit 251. The pooling module 200 includes a plurality of pooling circuits. 210 and a comparison module 220, and the pooling circuit 210 is configured to compare a plurality of pixels 10 0 and an arithmetic circuit 212 (not shown). It includes a comparison circuit 230 (not shown) and a determination circuit 221 (not shown).

[0024] The pixel 100 can obtain a first signal by converting light into an electrical signal, and In addition, the pixel 100 can multiply the first signal by any factor to generate a second signal. The first signal and the second signal are output as currents. This indicates the value of the weight data used in the network pooling process.

[0025] The pooling circuit 210 adds the second signals together using the arithmetic circuit 212 to generate a third signal. Furthermore, the calculation circuit 212 can average the plurality of second signals to generate a signal. A fifth signal can be generated by:

[0026] The comparison module 220 compares the plurality of third signals and selects the largest third signal. The third signal, which is the largest, can be output to the decision circuit 221. The decision circuit 221 The signal can be judged and binarized to generate a fourth signal.

[0027] The pooling module 200 performs the following operations according to the number of pixels that the pooling module 200 has: That is, the pooling module 200 can perform pooling. Pooling first signals acquired from a plurality of pixels included in the module 200 The fourth signal generated by the fourth signal generating circuit can be output.

[0028] The driver 11 outputs a fourth signal to the output circuit 251 in response to a selection signal applied to the wiring 111. The output circuit 251 can control the timing of outputting the signal to the external device. However, by outputting a fourth signal to the neural network that controls the image capture device 10, The neural network receives the first data from the image pickup device 10. By performing the filtering process, the data features are extracted and input as data. Since neural networks only need to process the extracted data features, This reduces the amount of data that needs to be transferred from the image sensor to the neural network. This reduces data transfer time and also reduces the amount of calculation required for neural networks. The amount of calculation required for the neural network is reduced, which reduces power consumption. It is possible.

[0029] The pooling module 200 preferably includes a plurality of pooling circuits 210. In FIG. 1, the pooling module 200 has four pooling circuits 210. The number of pooling circuits 210 included in the pooling module 200 is 1 or more. The number of pooling circuits can be up to n (n is a natural number equal to or greater than 2). This makes it easier to extract the features of the data. As the number increases, the data compression rate increases, reducing the amount of calculation required for the neural network. Therefore, the power consumption of the neural network is further reduced.

[0030] FIG. 2 illustrates an example of a pulley circuit 210 using a block diagram. The pixel circuit 210 includes a plurality of pixels 100, an arithmetic circuit 212, a switch 203, and a switch 204. 4. A plurality of wirings 112, a plurality of wirings 113a, a wiring 114, a wiring 115, and a wiring 210 The pixel 100 has a first output terminal, and the arithmetic circuit 212 has a transistor The transistor 212 includes a transistor 212a, a transistor 212b, and a transistor 212c. The pooling circuit 210 shown in FIG. 2 will be described as an example having four pixels.

[0031] The driver 12 is electrically connected to a plurality of pixels 100 extending in the row direction via wiring 112. The driver 13 is connected to a plurality of pixels 100 extending in the column direction via wiring 113a. are electrically connected.

[0032] The wiring 114 is connected to one of the source and drain of the transistor 212a and the One of the source or drain of transistor 212b and one of the source or drain of transistor 212c The gate of the transistor 212a is electrically connected to the gate of the transistor 212. the other of the source or drain of transistor 212a, the gate of transistor 212b, and transistor 21 The gate of transistor 212a is electrically connected to the gate of transistor 212c. The ring circuit 210 is electrically connected to the output terminals 100a of the plurality of pixels 100. There are.

[0033] The other of the source and drain of the transistor 212b is connected to one of the electrodes of the switch 203. The other of the source and drain of the transistor 212c is electrically connected to the switch 20 The other electrode of the switch 203 is electrically connected to one of the electrodes of the wiring 210. a is electrically connected to the other electrode of the switch 204 and the comparison module 220. do.

[0034] The driver 13 can output a selection signal to the wiring 113a. Any desired magnification can be set as weight data to the pixel 100 via the wiring 112 . Transistor 212a is connected to transistor 212b and transistor 212c in the same channel. The transistor 212b has the same channel width as the transistor 212a. By doing so, it is possible to output a third signal that is the sum of a plurality of second signals. 212c is a pixel 1 having the channel width of the transistor 212a in the pooling circuit 210. By dividing the channel width by the number of 00s, the magnitude of the third signal is divided by the number of pixels 100. The third signal and the fifth signal can be controlled by a current. The switches 203 and 204 are preferably complementary to each other.

[0035] The switches 203 and 204 are switched by a first switching signal applied to the wiring 115. In FIG. 2, a p-channel transistor is applied to the switch 203, and An example in which an n-channel transistor is applied to 204 is shown.

[0036] When the first switching signal is “L”, the pooling circuit 210 outputs the third signal to the wiring 21. 0a to the comparison module 220.

[0037] When the first switching signal is “H”, the pooling circuit 210 outputs the fifth signal to the wiring 21. 0a to the comparison module 220.

[0038] For example, in-vehicle image processing systems can instantly determine the situation around a fast-moving vehicle. Therefore, the imaging device 10 having the pooling module 200 By specializing in detecting features from data, the amount of calculation can be reduced and processing time can be shortened. can be done.

[0039] In FIG. 2, each pixel 100 in the pooling circuit 210 is assigned a different weight. The data shown is for illustrative purposes only. The same weight data may be given to each wiring module 200 as a unit. 112 and the wiring 113a connect the pooling circuit 210 or the pooling module 200 together. The imaging device 10 may be electrically connected as a single unit. By reducing 13a, the density can be increased.

[0040] FIG. 3A illustrates an example of the comparison module 220 using a block diagram. The comparison module 220 includes a plurality of comparison circuits 230 and a plurality of current mirror circuits 222. , and a judgment circuit 221. Each comparison circuit 230 has an input terminal 231a and The determination circuit 221 has an input terminal 231b and an output terminal 231c. The current mirror circuit has a first terminal 221a, an input terminal 221b, and an output terminal 221c. 222 has an input terminal 224a and an output terminal 224b.

[0041] In FIG. 3A, the comparison module 220 receives output signals from the four pooling circuits 210. In addition, the comparison module 220 is connected to the wiring 210a (i , j) to four different pooling circuits 210a(i+1, j+1) via wiring 210a(i+1, j+1). The number of comparison circuits 230 may correspond to the number of input signals. In the example shown in FIG. 3A, the comparison module 220 includes a comparison circuit 230a, a comparison circuit 230b, and a comparison circuit 230c. circuit 230b, comparison circuit 230c, current mirror circuit 222a, current mirror circuit 22 2b and a determination circuit 221.

[0042] Next, the comparison circuit 230a, the comparison circuit 230b, the comparison circuit 230c, the current mirror circuit An example of connections between the circuit 222a, the current mirror circuit 222b, and the determination circuit 221 will be described. The input terminal 231a of the comparison circuit 230a is electrically connected to the wiring 210a(i, j). The input terminal 231b is electrically connected to the wiring 210a(i+1, j), and the output terminal 23 1c is electrically connected to an input terminal 224a of a current mirror circuit 222a. The output terminal 224b of the mirror circuit 222a is connected to the input terminal 231a of the comparison circuit 230b. are electrically connected.

[0043] The input terminal 231b of the comparison circuit 230b is electrically connected to the wiring 210a(i, j+1). The output terminal 231c is electrically connected to the input terminal 224a of the current mirror circuit 222b. The output terminal 224b of the current mirror circuit 222b is connected to a comparator circuit 230c. The input terminal 231a of the comparison circuit 230c is electrically connected to the input terminal 231b of the comparison circuit 230c. is electrically connected to the wiring 210a(i+1, j+1), and the output terminal 231c is The input terminal 221a of the circuit 221 is electrically connected.

[0044] The current mirror circuit 222 includes a transistor 223a and a transistor 223b. The transistor 223a and the transistor 223b are p-channel transistors. One of the source and drain of the transistor 223a is preferably a transistor. The transistor 223b is electrically connected to one of the source and drain of the transistor 223b and the wiring 114. The gate of the transistor 223a is connected to the source or drain of the transistor 223a. The other terminal is electrically connected to the gate of the transistor 223b.

[0045] The input terminal 231a of the comparison circuit 230a receives a signal a1 via a wiring 210a(i, j). The input terminal 231b receives a signal a2 via a wiring 210a(i+1, j). The output terminal 231c outputs the signal a1 or a2, whichever is larger. The signal a3 is output and applied to the input terminal 224a of the current mirror circuit 222a. The signal a3 is converted into a signal b1 having the same magnitude as the signal a3 by passing through the current mirror circuit 222a. and is given to the output terminal 224b of the current mirror circuit. A signal b1 having the same magnitude as the signal a3 is applied to the input terminal 231a of b. Signal a3 and signal b1 have different signal directions.

[0046] The input terminal 231b of the comparison circuit 230b receives a signal via the wiring 210a(i, j+1). b2 is given, and the larger of the signals b1 and b2 is given from the output terminal 231c. The comparison circuit 230c outputs a signal b3 at its input terminal 231a. A signal c1 is given via a - circuit 222b, and a wiring 210a (i +1, j+1) and a signal c2 is given from the output terminal 231c. The larger of the signals a1 and c2 is output as signal c3 to the decision circuit 221. a2, a3, b1, b2, b3, c1, c2, and c3 are all analog signals. is preferred.

[0047] Therefore, the decision circuit 221 decides the signal c3 input to the input terminal 221a, and By converting the signal into a digital value, a fourth signal can be generated and output to the output terminal 221c. The fourth signal is output via the wiring 211 in response to a selection signal given to the wiring 111 by the bus 11. The timing of output to the circuit 251 can be controlled.

[0048] 3B, a circuit diagram of the comparison circuit 230 will be described. Transistors 241 to 246, input terminal 231a, input terminal 231b, output terminal The terminal 231c and the wiring 232 are provided.

[0049] The input terminal 231a is connected to one of the source and drain of the transistor 242. One of the source or drain of the transistor 244, the gate of the transistor 241, and the transistor The input terminal is electrically connected to the gate of the transistor 242 and the gate of the transistor 243. 231b is a connection between one of the source and drain of the transistor 245 and the One of the source or drain, the gate of transistor 244, and the gate of transistor 245 The output terminal 231c is electrically connected to the gate of the transistor 246. , one of the source or drain of the transistor 241 and the source or drain of the transistor 246 The wiring 232 is electrically connected to one of the drains of the transistors 241 to 243. It is electrically connected to the other of the source and drain of the transistor 246 .

[0050] Furthermore, transistors 241 to 246 have the same channel length. is doing.

[0051] The channel width of the transistor 241 is the same as the channel width of the transistor 242. The channel width of transistor 243 is preferably The transistors 241 to 243 are the first current A mirror circuit is formed.

[0052] The channel width of the transistor 246 is the same as that of the transistor 245. The channel width of transistor 244 is preferably Transistors 244 through 246 are the second current A mirror circuit is formed.

[0053] Next, the operation of the comparison circuit 230 will be described. A current is applied to the output terminal 31b as an analog signal, and a current is applied to the output terminal 231c as an analog signal. For example, if a signal input to input terminal 231a is input to input terminal 231b, the current is drawn. When the signal applied to input terminal 231b is greater than the signal applied to transistor 24, As another example, if a signal input to the input terminal 231b is absorbed by the input terminal 3, When the signal input to input terminal 231a is larger than the signal input to input terminal 231b, the signal input to input terminal 231a is Therefore, the output terminal 231c is connected to the first current mirror. The input terminal 231a or the input terminal 231b is connected to either the first circuit or the second current mirror circuit. The signal input to the output 231b can absorb a signal of the same magnitude as the larger signal. can.

[0054] However, when the magnitude of the input signals at the input terminals 231a and 231b is the same, The magnitude of the signal absorbed by transistor 242 and transistor 245 is half that of the signal absorbed by transistor 245. Therefore, the output terminal 231c is connected to the transistor 241 and the transistor The output terminal 231 therefore receives a signal of the combined magnitude with the transistor 246. c can absorb signals of the same magnitude as the input terminals 231a and 231b. The wiring 232 is preferably at a low potential so that it can sink signals.

[0055] Therefore, the decision circuit 221 in FIG. 3A receives the signal given to the comparison module 220. The largest signal among signals a1, a2, b2, and c2 is given as signal c3. The driver 221 can determine the signal c3 and binarize it to generate a fourth signal. 11 supplies a selection signal to a decision circuit 221 via a wiring 111, and outputs the decision result to an output circuit 25 It can be set to output 1.

[0056] FIG. 4 illustrates an example of a pixel 100 using a circuit diagram. A switching element 101, a transistor 102, a transistor 103, a capacitance element 104, a transistor The pixel 100 has a capacitor 105, a transistor 106, and an output terminal 100a. 112, wiring 113a, wiring 113b, wiring 117, wiring 118, and wiring 119 are electrically are actively connected.

[0057] One electrode of the photoelectric conversion element 101 is connected to one of the source and drain of the transistor 102. The other of the source and the drain of the transistor 102 is electrically connected to the transistor One of the source and drain of the transistor 103, the gate of the transistor 105, and the capacitor The source or drain of the transistor 105 is electrically connected to one electrode of the transistor 104. One of the electrodes of the capacitor 104 is electrically connected to the output terminal 100a, and the other electrode of the capacitor 104 is The transistor 106 is electrically connected to either the source or the drain of the transistor 106. The other of the source and drain of the transistor 106 is electrically connected to a wiring 112. The gate of the transistor 106 is electrically connected to the wiring 113a. The gate of the transistor 103 is electrically connected to the wiring 113b. The other of the source and drain of the transistor 103 is electrically connected to The other electrode of the photoelectric conversion element 101 is electrically connected to the wiring 117. The other of the source and the drain of the transistor 105 is electrically connected to the wiring 1. 19 is electrically connected to

[0058] The node FN is connected to the other of the source and drain of the transistor 102 and the 3, the gate of the transistor 105, and one of the sources or drains of the capacitor 104. The capacitor element 104 is not provided in the structure. It may be composed of

[0059] The transistor 103 can be turned on by a signal applied to a wiring 113c. Therefore, the node FN is initialized by the reset potential applied to the wiring 118. The transistor 102 can be turned on by a signal applied to the wiring 113b. Therefore, the photoelectric conversion element 101 can be turned on via the transistor 102. The data of the FN can be updated with the photoelectrically converted image data. The node 102 can be turned off by a signal applied to the wiring 113b. The FN can hold the image data by turning off the transistor 102. Therefore, the first signal is a signal obtained by applying image data to the gate of the transistor 105. This indicates the current that flows when

[0060] In FIG. 4, an n-channel transistor is used as the transistor 105. A p-channel transistor may be used, provided that the transistor 105 is an n-channel In the case of the transistor type, the potential applied to the wiring 119 is preferably low. Even when 105 is a p-channel type, the potential applied to the wiring 119 is low. It is preferable that:

[0061] The transistor 106 is turned on by a signal applied to the wiring 113a. The capacitor 104 is connected to a weighted detector 112 via a transistor 106. The node FN can be connected to the transistor 102 and the transistor 103. It is desirable for the transistor to be a floating node when it is in the off state. The transistor 102 and the transistor 103 are preferably transistors with low off-state current. A transistor having a low off-state current is preferably a transistor having a metal oxide in a channel formation region. It is preferable to use an OS transistor. A detailed explanation will be given in the second embodiment.

[0062] Weight data is added to the image data held in the node FN via the capacitor 104. That is, the gate of the transistor 105 receives a signal in which weight data is added to the image data. Therefore, the transistor 105 is turned on by the conductor Therefore, the second signal is A data voltage obtained by adding weight data to the image data is applied to the gate of the transistor 105. The figure shows the current that flows when the

[0063] FIG. 5 illustrates an example of how the pooling module 200 operates. ) for ease of explanation, the pooling module 200 is assumed to have four pooling circuits 21 0 and a comparison module 220. 10 has four pixels. The number of modules 200 is not limited.

[0064] FIG. 5B shows an example of the operation method of the pooling module 200 of FIG. 5A. The timing chart shown in FIG. 5(B) is not shown in the figure. However, when a signal of L is given to the wiring 115, the pooling circuit 210 This shows an example of adding a signal of 1.

[0065] At T1, a signal of H is applied to the wiring 113c, and the transistors of each pixel 100 The transistor 103 is turned on. Therefore, the node FN is connected to the potential applied to the wiring 118. Furthermore, a selection signal is applied to the wiring 113a, and the selection signal is applied via the wiring 112. The initial value Res of the weight data is given.

[0066] At T2, a signal of H is applied to the wiring 113b, and each pixel 100 receives a signal of H from the photoelectric conversion element 1 01 performs photoelectric conversion (sensing) and updates the node FN with the image data.

[0067] At T3, a signal of L is applied to the wiring 113b to determine the imaging data of the node FN. A selection signal is applied to the wiring 113a(1), and a selection signal is applied to the wirings 112(1) to 112(4). The pixels 100(1), 100(2), 100(5), and 100(6) Set the weight data.

[0068] At T4, a selection signal is applied to the wiring 113a(2), and the wirings 112(1) to 112( 4) through pixel 100(3), pixel 100(4), pixel 100(7), and pixel 100 (8) Set the weight data.

[0069] At T5, a selection signal is applied to the wiring 113a(3), and the wirings 112(1) to 112( 4) through pixel 100(9), pixel 100(10), pixel 100(13), and pixel 1 The weight data is set to 00(14). The data signal a1 obtained by adding weighting data to the image data is output to the wiring 210a(1,1). Furthermore, the pooling circuit 210(2,1) generates a signal a2 obtained by adding weighting data to the imaging data. The signal is output to the wiring 210a(2,1).

[0070] At T6, a selection signal is applied to the wiring 113a(4), and the wirings 112(1) to 112( 4) through pixel 100(11), pixel 100(12), pixel 100(15), and pixel Set the weight data to 100 (16).

[0071] T7 is a data signal obtained by adding weighting data to the imaging data by the pooling circuit 210(1,1). The pooling circuit 210(2,2) outputs the signal b2 to the wiring 210a(1,2). outputs a signal c2 obtained by adding weighting data to the imaging data to the wiring 210a(2,2).

[0072] T8 is determined by the comparison module 220 as the maximum signal among a1, a2, b2, and c2. The comparison module 220 has a decision circuit 221 that decides the maximum detected signal. The digital signal out is output to the wiring 211 after being binarized. The output signal is given to the output circuit 251. The output circuit 251 is easy to handle with a neural network. The digital signal out is combined and output as digital data of any data width. .

[0073] FIG. 6 shows an example of a pooling circuit 210 having a different configuration from that shown in FIG. 2 using a block diagram. In FIG. 6, the pooling circuit 210 is connected to a plurality of wires 113d, 211a, and 2 in that the pixel 100 has an output terminal 100b. It has become.

[0074] The wiring 113d is electrically connected to a plurality of pixels extending in the column direction. The wiring a is electrically connected to the output terminal 100b of the pixel 100 extending in the row direction. The imaging data is output to the wiring 211a or the wiring 211b. The signal is output to the analog-to-digital converter circuit 250 via the wiring 211b.

[0075] FIG. 7 illustrates an example of a pixel 100 having a different configuration from that shown in FIG. 4. In FIG. 7, 4 in that it has a stator 107 and a transistor 108.

[0076] The gate of the transistor 107 is electrically connected to the node FN. One of the source and drain of the transistor 107 is connected to one of the source and drain of the transistor 108. The other of the source and the drain of the transistor 108 is electrically connected to the output terminal The gate of the transistor 108 is electrically connected to the wiring 113d. The other of the source and the drain of the transistor 107 is electrically connected to the wiring 11. 9 is electrically connected to

[0077] The transistor 107 outputs a current corresponding to the potential of the image data held in the node FN. The transistor 108 is turned on by a selection signal applied to the wiring 113d. The image data can be output to the output terminal 100b. When the data is set, weight data is added to the image data and the capacitor of the transistor 105 is turned on. The multiplication result according to the inductance is output.

[0078] The imaging device 10 includes the pooling module 200, which allows for easy pooling processing. Therefore, the amount of data transferred to the neural network can be reduced. Furthermore, by reducing the amount of calculation, power consumption can be reduced.

[0079] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0080] (Embodiment 2) In this embodiment, the photoelectric conversion element 101 used in the imaging device 10 will be described with reference to FIGS. This will be explained using FIG.

[0081] <Pixel circuit configuration example> FIG. 8A illustrates a configuration of a pixel having the above-described pixel circuit. The element is an example having a stacked structure of a layer 61 and a layer 62.

[0082] The layer 61 has a photoelectric conversion element 101. The photoelectric conversion element 101 has a structure as shown in FIG. As shown, the layer 65a, the layer 65b, and the layer 65c can be stacked.

[0083] The photoelectric conversion element 101 shown in FIG. 8C is a pn junction photodiode, for example, Layer 65a to p+ layer 65b is an n-type semiconductor, layer 65c is an n-type semiconductor + Using a semiconductor Alternatively, the layer 65a may be + layer 65b is a p-type semiconductor, layer 65c is a p-type semiconductor + Type and a half Alternatively, a pin junction photodiode with the layer 65b being an i-type semiconductor may be used. may be.

[0084] The pn junction photodiode or pin junction photodiode is made of single crystal silicon. The pin junction photodiode can be formed using an amorphous silicon. It can also be formed using a thin film of crystalline silicon, microcrystalline silicon, polycrystalline silicon, etc. .

[0085] As shown in FIG. 8(D), the photoelectric conversion element 101 included in the layer 61 includes a layer 66a and a The layer 66b, the layer 66c, and the layer 66d may be stacked. Reference numeral 101 denotes an example of an avalanche photodiode, and layers 66a and 66d correspond to electrodes. The layers 66b and 66c correspond to the photoelectric conversion section.

[0086] The layer 66a is preferably a low resistance metal layer, such as aluminum or titanium. For example, tungsten, tantalum, silver, or a laminate thereof can be used.

[0087] The layer 66d may be a conductive layer having high transparency to visible light. Preferred are, for example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, Gallium-zinc oxide, indium-gallium-zinc oxide, or graphene The layer 66d may be omitted.

[0088] The layers 66b and 66c of the photoelectric conversion section are pn junction type photoelectric conversion layers made of, for example, a selenium-based material. The layer 66b is made of selenium, which is a p-type semiconductor. It is preferable to use a gallium oxide material, which is an n-type semiconductor, for the layer 66c. I wish.

[0089] Photoelectric conversion elements using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In this photoelectric conversion element, avalanche multiplication is used to convert the incident light amount into a In addition, selenium-based materials have a high optical absorption coefficient, This has the advantage in terms of production that the photoelectric conversion layer can be made as a thin film. The film can be formed by vacuum deposition, sputtering, or the like.

[0090] Selenium-based materials include crystalline selenium such as single crystal selenium and polycrystalline selenium, and amorphous selenium. Compounds of selenium, copper, indium, and selenium (CIS), or compounds of selenium, copper, indium, gallium, and selenium (CIS) Compounds of CIGS and the like can be used.

[0091] The n-type semiconductor is made of a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, Alternatively, oxides containing a mixture of these materials can be used. It also functions as a blocking layer and can reduce dark current.

[0092] The layer 62 shown in FIG. 8(A) can be, for example, a silicon substrate. The silicon substrate is provided with a silicon transistor and the like, and in addition to the pixel circuit described above, A circuit for driving the image sensor, a circuit for reading out an image signal, an image processing circuit, and the like can be provided.

[0093] As shown in FIG. 8B, the pixel has a laminated structure of a layer 61, a layer 63, and a layer 62. It's fine.

[0094] Layer 63 contains OS transistors (e.g., transistors 102 and 103 of the pixel circuit). At this time, the layer 62 is a Si transistor (for example, a transistor of a pixel circuit). It is preferable to have resistors 107, 108.

[0095] By adopting this configuration, the elements constituting the pixel circuit are distributed across multiple layers, and the elements Since the imaging device can be provided with the overlapping portions, the area of ​​the imaging device can be reduced. In the structure of FIG. 8(B), the layer 62 is a support substrate, and the pixel 100 and the peripheral Edge circuits may also be provided.

[0096] <OSトランジスタ> The semiconductor material used in the OS transistor is preferably a semiconductor having an energy gap of 2 eV or more. Preferably, a metal oxide having a conductivity of 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, and for example, the CAC -OS etc. can be used.

[0097] The semiconductor layer may be made of, for example, indium, zinc, and M (aluminum, titanium, gallium, germanium, etc.). Rumanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or halide The film can be a film represented by an In-M-Zn oxide containing a metal such as fluorine.

[0098] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form the oxide film is In≧ It is preferable that M and Zn satisfy the condition M. The metal elements of such a sputtering target The atomic ratios of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, I n:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4 .1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5 The atomic ratio of the semiconductor layers to be formed is preferably 1:1:8. The atomic ratio of metal elements contained in the target varies by ±40%. .

[0099] The semiconductor layer is made of an oxide semiconductor having a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Below, further Preferably 1 x 10 13 / cm 3 Less than 1×10, more preferably 11 / cm 3 Below, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a highly pure intrinsic or This is called a highly pure intrinsic oxide semiconductor. This results in a low impurity concentration and a low defect state density. Since the SiO2 has a low SiO2 content, it can be said that the oxide semiconductor has stable characteristics.

[0100] However, the semiconductor characteristics and electrical characteristics (electric field characteristics) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the characteristics (effective mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be determined. It is preferable to appropriately set the recess density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. It's nice.

[0101] In the oxide semiconductor that makes up the semiconductor layer, silicon and carbon, which are group 14 elements, If silicon dioxide is contained, oxygen vacancies increase and the semiconductor layer becomes n-type. The concentrations of corn and carbon (obtained by secondary ion mass spectrometry) were 2 × 10 18 ato ms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0102] In addition, when alkali metals and alkaline earth metals combine with oxide semiconductors, they attract carriers. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the semiconductor layer (by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0103] In addition, when nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, the electrons that are carriers This increases the carrier density and makes it easier to become n-type. Transistors using semiconductors tend to be normally-on. The nitrogen concentration in the sample (obtained by secondary ion mass spectrometry) was 5×10 18 atoms / cm 3 It is preferable to do the following:

[0104] The semiconductor layer may have a non-single crystal structure. CAAC-OS (C-Axis Aligned Crystallography) ine Oxide Semiconductor or C-Axis Aligne d and AB-plane Anchored Crystalline Oxi Semiconductor), including polycrystalline, microcrystalline, or amorphous structures In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density. The defect level density is low.

[0105] An oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film may have a completely amorphous structure and no crystalline portion. stomach.

[0106] The semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA region, or a crystalline structure region. The film may be a mixed film having two or more of the C-OS region and the single crystal structure region. The composite film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0107] Hereinafter, a CAC (Cloud-Aligned Crystal) layer, which is one type of non-single-crystal semiconductor layer, will be described. This paper explains the structure of the Composite OS.

[0108] CAC-OS is, for example, an oxide semiconductor in which elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. A structure of a material unevenly distributed in a size of 1 nm or more and 2 nm or less, preferably, in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The area containing the metal element is unevenly distributed and has a thickness of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or more or less, or in the vicinity of that size, is also called a mosaic or patch state. say.

[0109] Note that the oxide semiconductor preferably contains at least indium. and zinc. In addition to these, aluminum, gallium, iridium, tritium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, Germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium tantalum, tungsten, magnesium, or the like. It may also be used.

[0110] For example, CAC-OS in In-Ga-Zn oxide (In- Ga-Zn oxide may be specifically referred to as CAC-IGZO. (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4(X4, Y4, and Z 4 is a real number greater than 0). ) and so on, the material is separated into mosaics. , mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film (Hereinafter, this will also be referred to as cloud-like.)

[0111] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0112] IGZO is a common name and refers to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0113] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0114] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some of the nanoparticles are mainly composed of Ga. The region where In is observed as a nanoparticle and the region where In is observed as a nanoparticle are mainly composed of In are shown in Fig. Therefore, in CAC-OS, , the crystal structure is a secondary factor.

[0115] Note that CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, Not at all.

[0116] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0117] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. Aluminum, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The region observed is a nanoparticle with the metal element as the main component, and a nanoparticle with In as the main component in part. The structure is such that the areas observed as particles and the areas observed as particles are randomly dispersed in a mosaic pattern. cormorant.

[0118] CAC-OS is formed by sputtering under conditions where the substrate is not intentionally heated. When the CAC-OS is formed by a sputtering method, the deposition gas The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. In addition, the ratio of oxygen to the total flow rate of the deposition gas during deposition may be The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set it to 0% or more and 10% or less.

[0119] CAC-OS is an X-ray diffraction (XRD) measurement method. When measured using one of the out-of-plane θ / 2θ scans, In other words, from the X-ray diffraction, no clear peaks are observed in the measurement area. It can be seen that the orientation of the regions in the ab plane direction and the c axis direction is not observed.

[0120] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron beam diffraction pattern obtained by irradiating the sample with light, a ring-shaped region with high brightness and Several bright spots are observed in the ring region. Therefore, from the electron diffraction pattern, it is clear that CAC The crystal structure of -OS is nc(na It can be seen that the crystalline structure is no-crystal.

[0121] For example, in the case of CAC-OS made of In-Ga-Zn oxide, the energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectrometry) EDX mapping obtained using oscopy revealed that GaO X3 The area where is the main component Area and In X2 Zn Y2 O Z2 , or InOX1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0122] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from GZO compounds. X3 The main components are and the region where In X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0123] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 When carriers flow through the region where the oxide is the main component, Conductivity as a semiconductor is exhibited. X2 Zn Y2 O Z2 , or InO X The cloud-like distribution of the region where 1 is the main component in the oxide semiconductor results in a high field effect. Mobility (μ) can be achieved.

[0124] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0125] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation due to Sex and In X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) This can be done.

[0126] Furthermore, semiconductor devices using CAC-OS have high reliability. is suitable as a constituent material for various semiconductor devices.

[0127] FIG. 9A is a diagram illustrating an example of a cross section of the pixel shown in FIG. The conversion element 101 is a pn junction photodiode with a silicon photoelectric conversion layer. The layer 62 includes Si transistors and the like that constitute pixel circuits.

[0128] In the photoelectric conversion element 101, the layer 65a is p + layer 65b is an n-type region, layer 65c is an n-type region is n + The layer 65b can be used as a mold region. The layer 65b is also used to connect the power supply line to the layer 65c. For example, the area 36 is p + It can be a mold area.

[0129] In FIG. 9A, the Si transistor has a channel forming region in a silicon substrate 40. As shown in Figures 12(A) and 12(B), the planar structure is The plate 40 may have a fin-shaped semiconductor layer. FIG. 12(B) corresponds to a cross section in the channel width direction.

[0130] Alternatively, as shown in FIG. 12(C), a transistor having a semiconductor layer 45 made of a silicon thin film may be used. The semiconductor layer 45 may be formed on an insulating layer 46 on a silicon substrate 40, for example. The silicon-on-insulator (SOI) This can be done.

[0131] In FIG. 9(A), the electrical connection between the elements of the layer 61 and the elements of the layer 62 is This shows an example of a configuration in which the above is obtained using a bonding technique.

[0132] The layer 61 is provided with an insulating layer 42, a conductive layer 33 and a conductive layer 34. The conductive layer 34 has a region buried in the insulating layer 42. The conductive layer 33 is electrically connected to the layer 65a. The conductive layer 34 is electrically connected to the region 36. The insulating layer 42 and the conductive layer The surfaces of the conductive layer 33 and the conductive layer 34 are flattened so that they are at the same height.

[0133] The layer 62 is provided with an insulating layer 41, a conductive layer 31 and a conductive layer 32. The conductive layer 32 has a region buried in the insulating layer 41. The conductive layer 32 is electrically connected to the power supply line. The conductive layer 31 is electrically connected to the source or drain of the transistor 102. The surfaces of the insulating layer 41, the conductive layer 31, and the conductive layer 32 are arranged so that they are at the same height. It has been flattened like this.

[0134] Here, the conductive layer 31 and the conductive layer 33 preferably contain the same metal element as the main component. It is preferable that the conductive layer 32 and the conductive layer 34 have the same metal element as the main component. The insulating layer 41 and the insulating layer 42 are preferably made of the same component.

[0135] For example, the conductive layers 31, 32, 33, and 34 may be made of Cu, Al, Sn, Zn, W, Mo, or A. For ease of bonding, Cu, Au, etc. can be used. The insulating layers 41 and 42 are made of silicon oxide, silicon oxynitride, or the like. Silicon, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used.

[0136] That is, the combination of the conductive layer 31 and the conductive layer 33 and the combination of the conductive layer 32 and the conductive layer 34 It is preferable to use the same metal material as described above for each of the laminated layers. It is preferable to use the same insulating material as described above for both the insulating layer 41 and the insulating layer 42. By adopting this configuration, it is possible to perform bonding with the boundary between the layer 61 and the layer 62 as the bonding position. can.

[0137] By this bonding, a combination of the conductive layer 31 and the conductive layer 33 and a combination of the conductive layer 32 and Electrical connections can be obtained for each combination of conductive layers 34. 1 and the insulating layer 42, a connection having mechanical strength can be obtained.

[0138] To bond metal layers together, the oxide film on the surface and the adsorption layer of impurities are removed by sputtering or other methods. The surface activated bonding method is used to remove the surface and then bring the cleaned and activated surfaces into contact with each other to bond them. Alternatively, a diffusion bonding method can be used, which uses both temperature and pressure to bond the surfaces together. In both cases, bonding occurs at the atomic level, so they can be bonded not only electrically but also mechanically. Excellent bonding can be obtained even in

[0139] In addition, to bond the insulating layers together, after obtaining high flatness by polishing, etc., oxygen plasma is used. The surfaces are temporarily bonded by contacting each other after being treated with hydrophilic agents, etc., and then the actual bonding is carried out by dehydrating them with heat treatment. Hydrophilic bonding methods can also be used. Hydrophilic bonding methods also involve bonding at the atomic level, so Therefore, excellent mechanical bonding can be obtained.

[0140] When the layer 61 and the layer 62 are bonded together, an insulating layer and a metal layer are mixed on each bonding surface. To achieve this, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0141] For example, after polishing, the surface is cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment and then made hydrophilic. Alternatively, the surface of the metal layer may be treated with gold or other metals to bond the metal layer. It is also possible to use a metal that is difficult to oxidize and to perform hydrophilic treatment. It's fine.

[0142] FIG. 9(B) shows a pn-type photoelectric conversion layer made of a selenium-based material in the layer 61 of the pixel shown in FIG. 8(A). 10 is a cross-sectional view of a junction photodiode. It has layers 66b and 66c as the electric conversion layers and a layer 66d as the other electrode.

[0143] In this case, layer 61 can be formed directly on layer 62. Layer 66a is a transistor. The layer 66d is electrically connected to the source or drain of the capacitor 102 via the conductive layer 37. It is electrically connected to the power supply line.

[0144] 10A is a diagram illustrating an example of a cross section of the pixel shown in FIG. The photoelectric conversion element 101 is a pn junction photodiode with a silicon photoelectric conversion layer. The layer 62 includes a Si transistor and the like. The layer 63 includes an OS transistor and the like. The layer 61 and the layer 63 show an example of a configuration in which electrical connection is achieved by bonding them together.

[0145] In FIG. 10A, the OS transistor has a self-aligned structure. As shown in FIG. 12(D), a non-self-aligned top-gate transistor That's fine.

[0146] The transistor 102 has a back gate 35. The back gate 35 may be formed by a pair of opposing gate electrodes, as shown in FIG. In some cases, the buffer layer is electrically connected to the front gate of a transistor provided in the buffer layer. The gate 35 can be supplied with a fixed potential different from that of the front gate. Good too.

[0147] Between the region where the OS transistor is formed and the region where the Si transistor is formed, An insulating layer 43 having a function of preventing hydrogen diffusion is provided. The hydrogen in the insulating layer provided near the channel forming region 8 acts as a dangling bond of silicon. On the other hand, an insulating layer provided near the channel formation region of the transistor 102 The hydrogen in the oxide semiconductor layer is one of factors that generate carriers in the oxide semiconductor layer.

[0148] The insulating layer 43 confines hydrogen to one layer, thereby forming the transistors 107 and 108. This improves reliability. In addition, the diffusion of hydrogen from one layer to another is suppressed. This also improves the reliability of the transistor 102.

[0149] The insulating layer 43 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0150] FIG. 10(B) shows a p-type semiconductor device in which a selenium-based material is used as a photoelectric conversion layer in the layer 61 of the pixel shown in FIG. 8(B). This is a cross-sectional view of a case where an n-junction photodiode is used. Layer 61 is formed directly on layer 63. For details of the layers 61, 62, and 63, please refer to the above description.

[0151] FIG. 11(A) is a diagram illustrating the configuration of FIG. 10. The sensor area is a photoelectric conversion element 10 The calculation area is composed of a layer 61 having an OS transistor and a layer 63 having an OS transistor. The calculation area is made up of a layer 63 having a Si transistor etc. Registers 107 and 108, and the pooling circuit and drivers 11, 12, and 13 of the first embodiment The sensor area and the calculation area are laminated to form a circuit surface. The product can be made smaller.

[0152] Figure 11(B) shows a cross-sectional photograph of the sensor area and a cross-sectional photograph of the calculation area. , a pn junction photodiode with a selenium-based material as a photoelectric conversion layer, and an OS transistor ( The calculation area is composed of a silicon transistor (SiFET). Various circuits are configured.

[0153] <Other pixel components> FIG. 13A illustrates an example in which a color filter or the like is added to a pixel of an imaging device according to one embodiment of the present invention. This perspective view also shows cross sections of a plurality of pixels. An insulating layer 80 is formed on the layer 61 on which the conversion element 101 is formed. A silicon oxide film or the like having high light transmittance can be used for the passivation. A silicon nitride film may be laminated as the anti-reflection film. Alternatively, a dielectric film such as the above may be laminated.

[0154] A light-shielding layer 81 may be formed on the insulating layer 80. The light-shielding layer 81 may be formed by blocking the color filter on the upper side. The light-shielding layer 81 has a function of preventing the color mixing of light passing through the filter. A metal layer such as tantalum may be used. In addition, the metal layer and the function as an anti-reflection film may be used. A dielectric film having the above structure may be laminated.

[0155] An organic resin layer 82 may be provided on the insulating layer 80 and the light-shielding layer 81 as a planarization film. In addition, color filters 83 (color filters 83a, 83b, 83c) are formed for each pixel. For example, R (red), G (green), B (blue), and C (red), and D (green), and E (yellow), and E (yellow), and E (yellow), and C ... By assigning colors such as Y (blue), Y (yellow), C (cyan), and M (magenta), A large image can be obtained.

[0156] An insulating layer 86 or the like having transparency to visible light is provided on the color filter 83. This can be done.

[0157] As shown in FIG. 13(B), an optical conversion layer 85 is used instead of the color filter 83. With this configuration, it is possible to obtain images in various wavelength regions. The device may be a device.

[0158] For example, if a filter that blocks light having wavelengths shorter than visible light is used for the optical conversion layer 85, infrared In addition, the optical conversion layer 85 may be provided with a filter that blocks light having a wavelength shorter than that of near-infrared rays. If a filter is used, it can be used as a far-infrared imaging device. If a filter that blocks light longer than the wavelength of the light is used, it can be used as an ultraviolet imaging device. A visible light color filter may be combined with an infrared or ultraviolet filter.

[0159] Furthermore, if a scintillator is used for the optical conversion layer 85, the radiation used in X-ray imaging devices etc. It can be used as an imaging device to obtain an image that visualizes the intensity of radiation such as X-rays that has passed through the subject. When radiation is incident on the scintillator, visible light and ultraviolet light are emitted by the photoluminescence phenomenon. The light is converted into light (fluorescence) such as rays. The light is then detected by the photoelectric conversion element 101. Image data can also be obtained by using an imaging device with this configuration as a radiation detector. good.

[0160] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. These include materials that emit visible light and ultraviolet light as a result of the addition of ions. For example, Gd2O2S:Tb, Gd2O2S: Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used. This can be done.

[0161] In addition, the photoelectric conversion element 101 using a selenium-based material converts radiation such as X-rays into electric charges. Since direct conversion is possible, a configuration can be made in which a scintillator is not required.

[0162] Also, as shown in FIG. 13(C), a microlens array 84 is provided on the color filter 83. The light passing through each lens of the microlens array 84 is reflected by the color The light passes through the filter 83 and is irradiated onto the photoelectric conversion element 101. ) may be provided with a microlens array 84 on an optical conversion layer 85 shown in FIG.

[0163] <Package and module configuration example> Below, we will introduce an example of a package containing an image sensor chip and a camera module. The image sensor chip can use the configuration of the imaging device described above. do.

[0164] FIG. 14(A1) is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 410 on which an image sensor chip 450 is fixed. , a cover glass 420 and an adhesive 430 for bonding the two together.

[0165] FIG. 14(A2) is a perspective view of the appearance of the bottom surface of the package. The device has a BGA (Ball Grid Array) with solder balls as bumps 440. In addition to BGA, LGA (Land grid array) and PGA (Pi n Grid Array) or the like.

[0166] FIG. 14(A3) shows a package in which the cover glass 420 and the adhesive 430 are partially omitted. Electrode pads 460 are formed on the package substrate 410. The pad 460 and the bump 440 are electrically connected via a through hole. The head 460 is electrically connected to the image sensor chip 450 by a wire 470. There are.

[0167] Also, Figure 14(B1) shows an image sensor chip housed in a lens-integrated package. FIG. 1 is a perspective view of the top surface of a camera module. The package substrate 411 for fixing the chip 451, the lens cover 421, and the lens 43 5, etc. In addition, there is an imaging element between the package substrate 411 and the image sensor chip 451. An IC chip 490 having functions such as a driving circuit for the image device and a signal conversion circuit is also provided. It has a SiP (System in package) configuration.

[0168] Fig. 14(B2) is a perspective view showing the appearance of the lower surface side of the camera module. The bottom and side surfaces of the board 411 are provided with lands 441 for mounting. It has a structure of a lattice no-lead package. Note that this structure is just an example. QFP (Quad flat package) and the BGA mentioned above are provided. Good too.

[0169] FIG. 14(B3) shows a model in which the lens cover 421 and the lens 435 are partially omitted. The land 441 is electrically connected to the electrode pad 461. The wire 461 is connected to the image sensor chip 451 or the IC chip 490 by a wire 471. are electrically connected.

[0170] By placing the image sensor chip in the package as described above, the printed circuit board This makes it easier to mount image sensor chips on various semiconductor devices and electronic equipment. It can be done.

[0171] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0172] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, and the like. personal computers, image storage devices or image playback devices with recording media, mobile phones, Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of these electronic devices are shown in Figure 15.

[0173] FIG. 15(A) shows a surveillance camera, which includes a support base 951, a camera unit 952, and a protective cover. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling. This allows for the entire surrounding area to be captured. The imaging device of one embodiment of the present invention can be included as one of the products. This is a common name and does not limit its use. For example, it can be used as a surveillance camera. The device is also called a camera or video camera.

[0174] FIG. 15B shows a video camera, which includes a first housing 971, a second housing 972, and a display unit 973. , an operation key 974, a lens 975, a connection part 976, etc. The lens 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring images in the video camera, an embodiment of the present invention The camera may be equipped with an imaging device such as

[0175] FIG. 15C shows a digital camera, which includes a housing 961, a shutter button 962, a microphone, and the like. 963, a light emitting unit 967, a lens 965, etc. The imaging device according to one embodiment of the present invention can be provided as one of the components for obtaining the above object.

[0176] FIG. 15(D) shows a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, and a , a camera 939, etc. The display unit 932 is a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and can be easily attached to the body. The present invention is one of the components for acquiring images in the information terminal. The imaging device may include an imaging device according to an embodiment.

[0177] FIG. 15(E) shows an example of a mobile phone, which includes a housing 981, a display unit 982, and an operation button 983. , an external connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone has a touch sensor on the display unit 982. All operations, such as inputting, can be performed by touching the display 982 with a finger or a stylus. As one of the components for acquiring images in the mobile phone, The imaging device may be provided in the above embodiment.

[0178] FIG. 15(F) shows a portable data terminal, which includes a housing 911, a display portion 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. As one of the components for acquiring images in the portable data terminal, An imaging device may be provided.

[0179] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0180] In addition, in this specification and the like, the term "display element," "display device having a display element," "light emitting element," "light emitting device," "light emitting element ... A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be formed in various forms or in various forms. The display element, the display device, the light-emitting element or the light-emitting device may have, for example, an E EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements) , inorganic EL element), LED chip (white LED chip, red LED chip, green LED chip chips, blue LED chips, etc.), transistors (transistors that emit light according to the current), Plasma display panel (PDP), electron emission element, carbon nanotube Display elements, liquid crystal elements, electronic ink, electrowetting elements, electrophoretic elements, ME Display elements using MS (microelectromechanical systems) (e.g., grayscale Lighting light valve (GLV), Digital micromirror device (DMD), DM S (Digital Micro Shutter), MIRASOL (registered trademark), IMOD (In Terferometric modulation element, shutter-type MEMS display element, Optical interference type MEMS display element, piezoelectric ceramic display, etc.) or quantum dot In addition to these, display elements, display devices, light-emitting elements, or The light emitting device is a device that uses electrical or magnetic effects to improve contrast, brightness, reflectance, transmittance, etc. An example of a display device using an EL element is an E An example of a display device using electron-emitting devices is a field Emission display (FED) or SED type flat panel display (SED:Su rface-conduction Electron-emitter Displa An example of a display device using a liquid crystal element is a liquid crystal display (transmissive type LCD, semi-transmissive LCD, reflective LCD, direct-view LCD LCDs, projection LCDs, etc. Electronic ink, electronic liquid powder (registered trademark) ) or an example of a display device using an electrophoretic element is electronic paper. An example of a display device that uses dots for each pixel is a quantum dot display. The quantum dots may be provided as part of a backlight, rather than as a display element. By using the child dots, it is possible to display with high color purity. When realizing a liquid crystal display or a reflective liquid crystal display, a part of the pixel electrode or For example, a part of the pixel electrode or In this case, the entire surface may be made of aluminum, silver, etc. It is also possible to provide a memory circuit such as an SRAM under the projection electrode. When using an LED chip, the power consumption can be reduced. Graphene or graphite may be placed under the electrode or the nitride semiconductor. Graphite may be formed into a multilayer film by stacking multiple layers. By providing graphite, a nitride semiconductor, for example, an n-type G It is possible to easily form aN semiconductor layers and other layers. An LED chip can be constructed by providing a GaN semiconductor layer. An AlN layer may be provided between the graphite and the crystalline n-type GaN semiconductor layer. The GaN semiconductor layer of the LED chip may be formed by MOCVD. By providing graphene, the GaN semiconductor layer of the LED chip can be formed by sputtering. It is also possible to form films using MEMS (Micro-Electro-Mechanical Systems). In the case of a display element using a stem, the space in which the display element is sealed (for example, the space between the display element and the stem) between the element substrate on which the element is arranged and the opposing substrate arranged opposite the element substrate By providing a desiccant, MEMS and the like can be protected from moisture. This can prevent the product from becoming difficult to move and from deteriorating easily.

[0181] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0182] (Notes regarding the present specification) The following additional notes will be given regarding the description of each component in the above embodiment.

[0183] <Additional Notes Regarding One Aspect of the Present Invention Described in the Embodiments> The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments to realize the present invention. In addition, in one embodiment, multiple configuration examples may be shown. In this case, the configuration examples can be appropriately combined with each other.

[0184] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0185] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0186] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0187] <Note on ordinal numbers> In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, the number of components is not limited. The order of the components is not limited. The element referred to as "first" in one embodiment may be used in other embodiments or in the claims. In addition, for example, the second component may be the component referred to as "second" in the specification. A component referred to as "first" in one embodiment may be used in other embodiments, or It may be omitted in the claims.

[0188] <Notes regarding the description of the drawings> The embodiments are described with reference to the drawings. It is possible to implement the invention in various ways, and the form may be changed without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the mode and details of the present invention. The present invention should not be construed as being limited to the description of the embodiment. In the structure of the invention, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. The same is used in common between the two, and the repeated explanation will be omitted.

[0189] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in explaining the relationship with reference to the drawings. The terms and expressions indicating the arrangement may be changed as appropriate depending on the direction in which each configuration is depicted. The present invention is not limited to the above description and can be rephrased appropriately depending on the situation.

[0190] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below and directly connected to each other. For example, if the expression is "electrode B on insulating layer A," The electrode B does not need to be formed directly on the insulating layer A, and the insulating layer A and the electrode B This does not exclude the inclusion of other components in between.

[0191] In addition, in the drawings, the size, layer thickness, and area are shown at arbitrary scales for the convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the purpose of clarity, and are not limited to the shapes or values ​​shown in the drawings. fluctuations in signal, voltage, or current due to noise, or signal due to timing deviations These may include variations in signal, voltage, or current.

[0192] In addition, in the drawings, some components are shown in perspective views and the like in order to clarify the drawings. The description of the element may be omitted.

[0193] In addition, in the drawings, the same elements or elements having similar functions, elements made of the same material, or In some cases, the same reference numerals may be used to designate elements that are formed at the same time, and repeated explanations thereof will be omitted. It may be omitted.

[0194] <Notes regarding possible paraphrases> In this specification and the like, when describing the connection relationship of a transistor, The first electrode or the first terminal is referred to as the "source or drain" (or the first electrode or the first terminal). The other of the source and drain is referred to as the "other of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because the names of the source and drain of a transistor change depending on the operating conditions. In this case, the term source (drain) terminal, source (drain) electrode, etc. may be used appropriately depending on the situation. In this specification, the two terminals other than the gate are referred to as the first terminal and the second terminal. In some cases, they are called terminals, third terminals, and fourth terminals. When a transistor has two or more gates (this configuration is called a dual-gate structure), These gates are sometimes called the first gate, the second gate, the front gate, It is sometimes called a back gate. In particular, the term "front gate" is often used to refer to a gate " can be interchanged with the phrase "back gate." The term "gate" can be used interchangeably. When manufacturing a transistor, this refers to a terminal that is formed before the channel formation region. The term "top gate" refers to a gate formed behind the channel formation region during the manufacture of a transistor. This refers to a terminal formed on a

[0195] A transistor has three terminals called the gate, source, and drain. The terminal functions as a control terminal that controls the conduction state of the transistor. The two input and output terminals that function as drains are given to the transistor type and each terminal. Depending on the level of the potential, one becomes the source and the other becomes the drain. In the above, the terms source and drain can be used interchangeably.

[0196] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0197] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. It is the potential difference from the reference potential. For example, the reference potential is the ground potential (earth potential). If we use the term "potential"), we can translate voltage into potential. Ground potential is not necessarily 0V. It does not necessarily mean that the potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0198] In this specification, the terms "film" and "layer" may be used in some cases or depending on the situation. For example, the term "conductive layer" can be used interchangeably with "conductive layer" It may be possible to change the term to "insulating film" or, for example, The term may be changed to "insulating layer" in some cases. Alternatively, depending on the situation, words such as "film" and "layer" may be replaced with other terms. For example, the term "conductive layer" or "conductive film" can be changed to "conductor." In some cases, it may be possible to change the term to, for example, "insulating layer" or "insulating film." It may be possible to change the term to "insulator."

[0199] In this specification, terms such as "wiring," "signal line," and "power line" may be used in some cases. For example, "wiring" and "wiring" can be interchangeable. In some cases, it may be possible to change the term "signal line" to "signal line." It may be possible to change the term "wiring" to a term such as "power line." , and vice versa, terms such as "signal line" and "power line" will be changed to the term "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". The reverse is also true, and terms such as "signal line" may be used interchangeably with "power line" In some cases, it may be possible to change the term to "potential" applied to the wiring. Changing the term to "signal" or similar, as the case may be, or depending on the situation. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change it to a different word.

[0200] <Notes on definitions of terms> The following provides definitions of terms used in the above embodiments.

[0201] <<About impurities in semiconductors>> The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor layer. Elements with less than 0.1 atomic % are impurities. The formation of DOS (Density of States) and the carrier mobility The semiconductor may become an oxide semiconductor, and the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1 and Group 2. There are elements, group 13 elements, group 14 elements, group 15 elements, and transition metals other than the main component. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, for example, impurities such as hydrogen can be mixed in. In addition, if the semiconductor is a silicon layer, the characteristics of the semiconductor may be affected. The impurities that change the value of the valence band include, for example, oxygen, group 1 elements excluding hydrogen, group 2 elements, and group 1 elements. These include Group 3 elements and Group 15 elements.

[0202] <<About transistors>> In this specification, a transistor refers to a transistor that includes at least a gate, a drain, and a source. Both are elements with three terminals. The drain (drain terminal, drain region or A channel-shaped region is formed between the drain electrode and the source (source terminal, source region, or source electrode). By applying a voltage between the gate and source that exceeds the threshold voltage, A channel is formed in the channel formation region, allowing current to flow between the source and drain. .

[0203] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0204] <<About the Switch>> In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows.

[0205] For example, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific one as long as it can control the current.

[0206] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these There is.

[0207] When a transistor is used as a switch, the "conduction state" of the transistor is The state in which the source and drain electrodes of a transistor can be considered to be electrically shorted is called Also, the "non-conducting state" of a transistor means that the source electrode and drain electrode of the transistor are This refers to a state in which the electrodes can be considered to be electrically disconnected. When the transistor is operated as a transistor having a polarity (conductivity type), there is no particular limitation.

[0208] An example of a mechanical switch is a digital micromirror device (DMD). In 2013, a switch using MEMS (microelectromechanical systems) technology was developed. The switch has a mechanically movable electrode, and when the electrode moves, Therefore, the device operates by controlling conduction and non-conduction.

[0209] <<About connection>> In this specification, when it is stated that X and Y are connected, it means that X and Y are electrically connected. There are cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, a predetermined connection relationship, for example, a diagram or It is not limited to the connection relationships shown in the text, but also includes connection relationships other than those shown in the drawings or text. It shall be.

[0210] X, Y, etc. used here refer to objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, etc.). , conductive film, layer, etc.).

[0211] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. It has a function to control whether or not water is flushed.

[0212] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if X is transmitted to Y.

[0213] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly, the two are functionally connected via another circuit. (That is, when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it is not simply The same applies if the document is explicitly stated as being connected to the

[0214] For example, if the source (or first terminal, etc.) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. It may be electrically connected to Y through Z2 (or not), or the source of the transistor may be The first terminal (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When a part of Z2 is directly connected to Y, and another part of Z2 is directly connected to Y, it can be expressed as follows: It can be realized.

[0215] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" 2 terminals) are electrically connected to each other, and X, the source (or The first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and the Y are electrically connected in this order. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Or, "X is the source (or first terminal, etc.) of the transistor. ) and the drain (or second terminal, etc.) of the transistor Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor , Y are provided in this connection order." By using this expression, the order of connections in the circuit configuration can be specified. A distinction is made between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the coordinates of the object (for example, the device, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0216] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0217] <<About parallel and perpendicular>> In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Explanation of symbols]

[0218] 10: imaging device, 11: driver, 12: driver, 13: driver, 31: conductive layer, 3 2: conductive layer, 33: conductive layer, 34: conductive layer, 35: back gate, 36: region, 37: conductive layer, 40: silicon substrate, 41: insulating layer, 42: insulating layer, 43: insulating layer, 45: semiconductor layer, 46: insulating layer, 80: insulating layer, 81: light-shielding layer, 82: organic resin layer, 83: color filter 83a: Color filter, 83b: Color filter, 83c: Color filter, 8 4: Microlens array, 85: Optical conversion layer, 86: Insulation layer, 100: Pixel, 100a : output terminal, 100b: output terminal, 101: photoelectric conversion element, 102: transistor, 10 3: transistor, 104: capacitance element, 105: transistor, 106: transistor, 107: transistor, 108: transistor, 111: wiring, 112: wiring, 113a :Wiring, 113b:Wiring, 113c:Wiring, 113d:Wiring, 114:Wiring, 115:Wiring Wire, 117: Wiring, 118: Wiring, 119: Wiring, 200: Pooling module, 20 3: Switch, 204: Switch, 210: Pooling circuit, 210a: Wiring, 211: Wiring, 211a: wiring, 211b: wiring, 212: arithmetic circuit, 212a: transistor, 212b: transistor, 212c: transistor, 220: comparison module, 221: Determination circuit, 221a: input terminal, 221b: input terminal, 221c: output terminal, 223a: Transistor, 223b: transistor, 224a: input terminal, 224b: output terminal, 2 30: Comparison circuit, 230a: Comparison circuit, 230b: Comparison circuit, 230c: Comparison circuit, 23 1a: input terminal, 231b: input terminal, 231c: output terminal, 232: wiring, 236: Transistor, 241: transistor, 242: transistor, 243: transistor, 2 44: Transistor, 245: Transistor, 246: Transistor, 250: Analog Digital conversion circuit, 251: output circuit, 410: package substrate, 411: package substrate Plate, 420: cover glass, 421: lens cover, 430: adhesive, 435: lens, 440: Bump, 441: Land, 450: Image sensor chip, 451: Image sensor sensor chip, 460: electrode pad, 461: electrode pad, 470: wire, 471: wire Ya, 490: IC chip, 911: housing, 912: display unit, 919: camera, 932: table Display unit, 933: housing and wristband, 939: camera, 951: support stand, 952: camera Unit, 953: Protective cover, 961: Housing, 962: Shutter button, 963: 965: Lens, 967: Light-emitting part, 971: Housing, 972: Housing, 973: Display part 974: Operation keys, 975: Lens, 976: Connection section, 981: Housing, 982: Display section , 983: Operation button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera

Claims

1. 1. An imaging device having a pooling module, the pooling module includes a plurality of pooling circuits; The pooling module has a function of binarizing the largest signal among the first signals output from the plurality of pooling circuits to generate a second signal and output the second signal.

2. An electronic device comprising the imaging device according to claim 1 and a display device.

Images