Display device and manufacturing method for the same

Abstract

To suppress the decrease in reliability.SOLUTION: In an embodiment, a display device includes a first lower electrode, an inorganic insulating layer covering a peripheral part of the first lower electrode, a partition wall having a lower part disposed on the inorganic insulating layer and having conductivity and an upper part disposed on the lower part, a first organic layer disposed on the first lower electrode and including a first light-emitting layer, and a first upper electrode disposed on the first organic layer and in contact with the lower part of the partition wall. The lower part includes a bottom layer disposed on the inorganic insulating layer, and an axial layer disposed between the bottom layer and the upper part. The bottom layer and the upper part protrude from a side surface of the axial layer. The first organic layer includes a first end part overlapping on the bottom layer and a second end part overlapping on the bottom layer and existing on a side opposite to the first end part. A first length of the bottom layer overlapping with the first end part that project from the axial layer is different from a second length of the bottom layer overlapping with the second end part that project from the axial layer.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same. [Means for solving the problem]

[0005] According to one embodiment, the display device comprises: a first organic layer disposed on the first lower electrode and including a first light-emitting layer; and a first upper electrode disposed on the first organic layer and in contact with the lower part of the partition wall, wherein the partition wall surrounds the first organic layer and the first upper electrode, the lower part has a bottom layer disposed on the inorganic insulating layer and an axial layer disposed between the bottom layer and the upper part, the bottom layer and the upper part protruding from a side of the axial layer, and the first organic layer has a first end overlapping the bottom layer and a second end overlapping the bottom layer and opposite the first end, and a first length protruding from the axial layer of the bottom layer overlapping the first end is different from a second length protruding from the axial layer of the bottom layer overlapping the second end.

[0006] According to one embodiment, the display device comprises: a first organic layer disposed on the first lower electrode and including a first light-emitting layer; a first upper electrode disposed on the first organic layer and in contact with the lower part of the partition wall; a second organic layer disposed on the second lower electrode and including a second light-emitting layer formed of a material different from the first light-emitting layer; and a second upper electrode disposed on the second organic layer and in contact with the lower part of the partition wall, wherein the partition wall surrounds the first organic layer, the first upper electrode, the second organic layer, and the second upper electrode, and the lower part is a conductive layer formed on the inorganic insulating layer. the second organic layer has a third end located on the opposite side of the partition wall from the second end and overlapping the bottom layer, and a fourth end located on the opposite side of the partition wall from the third end, the second thickness of the first upper electrode directly above the second end being greater than the first thickness of the first upper electrode directly above the first end, and the fourth thickness of the second upper electrode directly above the fourth end being greater than the third thickness of the second upper electrode directly above the third end.

[0007] According to one embodiment, a method for manufacturing a display device includes the steps of: A processing substrate is prepared above a substrate, on which a first lower electrode, a second lower electrode, a third lower electrode, an inorganic insulating layer covering the peripheries of each of the first lower electrode, the second lower electrode, and the third lower electrode, and a partition wall including a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion are formed; a first laminated film is formed on the first lower electrode, the first laminated film including a first organic layer including a first light-emitting layer and a first upper electrode located on the first organic layer; a second laminated film is formed on the second lower electrode, the second laminated film including a second organic layer including a second light-emitting layer different from the first light-emitting layer, and a second upper electrode located on the second organic layer; a third organic layer including a third light-emitting layer different from the first light-emitting layer and the second light-emitting layer, and a third upper electrode located on the third organic layer, is formed on the third lower electrode; each of the first upper electrode, the second upper electrode, and the third upper electrode is formed by emitting a conductive material from a vapor deposition source tilted with respect to a normal to the processing substrate, and depositing the conductive material using the partition wall as a mask while transporting the processing substrate, and the vapor deposition directions when forming each of the first upper electrode, the second upper electrode, and the third upper electrode are the same. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the main part of the display device DSP taken along line CD in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the main part of the display device DSP taken along the line EF in FIG. [Figure 6] FIG. 6 is a diagram illustrating the vapor deposition apparatus EV. [Figure 7] FIG. 7 is a diagram for explaining an example of a deposition direction D when forming the upper electrode in each sub-pixel. [Figure 8] FIG. 8 is a diagram for explaining another example of the deposition direction D when forming the upper electrode in each sub-pixel. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 10] FIG. 10 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11] FIG. 11 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 12] FIG. 12 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 13] FIG. 13 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 14] FIG. 14 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 15] FIG. 15 is a cross-sectional view of the subpixels SP2 and SP3 on which the laminated film FL1 is formed. [Figure 16] FIG. 16 is a cross-sectional view of the subpixels SP2 and SP3 with the laminated film FL1 removed. [Figure 17] FIG. 17 is a diagram showing another example of the layout of the subpixels SP1, SP2, and SP3. [Figure 18] FIG. 18 is a diagram showing another example of the layout of the subpixels SP1, SP2, and SP3. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0010] In the drawings, mutually perpendicular X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0011] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] FIG. 1 is a diagram showing an example of the configuration of a display device DSP.

[0013] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0014] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0015] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, second color, and third color are different from each other. Note that the pixel PX may include subpixels SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0016] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0020] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each of the terminals TE extends in a second direction Y, but this is not limiting. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0021] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0022] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0023] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which multiple subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0024] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0025] In the display area DA, an inorganic insulating layer 5 and partition walls 6 are arranged. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0026] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the inorganic insulating layer 5. The partition wall 6 is conductive and electrically connected to the terminal TE of the common potential among the multiple terminals TE shown in FIG. 1 .

[0027] The subpixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0028] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each overlapping with the aperture AP1. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a planar view. The peripheries of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR1 includes a light-emitting layer that emits light in, for example, a blue wavelength region.

[0029] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the aperture AP2. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a planar view. The peripheries of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0030] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each overlapping with the aperture AP3. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a planar view. The peripheries of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR3 includes a light-emitting layer that emits light in the red wavelength range, for example.

[0031] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect their exact shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or common electrodes, and are in contact with the partition walls 6.

[0033] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1) through a contact hole CH1. The lower electrode LE2 is electrically connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0034] In the illustrated example, the areas of openings AP1, AP2, and AP3 are different from one another. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. In other words, the area of ​​the lower electrode LE1 exposed through opening AP1 is larger than the area of ​​the lower electrode LE2 exposed through opening AP2, and the area of ​​the lower electrode LE2 exposed through opening AP2 is larger than the area of ​​the lower electrode LE3 exposed through opening AP3.

[0035] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0036] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1 and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens unevenness caused by the circuit layer 11.

[0037] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and spaced apart from one another. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the inorganic insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted from FIG. 3 .

[0038] The partition wall 6 has a conductive lower portion 61 disposed on the inorganic insulating layer 5 and an upper portion 62 disposed on the lower portion 61 .

[0039] In the illustrated example, the lower part 61 has a bottom layer 63 disposed on the inorganic insulating layer 5 and an axial layer 64 disposed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a width greater than that of the axial layer 64. Both ends of the bottom layer 63 protrude from the side surfaces of the axial layer 64. The upper part 62 has a first thin film 65 disposed on the axial layer 64 and a second thin film 66 disposed on the first thin film 65. The upper part 62 has a width greater than that of the axial layer 64. Both ends of the upper part 62 protrude from the side surfaces of the axial layer 64. In the illustrated example, the upper portion 62 has a width greater than that of the bottom layer 63. The bottom layer 63 may have a width greater than that of the upper portion 62.

[0040] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0041] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0042] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0043] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0045] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3.

[0046] In the following description, the multilayer structure including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer structure including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer structure including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0047] In the illustrated example, a part of the laminated film FL1 is located on the partition wall 6 around the subpixel SP1, and is spaced apart from the laminated film FL1 (the part that constitutes the display element DE1) located in the aperture AP1. Similarly, a part of the laminated film FL2 is located on the partition wall 6 around the subpixel SP2, and is spaced apart from the laminated film FL2 (the part that constitutes the display element DE2) located in the aperture AP2. Similarly, a part of the laminated film FL3 is located on the partition wall 6 around the subpixel SP3, and is spaced apart from the laminated film FL3 (the part that constitutes the display element DE3) located in the aperture AP3. The stacked films FL1, FL2, and FL3 on the partition wall 6 may be omitted. In this case, a cavity is formed between the partition wall 6 and the sealing layers SE1, SE2, and SE3.

[0048] Ends of the sealing layers SE1, SE2, and SE3 are each located on the partition wall 6. In the example shown, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0049] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. When cavities are formed between the sealing layers SE1, SE2, and SE3 and the partition wall 6, the resin layer 13 fills these cavities. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0050] The inorganic insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0051] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The shaft layer 64 is formed of a material different from the bottom layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0052] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The first thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0053] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers.

[0054] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the emitting layer EM3 is formed of a material that emits light in the red wavelength range. Each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0055] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0056] The cap layers CP1, CP2, and CP3 are multilayer structures made up of multiple thin films, all of which are transparent and have different refractive indices.

[0057] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are disposed across the display area DA and the peripheral area SA.

[0058] FIG. 4 is a schematic cross-sectional view of the main part of the display device DSP taken along line CD in FIG.

[0059] 4 shows a cross section of a plurality of subpixels SP1 aligned in the second direction Y. Note that the substrate 10, the circuit layer 11, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in FIG.

[0060] Focus on the subpixel SP1 located in the center of the figure. The organic layer OR1 has an end P1 along the second direction Y and an end P2 opposite to the end P1. In FIG. 4, the region including the end P1 and the region including the end P2 are respectively enlarged and shown. The end P1 and the end P2 are located on the bottom layer 63 and spaced apart from the axial layer 64. The end P1 and the end P2 are also located directly below the upper portion 62.

[0061] The lower electrode LE1 has an electrode end LE1A on the side where the end P1 is located and an electrode end LE1B on the side where the end P2 is located. The partition wall 6 overlaps the electrode ends LE1A and LE1B. In the illustrated example, the electrode ends LE1A and LE1B are located directly below the axis layer 64.

[0062] The bottom layer 63 overlapping the end P1 has a length L1 that protrudes from the shaft layer 64. The bottom layer 63 overlapping the end P2 has a length L2 that protrudes from the shaft layer 64. The length L1 is different from the length L2. In the illustrated example, the length L2 is greater than the length L1 (L1 <L2)。

[0063] The upper electrode UE1 overlaps the organic layer OR1 and directly contacts the upper surface of the bottom layer 63 beyond the end portions P1 and P2. In this specification, the upper surface of the bottom layer 63 shall include the surface of the bottom layer 63 that the shaft layer 64 directly contacts and the surface that protrudes from the shaft layer 64 and faces the upper portion 62. In the illustrated example, the upper electrode UE1 directly contacts the side surface of the shaft layer 64 of the partition wall 6 facing the end portion P2. In this specification, the side surface of the shaft layer 64 shall be the surface that extends between the bottom layer 63 and the upper portion 62 of the shaft layer 64. Also, the upper electrode UE1 is separated from the shaft layer 64 of the partition wall 6 facing the end portion P1, but it may also contact this shaft layer 64. When the upper electrode UE1 is separated from the shaft layer 64 of the partition wall 6 facing the end portion P1, the cap layer CP1 directly contacts the upper surface of the bottom layer 63. Also, when the upper electrode UE1 is separated from the shaft layer 64 of the partition wall 6 facing the end portion P1, the upper electrode UE1 may directly contact the upper surface of the bottom layer 63 or may not contact the bottom layer 63.

[0064] As shown by expanding the regions including the end portion P1 and the regions including the end portion P2 respectively, in the upper electrode UE1, the thickness T2 directly above the end portion P2 is greater than the thickness T1 directly above the end portion P1 (T1 < T2). The contact area between the lower portion 61 facing the end portion P2 and the upper electrode UE1 is greater than the contact area between the lower portion 61 facing the end portion P1 and the upper electrode UE1.

[0065] The laminate of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is arranged over the entire upper surface of the upper portion 62 of the partition wall 6. The sealing layer SE1 covers the cap layer CP1 and the partition wall 6.

[0066] In the example shown in FIG. 4, for example, the lower electrode LE1 corresponds to the first lower electrode, the electrode end LE1A corresponds to the first electrode end, and the electrode end LE1B corresponds to the second electrode end. The organic layer OR1 corresponds to the first organic layer, the end P1 corresponds to the first end, and the end P2 corresponds to the second end. The length L1 corresponds to the first length, and the length L2 corresponds to the second length. The upper electrode UE1 corresponds to the first upper electrode, the thickness T1 corresponds to the first thickness, and the thickness T2 corresponds to the second thickness. The cap layer CP1 corresponds to the first cap layer, and the sealing layer SE1 corresponds to the first sealing layer.

[0067] When forming the subpixels SP1, SP2, and SP3, if the subpixel SP1 is formed first, the length L1 is approximately equal to the length L2.

[0068] FIG. 5 is a schematic cross-sectional view of the main part of the display device DSP taken along the line EF in FIG.

[0069] 5 shows a cross section of subpixels SP2 and subpixels SP3 arranged alternately in the second direction Y. In FIG. 5, the substrate 10, the circuit layer 11, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in FIG. 3 are omitted.

[0070] First, let us focus on the subpixel SP3 located on the left side of the figure. The organic layer OR3 has an end P11 along the second direction Y and an end P12 opposite to the end P11. In Figure 5, the area including the end P11 and the area including the end P12 are shown enlarged. The end P11 and the end P12 are located on the bottom layer 63 and spaced apart from the axis layer 64.

[0071] The bottom layer 63 overlapping the end P11 has a length L11 protruding from the shaft layer 64. The bottom layer 63 overlapping the end P12 has a length L12 protruding from the shaft layer 64. The length L11 is different from the length L12. In the illustrated example, the length L12 is greater than the length L11 (L11). <L12)。

[0072] The upper electrode UE3 overlaps the organic layer OR3 and is directly in contact with the upper surface of the bottom layer 63 beyond the end portions P11 and P12. In the illustrated example, the upper electrode UE3 is directly in contact with the side surface of the axial layer 64 of the partition wall 6 facing the end portion P12. Also, the upper electrode UE3 is spaced apart from the axial layer 64 of the partition wall 6 facing the end portion P11, but it may be in contact with this axial layer 64. When the upper electrode UE3 is spaced apart from the axial layer 64 of the partition wall 6 facing the end portion P11, the cap layer CP3 is directly in contact with the upper surface of the bottom layer 63. Also, when the upper electrode UE3 is spaced apart from the axial layer 64 of the partition wall 6 facing the end portion P11, the upper electrode UE3 may be directly in contact with the upper surface of the bottom layer 63, or may not be in contact with the bottom layer 63.

[0073] As shown by expanding the regions including the end portion P11 and the regions including the end portion P12 respectively, in the upper electrode UE3, the thickness T12 directly above the end portion P12 is greater than the thickness T11 directly above the end portion P11 (T11 < T12). The contact area between the lower portion 61 facing the end portion P12 and the upper electrode UE3 is greater than the contact area between the lower portion 61 facing the end portion P11 and the upper electrode UE3.

[0074] The laminate of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is disposed on the upper portion 62 of the partition wall 6. The sealing layer SE3 covers the cap layer CP3 and the partition wall 6. Also, the sealing layer SE3 is disposed on the laminate above the partition wall 6. Note that the laminate located on the upper portion 62 of the partition wall 6 may be omitted. In this case, a cavity is formed between the upper portion 62 of the partition wall 6 and the sealing layer SE3.

[0075] Next, pay attention to the sub-pixel SP2 located on the right side of the figure. The organic layer OR2 has an end portion P13 along the second direction Y and an end portion P14 on the opposite side of the end portion P13. In FIG. 5, the regions including the end portion P13 and the regions including the end portion P14 are respectively shown enlarged. The end portion P13 is located on the opposite side of the end portion P12 across the partition wall 6. The end portions P13 and P14 are located on the bottom layer 63 and are spaced apart from the axial layer 64.

[0076] The bottom layer 63 overlapping the end portion P13 has a length L13 protruding from the shaft layer 64. The bottom layer 63 overlapping the end portion P14 has a length L14 protruding from the shaft layer 64. The length L13 is different from the length L14. In the illustrated example, the length L14 is larger than the length L13 (L13 < L14).

[0077] The upper electrode UE2 overlaps the organic layer OR2 and is directly in contact with the upper surface of the bottom layer 63 beyond the end portions P13 and P14. In the illustrated example, the upper electrode UE2 is directly in contact with the side surface of the shaft layer 64 of the partition wall 6 facing the end portion P14. Also, the upper electrode UE2 is separated from the shaft layer 64 of the partition wall 6 facing the end portion P13, but it may be in contact with this shaft layer 64. When the upper electrode UE2 is separated from the shaft layer 64 of the partition wall 6 facing the end portion P13, the cap layer CP2 is directly in contact with the upper surface of the bottom layer 63. Also, when the upper electrode UE2 is separated from the shaft layer 64 of the partition wall 6 facing the end portion P13, the upper electrode UE2 may be directly in contact with the upper surface of the bottom layer 63, or it may not be in contact with the bottom layer 63.

[0078] As shown by expanding the regions including the end portion P13 and the region including the end portion P14 respectively, in the upper electrode UE2, the thickness T14 directly above the end portion P14 is larger than the thickness T13 directly above the end portion P13 (T13 < T14). The contact area between the lower portion 61 facing the end portion P14 and the upper electrode UE2 is larger than the contact area between the lower portion 61 facing the end portion P13 and the upper electrode UE2.

[0079] The laminate of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 is disposed on the upper portion 62 of the partition wall 6. The sealing layer SE2 covers the cap layer CP2 and the partition wall 6. Also, the sealing layer SE2 is disposed on the laminate on the partition wall 6. On the partition wall 6, the sealing layer SE2 is separated from the sealing layer SE3. Note that the laminate located on the upper portion 62 of the partition wall 6 may be omitted. In this case, a cavity is formed between the upper portion 62 of the partition wall 6 and the sealing layer SE2.

[0080] Next, attention will be focused on the partition wall 6 between the subpixel SP2 and the subpixel SP3.

[0081] In the bottom layer 63, the length L12 of the portion protruding from the axis layer 64 toward the subpixel SP3 is greater than the length L13 of the portion protruding from the axis layer 64 toward the subpixel SP2 (L12>L13).

[0082] Furthermore, the difference Δ3 between the lengths L11 and L12 in the subpixel SP3 is different from the difference Δ2 between the lengths L13 and L14 in the subpixel SP2 (Δ3≠Δ2). Furthermore, the difference Δ1 between the lengths L1 and L2 in the subpixel SP1 shown in FIG. 4 is different from both the difference Δ2 and the difference Δ3. For example, when the subpixels SP1, SP2, and SP3 are formed in this order, the magnitude relationship of the differences can be as follows. Δ3>Δ2>Δ1

[0083] The thickness T12 of the upper electrode UE3 immediately above the end P12 is greater than the thickness T13 of the upper electrode UE2 immediately above the end P13 (T12>T13).

[0084] In the example shown in FIG. 5, for example, the lower electrode LE3 corresponds to the first lower electrode, and the lower electrode LE2 corresponds to the second lower electrode. The organic layer OR3 corresponds to the first organic layer, the end P11 corresponds to the first end, and the end P12 corresponds to the second end. The organic layer OR2 corresponds to the second organic layer, the end P13 corresponds to the third end, and the end P14 corresponds to the fourth end. The length L11 corresponds to the first length, the length L12 corresponds to the second length, the length L13 corresponds to the third length, and the length L14 corresponds to the fourth length. The upper electrode UE3 corresponds to the first upper electrode, the thickness T11 corresponds to the first thickness, and the thickness T12 corresponds to the second thickness. The upper electrode UE2 corresponds to the second upper electrode, the thickness T13 corresponds to the third thickness, and the thickness T14 corresponds to the fourth thickness. The cap layer CP3 corresponds to the first cap layer, and the cap layer CP2 corresponds to the second cap layer. The sealing layer SE3 corresponds to the first sealing layer, and the sealing layer SE2 corresponds to the second sealing layer.

[0085] Next, the deposition apparatus EV for forming each upper electrode will be described.

[0086] FIG. 6 is a diagram illustrating the vapor deposition apparatus EV.

[0087] The vapor deposition apparatus EV includes a vapor deposition source 110 configured to emit a conductive material M for forming the upper electrode. The illustrated process substrate SUB has a substrate 10 on which a circuit layer 11, an insulating layer 12, a lower electrode LE, an inorganic insulating layer 5, a partition wall 6, and an organic layer OR are formed. The process substrate SUB has one end SUBA and another end SUBB opposite to the one end SUBA. In the illustrated example, the process substrate SUB is transported with the one end SUBA as the leading end. The transport direction TD of the process substrate SUB is indicated by an arrow in the figure.

[0088] The extension direction of the vapor deposition source 110 is indicated by a dotted line in the figure, and the normal to the substrate 10 is indicated by a dashed line in the figure. The extension direction of the vapor deposition source 110 is inclined with respect to the normal to the substrate 10. Here, the extension direction is, for example, the direction in which a nozzle 120 that regulates the emission direction of the conductive material M extends. The vapor deposition direction D of the conductive material M by the vapor deposition source 110 is indicated by an arrow in the figure. The vapor deposition direction D is the direction from the bottom 111 of the vapor deposition source 110 toward the opening 112 of the vapor deposition source 110. In other words, the bottom 111 is located upstream of the vapor deposition direction D, and the opening 112 is located downstream of the vapor deposition direction D. When the arrow indicating the vapor deposition direction D points to the right as shown in the figure, this means that the conductive material M is emitted from the left to the right in the figure. In the illustrated example, the vapor deposition direction D is opposite to the transport direction TD, but it may also be the same as the transport direction TD.

[0089] In such a deposition apparatus EV, the deposition source 110 is fixed and emits a conductive material M. The conductive material M is a mixture of magnesium and silver. While the processing substrate SUB is transported with one end SUBA as the leading end, the partition wall 6 is used as a mask and the conductive material M emitted from the deposition source 110 is deposited on the processing substrate SUB. In this way, an upper electrode UE is formed on the organic layer OR. In another example of the deposition apparatus EV, the deposition source 110 may be configured to be movable while emitting the conductive material M. In such a deposition apparatus EV, the deposition source 110 radiates the conductive material M while moving relative to the fixed processing substrate SUB, whereby the conductive material M is deposited on the processing substrate SUB. Furthermore, as another example of the deposition apparatus EV, the deposition source 110 may move while emitting the conductive material M, and the processing substrate may be transported. That is, the upper electrode is formed by depositing the conductive material M emitted from the deposition source 110 onto the processing substrate SUB while changing the relative positions of the processing substrate SUB and the deposition source 110 in the deposition apparatus EV.

[0090] As shown in the figure, when the deposition direction D is from left to right in the figure, in the subpixel SPX located in the center of the figure, the conductive material M is less likely to be deposited near the partition wall 6L on the left side and more likely to be deposited near the partition wall 6R on the right side. Therefore, the thickness of the upper electrode formed near the partition wall 6R is greater than the thickness of the upper electrode formed near the partition wall 6L.

[0091] As a result, the upper electrode UE1 having the thicknesses T1 and T2 described with reference to Fig. 4 is formed. Also, the upper electrode UE3 having the thicknesses T11 and T12 and the upper electrode UE2 having the thicknesses T13 and T14 described with reference to Fig. 5 are formed.

[0092] FIG. 7 is a diagram for explaining an example of a deposition direction D when forming the upper electrode in each sub-pixel.

[0093] In the subpixel SP1, the opening AP1 in the inorganic insulating layer 5 overlaps the lower electrode LE1, and the organic layer OR1 is disposed on the lower electrode LE1 in the opening AP1. The deposition direction D when forming the upper electrode UE1 on the organic layer OR1 is indicated by an arrow in the figure. An end P1 of the organic layer OR1 is located upstream of the deposition direction D. An end P2 of the organic layer OR1 is located downstream of the deposition direction D. In the vicinity of the end P1, the conductive material forming the upper electrode UE1 is less likely to be deposited due to the influence of the partition wall 6. On the other hand, in the vicinity of the end P2, the conductive material forming the upper electrode UE1 penetrates below the partition wall 6, and can electrically connect the upper electrode UE1 and the partition wall 6.

[0094] In the subpixel SP3, the opening AP3 in the inorganic insulating layer 5 overlaps with the lower electrode LE3, and the organic layer OR3 is disposed on the lower electrode LE3 in the opening AP3. The deposition direction D when the upper electrode UE3 is formed on the organic layer OR3 is indicated by an arrow in the figure. An end P11 of the organic layer OR3 is located upstream of the deposition direction D, and an end P12 of the organic layer OR3 is located downstream of the deposition direction D. In the vicinity of the end P11, the conductive material forming the upper electrode UE3 is less likely to be deposited due to the influence of the partition wall 6. On the other hand, in the vicinity of the end P12, the conductive material forming the upper electrode UE3 penetrates below the partition wall 6, and can electrically connect the upper electrode UE3 and the partition wall 6.

[0095] In the subpixel SP2, the opening AP2 in the inorganic insulating layer 5 overlaps with the lower electrode LE2, and the organic layer OR2 is disposed on the lower electrode LE2 in the opening AP2. The deposition direction D when the upper electrode UE2 is formed on the organic layer OR2 is indicated by an arrow in the figure. An end P13 of the organic layer OR2 is located upstream of the deposition direction D, and an end P14 of the organic layer OR2 is located downstream of the deposition direction D. In the vicinity of the end P13, the conductive material forming the upper electrode UE2 is less likely to be deposited due to the influence of the partition wall 6. On the other hand, in the vicinity of the end P14, the conductive material forming the upper electrode UE2 penetrates below the partition wall 6, and can electrically connect the upper electrode UE2 and the partition wall 6.

[0096] The upper electrodes UE1, UE2, and UE3 are all formed in the same deposition direction D. In the illustrated example, the deposition direction D is substantially parallel to the second direction Y in which the subpixels SP2 and SP3 are aligned. Ends P1 and P2 of the organic layer OR1 are located at both ends of the subpixel SP1 in the second direction Y. Ends P11 and P12 of the organic layer OR3 are located at both ends of the subpixel SP3 in the second direction Y. Ends P13 and P14 of the organic layer OR2 are located at both ends of the subpixel SP2 in the second direction Y.

[0097] FIG. 8 is a diagram for explaining another example of the deposition direction D when forming the upper electrode in each sub-pixel.

[0098] The example shown in FIG. 8 differs from the example shown in FIG. 7 in that the vapor deposition direction D when forming the upper electrodes UE1, UE2, and UE3 is substantially parallel to the first direction X.

[0099] Both ends P1, P2 of the organic layer OR1 are located at both ends of the subpixel SP1 in the first direction X. In the vicinity of the end P2 located on the downstream side in the deposition direction D, the conductive material forming the upper electrode UE1 penetrates below the partition wall 6, and can electrically connect the upper electrode UE1 and the partition wall 6.

[0100] Both end portions P11, P12 of the organic layer OR3 are located at both end portions of the subpixel SP3 along the first direction X. In the vicinity of the end portion P12 located on the downstream side in the deposition direction D, the conductive material forming the upper electrode UE3 penetrates below the partition wall 6, and can electrically connect the upper electrode UE3 and the partition wall 6.

[0101] Ends P13 and P14 of the organic layer OR2 are located at both ends of the subpixel SP2 in the first direction X. In the vicinity of end P14 located downstream in the deposition direction D, the conductive material forming the upper electrode UE2 penetrates below the partition wall 6, and can electrically connect the upper electrode UE2 and the partition wall 6.

[0102] 8, for example, the lower electrode LE1 corresponds to the first lower electrode, and the lower electrode LE2 or the lower electrode LE3 corresponds to the second lower electrode. The organic layer OR1 corresponds to the first organic layer, the end P1 corresponds to the first end, and the end P2 corresponds to the second end. The organic layer OR2 or the organic layer OR3 corresponds to the second organic layer, the end P11 or the end P13 corresponds to the third end, and the end P12 or the end P14 corresponds to the fourth end.

[0103] Next, a manufacturing method of the display device DSP will be described. Note that in each drawing for explaining the manufacturing method, illustration of the part below the insulating layer 12 is omitted. Figures 9 to 14 referred to in the following description correspond to a cross section taken along line AB in Figure 2.

[0104] First, as shown in FIG. 9 , a processing substrate SUB having lower electrodes LE1, LE2, and LE3, an inorganic insulating layer 5, and partition walls 6 is prepared. The process of preparing the processing substrate SUB includes the following steps: A circuit layer 11 and an insulating layer 12 are formed on a substrate 10 across the display area DA and the peripheral area SA. Then, a lower electrode LE1 for subpixel SP1, a lower electrode LE2 for subpixel SP2, and a lower electrode LE3 for subpixel SP3 are formed on the insulating layer 12. An inorganic insulating layer 5 is then formed to cover the peripheries of the lower electrodes LE1, LE2, and LE3. Then, a partition wall 6 is formed, having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61. The bottom layer 63 and upper portion 62 of the lower portion 61 protrude from the side surfaces of an axis layer 64 of the lower portion 61. The bottom layer 63 is formed of a titanium-based material, and the axis layer 64 is formed of an aluminum-based material. The step of forming the openings AP1, AP2, and AP3 in the inorganic insulating layer 5 may be performed before or after the partition walls 6 are formed.

[0105] Next, the display element DE1 is formed.

[0106] First, as shown in FIG. 10, a laminated film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The process of forming the laminated film FL1 includes the steps of forming the organic layer OR1 on the lower electrode LE1 in the opening AP1, forming the upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6, and forming the cap layer CP1 on the upper electrode UE1. The process of forming the organic layer OR1 includes the steps of forming a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer EM1, a hole blocking layer, an electron transport layer, an electron injection layer, etc. The upper electrode UE1 is formed from a mixture of magnesium and silver.

[0107] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by vapor deposition using the partition wall 6 as a mask. In particular, the upper electrode UE1 is formed by depositing a conductive material emitted from a vapor deposition source 110 tilted with respect to the normal to the process substrate SUB in the vapor deposition apparatus EV described with reference to FIG.

[0108] The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are continuously formed while maintaining a vacuum environment. The laminated film FL1 is also formed on the lower electrodes LE2 and LE3.

[0109] Then, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminated film FL1 by chemical vapor deposition (CVD). The sealing layer SE1 continuously covers each divided portion of the laminated film FL1 and the partition wall 6.

[0110] 11, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps the subpixel SP1 and part of the partition wall 6 around it.

[0111] Next, as shown in FIG. 12, etching is performed using the resist RS as a mask. That is, dry etching is performed using the resist RS as a mask to remove the sealing layer SE1 exposed from the resist RS. Then, the laminated film FL1 exposed from the resist RS is removed. At this time, in the laminated film FL1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 are removed in this order. As a result, the laminated film FL1 covered with the resist RS remains in the subpixel SP1. In addition, a part of the upper part 62 of the partition wall 6 is exposed, and the lower electrodes LE2 and LE3 are also exposed. Thereafter, the resist RS is removed, thereby forming the display element DE1 in the subpixel SP1. In the process of removing the sealing layer SE1 and the stacked film FL1 and then removing the resist RS, the stacked film FL1 located on the upper portion 62 of the partition wall 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE1.

[0112] Next, as shown in FIG. 13, a display element DE2 is formed. The process for forming the display element DE2 is similar to that for forming the display element DE1. That is, an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are sequentially formed on the lower electrode LE2 to form a stacked film FL2. Then, a sealing layer SE2 is formed on the stacked film FL2. A resist is then formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. This forms a display element DE2 in the subpixel SP2, and exposes the lower electrode LE3 of the subpixel SP3. Note that, during the process of removing the sealing layer SE2 and the stacked film FL2, and then removing the resist, the stacked film FL2 located on the upper portion 62 of the partition wall 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE2.

[0113] Next, as shown in FIG. 14, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are sequentially formed on the lower electrode LE3 to form a stacked film FL3. Then, a sealing layer SE3 is formed on the stacked film FL3. A resist is then formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. This results in the display element DE3 being formed in the subpixel SP3. Note that, during the process of removing the sealing layer SE3 and the stacked film FL3, the stacked film FL3 located on the upper portion 62 of the partition wall 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE3.

[0114] Thereafter, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in Fig. 3 are formed in this order, thereby completing the display device DSP.

[0115] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order in which display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0116] Incidentally, when each of the upper electrodes UE1, UE2, and UE3 is formed using the vapor deposition apparatus EV described with reference to FIG. 6, as described above, differences in thickness occur near both ends of each upper electrode. For example, if the thickness of one end of the upper electrode is extremely thin, or if the upper electrode exposes the bottom layer, when removing the sealing layers SE1 and SE2 by dry etching, the upper electrode may not function as an etching stopper and may damage the bottom layer. This point will be described in detail with reference to the drawings.

[0117] FIG. 15 is a cross-sectional view of the subpixels SP2 and SP3 on which the laminated film FL1 is formed.

[0118] The deposition direction D when forming the upper electrode UE1 is from left to right in the drawing, that is, from the end Pa to the end Pb of the organic layer OR1 formed in the subpixel SP2. Immediately after the laminated film FL1 is formed, the length La of the bottom layer 63 overlapping the end Pa protruding from the axial layer 64 is approximately equal to the length Lb of the bottom layer 63 overlapping the end Pb protruding from the axial layer 64. The thickness of the upper electrode UE1 covering the end Pa is smaller than the thickness of the upper electrode UE1 covering the end Pb.

[0119] FIG. 16 is a cross-sectional view of the subpixels SP2 and SP3 with the laminated film FL1 removed.

[0120] The upper electrode UE1 functions as an etching stopper when removing, for example, the sealing layer SE1 of the stacked film FL1. However, if the thickness of the upper electrode UE1 covering the end Pa is extremely small, or if the upper electrode UE1 exposes the bottom layer 63, the bottom layer 63 is damaged, the thickness of the bottom layer 63 decreases, and even a portion of the bottom layer 63 is removed. In the illustrated example, the bottom layer 63 on the left side of the figure is damaged and recedes. Therefore, the length La of the bottom layer 63 shown on the left side of the figure is shorter than the length Lb of the bottom layer 63 shown on the right side of the figure.

[0121] In such a subpixel SP2, when the stacked film FL2 is subsequently formed, the deposition direction D of the upper electrode UE2 is the same as the deposition direction D of the upper electrode UE1. Therefore, the upper electrode UE2 contacts the bottom layer 63 having the length Lb in the subpixel SP2 with almost no damage. This makes it possible to suppress poor connection between the upper electrode UE2 and the partition wall 6. Therefore, deterioration in reliability can be suppressed compared to when the deposition direction of the upper electrode UE2 is opposite to that of the upper electrode UE1.

[0122] In the subpixel SP3, when the sealing layers SE1 and SE2 are removed by dry etching, the same portion of the bottom layer 63 is likely to be damaged, and may recede further than the bottom layer 63 in the subpixel SP2. However, even in such a subpixel SP3, when the stacked film FL3 is subsequently formed, the deposition direction D of the upper electrode UE3 is the same as the deposition direction D of the upper electrodes UE1 and UE2. Therefore, the upper electrode UE3 contacts the bottom layer 63, which is hardly damaged in the subpixel SP3. This makes it possible to suppress poor connection between the upper electrode UE3 and the partition wall 6. Therefore, it is possible to suppress a decrease in reliability compared to when the deposition direction of the upper electrode UE3 is opposite to the deposition direction of the upper electrodes UE1 and UE2.

[0123] Next, another configuration example will be described.

[0124] FIG. 17 is a diagram showing another example of the layout of the subpixels SP1, SP2, and SP3.

[0125] 17 differs from the example shown in Fig. 7 in that, in plan view, some electrode edges of the lower electrodes do not overlap the partition walls 6. The deposition directions D when forming the upper electrodes UE1, UE2, and UE3 are all substantially parallel to the second direction Y.

[0126] In the illustrated example, the lower electrode LE1 has an electrode end LE1A on the side where the end P1 of the organic layer OR1 is located, and an electrode end LE1B on the side where the end P2 is located. The electrode end LE1A is located upstream in the deposition direction D, and the electrode end LE1B is located downstream in the deposition direction D. The partition wall 6 does not overlap the electrode end LE1A, but overlaps the electrode end LE1B.

[0127] To reliably electrically connect the upper electrode UE1 and the partition wall 6, it is important to prevent breakage of the upper electrode UE1 due to steps in the inorganic insulating layer 5 covering the lower electrode LE1. Therefore, on the downstream side in the deposition direction D, the electrode end LE1B of the lower electrode LE1 overlaps the partition wall 6, thereby preventing the formation of undesired steps in the inorganic insulating layer 5 and preventing breakage of the upper electrode UE1.

[0128] On the other hand, on the upstream side in the deposition direction D, there is no restriction that the upper electrode UE1 and the partition wall 6 must be securely connected. Therefore, on the upstream side in the deposition direction D, the electrode end LE1A of the lower electrode LE1 does not necessarily have to overlap the partition wall 6. Therefore, compared to the case where the electrode end and the partition wall 6 overlap over the entire periphery of the lower electrode LE1, the width of a part of the partition wall 6 can be reduced, and further, the opening AP1 can be enlarged. Therefore, the light-emitting surface of the subpixel SP1 can be enlarged.

[0129] Furthermore, in the illustrated example, also in the lower electrode LE3 of the subpixel SP3, the electrode end located on the upstream side in the deposition direction D does not overlap with the partition wall 6, and the electrode end located on the downstream side in the deposition direction D overlaps with the partition wall 6. Therefore, similar to the subpixel SP1, the upper electrode UE3 and the partition wall 6 can be reliably electrically connected, and the light-emitting area of ​​the subpixel SP3 can be increased.

[0130] FIG. 18 is a diagram showing another example of the layout of the subpixels SP1, SP2, and SP3.

[0131] The example shown in FIG. 18 differs from the example shown in FIG. 17 in that the vapor deposition direction D when forming the upper electrodes UE1, UE2, and UE3 is substantially parallel to the first direction X.

[0132] In the lower electrode LE1 of the subpixel SP1, the electrode end LE1A located on the upstream side in the deposition direction D does not overlap with the partition wall 6, and the electrode end LE1B located on the downstream side in the deposition direction D overlaps with the partition wall 6. This ensures reliable electrical connection between the upper electrode UE1 and the partition wall 6, and also increases the light-emitting area of ​​the subpixel SP1.

[0133] Furthermore, in the illustrated example, in the lower electrode LE2 of the subpixel SP2, the electrode end located on the upstream side in the deposition direction D does not overlap with the partition wall 6, and the electrode end located on the downstream side in the deposition direction D overlaps with the partition wall 6. Therefore, similar to the subpixel SP1, the upper electrode UE2 and the partition wall 6 can be reliably electrically connected, and the light-emitting area of ​​the subpixel SP2 can be increased.

[0134] Furthermore, in the lower electrode LE3 of the subpixel SP3, the electrode end located on the upstream side in the deposition direction D does not overlap with the partition wall 6, and the electrode end located on the downstream side in the deposition direction D overlaps with the partition wall 6. Therefore, similar to the subpixel SP1, the upper electrode UE3 and the partition wall 6 can be reliably electrically connected, and the light-emitting area of ​​the subpixel SP3 can be increased.

[0135] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a manufacturing method thereof.

[0136] All display devices and manufacturing methods thereof that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices and manufacturing methods thereof described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0137] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0138] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0139] DSP…display device 10…board 5...Inorganic insulating layer AP1, AP2, AP3...Openings 6...Partition wall 61...Lower part 62...Upper part 63...Bottom layer 64...Axial layer SP1, SP2, SP3...subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3...lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer CP1, CP2, CP3...cap layer SE1, SE2, SE3...Sealing layer DA: Display area SA: Surrounding area SUB...Processing substrate EV...evaporation equipment 110...evaporation source

Claims

1. A substrate; a first lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral portion of the first lower electrode; a partition wall having a conductive lower portion disposed on the inorganic insulating layer and an upper portion disposed on the lower portion; a first organic layer disposed on the first lower electrode and including a first light-emitting layer; a first upper electrode disposed on the first organic layer and in contact with the lower portion of the partition wall; the partition wall surrounds the first organic layer and the first upper electrode; The lower portion has a bottom layer disposed on the inorganic insulating layer and an axial layer disposed between the bottom layer and the upper portion, The bottom layer and the top layer protrude from the side of the shaft layer, the first organic layer has a first end overlying the bottom layer and a second end overlying the bottom layer opposite the first end; a first length of the bottom layer overlapping the first end portion protruding from the shaft layer is different from a second length of the bottom layer overlapping the second end portion protruding from the shaft layer; Display device.

2. the second length is greater than the first length; a second thickness of the first upper electrode directly above the second end portion is greater than a first thickness of the first upper electrode directly above the first end portion; The display device according to claim 1 .

3. moreover, a second lower electrode having a periphery covered with the inorganic insulating layer; a second organic layer disposed on the second lower electrode and including a second light-emitting layer formed of a material different from that of the first light-emitting layer; a second upper electrode disposed on the second organic layer and in contact with the lower portion of the partition wall; the partition wall surrounds the second organic layer and the second upper electrode; the second organic layer has a third end overlying the bottom layer and a fourth end overlying the bottom layer opposite the third end; a difference between a third length of the bottom layer overlapping the third end portion and projecting from the shaft layer and a fourth length of the bottom layer overlapping the fourth end portion and projecting from the shaft layer is different from a difference between the first length and the second length; The display device according to claim 1 .

4. the first lower electrode has a first electrode end on a side where the first end is located and a second electrode end on a side where the second end is located; the partition wall overlaps the first electrode end and the second electrode end; The display device according to claim 1 .

5. the first lower electrode has a first electrode end on a side where the first end is located and a second electrode end on a side where the second end is located; the partition wall does not overlap the first electrode end but overlaps the second electrode end; The display device according to claim 1 .

6. moreover, a first cap layer disposed on the first upper electrode; a first sealing layer that covers the first cap layer and the partition wall and is made of an inorganic insulating material; The display device according to claim 1 .

7. A substrate; a first lower electrode and a second lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral portion of each of the first lower electrode and the second lower electrode; a partition wall having a conductive lower portion disposed on the inorganic insulating layer and an upper portion disposed on the lower portion; a first organic layer disposed on the first lower electrode and including a first light-emitting layer; a first upper electrode disposed on the first organic layer and in contact with the lower portion of the partition wall; a second organic layer disposed on the second lower electrode and including a second light-emitting layer formed of a material different from that of the first light-emitting layer; a second upper electrode disposed on the second organic layer and in contact with the lower portion of the partition wall; the partition wall surrounds the first organic layer, the first upper electrode, the second organic layer, and the second upper electrode; The lower portion has a bottom layer disposed on the inorganic insulating layer and an axial layer disposed between the bottom layer and the upper portion, The bottom layer and the top layer protrude from the side of the shaft layer, the first organic layer has a first end overlying the bottom layer and a second end overlying the bottom layer opposite the first end; the second organic layer has a third end portion located on the opposite side of the partition wall from the second end portion and overlapping the bottom layer, and a fourth end portion located on the opposite side of the partition wall from the third end portion and overlapping the bottom layer, a second thickness of the first upper electrode directly above the second end portion is greater than a first thickness of the first upper electrode directly above the first end portion; a fourth thickness of the second upper electrode immediately above the fourth end portion is greater than a third thickness of the second upper electrode immediately above the third end portion; Display device.

8. The second thickness is greater than the third thickness. The display device according to claim 7 .

9. a second length of the bottom layer overlapping the second end portion protruding from the shaft layer that is greater than a first length of the bottom layer overlapping the first end portion protruding from the shaft layer; The display device according to claim 7 .

10. a fourth length of the bottom layer overlapping the fourth end portion protruding from the shaft layer that is greater than a third length of the bottom layer overlapping the third end portion protruding from the shaft layer that is greater than a fourth length of the bottom layer overlapping the third end portion protruding from the shaft layer that is greater than a third length of the bottom layer overlapping the third end portion. The display device according to claim 9 .

11. The second length is greater than the third length. The display device according to claim 10.

12. moreover, a first cap layer disposed on the first upper electrode; a first sealing layer that covers the first cap layer and the partition wall and is made of an inorganic insulating material; a second cap layer disposed on the second upper electrode; a second sealing layer that covers the second cap layer and the partition wall and is made of an inorganic insulating material; The first sealing layer is spaced apart from the second sealing layer on the partition wall. The display device according to claim 7 .

13. a processing substrate is prepared on which a first lower electrode, a second lower electrode, a third lower electrode, an inorganic insulating layer covering peripheral edges of the first lower electrode, the second lower electrode, and the third lower electrode, and a partition wall including a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion are formed above a substrate; forming a first laminated film on the first lower electrode, the first laminated film including a first organic layer including a first light-emitting layer, and a first upper electrode located on the first organic layer; forming a second stacked film on the second lower electrode, the second stacked film including a second organic layer including a second light-emitting layer different from the first light-emitting layer, and a second upper electrode located on the second organic layer; forming a third stacked film on the third lower electrode, the third stacked film including a third organic layer including a third light-emitting layer different from the first light-emitting layer and the second light-emitting layer, and a third upper electrode located on the third organic layer; each of the first upper electrode, the second upper electrode, and the third upper electrode is formed by emitting a conductive material from a vapor deposition source tilted with respect to a normal line of the processing substrate, and depositing the conductive material using the partition wall as a mask while changing a relative position between the vapor deposition source and the processing substrate; The first upper electrode, the second upper electrode, and the third upper electrode are formed in the same deposition direction. A method for manufacturing a display device.

14. moreover, After forming the first laminated film, a first sealing layer is formed on the first laminated film using an inorganic insulating material; forming a resist patterned into a predetermined shape on the first sealing layer; using the resist as a mask, sequentially removing the first sealing layer and the first stacked film; Thereafter, the second laminated film is formed. The method for manufacturing a display device according to claim 13 .

15. When forming each of the first upper electrode, the second upper electrode, and the third upper electrode, changing the relative position by transporting the processing substrate with respect to the fixed deposition source; The method for manufacturing a display device according to claim 13 .

16. When forming each of the first upper electrode, the second upper electrode, and the third upper electrode, changing the relative position by moving the deposition source with respect to the fixed processing substrate; The method for manufacturing a display device according to claim 13 .

17. When forming each of the first upper electrode, the second upper electrode, and the third upper electrode, the relative positions are changed by moving the deposition source while transporting the processing substrate; The method for manufacturing a display device according to claim 13 .

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