Semiconductor device and power conversion device

Abstract

To provide a semiconductor device and a power conversion device which enable thinning and downsizing of a contour package, and achieve reduction, downsizing and higher capacity of a heat resistance of the semiconductor device.SOLUTION: A semiconductor device 200 includes: a control IC chip 22 for controlling a MOSFET 3 for power conversion; a first package 1 having a single capacitor 21 for supplying power to the control IC chip 22; the MOSFET 3 which is outside of the first package 1, and is turned ON / OFF by receiving a control signal from the control IC chip 22; and a second package 2 which has wirings (lead frame 4, wiring 5, source electrode wiring 6 and gate electrode wiring 7) for electrically connecting the control IC chip 22 in the first package 1 and electrodes of the MOSFET 3, and seals the first package 1, the MOSFET 3 and the wirings with a mold resin 33.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a power conversion device. [Background technology]

[0002] Semiconductor devices that use multiple semiconductor elements, such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), and freewheel diodes, mounted on a single module, are used for power control and motor control in industrial equipment, electric railway vehicles, automobiles, home appliances, and other devices.

[0003] To drive MOSFETs for power conversion, a circuit to control on / off and its power supply are required. To support large conversion capacities, the MOSFET chips also become larger, requiring large-capacity capacitors that are difficult to integrate into ICs for power supplies. However, when mounting these in an integrated package to reduce size and improve performance, it is difficult to mount the capacitors with the existing pin arrangement. This is because the positive terminal of the lead frame that mounts the capacitor is exposed from the mounting package. To avoid this, a package that further covers the entire circuit from the outside is required.

[0004] Examples of such techniques include those disclosed in Patent Documents 1 and 2. In Patent Document 1, a single capacitor, a MOSFET, and an IC are integrally mounted in a single package, and this package is then mounted in an external package. In other words, the entire circuit is once mounted in a package, and this is then further packaged twice. In Patent Document 2, a single capacitor, a MOSFET, and an IC are integrally mounted in a single package. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2017-98276 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-116053 Summary of the Invention [Problem to be solved by the invention]

[0006] In the devices described in Patent Documents 1 and 2, the entire circuit consisting of a single capacitor, MOSFET, and IC is packaged once. In the device described in Patent Document 1, this is packaged twice. This inevitably results in a larger external package, making it difficult to reduce the size and thickness of the device, and also presents challenges such as making it difficult to improve power conversion capacity due to reduced heat dissipation.

[0007] The present invention has been made in consideration of the above circumstances, and aims to provide a semiconductor device and a power conversion device that enable the external package to be made thinner and smaller, and that realizes reduced thermal resistance, miniaturization, and increased capacity of the semiconductor device. [Means for solving the problem]

[0008] In order to solve the above problems, the semiconductor device of the present invention is a semiconductor device for power conversion, comprising: a first package having a control IC chip that controls a MOSFET element for power conversion and a standalone capacitor that supplies power to the control IC chip; the MOSFET element that is located outside the first package and turns on and off in response to a control signal from the control IC chip; and a second package that has wiring that electrically connects the control IC chip in the first package to electrodes of the MOSFET element, and in which the control IC chip, the MOSFET element, and the wiring are sealed with a molding member. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device and a power conversion device that can reduce the thickness and size of the external package, and that can achieve reduced thermal resistance, miniaturization, and increased capacity of the semiconductor device. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment of the present invention. [Figure 2] 1 is a side view of a semiconductor device according to a first embodiment of the present invention. [Figure 3] 1 is a plan view showing a configuration of a first package of a semiconductor device according to a first embodiment of the present invention. [Figure 4] FIG. 4 is a side view of FIG. 3. [Figure 5] 1 is a circuit diagram of a control IC chip of a semiconductor device according to a first embodiment of the present invention. [Figure 6] FIG. 10 is a side view showing the configuration of a first package of a semiconductor device according to a second embodiment of the present invention. [Figure 7] This is an example of an autonomous synchronous rectification half-bridge power conversion device configured using the first package of FIG. [Figure 8] FIG. 8 is a circuit diagram of the autonomous synchronous rectification half-bridge power conversion device of FIG. 7. [Figure 9] FIG. 10 is a side view showing the configuration of a first package of a semiconductor device according to a third embodiment of the present invention. [Figure 10] FIG. 10 is a side view showing the configuration of a first package of a semiconductor device according to a fourth embodiment of the present invention. [Figure 11] FIG. 10 is a side view showing the configuration of a semiconductor device including a first package according to a fifth embodiment of the present invention. [Figure 12] FIG. 13 is a side view showing the configuration of a first package of a semiconductor device according to a sixth embodiment of the present invention. [Figure 13] FIG. 1 is a diagram showing the relationship between the gate voltage normalized by the threshold voltage of the MOSFET and the resistance (au) of the MOSFET when it is on. [Figure 14]13 is an example in which an autonomous synchronous rectification full-bridge power conversion device is configured using the first package of the semiconductor device according to the seventh embodiment of the present invention. [Figure 15] FIG. 15 is a circuit diagram of the autonomous synchronous rectification full-bridge power conversion device of FIG. [Figure 16] 13 is an example in which an autonomous synchronous rectification full-bridge power conversion device is configured using the first package of the semiconductor device according to the eighth embodiment of the present invention. [Figure 17] 17 is a side view showing the configuration of a first package 1 of the semiconductor device of FIG. 16. FIG. [Figure 18] FIG. 10 is a block diagram showing a circuit configuration of a power conversion device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (First embodiment) A semiconductor device according to a first embodiment of the present invention will be described. In this embodiment, a vertical Nch MOSFET will be used as an example of a power conversion element, but other MOS gate-driven transistors such as IGBTs and other power transistors may also be used.

[0012] Fig. 1 is a diagram showing the configuration of a semiconductor device 200 according to a first embodiment, and is a plan view (top perspective view) of the semiconductor device 200 as seen from above. Fig. 2 is a side view (side perspective view) of Fig. 1. In each drawing, the same components or components having similar functions are denoted by the same reference numerals, and detailed descriptions of overlapping parts will be omitted. It should also be noted that in the plan view of Figure 1, the layout of components on lower layers, which are not visible due to the presence of components on upper layers, is shown, for convenience, as if the components on the upper layers were visible through the view.

[0013] As shown in FIG. 1, the semiconductor device 200 is a semiconductor device for power conversion, and includes a package 1 (hereinafter referred to as the first package 1) that mounts a control IC chip and a single capacitor, an outer package 2 (hereinafter referred to as the second package 2), a MOSFET 3 (a MOSFET element for power conversion), a lead frame 4, wiring 5, a source electrode wiring 6 (wiring that connects the first package 1 and the MOSFET 3), a gate electrode wiring 7 (wiring that connects the first package 1 and the MOSFET 2), a molded resin 8 (molded member) (FIG. 2), and solders 9, 10, 11, 12, and 13 (FIG. 2).

[0014] The first package 1 has a control IC chip 22 that controls the rectifying MOSFET 3, and a single capacitor 21 that supplies power to the control IC chip 22 and the MOSFET 3.

[0015] The MOSFET 3 is located outside the first package 1 and turns on and off in response to a control signal from a control IC chip 22 inside the first package 1 .

[0016] The second package 2 has wiring (lead frame 4, wiring 5, source electrode wiring 6, gate electrode wiring 7) that electrically connects the control IC chip 22 (see Figures 3 and 4 below) in the first package 1 to the electrodes of the MOSFET 3, and is formed by sealing the control IC chip 22, the MOSFET 3, and the wiring 4 to 7 with mold resin 8.

[0017] In the semiconductor device 200, the drain electrode on the back surface of the MOSFET 3 and the first package 1 are connected to the lead frame 4 with solders 9 and 13. In the semiconductor device 200, the source electrode and gate electrode of the MOSFET 3 are connected to a source electrode wiring 6 and a gate electrode wiring 7 via a bonding material such as solder, and the source electrode wiring 6 and the gate electrode wiring 7 are further connected to a control IC chip 22 (a control circuit IC) (see later-described FIGS. 3 and 4) mounted inside the first package 1 via a bonding material such as solder.

[0018] In the semiconductor device 200, the drain electrode of the MOSFET 3 is output from the outer package 2 to the outside via the lead frame 4, and the source electrode of the MOSFET 3 is output from the second package 2 to the outside via a clip and a lead frame 5 to which the clip is connected. The drain electrode and source electrode of the MOSFET 3 correspond to the control of the power supply of the semiconductor device 200.

[0019] The control IC chip 22 is connected to the source electrode (terminal), gate electrode (terminal), and drain electrode (terminal) of the MOSFET 3, and can control the on / off of the MOSFET 3 using a single capacitor 21 (see Figures 3 and 4 below) in the same package as a power source depending on the state of the MOSFET 3.

[0020] Thus, the semiconductor device 200 comprises a first package 1 containing a control IC chip 22 that constitutes a circuit for driving the MOSFET 3 and a standalone capacitor 21 (see Figures 3 and 4 below) that supplies power to the control IC chip 22; a MOSFET 3 that is located outside the first package 1 and turns on and off in response to a control signal from the control IC chip 22; and a second package 2 that has a source electrode wiring 6 and a gate electrode wiring 7 (wiring that connects the first package 1 and the MOSFET 2) that connect the first package 1 and the MOSFET 2, and that seals the control IC chip 22, the MOSFET 3, the wiring 6, 7, etc. with molded resin 8.

[0021] The semiconductor device 200 accommodates a control IC chip 22 (see FIGS. 3 and 4 described below) and a standalone capacitor 21 (see FIGS. 3 and 4 described below) in a first package 1, and the control IC chip 22 in the first package 1 receives power supply from the standalone capacitor 21 and autonomously controls the power of a MOSFET 3 arranged outside the first package 1. This enables the semiconductor device 200 to autonomously control the power of the MOSFET 3 without providing a control signal for the MOSFET 3 or an external power supply terminal.

[0022] Furthermore, in semiconductor device 200, wiring 5 (FIG. 1), which serves as the main wiring of the source electrode, is directly connected to MOSFET 3, which enables a reduction in wiring height and a reduction in thickness of second package 2, which is an outer package. This enables reduction in thermal resistance, miniaturization, and increase in capacity of semiconductor device 200, and further enables miniaturization, increase in capacity, and high efficiency of a power conversion device (FIG. 18) using the same.

[0023] <First package 1> FIG. 3 is a plan view (top perspective view) showing the configuration of the first package 1 of the semiconductor device 200 of the first embodiment, and FIG. 4 is a side view (side perspective view) of FIG. 3 and 4, semiconductor device 200 (FIG. 1) includes, in first package 1, single capacitor 21, control IC chip 22, lead frames 23, 24, 25, and 26, capacitor terminal (positive voltage side) 27, capacitor terminal (negative voltage side) 28, wiring 29, 30, 31, and 32 (wiring electrically connecting control IC chip 22 and electrodes of MOSFET 3), molded resin 33, and bonding materials 34, 35, and 36. First package 1 has a rectangular parallelepiped shape whose outline is formed by molded resin 33, and has a front surface (upper surface) 1a, a back surface 1b, and side surfaces 1c (FIG. 4). The wirings 29, 30, 31, and 32 may be wires or ribbons. The lead frame may also be referred to as a terminal. Because both the terminal and the lead frame are parts that connect to external wiring, they are referred to as lead frames without distinction. On the other hand, parts that extend from the element (parts of the element), such as capacitor terminals 27 and 28, are called "terminals."

[0024] The positive voltage side capacitor terminal 27 and the negative voltage side capacitor terminal 28 of the single capacitor 21 in the first package 1 are connected by a bonding material to the lead frames 23 and 24, respectively. The control IC chip 22 is connected to the lead frame 24 by a bonding material, and is connected to the lead frames 23, 24, 25, and 26 by wiring 29, 30, 31, and 32, respectively. These are sealed with molded resin 33. The ends of the lead frames 23, 24, 25, and 26 are exposed from the side (side surface 1c of the first package 1), back surface (back surface 1b of the first package 1), or front surface (front surface 1a of the first package 1) of the molded resin 33, allowing connection to an external circuit. Also, in FIGS. 3 and 4, the capacitor terminals 27 and 28 are exposed from the front surface (front surface 1a of the first package 1) of the molded resin 33. This allows the control IC chip 22 in the first package 1 to be connected to the MOSFET 3 in FIG. 1 or an external circuit (not shown) for electrical characteristic testing. In the following description, the drain electrode, source electrode, and gate electrode of a MOSFET may be abbreviated to simply "drain," "source," and "gate," respectively.

[0025] 3 and 4, capacitor terminal 28 (terminal connected to the drain, source, and gate electrodes of the MOSFET element) of single capacitor 21 in first package 1 is connected to the source of MOSFET 3, and lead frame 25 (terminal connected to the drain, source, and gate electrodes of the MOSFET element) is connected to the gate of MOSFET 3 with clips. Also, back surface 26b of lead frame 26 (terminal connected to the drain, source, and gate electrodes of the MOSFET element) is connected with solder to lead frame 4 (FIGS. 1 and 2) on which MOSFET 3 is mounted. This connects the gate, source, and drain of MOSFET 3 to control IC chip 22, enabling control of MOSFET 3.

[0026] By providing each terminal exposed on the front surface 1a or rear surface 1b of the first package 1 and connecting each terminal to each electrode of the MOSFET, the wiring between the MOSFET 3 can be simplified and made smaller. It is also possible to use the terminals exposed from the side surface 1c of the first package 1 for wiring.

[0027] <Control IC chip 22> FIG. 5 is a diagram showing an example of the circuit of the control IC chip 22 in which a MOSFET is driven by autonomous synchronous rectification. The control IC chip 22 includes a voltage conversion circuit 41 connected to a terminal connected to the drain of the MOSFET 3, a diode 42, a control determination circuit 43, and a drive circuit 44. The control IC chip 22 is housed in the first package 1 together with the single capacitor 21. The output of the voltage conversion circuit 41 of the control IC chip 22 is connected to the drain of the MOSFET 3, the output of the drive circuit 44 is connected to the gate of the MOSFET 3, and the capacitor terminal (negative voltage side) of the single capacitor 21 is connected to the source of the MOSFET 3 as a low-potential-side power supply for the control IC chip 22.

[0028] In the control IC chip 22, the unit capacitor 21 is charged when a positive voltage is applied to the drain of the MOSFET 3. The control IC chip 22 uses a self-supply power supply based on the voltage charged in the unit capacitor 21, and has a control determination circuit 43 determine the direction of the current in the MOSFET 3. In response to the result, a drive circuit 44 applies a voltage between the gate and source of the MOSFET 3, thereby controlling the on / off state of the MOSFET 3.

[0029] When a voltage is applied to the MOSFET 3, the unit capacitor 21 is charged by self-supplying from the drain voltage of the MOSFET 3, and when the MOSFET 3 is turned off, the charged charge is used as a power source to supply power to the load side (control IC chip 22 and MOSFET 3) (current flows back through the path passing through diode 42 in FIG. 5). In other words, the self-supply of the unit capacitor 21 is premised on the application of a positive voltage to the drain of the MOSFET 3, and therefore the terminal of the unit capacitor 21 is connected to the drain of the MOSFET 3 via the source of the MOSFET 3 and the control IC circuit.

[0030] The control IC chip 22 does not require an external control signal or power supply to the MOSFET 3, which is the control target, and can turn on the MOSFET 3 without an external command when the current flowing through the MOSFET 3 changes from source to drain. In other words, the control IC chip 22 can be used as a control IC for autonomous synchronous rectification that reduces the conduction loss of the MOSFET's built-in diode.

[0031] [Effects of the first embodiment] A semiconductor device 200 (FIGS. 1 and 2) according to a first embodiment of the present invention comprises: a first package 1 having a control IC chip 22 that controls a rectifying MOSFET 3 and a standalone capacitor 21 that supplies power to the control IC chip 22; a MOSFET 3 that is located outside the first package 1 and turns on and off in response to a control signal from the control IC chip 22; and a second package 2 that has wiring (a lead frame 4, wiring 5, a source electrode wiring 6, and a gate electrode wiring 7) that electrically connects the control IC chip 22 and the electrodes of the MOSFET 3 within the first package 1, and that seals the control IC chip 22, the MOSFET 3, and these wirings with molded resin 33.

[0032] With this configuration, even when a large-capacity standalone capacitor 21 that is difficult to integrate is mounted, the standalone capacitor 21 can be housed in the first package 1, which does not include the MOSFET 3 and can be made smaller. Furthermore, the control IC chip 22 and standalone capacitor 21 in the first package 1 are connected to the MOSFET 3 outside the first package 1 via wiring (lead frame 4, wiring 5, source electrode wiring 6, and gate electrode wiring 7), and these are sealed with molded resin 33 to form the second package 2. This prevents the positive terminal of the lead frame carrying the standalone capacitor 21 from being exposed from the mounting package (second package 2), allowing it to be mounted using the existing pin arrangement. Furthermore, this eliminates the need for a package configuration that is large, difficult to miniaturize, and has limited flexibility, as in Patent Documents 1 and 2, where the entire circuit consisting of the MOSFET 3, control IC chip 22, and standalone capacitor 21 is externally covered.

[0033] As a result, in this embodiment, even when a large-capacity single capacitor 21 or a large-scale MOSFET 3 is mounted, the second package 2, which is the outer package, can be made thinner and smaller, and the thermal resistance of the semiconductor device can be reduced, made smaller, and the capacity can be increased.Furthermore, a power conversion device using this can be made smaller, have a larger capacity, and be more efficient.

[0034] In particular, according to this embodiment, the control IC chip 22 for controlling the drive of the MOSFET 3 and the individual capacitor 21 for self-supplying power are housed in the first package 1. The first package 1 and the MOSFET 3 arranged outside it are connected by wiring and sealed with molded resin 33 to form the second package 2. This not only reduces the thermal resistance, miniaturizes, and increases the capacity of the semiconductor device, but also significantly improves the flexibility in the layout and shape of the wiring of the first package 1, MOSFET 3, lead frame, etc. in the second package 2. This improved flexibility in layout and shape has the effect of leading to easier implementation and greater versatility when mounting the semiconductor device. Furthermore, by improving the layout and shape, it is expected that the thickness of the external package (second package 2) can be further reduced.

[0035] Furthermore, in the semiconductor device 200, the control IC chip 22 in the first package 1 receives power supply from the standalone capacitor 21 and autonomously controls the power of the MOSFET 3 arranged outside the first package 1. This allows the semiconductor device 200 to autonomously control the power of the MOSFET 3 without providing a control signal for the MOSFET 3 or an external power supply terminal.

[0036] In addition, in this embodiment, in the first package 1 (Figures 3 and 4), the capacitor terminal 27 (one terminal) on the positive voltage side of the single capacitor 21 is connected to the source electrode of the MOSFET 3, and the capacitor terminal 28 (the other terminal) on the negative voltage side of the single capacitor 21 is connected to the drain electrode of the MOSFET 3 via the circuit of the control IC chip 22.

[0037] With this configuration, the gate, source, and drain of the MOSFET 3 are connected to the control IC chip 22, making it possible to control the MOSFET 3.

[0038] In addition, in this embodiment, the first package 1 (FIGS. 3 and 4) has terminals connected to the drain electrode, source electrode, and gate electrode of the MOSFET 3, and the terminals are formed on the front surface (first main surface) or back surface (second main surface) of the control IC chip 22 in the first package 1. 3 and 4, capacitor terminal 28 of single capacitor 21 in first package 1 is connected to the source of MOSFET 3, and lead frame 25 is connected to the gate of MOSFET 3 with clips. These terminals are formed on the front surface (first main surface) of control IC chip 22 in first package 1. In addition, back surface 26b of lead frame 26 is connected by solder to lead frame 4 (FIGS. 1 and 2) on which MOSFET 3 is mounted. The terminal connected to back surface 26b of lead frame 26 is formed on the back surface (second main surface) of control IC chip 22 in first package 1. With this configuration, the source and gate of MOSFET 3 are connected to the front surface (first main surface) of control IC chip 22, and the drain of MOSFET 3 is connected to the back surface (second main surface) via back surface 26b of lead frame 26, making it possible to control MOSFET 3.

[0039] (Second embodiment) 6 is a side view (side perspective view) showing the configuration of the first package 1 of the semiconductor device of the second embodiment. The same components as those in FIG. 4 are denoted by the same reference numerals. The first package 1 shown in FIG. 6 can be used in place of the first package 1 of the semiconductor device 200 shown in FIG. In the second embodiment, the first package 1 has terminals 24, 25, and 26 (see Figure 6 for terminals 24 and 26, and Figure 7 for terminal 25) that extend to the outside from the side surface 1c and are connected to the MIOSFETs 51 and 52 (see Figure 7) that it drives.

[0040] Because the terminals 24, 25, and 26 protrude from the side surface 1c, the first package 1 and its terminals 24, 25, and 26 can be manufactured flat. This simplifies the processing steps because it is no longer necessary to bend the terminals 24, 25, and 26 or the lead frame connected to these terminals 24, 25, and 26. However, a configuration in which any of the terminals 24, 25, and 26 protrude from the side surface 1c imposes mounting restrictions on the placement of the first package 1.

[0041] FIG. 7 shows an example in which an autonomous synchronous rectification half-bridge power conversion device (semiconductor device) is configured using the first package 1 of FIG. As shown in FIG. 7, the semiconductor device 200A is an autonomous synchronous rectification half-bridge power conversion device, and includes two first packages 1, a second package 2, MOSFETs 51 and 52 (rectifying MOSFET elements), lead frames 55, 56, and 57 (first lead frames that mount the MOSFET elements and the first packages), wiring 58, 59, 60, and 61, and source electrode wiring 6 (wiring that connects the first packages and the MOSFET elements).

[0042] FIG. 8 is a circuit diagram of the autonomous synchronous rectification half-bridge power conversion device (semiconductor device 200A) of FIG. In the circuit configuration of the semiconductor device 200A shown in FIG. 8, the input of a voltage conversion circuit (not shown, see FIG. 5) of a control IC chip (not shown, see FIG. 5) in the first package 1 is connected to the drains of MOSFETs 51 and 52, the output of a drive circuit 44 is connected to the gates of MOSFETs 51 and 52, and the capacitor terminal (negative voltage side) of a standalone capacitor (not shown, see FIG. 5) is connected to the sources of MOSFETs 51 and 52 as a low-potential power supply for the control IC chip. When a positive voltage is applied to the drains of MOSFETs 51 and 52 by the control IC chip, the standalone capacitor is charged. The control IC chip applies a voltage between the gate and source of MOSFETs 51 and 52 to turn MOSFETs 51 and 52 on and off.

[0043] [Effects of the second embodiment] In this embodiment, the second package 2 (Figure 7) has first lead frames 55, 56, and 57 on which the MOSFETs 51 and 52 and the first package 1 are mounted, and the terminals of the first package 1 are connected to the drain electrodes or source electrodes of the MOSFETs 51 and 52 by the first lead frames 55, 56, and 57.

[0044] Such a mounting structure makes it possible to reduce the amount of wiring material connecting the first package 1 to the MOSFETs 51 and 52. Furthermore, the mounting process can be simplified by making it easier to fill the mold resin under the first package 1, and it becomes possible to provide a semiconductor device 200A that is smaller in size and easier to assemble.

[0045] (Third embodiment) 9 is a side view (side perspective view) showing the configuration of the first package 1 of the semiconductor device of the third embodiment. The same components as those in FIG. 6 are denoted by the same reference numerals. The first package 1 shown in FIG. 9 can be used for the semiconductor device 200 shown in FIGS. 1 and 2 and the semiconductor device 200A shown in FIG. 7. As shown in FIG. 9, a single capacitor 21 is mounted on the outside (here, the top surface) of a first package 1. Terminals 23 and 24 (terminals to which the drain electrode, source electrode, and gate electrode of a MOSFET element are connected) made of a lead frame are exposed on the top surface (surface 1a) of the first package 1, and a positive voltage side capacitor terminal 27 and a negative voltage side capacitor terminal 28 of the single capacitor 21 are connected to these terminals 23 and 24 via bonding materials 36 and 35. Although not shown, terminal 24 is exposed at multiple locations on the surface so that it can be bonded to wiring, one of which is connected to the negative voltage side capacitor terminal 28 of the single capacitor 21, and the others are connected to the source of the MOSFET (not shown). An example of mounting the first package 1 on a MOSFET is shown in FIG. 11, which will be described later.

[0046] [Effects of the third embodiment] In the semiconductor device of this embodiment (FIG. 9), the first package 1 includes lead frames 23, 24, and 25 (terminal 25 is not shown in FIG. 9) to which the drain electrode, source electrode, and gate electrode of the MOSFET 3 (FIGS. 1 and 2) are connected, and at least one of the terminals (terminals 23 and 24 in FIG. 9) is formed in the side direction of the first package 1.

[0047] This configuration makes it possible to reduce the amount of wiring material connecting the first package 1 to the MOSFET 3. In addition, the mounting process can be simplified by making it easier to fill the mold resin under the first package 1, making it possible to provide a semiconductor device that is smaller in size and easier to assemble.

[0048] Furthermore, in the semiconductor device of this embodiment (FIG. 9), the first package 1 has terminals 23, 24 (fourth lead frame) that connect the control IC chip 22 and the single capacitor 21, and portions of the terminals 23, 24 are exposed from the front surface 1a or the back surface 1b (front surface 1a in this embodiment) of the first package 1 as bonding materials 36, 35, and a positive voltage side capacitor terminal 27 and a negative voltage side capacitor terminal 28 of the single capacitor 21 are connected to the bonding materials 36, 35.

[0049] With this configuration, the single capacitor 21 is mounted outside the first package 1, which allows the first package 1 to be made thinner, thereby making it possible to reduce its size and simplify the assembly process.

[0050] (Fourth embodiment) Fig. 10 is a side view (side perspective view) showing the configuration of the first package 1 of the semiconductor device of the fourth embodiment. The same components as those in Fig. 9 are given the same reference numerals. The first package 1 shown in Fig. 10 can be used for the semiconductor device 200 shown in Figs. 1 and 2 and the semiconductor device 200A shown in Fig. 7. As shown in FIG. 10, the first package 1 has a single capacitor 21 mounted on the surface 1a of the first package 1, similar to the first package 1 of FIG. 10, lead frames 23, 24, and 25, to which a control IC 22 for a single capacitor 21 and wiring 31 for driving the gate of a MOSFET 3 (FIGS. 1 and 2) are connected, are exposed as terminals on the front surface 1a of the first package 1. The first package 1 is configured so that the lead frames 24 and 25 are connected to the source and gate of the MOSFET to be driven, respectively. The lead frame 26 is exposed on the back surface 1b of the first package 1 as an exposed portion 26b, and the exposed portion 26b is connected to the drain of the MOSFET 3 to be driven.

[0051] [Effects of the fourth embodiment] In the semiconductor device of this embodiment (FIG. 10), the first package 1 has terminals (referred to as lead frames in FIG. 10) 23, 24, and 25 to which the drain electrode, source electrode, and gate electrode of the MOSFET 3 (FIGS. 1 and 2) are connected, and at least one of the lead frames 23, 24, and 25 (lead frame 23, 24 in FIG. 10) is formed on the surface 1a side of the first package 1.

[0052] With this configuration, similar to the first package 1 in Figure 9, the single capacitor 21 is mounted outside the first package 1, which makes it possible to make the first package 1 thinner, thereby reducing its size and simplifying the assembly process.

[0053] (Fifth embodiment) Fig. 11 is a side view (side perspective view) showing the configuration of a semiconductor device 200B including a first package 1 according to the fifth embodiment. Fig. 11 shows an example of a structure in which the first package 1 is disposed on a MOSFET. The same components as those in Fig. 6 are denoted by the same reference numerals. In the semiconductor device 200B shown in FIG. In particular, when the MOSFET 3 is large in size, the first package 1 can be placed on top of the MOSFET 3 .

[0054] In semiconductor device 200B, lead frame 25 connected to the source of MOSFET 3 (second lead frame connected to the source electrode and gate electrode of the MOSFET element) and lead frame 24 connected to the gate of MOSFET 3 (second lead frame connected to the source electrode and gate electrode of the MOSFET element) are exposed from back surface 1b of first package 1, and exposed lead frames 25 and 24 are connected to the source and gate of MOSFET 3 with solder 61. Also, lead frame 26 connected to the drain of MOSFET 3 (third lead frame connected to the drain electrode of the MOSFET element) is exposed from side surface 1c of first package 1 and is connected to the drain of MOSFET 3 via lead frame 4.

[0055] [Effects of the fifth embodiment] In the semiconductor device of this embodiment (FIG. 11), the first package 1 includes lead frames 24 and 25 connected to the source and gate electrodes of the MOSFET 3, and a lead frame 26 connected to the drain electrode of the MOSFET 3. The second lead frame has a portion exposed from the back surface 1b of the first package 1 as an exposed portion, which is electrically joined to the source and gate electrodes of the MOSFET 3. The lead frame 26 is exposed from the side surface of the first package 1, connected to first lead frames 55, 56, and 57 (FIG. 7), and connected to the drain electrode of the MOSFET 3 via the first lead frames 55, 56, and 57 (FIG. 7).

[0056] With this configuration, the area required for mounting the first package 1 of the semiconductor device 200B is reduced, making it possible to miniaturize the package of the semiconductor device 200B and mount a larger MOSFET, thereby enabling the semiconductor device to have a larger capacity.

[0057] (Sixth embodiment) Fig. 12 is a side view (side perspective view) showing the configuration of the first package 1 of the semiconductor device of the sixth embodiment. The same components as those in Fig. 6 are given the same reference numerals. The first package 1 shown in Fig. 12 can be used for the semiconductor device 200 shown in Figs. 1 and 2, the semiconductor device 200A shown in Fig. 7, and the semiconductor device 200B shown in Fig. 11. As shown in FIG. 12, the first package 1 is placed vertically on the lead frame 24 so that the positive voltage side capacitor terminal 27 and the negative voltage side capacitor terminal 28 of the single capacitor 21 face the front surface 1a and the back surface 1b of the first package 1, respectively.

[0058] In the first package 1 shown in Figure 12, the positive voltage side capacitor terminal 27 and the negative voltage side capacitor terminal 28 of the single capacitor 21 are installed vertically on the lead frame 24, so that the single capacitor 21 is arranged parallel to the control IC chip 220.

[0059] [Effects of the sixth embodiment] The unit capacitor 21 is a thin unit capacitor (a planar and thin capacitor) such as a chip capacitor with capacitance formed on silicon. By using a thin unit capacitor 21, the first package 1 can be made thinner. This allows the thickness of the package of a semiconductor device using this first package 1 to be reduced. This makes it possible to miniaturize the semiconductor device and increase its capacitance by reducing thermal resistance. When using a thin capacitor, attention should be paid to the voltage applied to the unit capacitor (see Figure 13 below).

[0060] <Voltage applied to a single capacitor> The voltage applied to the single capacitor 21 will be described. The first package 1 of the semiconductor device according to the first to sixth embodiments is equipped with an IC and a unit capacitor 21. Therefore, knowledge about the voltage applied to the unit capacitor 21 is reflected in all of the semiconductor devices according to the first to sixth embodiments. Take the unit capacitor 21 (FIG. 12) in the first package 1 of the semiconductor device 200 according to the first embodiment as an example.

[0061] In the semiconductor devices 200, 200A, and 200B of the first to sixth embodiments, the voltage conversion circuit 41 of the control IC chip 22 shown in Fig. 5 generates a voltage to be applied to the single capacitor 21. In this case, the voltage conversion circuit 41 sets the voltage to be applied to the single capacitor 21 to be four times or less the threshold voltage of the MOSFET to be controlled.

[0062] FIG. 13 is a graph showing the relationship between the gate voltage normalized by the threshold voltage of the MOSFET and the resistance (au) of the MOSFET when it is on. The on-resistance of a MOSFET is the resistance between the drain and source when the MOSFET is turned on; the smaller this value, the less loss (power loss) occurs during operation. 13, the resistance of the MOSFET when it is on decreases as the gate voltage increases from the threshold voltage at which the MOSFET turns on, but the decrease saturates and can be made sufficiently low at about three times the threshold voltage. Therefore, by setting the voltage applied to the unit capacitor 21 to four times or less the threshold voltage of the MOSFET it controls, the voltage of this unit capacitor 21 is applied as the gate voltage of the MOSFET when it is on via the control IC, even taking into account the drop in capacitor voltage due to current consumption during circuit operation.

[0063] This results in a sufficiently low resistance when the MOSFET is on, resulting in a semiconductor device with low loss, while also enabling miniaturization by thinning the insulating film of the single capacitor 21, and realizing miniaturization and increased capacity of the semiconductor devices 200, 200A, and 200B using the single capacitor 21. The voltage applied to the single capacitor 21 varies depending on the MOSFET in question, but as an example, a voltage of 16 V or less can be considered.

[0064] The same applies to semiconductor devices 200C and 200D of the seventh and eighth embodiments described below, in which the voltage applied to the single capacitor 21 is four times or less the threshold voltage of the MOSFET to be controlled. This is also applicable not only to the first package 1 in the semiconductor device of each embodiment, but also to a package in which a MOSFET, a control IC chip, and a single capacitor are integrally mounted (for example, the device of Patent Document 2).

[0065] In the semiconductor device of each embodiment, the voltage applied to the unit capacitor 21 is set to four times or less the threshold voltage of the MOSFET to be controlled, thereby making it possible to reduce the size of the unit capacitor 21. This makes it possible to reduce the size and thickness of the first package 1 that mounts the unit capacitor 21, and thus makes it possible to reduce the size and increase the capacity of a semiconductor device that uses the first package 1.

[0066] Seventh embodiment 14 shows an example in which a single-phase autonomous synchronous rectification full-bridge power conversion device (semiconductor device) is configured using the first package 1 of the semiconductor device of the seventh embodiment. The same components as those in FIG. 7 are denoted by the same reference numerals. As shown in FIG. 14, the semiconductor device 200C is an autonomous synchronous rectification full-bridge power conversion device, and includes four first packages 1, a diode bridge 81 (second package), MOSFETs 86, 87, 88, 89 (rectifying MOSFET elements), lead frames 91, 92, 93, 94, gate electrode wirings 95, 96, 97, 98, source electrode wirings 99, 100, 101, 102 (wirings connecting the first packages 1 and the MOSFETs 86, 87, 88, 89), wirings 103, 104, 105, 106, molding resin 107, and an opening hole 108. 14 configures a diode bridge circuit using four combinations of MOSFETs and a first package 1. As described above, the first package 1 is a package that mounts a control IC chip 22 (e.g., FIG. 3) having an autonomous synchronous rectification control function and a single capacitor 21 (e.g., FIG. 3).

[0067] The four first packages 1 are connected via drain terminals on the back surfaces of lead frames 91, 92, 93, and 94 to which the drains of the MOSFETs 86, 87, 88, and 89 are connected, respectively. Furthermore, the four first packages 1 are connected to the MOSFETs 86, 87, 88, and 89 by gate electrode wirings 95, 96, 97, and 98 and source electrode wirings 99, 100, 101, and 102, respectively.

[0068] The semiconductor device 200C is entirely sealed with a mold resin 107 and forms a diode bridge 81 with an autonomous synchronous rectification function. In this case, the first package 1 is suitably the first package having the configuration shown in FIGS. 3 and 4.

[0069] FIG. 15 is a circuit diagram of the autonomous synchronous rectification full-bridge power conversion device (semiconductor device 200C) of FIG. In the circuit configuration of the semiconductor device 200C shown in FIG. 15, the output of a voltage conversion circuit (not shown, see FIG. 5) of a control IC chip (not shown, see FIG. 5) in the first package 1 is connected to the drain of the MOSFET 3, the output of a drive circuit 44 is connected to the gates of the MOSFETs 86, 87, 88, and 89, and the capacitor terminal (negative voltage side) of a standalone capacitor (not shown, see FIG. 5) is connected to the sources of the MOSFETs 86, 87, 88, and 89 as the low-potential power supply for the control IC chip. The control IC chip charges the standalone capacitor when a positive voltage is applied to the drains of the MOSFETs 86, 87, 88, and 89. The control IC chip applies a voltage between the gate and source of the MOSFETs 86, 87, 88, and 89 to turn the MOSFETs 86, 87, 88, and 89 on and off.

[0070] [Effects of the Seventh Embodiment] According to the semiconductor device 200C of this embodiment, it is possible to reduce the thickness of the diode bridge 81 that performs autonomous synchronous rectification, thereby enabling the semiconductor device to be made smaller, with reduced thermal resistance, and with increased capacity. If the diode bridge 81 having such effects is applied to a power conversion device (FIG. 18) that uses, for example, rectifying diodes for converting AC to DC from a commercial AC power source, it becomes possible to make this power conversion device smaller, with increased capacity, and more efficient.

[0071] Furthermore, the arrangement of the circuit that drives MOSFETs 86, 87, 88, and 89 within the external package (second package; diode bridge 81) can be changed to suit the shape of the wiring and the orientation of each component, which allows for greater freedom in the placement of openings for attaching cooling fins, thereby providing a semiconductor device with higher output and smaller size.

[0072] (Eighth embodiment) 16 shows an example in which an autonomous synchronous rectification full-bridge power conversion device (semiconductor device) is configured using the first package 1 of the semiconductor device of the eighth embodiment. The same components as those in FIG. 14 are denoted by the same reference numerals. As shown in FIG. 16, the semiconductor device 200D is an autonomous synchronous rectification full-bridge power conversion device, and includes four first packages 1 (see FIG. 17 below), a diode bridge 81 (second package), MOSFETs 86, 87, 88, 89 (rectifying MOSFET elements), lead frames 91, 92, 93, 94, gate electrode wirings 95, 96, 97, 98, source electrode wirings 99, 100, 101, 102 (wirings connecting the first packages 1 and the MOSFETs 86, 87, 88, 89), drain electrode wirings 112, 113, 114, 115, wirings 103, 104, 105, 106, molding resin 107, and an opening hole 108. The semiconductor device 200D shown in FIG. 16 configures a diode bridge circuit using four combinations of the first package 1 and MOSFETs.

[0073] The four first packages 1 are connected via drain terminals on the back surfaces of lead frames 91, 92, 93, and 94 to which the drains of the MOSFETs 86, 87, 88, and 89 are connected, respectively. Furthermore, the four first packages 1 are connected to the MOSFETs 86, 87, 88, and 89 by gate electrode wirings 95, 96, 97, and 98 and source electrode wirings 99, 100, 101, and 102, respectively.

[0074] The four first packages 1 are connected via source terminals on their back surfaces to lead frames 91, 92, 93, and 94 to which the sources of MOSFETs 86, 87, 88, and 89 are connected, respectively. Furthermore, the four first packages 1 are connected to MOSFETs 86, 87, 88, and 89T by respective gate electrode wirings 95, 96, 97, and 98. Furthermore, the lead frames 91, 92, 93, and 94 connected to the drains of MOSFETs 86, 87, 88, and 89 and the respective first packages 1 are connected to MOSFETs 86, 87, 88, and 89 by drain electrode wirings 112, 113, 114, and 115. The semiconductor device 200D is entirely sealed with a molding resin 107, and constitutes a diode bridge 81 having an autonomous synchronous rectification function. In this case, the first package 1 is suitably a package having a configuration shown in FIG.

[0075] Fig. 17 is a side view (side perspective view) showing the configuration of the first package 1 of the semiconductor device 200D of Fig. 16. The same components as those in Fig. 12 are denoted by the same reference numerals. In the first package 1 shown in FIG. 17, terminals 26 and 25 connected to the drains and gates of MOSFEs 86, 87, 88, and 89 (FIG. 16) are exposed from the front surface 1a of the first package 1, and terminal 24 connected to the sources of MOSFEs 86, 87, 88, and 89 is exposed from the back surface 1b of the first package 1.

[0076] [Effects of the Eighth Embodiment] According to the semiconductor device 200D of this embodiment, similar to the semiconductor device 200C of the seventh embodiment, it is possible to reduce the thickness of the diode bridge 81 that performs autonomous synchronous rectification, thereby enabling the semiconductor device to have a reduced thermal resistance, a smaller size, and a larger capacity. If the diode bridge 81 having such effects is applied to a power conversion device (FIG. 18), it is possible to reduce the size of the power conversion device, increase its capacity, and improve its efficiency.

[0077] (Ninth embodiment) A power conversion device according to a ninth embodiment of the present invention will be described. FIG. 18 is a block diagram showing a circuit configuration of a power conversion device according to a ninth embodiment of the present invention. FIG. 18 shows an example of a power conversion device 300 that converts power from an input AC power supply 301, such as a commercial power supply, to a DC output 302. The power conversion device 300 includes semiconductor devices 200, 200A to 200D, a power factor correction (PFC) circuit 310 that suppresses harmonic components and brings the power factor closer to 1, a smoothing capacitor 320, and a DC / DC conversion circuit 330. The semiconductor devices 200, 200A to 200D are, for example, diode bridges.

[0078] [Effects of the ninth embodiment] According to the power conversion device 300 of this embodiment, by applying the semiconductor devices 200, 200A, 200B, 200C, and 200D of the first to eighth embodiments to the power conversion device 300, it is possible to make the power conversion device 300 smaller, larger in capacity, and more efficient.

[0079] The present invention is not limited to the above-described embodiments, and includes other modifications and applications without departing from the spirit of the present invention as defined in the claims. For example, the above-described embodiments have been described in detail to facilitate understanding of the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. For example, the chip layout and wiring of the semiconductor elements that constitute the semiconductor devices 200, 200A, 200B, 200C, and 200D are not limited to the forms shown in the drawings.

[0080] The semiconductor element may be a MOSFET, a unipolar device such as a JFET (Junction Field Effect Transistor), or a bipolar device such as an IGBT. Depending on the device, the main terminal and sense terminal may be called the "collector" and "emitter" instead of the above-mentioned "drain" and "source." [Explanation of symbols]

[0081] 1 First package (package containing control IC chip and individual capacitor) 1a Surface of first package 1b Back of the first package 1c First package side 2 Second package (outer package) 3, 51, 52, 87-89 MOSFET (MOSFET elements for power conversion) 4 Lead frame (electrodes of the control IC chip and MOSFET element, as well as wiring that electrically connects them to the outside) 5. Wiring (wires that electrically connect the electrodes of the MOSFET element to the outside) 6. Source electrode wiring (wiring that electrically connects the control IC chip and the electrode of the MOSFET element) 7. Gate electrode wiring (wiring that electrically connects the control IC chip and the electrode of the MOSFET element) 8,33,107 Molding resin (molding material) 9, 10, 11, 12, 13, 34, 35, 36 Bonding materials (solder, conductive paste, etc.) 21 Single capacitor 22 Control IC chip 23 terminal (lead frame) (terminal to which the drain electrode, source electrode, and gate electrode of the MOSFET element are connected) (terminal 23 is the fourth lead frame in FIGS. 9 and 10) 24, 25 terminals (lead frame) (terminals to which the drain electrode, source electrode, and gate electrode of the MOSFET element are connected) (second lead frame connected to the source electrode and gate electrode of the MOSFET element) (terminal 24 is the fourth lead frame in Figures 9 and 10) 26 Lead frame (third lead frame connected to the drain electrode of the MOSFET element) 27 Positive voltage side capacitor terminal of a single capacitor (one terminal of a single capacitor) 28 The negative voltage side capacitor terminal of a single capacitor (the other terminal of the single capacitor, the terminal connected to the drain electrode, source electrode, and gate electrode of the MOSFET element) 55, 56, 57 Lead frame (first lead frame carrying a MOSFET element and a first package) 81 Diode Bridge (Second Package) 91,92,93,94 Lead frame 95, 96, 97, 98 Gate electrode wiring 99, 100, 101, 102 Source electrode wiring (wiring connecting the first package and the MOSFET element) 103, 104, 105, 106 Wiring 108 Opening hole 200, 200A, 200B, 200C, 200D Semiconductor devices 300 Power conversion device

Claims

1. A semiconductor device for power conversion, a first package having a control IC chip for controlling a MOSFET element for power conversion and a single capacitor for supplying power to the control IC chip; the MOSFET element, which is located outside the first package and turns on and off in response to a control signal from the control IC chip; a second package having wiring that electrically connects the control IC chip in the first package to electrodes of the MOSFET element, the second package being formed by sealing the control IC chip, the MOSFET element, and the wiring with a molding member. A semiconductor device characterized by:

2. In the first package, one terminal of the single capacitor is connected to the source electrode of the MOSFET element, and the other terminal of the single capacitor is connected to the drain electrode of the MOSFET element via a circuit of the control IC chip.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

3. the first package includes terminals connected to a drain electrode, a source electrode, and a gate electrode of the MOSFET element; The terminals are formed on the first main surface side or the second main surface side of the control IC chip in the first package.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

4. The second package includes a first lead frame that mounts the MOSFET element and the first package, and the terminal of the first package is connected to a drain electrode or a source electrode of the MOSFET element by the first lead frame.

4. The semiconductor device according to claim 3.

5. the first package includes terminals to which a drain electrode, a source electrode, and a gate electrode of the MOSFET element are connected; At least one of the terminals is formed in a side surface direction of the first package.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

6. the first package includes a second lead frame connected to a source electrode and a gate electrode of the MOSFET element, and a third lead frame connected to a drain electrode of the MOSFET element; a part of the second lead frame is exposed from the back surface of the first package as an exposed portion, and the exposed portion is electrically connected to a source electrode and a gate electrode of the MOSFET element; The third lead frame is exposed from a side surface of the first package and connected to the first lead frame, and is connected to the drain electrode of the MOSFET element via the first lead frame.

5. The semiconductor device according to claim 4.

7. The first package includes a fourth lead frame that connects the control IC chip and the single capacitor, and a portion of the fourth lead frame is exposed from the front or back surface of the first package as a terminal, and a terminal of the single capacitor is connected to the terminal.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

8. The voltage applied to the single capacitor is four times or less the threshold voltage of the MOSFET element.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

9. The first package and the MOSFET element form a rectifier bridge circuit with a synchronous rectification function.

9. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor substrate.

10. A power conversion device comprising the semiconductor device according to any one of claims 1 to 9.

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