Semiconductor memory device

Abstract

To provide a semiconductor memory device having a structure that can be easily manufactured.SOLUTION: The present invention provides a semiconductor memory device. In a first plane xy, wirings TG, SG, and CG and a first conductor 26 are arranged in a first direction Y, a first insulator 31 has a part surrounding a third wiring (CG) 24 and located between the third wiring and a second wiring (SG) 22. The first semiconductor 35 sandwiches a first insulator together with the third wiring, and a second insulator 36 is provided between the second wiring and the first semiconductor. A third insulator 32 surrounds a first conductor, and a second conductor 46 is in contact with the first semiconductor. A second semiconductor sandwiches the third insulator 32 with the first conductor, and is contacted with the second conductor. A fourth insulator 41 covers the second wiring, the first semiconductor, and the second wiring. The third semiconductor 42 is in contact with a first wiring (TG) 26, and includes a portion sandwiching the fourth insulator together with the second wiring and a portion sandwiching the fourth insulator together with the first semiconductor. The fourth semiconductor 44 is in contact with the third semiconductor and the third conductor 46, and sandwiches the fourth insulator together with the second semiconductor.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD Embodiments generally relate to semiconductor memory devices. [Background technology]

[0002] Semiconductor memory devices including memory cells arranged three-dimensionally are known. Examples of semiconductor memory devices include RAM (Random Access Memory). Examples of RAM memory cells include memory cells having a gain cell structure. The structure and manufacturing method of a memory device including memory cells arranged three-dimensionally and having a gain cell structure are complicated. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-159956 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a semiconductor memory device having a structure that can be manufactured more easily. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a first wiring, a second wiring, a third wiring, a first conductor, a first insulator, a first semiconductor, a second insulator, a third insulator, a second conductor, a second semiconductor, a fourth insulator, a third semiconductor, a fourth semiconductor, and a third conductor.

[0006] The first wiring extends along a first plane formed by a first axis and a second axis intersecting the first axis, and the first axis extends in a first direction. The second wiring extends along the first plane and is provided in the first direction from the first wiring. The third wiring extends along the first plane and is provided in the first direction from the second wiring. The first conductor extends along the first plane and is provided in the first direction from the second wiring. The first insulator surrounds the third wiring along the first plane and has a portion located between the third wiring and the second wiring. The first semiconductor sandwiches the first insulator together with the third wiring. The second insulator is located between the second wiring and the first semiconductor. The third insulator surrounds the first conductor along the first plane. The second conductor is in contact with the first semiconductor. The second semiconductor sandwiches the third insulator together with the first conductor and is in contact with the second conductor. The fourth insulator extends along the first plane over the second wiring, the first semiconductor, and the second semiconductor. The third semiconductor is in contact with the first wiring and includes a portion that sandwiches the fourth insulator together with the second wiring and a portion that sandwiches the fourth insulator together with the first semiconductor. The fourth semiconductor is in contact with the third semiconductor and sandwiches the fourth insulator together with the second semiconductor. The third conductor is in contact with the fourth semiconductor. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 shows functional blocks of a semiconductor memory device according to the first embodiment. [Figure 2] FIG. 2 shows the components of a memory cell of the semiconductor memory device of the first embodiment and the connections of the components. [Figure 3] FIG. 3 shows the structure of a part of the semiconductor memory device of the first embodiment along the xy plane. [Figure 4] FIG. 4 shows a cross-sectional structure of a part of the semiconductor memory device of the first embodiment. [Figure 5] FIG. 5 shows a cross-sectional structure of a part of the semiconductor memory device of the first embodiment. [Figure 6]FIG. 6 shows a cross-sectional structure of a part of the semiconductor memory device of the first embodiment. [Figure 7] FIG. 7 shows a cross-sectional structure of a part of the semiconductor memory device of the first embodiment. [Figure 8] FIG. 8 shows the structure of a part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 9] FIG. 9 shows the structure of a part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 10] FIG. 10 shows the structure of a part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 11] FIG. 11 shows the structure of a part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 12] FIG. 12 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 13] FIG. 13 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 14] FIG. 14 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 15] FIG. 15 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 16] FIG. 16 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 17] FIG. 17 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 18] FIG. 18 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 19] FIG. 19 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 20] FIG. 20 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 21] FIG. 21 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 22]FIG. 22 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 23] FIG. 23 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 24] FIG. 24 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 25] FIG. 25 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 26] FIG. 26 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 27] FIG. 27 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 28] FIG. 28 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 29] FIG. 29 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 30] FIG. 30 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 31] FIG. 31 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 32] FIG. 32 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 33] FIG. 33 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 34] FIG. 34 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 35] FIG. 35 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 36] FIG. 36 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 37] FIG. 37 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 38]FIG. 38 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 39] FIG. 39 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 40] FIG. 40 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 41] FIG. 41 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 42] FIG. 42 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 43] FIG. 43 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 44] FIG. 44 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 45] FIG. 45 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 46] FIG. 46 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 47] FIG. 47 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 48] FIG. 48 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 49] FIG. 49 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 50] FIG. 50 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 51] FIG. 51 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 52] FIG. 52 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 53] FIG. 53 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 54]FIG. 54 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 55] FIG. 55 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 56] FIG. 56 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 57] FIG. 57 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 58] FIG. 58 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 59] FIG. 59 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 60] FIG. 60 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 61] FIG. 61 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 62] FIG. 62 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 63] FIG. 63 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 64] FIG. 64 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 65] FIG. 65 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 66] FIG. 66 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 67] FIG. 67 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 68] FIG. 68 shows the structure of part of the semiconductor memory device of the first embodiment during the manufacturing process. [Figure 69] FIG. 69 shows the structure of a part of the semiconductor memory device according to the first modification of the first embodiment during the manufacturing process. [Figure 70]FIG. 70 shows the structure of a part of the semiconductor memory device of the first modified example of the first embodiment along the xy plane. [Figure 71] FIG. 71 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 72] FIG. 72 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 73] FIG. 73 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 74] FIG. 74 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 75] FIG. 75 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 76] FIG. 76 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 77] FIG. 77 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 78] FIG. 78 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 79] FIG. 79 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 80] FIG. 80 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 81] FIG. 81 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 82] FIG. 82 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 83] FIG. 83 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 84] FIG. 84 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 85] FIG. 85 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 86] FIG. 86 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 87] FIG. 87 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 88] FIG. 88 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 89] FIG. 89 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 90] FIG. 90 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 91] FIG. 91 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 92] FIG. 92 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. [Figure 93] FIG. 93 shows the structure of a part of the semiconductor memory device according to the second modification of the first embodiment during the manufacturing process. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. In some embodiments or different embodiments, a plurality of components having substantially the same functions and configurations may be distinguished from each other by adding an additional number or letter to the end of the reference numeral.

[0009] The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include portions in which the relationship and ratio of dimensions differ from one another.

[0010] Hereinafter, embodiments will be described using an xyz Cartesian coordinate system. The x-axis extends in the X direction. The y-axis extends in the Y direction. The z-axis extends in the Z direction. The positive direction of the vertical axis of the diagram may be referred to as the upper side, and the negative direction as the lower side. The positive direction of the horizontal axis of the diagram may be referred to as the right side, and the negative direction as the left side. Furthermore, the side with a larger coordinate on the z-axis may be referred to as the upper side, and the side with a smaller coordinate may be referred to as the lower side.

[0011] 1. First embodiment 1.1.Structure (composition) 1 shows functional blocks of a semiconductor memory device according to a first embodiment. The semiconductor memory device 1 is a device for storing data. As shown in FIG. 1, the semiconductor memory device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a voltage generation circuit 14, a row selection circuit 15, a column selection circuit 16, a write circuit 17, a read circuit 18, and a sense amplifier 19.

[0012] The memory cell array 11 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. Each memory cell MC can store one bit of data. Each memory cell MC is connected to one bit line BL and one word line WL. The memory cells MC are connected between the bit lines BL and a source line (not shown). The word lines WL are associated with rows. The bit lines BL are associated with columns. One memory cell MC is specified by selecting one row and one column.

[0013] The input / output circuit 12 is a circuit for inputting and outputting data and signals, and receives a control signal CNT, a command CMD, an address signal ADD, and data DAT from outside the semiconductor memory device 1.

[0014] The control circuit 13 is a circuit that controls the operation of the semiconductor memory device 1. The control circuit 13 receives a command CMD and a control signal CNT from the input / output circuit 12. The control circuit 13 controls the write circuit 17 and the read circuit 18 based on the control indicated by the command CMD and the control signal CNT.

[0015] The voltage generation circuit 14 is a circuit that generates various voltages used in the semiconductor memory device 1. The voltage generation circuit 14 generates a plurality of voltages of different magnitudes under the control of the control circuit 13. The voltage generation circuit 14 supplies the generated voltages to the memory cell array 11, the write circuit 17, the read circuit 18, and the sense amplifier 19.

[0016] The row selection circuit 15 is a circuit that selects a row of memory cells MC. The row selection circuit 15 receives an address signal ADD from the input / output circuit 12. The row selection circuit 15 uses the voltage received from the voltage generation circuit 14 to select one word line WL associated with the row specified by the received address signal ADD.

[0017] The column selection circuit 16 is a circuit that selects a column of memory cells MC. The column selection circuit 16 receives an address signal ADD from the input / output circuit 12. The column selection circuit 16 uses the voltage received from the voltage generation circuit 14 to select a bit line BL associated with a column identified by the received address signal ADD.

[0018] The write circuit 17 is a circuit that controls writing of data to the memory cells MC. The write circuit 17 receives data to be written from the input / output circuit 12. Based on the control and data of the control circuit 13, the write circuit 17 supplies the voltage received from the voltage generation circuit 14 to the column selection circuit 16.

[0019] The read circuit 18 is a circuit that controls reading of data from the memory cells MC. Based on the control of the control circuit 13, the read circuit 18 supplies the voltage received from the voltage generation circuit 14 to the column selection circuit 16. The read circuit 18 supplies a plurality of control signals to the sense amplifier 19 for data reading.

[0020] The sense amplifier 19 is a circuit for determining data stored in the memory cell MC. The sense amplifier 19 includes multiple sense amplifier circuits. The sense amplifier 19 receives multiple voltages from the voltage generating circuit 14 and operates using the received voltages. During data read, the sense amplifier 19 amplifies the potential on the bit line BL to determine the data stored in the memory cell MC from which data is to be read. The determined data is supplied to the input / output circuit 12.

[0021] Memory Cell 2 shows the components and connections of the components of a memory cell of the semiconductor memory device of Embodiment 1. Hereinafter, one of the source and drain of a transistor may be referred to as one end of the transistor, and the other may be referred to as the other end of the transistor.

[0022] 2, the memory cell MC has a gain cell structure, that is, the memory cell MC includes a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) TrS, a p-type floating gate MOSFET TrC, and an n-type MOSFET TG.

[0023] One end of the transistor TrS is connected to one source line CSL, and the gate of the transistor TrS is connected to the line SG.

[0024] The transistor TrC includes a floating gate insulated from the surroundings. One end of the transistor TrC is connected to the other end of the transistor TrS. The other end of the transistor TrC is connected to a bit line BL. The control gate of the transistor TrC is connected to a line CG. The line CG is connected to one word line WL.

[0025] One end of the transistor TrT is connected to the floating gate of the transistor TrC, the other end of the transistor TrT is connected to the bit line BL, and the gate of the transistor TrT is connected to the wiring TG.

[0026] 1.1.2.Memory Cell Array FIG. 3 shows the structure of a portion of the semiconductor memory device of the first embodiment along the xy plane. FIGS. 4 to 7 show the cross-sectional structure of a portion of the semiconductor memory device of the first embodiment. FIG. 4 shows the structure along line IV-IV in FIG. 3, and shows the structure along the xz plane. FIG. 5 shows the structure along line VV in FIG. 3, and shows the structure along the xz plane. FIG. 6 shows the structure along line VI-VI in FIG. 3, and shows the structure along the xz plane. FIG. 7 shows the structure along line VII-VII in FIG. 3, and shows the structure along the yz plane.

[0027] As shown in FIG. 3, the semiconductor memory device 1 includes multiple unit structures US. Each unit structure US functions as one memory cell MC. The unit structures US extend in the Y direction and are aligned in the X direction. Two unit structures US aligned in the Y direction have symmetrical structures with respect to the x axis and share some of their structures. Below, the lower unit structure US among the unit structures US aligned in the Y direction will be described. Each unit structure US includes semiconductors 21, 22, 24, 35, 37, 42, 44, conductors 26, 38, 46, and insulators 28, 31, 32, 36, and 41. The semiconductor memory device 1 further includes an insulator 48.

[0028] In each unit structure US, the semiconductors 21, 22, 24, the conductors 25 and 26, and the insulator 28 are aligned in the Y direction.

[0029] The semiconductor 21 extends along the xy plane. In one example, the semiconductor 21 has a shape based on a circle or an ellipse along the xy plane. The semiconductor 21 includes one first portion 21a and two second portions 21b. The first portion 21a has a shape with a portion of the upper side of a circle or ellipse missing. Therefore, the shape of the lower half and the shape of the upper half of the first portion 21a are different. The upper end of the first portion 21a has a contour that follows the contour of the semiconductor 22. In one example, the semiconductor 21 includes silicon. The semiconductor 21 is doped with impurities and is conductive. In one example, the semiconductor 21 contains p-type impurities. An example of the p-type impurity includes boron. The semiconductor 21 functions as an interconnect and functions as at least a part of the source line CSL.

[0030] A conductor may be provided instead of the semiconductor 21. In one example, the conductor includes titanium nitride. Alternatively, instead of the semiconductor 22, a semiconductor located on the side of the central conductor and the conductor and doped with p-type impurities may be provided. An example of the p-type impurity includes boron.

[0031] The lower side of each second portion 21b is connected to the upper end of the first portion 21a and is continuous with the first portion 21a. The second portions 21b have a shape that follows the outline of the semiconductor 22 and extend along the semiconductor 22. The second portions 21b are spaced apart from one another.

[0032] The semiconductor 22 extends along the xy plane. In one example, the semiconductor 22 has a shape based on a circle or an ellipse along the xy plane. The semiconductor 22 includes one first portion 22a and two second portions 22b. The first portion 22a has a shape in which a portion of the upper side of a circle or an ellipse is missing. Therefore, the shape of the lower half and the shape of the upper half of the first portion 22a are different. The upper end of the first portion 22a has a contour that follows the contour of the semiconductor 24. The lower end of the first portion 22a is located between the second portions 21b of the semiconductor 21. In one example, the semiconductor 22 includes silicon. The semiconductor 22 is doped with impurities and is conductive. In one example, the semiconductor 22 contains p-type impurities. An example of the p-type impurity includes boron. The semiconductor 22 functions as at least a part of the wiring SG. In another example, the semiconductor 22 contains n-type impurities. An example of the n-type impurity includes arsenic.

[0033] A conductor may be provided instead of the semiconductor 22. In one example, the conductor includes titanium nitride. Alternatively, instead of the semiconductor 22, a central conductor and semiconductors located on the sides of the conductor and doped with impurities may be provided. The impurities, like the semiconductor 22, may be n-type or p-type.

[0034] The second portions 22b are connected at their lower sides to the upper ends of the first portions 22a and are continuous with the first portions 22a. The second portions 22b are curved. The second portions 22b have a curvature radius greater than that of the first portions 22a. The second portions 22b are spaced apart from each other.

[0035] The semiconductor 24 extends along the xy plane. The semiconductor 24 functions as at least a part of the wiring CG. In one example, the semiconductor 24 has a circular or elliptical shape. The lower end of the semiconductor 24 is located between the second portions 22b of the semiconductor 22. In one example, the semiconductor 24 includes silicon. The semiconductor 24 is doped with impurities and is conductive. In one example, the semiconductor 24 contains p-type impurities. An example of the p-type impurity includes boron. In another example, the semiconductor 24 contains n-type impurities. An example of the n-type impurity includes arsenic.

[0036] A conductor may be provided instead of the semiconductor 24. In one example, the conductor includes titanium nitride. Alternatively, instead of the semiconductor 24, a central conductor and semiconductors located on the sides of the conductor and doped with impurities may be provided. The impurities, like the semiconductor 24, may be n-type or p-type.

[0037] The conductor 26 extends along the xy plane. In one example, the conductor 26 has a circular or elliptical shape along the xy plane. In one example, the conductor 26 includes titanium nitride. The conductor 26 functions as at least a part of the wiring TG.

[0038] The insulator 28 extends along the xy plane. In one example, the insulator 28 has a circular or elliptical shape along the xy plane. In one example, the insulator 28 includes silicon oxide.

[0039] The insulator 31 surrounds the semiconductor 24 along the xy plane and extends along the contour of the semiconductor 24. The insulator 31 extends over the surface of the semiconductor 24 along the xy plane. The insulator 31 has an annular shape along the xy plane. The insulator 31 has a radius or curvature along the xy plane that is larger than the radius of the semiconductor 24. In one example, the insulator 31 includes silicon oxide. The insulator 31 functions as a blocking insulator for the transistor TrT. The insulator 31 has a thickness that can prevent electrons stored in the semiconductor 35 from escaping through the insulator 31. In one example, the insulator 31 has a thickness of 6 nm or more.

[0040] The insulator 32 surrounds the conductor 26 along the xy plane and extends along the contour of the conductor 26. The insulator 32 extends over the surface of the conductor 26 along the xy plane. The insulator 32 has a radius or curvature along the xy plane that is larger than the radius of the conductor 26. The insulator 32 has an annular shape along the xy plane. In one example, the insulator 32 includes silicon oxide. The insulator 32 functions as a gate insulator for the transistor TrT.

[0041] The semiconductor 35 extends along the contour of the insulator 31 on the right or left side of the insulator 31. The semiconductor 35 is curved along the contour of the semiconductor 24. The semiconductor 35 extends over the surface of the insulator 31 along the xy plane. The semiconductor 35 has a curvature along the xy plane that is greater than the radius or curvature of each of the semiconductor 24 and the insulator 31. The semiconductor 35 covers a portion of the insulator 31. The pair of two semiconductors 35 in contact with each insulator 31 does not cover the bottom and top ends of the insulator 31. In one example, the semiconductor 35 includes silicon. The semiconductor 35 functions as a floating gate of the transistor TrC.

[0042] The insulator 36 is located between the semiconductor 22 and the semiconductor 35. The insulator 36 contacts the semiconductor 22, the semiconductor 35, and the insulator 31. The insulator 36 has a shape that follows the contour of the second portion 22b of the semiconductor 22. The insulator 36 has a curvature that is greater than the radius of the first portion 22a of the semiconductor 22 and the curvature of the second portion 22b. The insulator 36 covers the surface of the second portion 22b of the semiconductor 22 that faces the semiconductor 35, and insulates the semiconductor 22 from the semiconductor 35. In one example, the insulator 36 includes silicon oxide.

[0043] The semiconductor 37 extends along the xy plane, following the contour of the insulator 32. The semiconductor 37 partially surrounds the insulator 32. The semiconductor 37 is curved to follow the contour of the conductor 26. In one example, the semiconductor 37 has a ring shape with an opening at the bottom. The semiconductor 37 contacts the insulator 31. In one example, the semiconductor 37 contacts the insulator 31 at the opening. The semiconductor 37 includes a material having a high energy bandgap. In one example, the semiconductor 37 includes a material having an energy bandgap of 2.0 eV or greater. In one example, the semiconductor 37 includes a titanium oxide semiconductor. In another example, the semiconductor 37 includes a semiconductor including a combination of indium (In), gallium (Ga), zinc (Zn), and oxygen (O). When the semiconductor 37 is a titanium oxide semiconductor or a metal oxide semiconductor including a combination of indium, gallium, zinc, and oxygen, leakage of charge stored in the semiconductor 35 to the semiconductor 35 can be suppressed. The semiconductor 37 functions as the channel of the transistor TrT.

[0044] The conductor 38 is located between the semiconductor 35 and the semiconductor 37. The conductor 38 contacts the semiconductor 35, the semiconductor 37, and the insulator 31. The conductor 38 has a shape that follows the contour of the semiconductor 37. The conductor 38 is curved. The conductor 38 has a curvature that is greater than the radius of the conductor 26, the radius of the insulator 32, and the radius (or curvature) of the semiconductor 37. In one example, the conductor 38 includes titanium nitride.

[0045] The insulator 41 extends along the xy plane along the semiconductor 22, the insulator 36, the semiconductor 35, the conductor 38, and the semiconductor 37. The insulator 41 contacts the semiconductor 22, the insulator 36, the semiconductor 35, the conductor 38, and the semiconductor 37. The insulator 41 covers the surfaces of the semiconductor 22, the insulator 36, the semiconductor 35, the conductor 38, and the semiconductor 37.

[0046] The insulator 41 is curved. In the portion surrounding the semiconductor 22, the insulator 41 has a shape that follows the contour of the semiconductor 22. In the portion surrounding the semiconductor 22, the insulator 41 has a curvature that is greater than the radius or curvature of the semiconductor 22.

[0047] The insulator 41 has a shape that follows the contour of the semiconductor 35 in the portion surrounding the semiconductor 35. The insulator 41 has a curvature that is larger than the radius or curvature of the semiconductor 35 in the portion surrounding the semiconductor 35.

[0048] The insulator 41 has a shape that follows the contour of the semiconductor 37 in the portion surrounding the semiconductor 37. The insulator 41 has a curvature that is larger than the radius or curvature of the semiconductor 37 in the portion surrounding the semiconductor 37.

[0049] The insulator 41 has a ring shape that is open at the top end. The insulator 41 does not cover the semiconductor 37 at the opening.

[0050] In one example, the insulator 41 includes silicon oxide. The insulator 41 has a thickness that can prevent electrons stored in the semiconductor 35 from escaping through the insulator 31. In one example, the insulator 41 has a thickness of 6 nm or more. The insulator 41 functions as a gate insulator for the transistor TrS in the area surrounding the semiconductor 22. The insulator 41 also electrically insulates the semiconductor 37 from the semiconductor 44 in the area surrounding the semiconductor 37.

[0051] The semiconductor 42 extends along the xy plane and along a part of the insulator 41. The semiconductor 42 is in contact with the insulator 41. The semiconductor 42 covers the entire lateral (i.e., right and left) portions of the semiconductor 22 in the insulator 41. The semiconductor 42 does not cover the lower end portion of the insulator 41. The semiconductor 42 covers the entire lateral (i.e., right and left) portions of the semiconductor 24 in the insulator 41. The semiconductor 42 covers the lower portions of the lateral (i.e., right and left) portions of the semiconductor 37 in the insulator 41.

[0052] The semiconductor 42 is curved. The semiconductor 42 has a shape that follows the contour of the semiconductor 22 in the peripheral portion of the semiconductor 22. The semiconductor 42 has a curvature that is greater than the radius or curvature of the semiconductor 22 in the peripheral portion of the semiconductor 22.

[0053] The semiconductor 42 has a shape that follows the contour of the semiconductor 35 in the peripheral portion of the semiconductor 35. The semiconductor 42 has a curvature that is larger than the radius or curvature of the semiconductor 35 in the peripheral portion of the semiconductor 35.

[0054] The semiconductor 42 has a shape that follows the contour of the semiconductor 37 in the peripheral portion of the semiconductor 37. The semiconductor 42 has a curvature that is larger than the radius or curvature of the semiconductor 37 in the peripheral portion of the semiconductor 37.

[0055] The semiconductor 42 is in contact with the semiconductor 21 and the second portion 21b of the semiconductor 21. In one example, the semiconductor 42 includes silicon. The semiconductor 42 functions as a channel of the transistor TrS in a portion surrounding the semiconductor 22. The semiconductor 42 functions as a channel of the transistor TrC in a portion surrounding the semiconductor 35.

[0056] The semiconductor 44 extends along a portion of the insulator 41 along the xy plane. The semiconductor 44 is in contact with the insulator 41. The semiconductor 44 covers a portion of the insulator 41 on the sides (i.e., the right and left sides) of the conductor 26. The semiconductor 44 covers a portion of the insulator 41 on the sides of the conductor 26 that is not covered by the semiconductor 42. The semiconductor 44 has a shape that follows the contour of the semiconductor 37. The semiconductor 44 has a curvature that is greater than the radius or curvature of the semiconductor 37. The semiconductor 44 does not cover the top of the insulator 41 at its top. The semiconductor 44 is deposited by a process separate from that of the semiconductor 42, as described below, and therefore may have properties different from those of the semiconductor 42. Examples of the properties include density and impurity concentration. In one example, the semiconductor 44 includes silicon. The semiconductor 44 is doped with impurities and is conductive. In one example, the semiconductor 44 contains p-type impurities. An example of the p-type impurity includes boron. In one example, the semiconductor 42 includes silicon containing boron. The semiconductor 44 functions as a wiring that connects the bit line BL and the source or drain of the transistor TrT.

[0057] The conductor 46 extends in the X direction. The conductor 46 surrounds the insulator 28. The conductor 46 has a shape in which multiple circles or ellipses, with their top and bottom portions missing, are joined in the X direction. The conductor 46 contacts the semiconductor 37 at its lower end and upper end. The conductor 46 contacts the semiconductor 44 at its lower end and upper end. In one example, the conductor 46 includes titanium nitride. The conductor 46 is shared by two unit structures US aligned in the Y direction.

[0058] Insulator 48 embeds areas that are free of semiconductors 21, 22, 24, 35, 37, 42, 44, conductors 26, 38, 46, and insulators 28, 31, 32, 36, and 41. In one example, insulator 48 includes silicon nitride.

[0059] The combination of the semiconductor 22, the portion of the insulator 41 covering the semiconductor 22, and the portion of the semiconductor 42 on the side of the semiconductor 22 functions as one transistor TrS. The portion of the semiconductor 42 functions as the channel of the transistor TrS. The portion of the insulator 41 functions as the gate insulator of the transistor TrS.

[0060] The set of semiconductor 24, the portion of insulator 31 lateral to semiconductor 24, semiconductor 35, the portion of insulator 41 lateral to semiconductor 24, and the portion of semiconductor 42 lateral to semiconductor 24 functions as one transistor TrC. The portion of insulator 31 functions as a block insulator of transistor TrC. Semiconductor 35 functions as a floating gate of transistor TrC. The portion of insulator 41 lateral to semiconductor 24 functions as a tunnel insulator of transistor TrC. The portion of semiconductor 42 lateral to semiconductor 24 functions as a channel of transistor TrC.

[0061] The set of the conductor 26, the portion of the insulator 32 on either side of the conductor 26, and the portion of the semiconductor 37 on either side of the conductor 26 functions as one transistor TrG. The portion of the semiconductor 37 functions as the channel of the transistor TrT. The portion of the insulator 32 functions as the gate insulator of the transistor TrT.

[0062] 4 to 7, the structure shown in Fig. 3 is repeatedly provided in the Z direction. The semiconductor memory device 1 further includes a substrate 51, and insulators 52 and 54.

[0063] The substrate 51 extends along the xy plane. In one example, the substrate 51 includes silicon.

[0064] An insulator 52 is located on the top surface of the substrate 51. In one example, the insulator 52 comprises silicon dioxide.

[0065] The insulator 54 extends along the xy plane. In one example, the insulator 54 includes silicon oxide. The layer in which the insulator 54 is located and the layer in which the structure shown in FIG. 3 is located are alternately located one by one on the top surface of the insulator 52. Hereinafter, the layer in which the structure shown in FIG. 3 is located may be referred to as the layer in which the memory cells MC are located. FIGS. 4 to 7 show three pairs of the layer in which the insulator 54 is located and the layer in which the memory cells MC are located, as examples. The semiconductor memory device 1 has holes HP, HS, HC, HT, and HB.

[0066] As shown in FIGS. 4 and 7 , the holes HS extend in the Z direction. The holes HC are buried by the semiconductor 22. A portion of the semiconductor 22 within the holes HC may hereinafter be referred to as a central portion 221. A portion of the semiconductor 22 other than the central portion 221 may be referred to as a protruding portion 222. The protruding portion 222 surrounds the central portion 221 along the xy plane. The protruding portion 222 protrudes from the central portion 221 in a direction away from the central portion 221. The protruding portion 222 is connected to and continuous with the central portion 221. The protruding portion 222 is located in a layer in which the memory cells MC are located. The protruding portion 222 is located between the insulators 54 aligned in the Z direction. The protruding portions 222 located in different layers are connected by the central portion 221. The protruding portion 222 contacts the insulator 41 and the insulator 31. The first portion 22a shown in FIG. 3 includes the central portion 221 and the protruding portion 222. The second portion 22b shown in FIG.

[0067] 5 and 7, the holes HC extend in the Z direction. The holes HC are filled with the semiconductor 24.

[0068] As shown in FIGS. 6 and 7 , the hole HT extends in the Z direction. The hole HT is filled with a portion of the conductor 26. The portion of the conductor 26 in the hole HT may hereinafter be referred to as a center portion 261. The portion of the conductor 26 other than the center portion 261 may be referred to as a protrusion 262. The protrusion 262 surrounds the center portion 261 along the xy plane. The protrusion 262 protrudes from the center portion 261 in a direction away from the center portion 261. The protrusion 262 is connected to and continuous with the center portion 261. The protrusion 262 is located in a layer in which the memory cell MC is located. The protrusion 262 is located between the insulators 54 aligned in the Z direction. The protrusions 262 located in different layers are connected by the center portion 261. The protrusion 262 contacts the insulator 32.

[0069] Insulator 32 covers the surface of conductor 26 along the z-axis.

[0070] As shown in FIG. 7 , the hole HP extends in the Z direction. The hole HP is buried in a portion of the semiconductor 21. The portion of the semiconductor 21 within the hole HP may hereinafter be referred to as the central portion 211. The portion of the semiconductor 21 other than the central portion 211 may be referred to as the protruding portion 212. The protruding portion 212 surrounds the central portion 211 along the xy plane. The protruding portion 212 protrudes from the central portion 211 in a direction away from the central portion 211. The protruding portion 212 is connected to and continuous with the central portion 211. The protruding portion 212 is located in a layer in which the memory cell MC is located. The protruding portion 212 is located between the insulators 54 aligned in the Z direction. The protruding portions 212 located in different layers are connected by the central portion 211. The protruding portion 212 contacts the insulator 41.

[0071] The holes HB extend in the Z direction. The holes HB are filled with the insulator 28.

[0072] 1.2. Manufacturing method 8 to 68 show examples of the structure of the semiconductor memory device of the first embodiment during some manufacturing steps.

[0073] Figure 8 shows a portion of the area shown in Figure 3. Figure 9 shows the area shown in Figure 4.

[0074] 8 and 9, an insulator 52 is formed on the upper surface of a substrate 51. Then, an insulator 48A and an insulator 54A are alternately deposited one by one on the upper surface of the insulator 52. The insulator 48A is an element that will be formed into the insulator 48 in a later process. The insulator 54A is an element that will be formed into the insulator 54 in a later process.

[0075] Figure 10 shows part of the area shown in Figure 3. Figure 11 shows the area shown in Figure 4. Figure 12 shows the area shown in Figure 7.

[0076] 10 to 12, holes HP, HS, HC, HT, and HB are formed in the insulators 54A and 48A. An example of a formation method includes a combination of a lithography process and RIE (Reactive Ion Etching). The holes HP, HS, HC, HT, and HB extend in the Z direction through the insulators 54A and 48A. The formation of the holes HS, HC, HT, and HB turns the insulator 54A into the insulator 54.

[0077] The holes HP, HS, HC, HT, and HB are filled with a sacrificial material SM1. In one example, the sacrificial material SM1 includes silicon oxide and / or polysilicon. The sacrificial material SM1 may include polysilicon and silicon oxide covering the polysilicon. An example of a filling method includes CVD (Chemical Vapor Deposition).

[0078] The sacrificial material SM1 in the holes HS, HC, and HT is removed. An example of a removal method includes a combination of a lithography process and RIE. That is, a mask with openings is formed on the top surface of the structure obtained by the steps up to this point by a lithography process. The mask has openings above the holes HS, HC, and HT. Then, the sacrificial material SM1 below the openings is removed by RIE using the mask. Subsequent steps, including removing one or more sacrificial materials similar to the sacrificial material SM1 in the holes HP, HS, HC, HT, and HB, are also performed in a similar manner.

[0079] The portions of the insulator 48A exposed in the holes HS, HC, and HT are removed. An example of a removal method includes wet etching. By the removal, a space SP1 is formed around the holes HS, HC, and HT in the insulator 48A (i.e., the layer in which the memory cells MC are located). The space SP1 has an annular shape surrounding the holes HS, HC, and HT.

[0080] A semiconductor 42A is formed in the space SP1. The semiconductor 42A is an element that will be formed into the semiconductor 42 in a later process. An example of a formation method includes CVD.

[0081] During the process of forming the semiconductor 42A, the semiconductor 42A formed in the holes HS, HC, and HT is removed, thereby forming the holes HS, HC, and HT again.

[0082] Figure 13 shows part of the area shown in Figure 3. Figure 14 shows the area shown in Figure 4. Figure 15 shows the area shown in Figure 7.

[0083] As shown in FIGS. 13 to 15, a sacrificial material SM2 is deposited in the holes HS, HC, and HT. In one example, the sacrificial material SM2 includes silicon oxide and / or polysilicon. An example of a deposition method includes CVD. Through the deposition, the holes HS, HC, and HT are filled with the sacrificial material SM2.

[0084] The sacrificial material SM1 in the hole HB is removed. An example of a removal method includes CVD. By the removal, the hole HB is formed again.

[0085] The portion of the insulator 48A exposed in the hole HB is removed. An example of a removal method includes wet etching. As a result of the removal, a space SP3 is formed around the hole HB in the layer where the insulator 48A is located. The space SP3 has an annular shape surrounding the hole HB. The removal is continued until the space SP3 reaches the semiconductor 42A. As a result of the removal, the semiconductor 42A is exposed in the space SP3.

[0086] The portion of the semiconductor 42A exposed in the space SP3 is removed. An example of a removal method includes wet etching. A wet etching solution reaches the semiconductor 42A from the space SP3. The wet etching removes the upper portion of the semiconductor 42A in the layer where the insulator 48A is located. The removal causes the surface of the semiconductor 42A exposed in the space SP3 to recede. The removal turns the semiconductor 42A into semiconductor 42B. The removal expands the space SP3 in the layer where the insulator 48A is located.

[0087] A sacrificial material SM3 is deposited in the space SP3. In one example, the sacrificial material SM3 includes silicon nitride. An example of a deposition method includes CVD. By the deposition, the space SP3 is filled with the sacrificial material SM3.

[0088] In the process of forming the sacrificial material SM3, the sacrificial material SM3 formed in the hole HB is removed, thereby forming the hole HB again.

[0089] A sacrificial material SM4 is deposited in the hole HB. In one example, the sacrificial material SM4 includes silicon oxide and / or polysilicon. An example of a deposition method includes CVD. Through the deposition, the hole HB is filled with the sacrificial material SM4.

[0090] Figure 16 shows part of the area shown in Figure 3. Figure 17 shows the area shown in Figure 4. Figure 18 shows the area shown in Figure 7.

[0091] As shown in Figures 16 to 18, the sacrificial material SM2 is removed. An example of a removal method includes a combination of a lithography process and RIE. By the removal, holes HS, HC, and HT are formed again. By forming holes HS, HC, and HT, semiconductor 42B is exposed in holes HS, HC, and HT.

[0092] The portions of the semiconductor 42B exposed in the holes HS, HC, and HT are removed. An example of a removal method includes wet etching. The removal is performed until the thickness of the semiconductor 42B becomes the same as that of the semiconductor 42. As a result of the removal, the surfaces of the semiconductor 42B exposed in the holes HS, HC, and HT are recessed. As a result of the removal, the surfaces of the semiconductor 42B exposed in the holes HS, HC, and HT are recessed. As a result of the removal, a space SP4 is formed in the layer where the insulator 48A is located, in the region where the semiconductor 42B was located. Due to the space SP4, the sacrificial material SM3 is exposed in the region above the hole HT of the semiconductor 42B, in the layer where the insulator 48A is located.

[0093] An insulator 41 is formed on the surface of the semiconductor 42B exposed in the space SP4. An example of the formation includes oxidation of the surface of the semiconductor 42B. The insulator 41 is not formed on the surface of the sacrificial material SM3 exposed in the space SP4 in the region above the hole HT because the sacrificial material SM3 contains a material different from that of the semiconductor 42B.

[0094] A semiconductor 35A is deposited on the portion of the insulator 41 exposed in the space SP4. The semiconductor 35A is an element that will be formed into the semiconductor 35 in a later process. An example of a deposition method includes CVD.

[0095] The semiconductor 35A formed in the holes HS, HC, and HT during the deposition of the semiconductor 35A is removed, thereby forming the holes HS, HC, and HT again.

[0096] Figure 19 shows a portion of the area shown in Figure 3. Figure 20 shows the area shown in Figure 4. Figure 21 shows the area shown in Figure 5. Figure 22 shows the area shown in Figure 7.

[0097] As shown in Figures 19, 20, 21, and 22, a sacrificial material SM6 is deposited in the holes HS and HT. In one example, the sacrificial material SM6 includes silicon oxide and / or polysilicon. An example of a deposition method includes CVD. Through the deposition, the holes HS and HT are filled with the sacrificial material SM6.

[0098] The hole HC is not filled in. In an example of a method for doing so, after the holes HS, HC, and HT are filled with the sacrificial material SM6, the sacrificial material SM6 in the hole HC is removed.

[0099] An insulator 31 is formed on the portion of the semiconductor 35A exposed in the hole HC, an example of a formation method including oxidation of the semiconductor 35A.

[0100] The semiconductor 24 is deposited in the hole HC. An example of the deposition method includes CVD. By the deposition, the hole HC is filled with the semiconductor 24.

[0101] Figure 23 shows part of the area shown in Figure 3. Figure 24 shows the area shown in Figure 4. Figure 25 shows the area shown in Figure 7.

[0102] As shown in Figures 23 to 25, the sacrificial material SM6 in the hole HS is removed. An example of a removal method includes RIE. By removing, the hole HS is formed again. By forming the hole HS, the semiconductor 35A is exposed in the hole HS in the layer where the insulator 48A is located.

[0103] The portion of the semiconductor 35A exposed in the hole HS is removed. An example of a removal method includes wet etching. As a result of the removal, a space SP6 is formed around the hole HS in the layer where the insulator 48A is located. The space SP6 has an annular shape surrounding the hole HS. As a result of the removal, the insulator 41 is exposed in the space SP6.

[0104] By partially removing the semiconductor 35A, the space SP6 extends to the region of the semiconductor 35A above the hole HS. The space SP6 removes the lower portions of the portions of the semiconductor 35A on the sides (i.e., the right and left sides) of the semiconductor 24. This exposes the semiconductor 35A on the sides of the semiconductor 24.

[0105] Figure 26 shows a portion of the area shown in Figure 3. As shown in Figure 26, an insulator 36 is formed on the portion of semiconductor 35A exposed by space SP6. An example method of formation includes oxidation of semiconductor 35A.

[0106] Figure 27 shows part of the area shown in Figure 3. Figure 28 shows the area shown in Figure 4. Figure 29 shows the area shown in Figure 7.

[0107] 27 to 29, the semiconductor 22 is deposited in the hole HS and the space SP6. An example of the deposition method includes CVD. By the deposition, the hole HS and the space SP6 are filled with the semiconductor 22.

[0108] Figure 30 shows part of the area shown in Figure 3. Figure 31 shows the area shown in Figure 6. Figure 32 shows the area shown in Figure 7.

[0109] As shown in Figures 30 to 32, the sacrificial material SM6 in the hole HT is removed. An example of a removal method includes RIE. By removing, the hole HT is formed again. By forming the hole HT, the semiconductor 35A is exposed in the hole HT in the layer where the insulator 48A is located.

[0110] Figure 33 shows part of the area shown in Figure 3. Figure 34 shows the area shown in Figure 6. Figure 35 shows the area shown in Figure 7.

[0111] As shown in FIGS. 33 to 35, the portion of the semiconductor 35A exposed in the hole HT is removed. An example of a removal method includes wet etching. As a result of the removal, a space SP7 is formed around the hole HT in the layer where the insulator 48A is located. The space SP7 has an annular shape surrounding the hole HT. As a result of the removal, the insulator 41, the sacrificial material SM3, and the insulator 31 are exposed in the space SP7.

[0112] By partially removing the semiconductor 35A, the space SP7 removes the upper portions of the portions of the semiconductor 35A that are on the sides (i.e., the right and left sides) of the semiconductor 24. As a result, the semiconductor 35A becomes the semiconductor 35.

[0113] Figure 36 shows part of the area shown in Figure 3. Figure 37 shows the area shown in Figure 6. Figure 38 shows the area shown in Figure 7.

[0114] As shown in FIGS. 36 to 38, a sacrificial material SM7 is deposited in the space SP7. In one example, the sacrificial material SM7 is silicon nitride. Examples of deposition methods include CVD. Through the deposition, the space SP7 is filled with the sacrificial material SM7.

[0115] A sacrificial material SM8 is deposited in the hole HT. In one example, the sacrificial material SM8 includes silicon oxide and / or polysilicon. An example of a deposition method includes CVD. Through the deposition, the hole HT is filled with the sacrificial material SM8.

[0116] Figure 39 shows part of the area shown in Figure 3. Figure 40 shows the area shown in Figure 7.

[0117] As shown in Figures 39 and 40, the sacrificial material SM4 in the hole HB is removed. An example of a removal method includes RIE. By removing, the hole HB is formed again. By forming the hole HB, the sacrificial material SM3 is exposed in the hole HB in the layer where the insulator 48A is located.

[0118] Figure 41 shows part of the area shown in Figure 3. Figure 42 shows the area shown in Figure 7.

[0119] 41 and 42, the sacrificial material SM3 is removed. An example of a removal method includes wet etching. By removing the sacrificial material SM3, a space SP8 is formed in the layer where the insulator 48A is located, in the area where the sacrificial material SM3 was located. In the space SP8, part of the insulator 48A is exposed.

[0120] The portion of the insulator 48A exposed in the space SP8 is removed. An example of a removal method includes wet etching. As a result of the removal, the space SP8 expands in the layer where the insulator 48A is located. The partial removal of the insulator 48A continues until the portion of the insulator 48A between the holes HB aligned in the X direction is removed. As a result, the space SP8 has a shape formed by combining annular shapes surrounding the holes HB. In the space SP8, the sacrificial material SM8, the insulator 41, and the semiconductor 42B are exposed.

[0121] The partial removal of the insulator 48A also removes the upper portions of the portions of the sacrificial material SM7 that are on the sides (i.e., the right and left sides) of the sacrificial material SM8, so that the space SP8 includes the portion SP81 in the upper portions of the portions of the sacrificial material SM7 that are on the sides of the sacrificial material SM8.

[0122] Figure 43 shows part of the area shown in Figure 3. Figure 44 shows the area shown in Figure 6.

[0123] 43 and 44, the portion of the semiconductor 42B exposed in the space SP8 is removed. An example of a removal method includes wet etching. As a result of the removal, the space SP8 expands to cover the area where the semiconductor 42B was located and includes the portion SP82. The lower end of the portion SP82 reaches near the lower end of the sacrificial material SM8. Even with the partial removal of the semiconductor 42B, the insulator 41 remains.

[0124] Figure 45 shows part of the area shown in Figure 3. Figure 46 shows the area shown in Figure 6.

[0125] 45 and 46, the semiconductor 44 is deposited in the portion SP82 of the space SP8. An example of the deposition method includes CVD. By the deposition, the space SP8 is filled with the semiconductor 44.

[0126] Figure 47 shows part of the area shown in Figure 3. Figure 48 shows the area shown in Figure 7.

[0127] 47 and 48, the conductor 46 is deposited in the entire space SP8 except for the portion SP82. An example of the deposition method includes CVD. By the deposition, the entire space SP8 except for the portion SP82 is filled with the conductor 46.

[0128] The conductor 46 deposited in the hole HB is removed during the deposition of the conductor 46. As a result, the hole HB is formed again.

[0129] An insulator 28 is deposited in the hole HB. An example of the deposition method includes CVD. By the deposition, the hole HB is filled with the insulator 28.

[0130] Figure 49 shows part of the area shown in Figure 3. Figure 50 shows the area shown in Figure 7.

[0131] As shown in Figures 49 and 50, the sacrificial material SM1 in the holes HP is removed. An example of a removal method includes RIE. By removing, the holes HP are formed again. By forming the holes HP, the insulator 48A is exposed in the holes HP in the layer where the insulator 48A is located.

[0132] Figure 51 shows part of the area shown in Figure 3. Figure 52 shows the area shown in Figure 7.

[0133] As shown in Figures 51 and 52, the portion of the insulator 48A exposed in the hole HP is removed. An example of a removal method includes wet etching. By the removal, a space SP9 is formed around the hole HP in the layer in which the insulator 48A is located. The space SP9 has an annular shape surrounding the hole HP. In the space SP9, a portion of the semiconductor 42B along the bottom edge of the semiconductor 22 is exposed. By partially removing the insulator 48A, the insulator 48A becomes the insulator 48.

[0134] Figure 53 shows part of the area shown in Figure 3. Figure 54 shows the area shown in Figure 7.

[0135] 53 and 54, the portion of semiconductor 42B exposed in space SP9 is removed. An example of a removal method includes wet etching. As a result of the removal, space SP9 expands below the portion of semiconductor 42B that is lateral to semiconductor 22, and includes portion SP91. Portion SP91 is located between insulator 41 and insulator 48. By partially removing semiconductor 42B, semiconductor 42B becomes semiconductor 42.

[0136] Figure 55 shows part of the area shown in Figure 3. Figure 56 shows the area shown in Figure 7.

[0137] 55 and 56, semiconductor 21 is deposited in the hole HP and space SP9. An example of the deposition method includes CVD. Through the deposition, the hole HP and space SP9 are filled with semiconductor 21. The semiconductor 21 contacts the semiconductor 42 at a portion SP91 of the space SP9.

[0138] Figure 57 shows part of the area shown in Figure 3. Figure 58 shows the area shown in Figure 6. Figure 59 shows the area shown in Figure 7.

[0139] As shown in Figures 57 to 59, the sacrificial material SM8 in the hole HT is removed. An example of a removal method includes RIE. By removing, the hole HT is formed again. By forming the hole HT, the sacrificial material SM7 and the conductor 46 are exposed in the hole HT.

[0140] Figure 60 shows part of the area shown in Figure 3. Figure 61 shows the area shown in Figure 6. Figure 62 shows the area shown in Figure 7.

[0141] As shown in Figures 60 to 62, the sacrificial material SM7 is removed. An example of a removal method includes wet etching. By the removal, a space SP11 is formed in the layer where the insulator 48 is located, in the region where the sacrificial material SM7 was located. In the space SP11, the insulators 31 and 41, the conductor 46, and the semiconductor 35 are exposed.

[0142] Figure 63 shows part of the area shown in Figure 3. Figure 64 shows the area shown in Figure 6. Figure 65 shows the area shown in Figure 7.

[0143] As shown in FIGS. 63 to 65, a conductor 38A is deposited in the space SP11. The conductor 38A is an element that will be formed into the conductor 38 in a later step. An example of a deposition method includes CVD. The portion of the conductor 38A exposed in the space SP11 is removed. Due to the removal, the surface of the conductor 38A exposed in the space SP11 recedes. As a result, the conductor 38A remains on the surface of the semiconductor 35 and on the surface of the insulator 41 in the layer where the insulator 48 is located.

[0144] The partial removal of conductor 38A removes the portion of conductor 46 exposed by space SP11 in the layer where insulator 48A is located. The removal expands space SP11 to the area where the portion of conductor 46 was located.

[0145] Figure 66 shows part of the area shown in Figure 3. Figure 67 shows the area shown in Figure 6. Figure 68 shows the area shown in Figure 7.

[0146] As shown in Figures 66 to 68, semiconductors 37 are formed on the surfaces of conductors 38A and 46. Examples of formation methods include oxidizing the surface of conductor 38A and sputtering metal oxide. In one example, the formation of semiconductors 37 is continued until the entire portion of conductor 38A on insulator 41 becomes semiconductor 37. As a result of the formation of semiconductor 37, a portion of conductor 38A becomes conductor 38.

[0147] As shown in Figures 3-7, an insulator 32 is deposited on the surface of a semiconductor 37. Examples of deposition methods include CVD.

[0148] Conductor 26 is deposited in hole HB. An example of the deposition method includes CVD. By depositing conductor 26, hole HB is filled with conductor 26. This completes the structure shown in FIGS. 3 to 7.

[0149] 1.3.Advantages (Effects) According to the first embodiment, the semiconductor 22 and semiconductor 24 functioning as the gate of transistor TrS are insulated by an insulator 31 surrounding the semiconductor 24 as the gate of transistor TrC, and the semiconductor 24 and conductor 26 functioning as the gate of transistor TrT are insulated by the insulator 31 and the insulator 32 surrounding the conductor 26. Furthermore, the semiconductor 35 functioning as the floating gate of transistor TrC is insulated from the semiconductor 22 by the insulator 36 and is in contact with the semiconductor 37 functioning as the channel of transistor TrT. The pair of semiconductors 42 and 44 faces the semiconductors 22 and 35 and the semiconductor 37 via the insulator 41. With this structure, it is possible to realize a memory cell MC including a pair of transistors Trc and TrT constituting a gain cell structure and a transistor TrS connected in series with the gain cell structure.

[0150] Furthermore, the structure of the memory cell MC is formed by a combination of depositing and removing semiconductors, insulators, and conductors using the holes HS, HC, and HT as centers. This method of formation facilitates the formation of multiple memory cells MC in multiple layers aligned in the direction of the holes HS, HC, and HT, because the deposition and removal of semiconductors, insulators, and conductors in multiple layers can be performed in parallel.

[0151] 1.4. Variations 1.4.1. First Variant 43 and 44, the steps described below with reference to Fig. 69 may be performed. Fig. 69 shows a first modified example of the structure of the manufacturing process for the memory device of the first embodiment. Fig. 69 shows a part of the area shown in Fig. 3.

[0152] As shown in Fig. 69, removal of the portion of semiconductor 42B exposed in space SP8 continues longer than in the steps described above with reference to Figs. 43 and 44. As a result, space SP8 reaches the lateral regions of semiconductor 24.

[0153] Based on the shape of the space SP82, as shown in FIG. 70, the semiconductor 44 formed by the process described above with reference to FIGS. 45 and 46 reaches the sides of the semiconductor 24.

[0154] 1.4.2. Second Variant 71 to 93 show an example of the structure of a part of the memory device according to the second modified example of the first embodiment during the manufacturing process.

[0155] The steps described above with reference to Figures 49 and 50 continue with the steps described below with reference to Figures 71 to 75. Figure 71 shows part of the area shown in Figure 3. Figure 72 shows the area shown in Figure 4. Figure 73 shows the area shown in Figure 5. Figure 74 shows the area shown in Figure 6. Figure 75 shows the area shown in Figure 7.

[0156] As shown in FIGS. 71 to 75, the insulator 48A is removed. An example of a removal method includes wet etching. As a result of the removal, a space SP13 is formed in the layer where the insulator 48A was located (i.e., the layer where the memory cell MC is located) in the region where the insulator 48A was located. In the space SP13, the semiconductors 42B and 44 and the conductor 46 are exposed.

[0157] The hole HP is formed again by removing the insulator 48A, and the insulator 54 is exposed in the hole HP and the space SP13.

[0158] Fig. 76 shows part of the area shown in Fig. 3. Fig. 77 shows the area shown in Fig. 4. Fig. 78 shows the area shown in Fig. 5. Fig. 79 shows the area shown in Fig. 6. Fig. 80 shows the area shown in Fig. 7.

[0159] As shown in FIGS. 76 to 80, an insulator 61A is deposited. In one example, the insulator 61A includes silicon oxide. Examples of deposition methods include CVD. The insulator 61A covers the surfaces of the semiconductors 42B and 44, the conductor 46, and the insulator 54. The insulator 61A is thin. Therefore, in one example, the space SP13 is not filled with the insulator 61A.

[0160] Fig. 81 shows part of the area shown in Fig. 3. Fig. 82 shows the area shown in Fig. 4. Fig. 83 shows the area shown in Fig. 5. Fig. 84 shows the area shown in Fig. 6. Fig. 85 shows the area shown in Fig. 7.

[0161] As shown in FIGS. 81 to 85, a conductor 62A is deposited in the space SP13. In one example, the conductor 62A includes titanium nitride. An example of a deposition method includes CVD. Through the deposition, the space SP13 is filled with the conductor 62A.

[0162] The conductor 62A formed in the hole HP during the process of forming the conductor 62A is removed. As a result, the hole HP is formed again. The conductor 62A is exposed in the hole HP.

[0163] Figure 86 shows part of the area shown in Figure 3. Figure 87 shows the area shown in Figure 4.

[0164] As shown in FIGS. 86 and 87, the portion of the conductor 62A exposed in the hole HP is removed. An example of a removal method includes wet etching. As a result of the removal, a space SP14 is formed around the hole HP in the layer where the memory cell MC is located (the layer where the insulator 48A was located). The space SP14 has a shape formed by combining annular shapes surrounding the hole HP. In the space SP14, a portion of the insulator 61A along the bottom edge of the semiconductor 22 is exposed.

[0165] Figure 88 shows part of the area shown in Figure 3. Figure 89 shows the area shown in Figure 4.

[0166] As shown in Figures 88 and 89, the portions of the insulator 61A exposed in the space SP14 and the hole HP are removed. An example of a removal method includes wet etching. By partially removing the insulator 61A, the insulator 61A becomes the insulator 61. In the space SP14, the semiconductor 42B is exposed.

[0167] Figure 90 shows a portion of the area shown in Figure 3. Figure 91 shows the area shown in Figure 4.

[0168] As shown in Figures 90 and 91, the portion of semiconductor 42B exposed in space SP14 is removed. An example of a removal method includes wet etching. As a result of the removal, space SP14 extends to the lower region of the lateral portion of semiconductor 22 of semiconductor 42B and comes to include portion SP141. Portion SP141 is located between insulator 41 and insulator 61. As a result of the partial removal of semiconductor 42B, semiconductor 42B becomes semiconductor 42. In space SP141, insulator 61 is exposed.

[0169] Figure 92 shows a portion of the area shown in Figure 3. Figure 93 shows the area shown in Figure 4.

[0170] As shown in Figures 92 and 93, a semiconductor 64 is deposited in the hole HP and the space SP14. In one example, the semiconductor 64 includes silicon. The semiconductor 64 is doped with impurities and is conductive. In one example, v includes p-type impurities. An example of the p-type impurity includes boron. An example of the deposition method includes CVD.

[0171] The steps described above with reference to Figures 92 and 93 are continuations of the steps described above with reference to Figures 57 to 59.

[0172] According to the second modification, it is possible to suppress the influence of noise from memory cells MC adjacent to each other along the xy plane.

[0173] 1.3. Other Modifications The transistors TrS and TrC may be n-type, while the transistor TrT may be p-type. In this example, the semiconductor 44 is doped with n-type impurities. Examples of n-type impurities include phosphorus. Furthermore, the semiconductors 21, 22, and 24 may also be doped with n-type impurities instead of p-type impurities.

[0174] Instead of depositing the sacrificial material SM7 in the steps described above with reference to Figures 36 to 38, a conductor 38A may be deposited. In this case, the semiconductor 37 has the same shape as SM7. The manufacturing process continues with the steps described above with reference to Figures 66 to 68.

[0175] The holes HP may be filled with a metal instead of the semiconductor 21.

[0176] The two semiconductors 35 on either side of the semiconductor 24 may be connected to each other on the upper side of the semiconductor 24. This structure is The semiconductor 37 surrounding the conductor 26 may be connected to the underside of the conductor 26 without having an opening.

[0177] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0178] 1...semiconductor memory device, 11...memory cell array, 12...input / output circuit, 13...control circuit, 14...voltage generation circuit, 15...row selection circuit, 16...column selection circuit, 17...write circuit, 18...read circuit, 19...sense amplifier, MC...memory cell, WL...word line, BL...bit line, TrS...transistor, TrC...transistor, TrT...transistor, CSL...source line, SG...wiring, CG...wiring, TG...wiring, US...unit structure, 21...semiconductor, 22...semiconductor, 24...semiconductor, 26...conductor, 28...insulator, 31...insulator, 32...insulator, 35...semiconductor, 36...insulator, 37...semiconductor, 38...conductor, 41...insulator, 42...semiconductor, 44...semiconductor, 46...conductor, 48...insulator

Claims

1. a first wiring extending along a first plane formed by a first axis and a second axis intersecting the first axis, the first axis extending in a first direction; a second wiring extending along the first plane and provided in the first direction from the first wiring; a third wiring extending along the first plane and provided in the first direction from the second wiring; a first conductor extending along the first plane and extending in the first direction from the second wiring; a first insulator surrounding the third wiring along the first plane and having a portion located between the third wiring and the second wiring; a first semiconductor sandwiching the first insulator together with the third wiring; a second insulator between the second wiring and the first semiconductor; a third insulator surrounding the first conductor along the first plane; a second conductor in contact with the first semiconductor; a second semiconductor that sandwiches the third insulator together with the first conductor and is in contact with the second conductor; a fourth insulator extending along the first plane over the second wiring, the first semiconductor, and the second semiconductor; a third semiconductor in contact with the first wiring and including a portion that sandwiches the fourth insulator together with the second wiring and a portion that sandwiches the fourth insulator together with the first semiconductor; a fourth semiconductor in contact with the third semiconductor and sandwiching the fourth insulator together with the second semiconductor; a third conductor in contact with the fourth semiconductor; A semiconductor memory device comprising:

2. the fourth insulator covers a portion of the second wiring that faces the first wiring; 2. The semiconductor memory device according to claim 1.

3. the first insulator covers a portion of the third wiring that faces the second wiring; 2. The semiconductor memory device according to claim 1.

4. the second insulator covers a portion of the second wiring that faces the first semiconductor; 2. The semiconductor memory device according to claim 1.

5. the first insulator covers a portion of the third wiring that faces the first conductor; 2. The semiconductor memory device according to claim 1.

6. the third insulator covers a portion of the first conductor facing the third wiring; 2. The semiconductor memory device according to claim 1.

7. the third insulator covers a portion of the first conductor facing the third conductor; 2. The semiconductor memory device according to claim 1.

8. the second wiring includes a portion aligned with the third wiring along the first axis; 2. The semiconductor memory device according to claim 1.

9. the first wiring includes a portion aligned with the second wiring along the first axis; 2. The semiconductor memory device according to claim 1.

10. the second wiring, the third wiring, and the first conductor are curved along the first plane; 2. The semiconductor memory device according to claim 1.

11. the third semiconductor includes a portion curved along the second wiring, a portion curved along the third wiring, and a portion curved along the first conductor; 11. The semiconductor memory device according to claim 10.

12. the first semiconductor is curved along the third wiring; 11. The semiconductor memory device according to claim 10.

13. the second semiconductor includes a portion that is curved along the first conductor; 11. The semiconductor memory device according to claim 10.

14. the fourth semiconductor is curved along the first conductor; 11. The semiconductor memory device according to claim 10.

15. a fifth insulator surrounding the first wiring, the third semiconductor, the fourth semiconductor, and the third conductor along the first plane; 2. The semiconductor memory device according to claim 1.

16. a surface where the third semiconductor and the fourth semiconductor are in contact is aligned with the first conductor along the first axis; 2. The semiconductor memory device according to claim 1.

17. a surface where the third semiconductor and the fourth semiconductor are in contact with each other is aligned with the third wiring along the first axis; 2. The semiconductor memory device according to claim 1.

18. a sixth insulator extending along the first plane across a region on the first wiring, a region on the third semiconductor, a region on the fourth semiconductor, and a region on the third conductor; 2. The semiconductor memory device according to claim 1.

19. further comprising a fourth conductor surrounding the sixth insulator along the first plane; 19. The semiconductor memory device according to claim 18.

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