Semiconductor device

Abstract

To prevent the generation of an active trench gate insulated from a gate wiring electrode while suppressing deterioration of a filling property of a gate electrode.SOLUTION: A semiconductor device includes: a plurality of first active trench gates (1) extending in a first direction and opposed to a source layer (5) and a base layer (14) via a trench gate insulating film (9); and a second active trench gate (4) extending in a second direction intersecting the first direction and connecting adjacent first active trench gates (1). The gate wiring electrode (2) is connected to a wide part of the first active trench gate (1). The second active trench gate (4) is disposed below the gate wiring electrode (2). A connection portion between the first active trench gate (1) and the second active trench gate (4) has a T-shape in plan view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a trench gate type semiconductor element. [Background technology]

[0002] Semiconductor devices equipped with trench-gate semiconductor elements having gate electrodes embedded in trenches (hereinafter referred to as "trench gates") are known. For example, in a semiconductor device equipped with a trench-gate IGBT (Insulated Gate Bipolar Transistor), a gate drive signal for driving the IGBT is input to a gate pad provided on the top surface of the semiconductor device and supplied to multiple trench gates via gate wiring electrodes.

[0003] Typically, multiple trench gates extend in a fixed direction and are arranged at regular intervals in a direction intersecting the extension direction. A gate wiring electrode is connected to all trench gates (hereinafter referred to as "active trench gates") to which a gate drive signal should be supplied. Therefore, if voids occur at the connection between the gate wiring electrode and some of the active trench gates, those active trench gates will be insulated from the gate wiring electrode, causing the IGBT to partially stop operating. As a technology to solve this problem, Patent Document 1 listed below discloses a structure in which connecting trench gates are provided to connect adjacent active trench gates. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-235913 Summary of the Invention [Problem to be solved by the invention]

[0005] The technique of Patent Document 1 has a problem in that the trench becomes locally deep at the intersection of the active trench gate and the connecting trench gate, which deteriorates the embeddability of the gate electrode in that area.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can prevent the formation of an active trench gate that is insulated from the gate wiring electrode while suppressing deterioration of the embeddability of the gate electrode. [Means for solving the problem]

[0007] a first conductivity type source layer disposed on a surface portion of the upper surface of the semiconductor substrate and connected to the emitter electrode; a second conductivity type base layer disposed below the source layer; a collector electrode disposed on the lower surface of the semiconductor substrate; a plurality of first active trench gates extending in a first direction and facing the source layer and the base layer via a trench gate insulating film; and second active trench gates extending in a second direction intersecting the first direction and connecting adjacent first active trench gates, each of the plurality of first active trench gates having a portion wider than other portions, the gate wiring electrode extending in the second direction and connected to the wider portions of the plurality of first active trench gates, the second active trench gate being disposed below the gate wiring electrode, and a connection portion between the first active trench gate and the second active trench gate being T-shaped in a plan view. [Effects of the Invention]

[0008] According to the semiconductor device according to the present disclosure, it is possible to prevent the formation of an active trench gate insulated from the gate wiring electrode while suppressing deterioration in the embedding property of the gate electrode. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along line CC in FIG. [Figure 5] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 7] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along line DD in FIG. 7. [Figure 9] FIG. 8 is a cross-sectional view taken along line EE in FIG. [Figure 10] FIG. 8 is a cross-sectional view taken along line FF in FIG. 7. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following embodiments, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. + ", and n-type with a relatively low impurity concentration is called "n - ", and n-type with a relatively high impurity concentration is called "p + ", and p-type with a relatively low impurity concentration is called "p - Here, the impurity concentration of each region is defined by the peak concentration. In other words, a region with a high (or low) impurity concentration means a region with a high (or low) peak impurity concentration.

[0011] <First Embodiment> 1 to 4 are diagrams showing the configuration of a semiconductor device according to a first embodiment. FIG. 1 is a plan view of the semiconductor device. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. FIG. 4 is a cross-sectional view taken along line CC in FIG. 1. In this embodiment, it is assumed that the semiconductor element provided in the semiconductor device is an IGBT. However, the semiconductor element may be any trench-gate type semiconductor element, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0012] FIG. 1 shows the periphery of a main part of a semiconductor device according to the first embodiment, specifically showing the edge of an active region of the semiconductor device and the termination region outside the active region. The active region is a region in which cells of a semiconductor element are arranged and through which a main current flows. The termination region is provided to surround the active region and is a region in which a breakdown voltage retention structure and gate wiring that controls the semiconductor elements in the active region are arranged. FIG. 1 shows a gate wiring region 100 in the termination region and a cell region 200 in the active region.

[0013] The semiconductor device according to the first embodiment is formed using a semiconductor substrate on which an n-type drift layer 11 is formed. The upper main surface of the semiconductor substrate in Figures 2 to 4 is defined as the "upper surface" and the lower main surface is defined as the "lower surface." That is, Figure 1 shows the configuration of the upper surface of the semiconductor device.

[0014] The semiconductor substrate may be made of silicon or a wide bandgap semiconductor such as silicon carbide (SiC). Compared to conventional silicon-based semiconductor devices, semiconductor devices made of wide bandgap semiconductors are superior in terms of operation at high voltages, large currents, and high temperatures. Wide bandgap semiconductors include silicon carbide, gallium nitride (GaN)-based materials, and diamond.

[0015] A p-type collector layer 12 is formed in the surface layer portion on the lower surface side of the semiconductor substrate, i.e., below the n-type drift layer 11. A collector electrode 13 connected to the p-type collector layer 12 is formed on the lower surface of the semiconductor substrate. The p-type collector layer 12 and the collector electrode 13 are formed over the entire gate wiring region 100 and the cell region 200.

[0016] In the cell region 200, a p-type base layer 14 is formed on the surface layer portion of the upper surface side of the semiconductor substrate, i.e., on the upper side of the n-type drift layer 11. The surface layer portion of the p-type base layer 14 has n + Type source layer 5 and p + The n-type contact layer 6 is selectively formed. + type source layer 5 and p + The n-type contact layer 6 is disposed on the surface of the semiconductor substrate. + type source layer 5 and p + A p-type base layer 14 is disposed below the p-type contact layer 6 .

[0017] A plurality of trenches extending in a first direction are formed on the upper surface of the semiconductor substrate. + The trench is in contact with the n-type source layer 5 and the p-type base layer 14, and reaches the n-type drift layer 11 below the p-type base layer 14. A trench gate insulating film 9 is formed on the inner surface of the trench, and a first active trench gate 1 is formed on the trench gate insulating film 9 so as to fill the trench.

[0018] The first active trench gate 1 extends in a first direction and includes a p-type base layer 14 and an n-type + type source layer 5 and p + The contact layer 6 is disposed between the first active trench gates 1. The first active trench gates 1 are connected to the n-type contact layer 6 via the trench gate insulating film 9. + The first active trench gate 1 faces the p-type source layer 5 and the p-type base layer 14. An end of the first active trench gate 1 is disposed in the gate wiring region 100.

[0019] An interlayer insulating film 10 is formed on the upper surface of the semiconductor substrate. A gate wiring electrode 2 is formed on the interlayer insulating film 10 in a gate wiring region 100. The gate wiring electrode 2 is connected to a gate pad (not shown) to which a gate drive signal is input. The gate wiring electrode 2 is connected to a first active trench gate 1 through a contact hole formed in the interlayer insulating film 10. A first conductive portion 3 is a contact portion between the gate wiring electrode 2 and the first active trench gate 1. The first active trench gate 1 has a portion in the gate wiring region 100 that is wider than other portions, and the first conductive portion 3 is disposed on the wider portion.

[0020] A trench extending in a second direction intersecting the first direction is formed on the upper surface of the semiconductor substrate in the gate wiring region 100. A trench gate insulating film 9 is formed on the inner surface of the trench, and a second active trench gate 4 is formed on the trench gate insulating film 9 so as to fill the trench.

[0021] The second active trench gates 4 extend in the second direction and connect between adjacent first active trench gates 1. The connection between the first active trench gates 1 and the second active trench gates 4 is T-shaped in plan view. The second active trench gates 4 are disposed below the gate wiring electrode 2, specifically, between the first conductive portion 3 and the end of the gate wiring electrode 2.

[0022] An emitter electrode 7 is formed on the interlayer insulating film 10 in the cell region 200. The emitter electrode 7 is connected to the n-type semiconductor layer 200 through a contact hole formed in the interlayer insulating film 10. + type source layer 5 and p + The second conductive portion 8 is connected to the emitter electrode 7 and the n-type contact layer 6. + type source layer 5 and p + This is a contact portion with the mold contact layer 6 .

[0023] According to the semiconductor device of the first embodiment, adjacent first active trench gates 1 are connected by the second active trench gates 4. Therefore, even if, for example, a void occurs in the first conductive portion 3, causing a connection failure between some of the first active trench gates 1 and the gate wiring electrode 2, the first active trench gates 1 will not be insulated from the gate wiring electrode 2. Furthermore, because the connection portion between the first active trench gates 1 and the second active trench gates 4 is T-shaped, this prevents the trench from becoming locally deep at the connection portion between the first active trench gates 1 and the second active trench gates 4, which has the advantage of making it difficult for the embeddability of the gate electrode to deteriorate at this connection portion. Furthermore, because the second active trench gates 4 are disposed within the gate wiring region 100 (below the gate wiring electrode 2), providing the second active trench gates 4 prevents the effective area of ​​the semiconductor element from being narrowed.

[0024] <Embodiment 2> Fig. 5 is a plan view of a semiconductor device according to embodiment 2. In Fig. 5, elements that are the same as or correspond to those shown in Fig. 1 to Fig. 4 are assigned the same reference numerals as in Fig. 1 to Fig. 4, and therefore description of those elements will be omitted.

[0025] In the semiconductor device according to the second embodiment, the second active trench gate 4 is disposed at the end of the first active trench gate 1. That is, the second active trench gate 4 connects the ends of adjacent first active trench gates 1. In this case as well, the connection between the first active trench gate 1 and the second active trench gate 4 is T-shaped in plan view.

[0026] According to the semiconductor device of the second embodiment, the number of T-junctions between the first active trench gate 1 and the second active trench gate 4 is reduced compared to the first embodiment. An electric field concentrates at the corners of the T-junctions, and the concentration of the electric field causes gate leakage current. Therefore, by reducing the number of T-junctions, the effect of suppressing gate leakage current can be obtained.

[0027] <Third Embodiment> Fig. 6 is a plan view of a semiconductor device according to embodiment 3. In Fig. 6, elements that are the same as or correspond to those shown in Fig. 1 to Fig. 4 are also denoted by the same reference numerals as in Fig. 1 to Fig. 4, and therefore description of those elements will be omitted.

[0028] In the semiconductor device according to the third embodiment, first active trench gates 1 and dummy trench gates 15 are alternately arranged in the second direction on the upper surface of the semiconductor substrate. The dummy trench gates 15 are embedded in trenches extending in the first direction, similar to the first active trench gates 1, and are connected to the n-type trench via trench gate insulating films 9. + The dummy trench gate 15 faces the p-type source layer 5 and the p-type base layer 14. However, the dummy trench gate 15 is connected to the emitter electrode 7, not to the gate wiring electrode 2. Therefore, in the third embodiment, as shown in FIG. 6, the second conductive portion 8 is formed so as to partially overlap the dummy trench gate 15. The end of the dummy trench gate 15 does not have to reach the gate wiring region 100.

[0029] The second active trench gates 4 extending in the second direction connect the adjacent first active trench gates 1 with the dummy trench gate 15 in between. The connection points between the first active trench gates 1 and the second active trench gates 4 are T-shaped in plan view. The position of the second active trench gates 4 may be closer to the cell region 200 than the first conductive portion 3 as in the first embodiment, or may be at the end of the first active trench gates 1 as in the second embodiment.

[0030] According to the semiconductor device of the third embodiment, in addition to the same effects as those of the first or second embodiment, by reducing the number of first active trench gates 1, it is possible to obtain the effect of reducing the gate leakage current that occurs when a gate drive signal is input.

[0031] <Fourth Embodiment> 7 to 10 are diagrams showing the configuration of a semiconductor device according to a fourth embodiment. FIG. 7 is a plan view of the semiconductor device. FIG. 8 is a cross-sectional view taken along line DD in FIG. 7. FIG. 9 is a cross-sectional view taken along line EE in FIG. 7. FIG. 10 is a cross-sectional view taken along line FF in FIG. 7.

[0032] On the upper surface of the semiconductor substrate, first trenches 21 and second trenches 22, both of which extend in a first direction, are alternately arranged in a second direction.

[0033] A trench gate insulating film 9 is formed on the inner surface (bottom and side surfaces) of the first trench 21, and a first lower electrode 25 serving as a first active trench gate is disposed on the trench gate insulating film 9. Furthermore, within the first trench 21, a first upper electrode 24 is disposed on the first lower electrode 25 with an electrode isolation insulating film 23 interposed therebetween. That is, the first lower electrode 25 is disposed in a lower portion of the first trench 21, and the first upper electrode 24 is disposed in an upper portion of the first trench 21. However, as shown in FIG. 8 , the first lower electrode 25 extends further outside the gate wiring region 100 than the first upper electrode 24, and the first lower electrode 25 is embedded in the entire first trench 21 in the portion extending beyond the first upper electrode 24. The first lower electrode 25 is connected to the gate wiring electrode 2 through a contact hole formed in the interlayer insulating film 10 in the portion extending beyond the first upper electrode 24. The third conductive portion 17 is a contact portion between the gate wiring electrode 2 and the first active trench gate (a first lower-stage electrode 25 and a second lower-stage electrode 27 described later). In the first trench 21, the third conductive portion 17 is a contact portion between the gate wiring electrode 2 and the first lower-stage electrode 25. The first lower-stage electrode 25 has a portion where the third conductive portion 17 is arranged that is wider than other portions.

[0034] Furthermore, an electrode connection wiring 20 extending in the second direction is formed on the interlayer insulating film 10 in the gate wiring region 100. The electrode connection wiring 20 is connected to a first upper-stage electrode 24 through a contact hole formed in the interlayer insulating film 10. The first upper-stage electrode 24 has a portion at the contact portion with the electrode connection wiring 20 that is wider than other portions.

[0035] 10 , the electrode connecting wiring 20 extends in the second direction so as to cross over the first trench 21 and the second trench 22. The emitter electrode 7 is connected to the electrode connecting wiring 20 through a contact hole formed in the interlayer insulating film 10 that covers the electrode connecting wiring 20. The fourth conductive portion 18 is a contact portion between the emitter electrode 7 and the electrode connecting wiring 20. In this way, the electrode connecting wiring 20 connects the first upper-stage electrodes 24 to each other, and also connects the plurality of first upper-stage electrodes 24 to the emitter electrode 7.

[0036] A trench gate insulating film 9 is formed on the inner surface (bottom and side surfaces) of the second trench 22, and a second lower electrode 27 serving as a first active trench gate is disposed on the trench gate insulating film 9. Furthermore, within the second trench 22, a second upper electrode 26 is disposed on the second lower electrode 27 with an electrode isolation insulating film 23 interposed therebetween. That is, the second lower electrode 27 is disposed in a lower portion of the second trench 22, and the second upper electrode 26 is disposed in an upper portion of the second trench 22. However, as shown in FIG. 9 , the second lower electrode 27 extends further outside the gate wiring region 100 than the second upper electrode 26, and the second lower electrode 27 is embedded in the entire second trench 22 in the portion extending beyond the second upper electrode 26. The second lower electrode 27 is connected to the gate wiring electrode 2 through a contact hole formed in the interlayer insulating film 10 in the portion extending beyond the second upper electrode 26. In the second trench 22, the third conductive portion 17 is a contact portion between the gate wiring electrode 2 and the second lower electrode 27. The second lower electrode 27 has a portion where the third conductive portion 17 is arranged that is wider than other portions.

[0037] 10, the electrode connection wiring 20 crosses over the second lower-stage electrode 27 in the second trench 22, but the electrode connection wiring 20 and the second lower-stage electrode 27 are insulated from each other by the interlayer insulating film 10. Therefore, the electrode connection wiring 20 can connect the first upper-stage electrodes 24 in the first trenches 21 to each other across the second lower-stage electrode 27 in the second trench 22.

[0038] The second upper-stage electrode 26 is connected to the emitter electrode 7 at the end of the cell region 200 through a contact hole formed in the interlayer insulating film 10. Therefore, the end of the second upper-stage electrode 26 does not need to reach the gate wiring region 100. The fifth conductive portion 19 is a contact portion between the emitter electrode 7 and the second upper-stage electrode 26. The second upper-stage electrode 26 has a portion where the fifth conductive portion 19 is arranged that is wider than other portions.

[0039] 7, the second active trench gate 4 extending in the second direction connects the adjacent first lower electrodes 25 and second lower electrodes 27. The connection portion between the first active trench gate 1 and the first lower electrode 25 and the connection portion between the first active trench gate 1 and the second lower electrode 27 are T-shaped in plan view. The position of the second active trench gate 4 may be closer to the cell region 200 than the third conductive portion 17, or may be at the end of the first lower electrode 25 and the second lower electrode 27.

[0040] According to the semiconductor device of the fourth embodiment, the first lower electrode 25 and the second lower electrode 27 are connected by the second active trench gate 4, so even if a break occurs in some of the third conductive portions 17, it is possible to maintain conduction between the electrode connecting wiring 20 and the first lower electrode 25 and the second lower electrode 27. Furthermore, since the first upper electrodes 24 are connected to each other by the electrode connecting wiring 20, it is possible to maintain conduction between the electrode connecting wiring 20 and the first upper electrode 24, even if a break occurs in some of the fourth conductive portions 18.

[0041] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0042] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0043] (Appendix 1) a semiconductor substrate; an emitter electrode and a gate wiring electrode provided on the upper surface of the semiconductor substrate; a first conductivity type source layer disposed in a surface layer portion on the upper surface side of the semiconductor substrate and connected to the emitter electrode; a base layer of a second conductivity type disposed below the source layer; a collector electrode provided on the lower surface of the semiconductor substrate; a plurality of first active trench gates extending in a first direction and facing the source layer and the base layer via a trench gate insulating film; second active trench gates extending in a second direction intersecting the first direction and connecting adjacent first active trench gates; Equipped with Each of the plurality of first active trench gates has a portion that is wider than other portions, the gate wiring electrode extends in the second direction and is connected to the wide portions of the plurality of first active trench gates; the second active trench gate is disposed below the gate wiring electrode; a connection portion between the first active trench gate and the second active trench gate has a T-shape in plan view; Semiconductor device.

[0044] (Appendix 2) the second active trench gate is connected to an end of the first active trench gate; 2. The semiconductor device according to claim 1.

[0045] (Appendix 3) a dummy trench gate extending in the first direction and connected to the emitter electrode is provided between the first active trench gates; 10. The semiconductor device according to claim 1 or 2.

[0046] (Appendix 4) a first trench extending in the first direction and embedded with a first lower electrode serving as the first active trench gate and a first upper electrode provided on the first lower electrode via an electrode isolation insulating film; a second trench extending in the first direction and embedded with a second lower electrode serving as the first active trench gate and a second upper electrode provided on the second lower electrode via an electrode isolation insulating film; Equipped with the first trenches and the second trenches are alternately provided in the second direction, further comprising an electrode connection wiring extending in the second direction, spanning the second trench, and connecting the first upper electrodes adjacent to each other across the second trench; the electrode connection wiring is connected to the gate wiring electrode; 10. The semiconductor device according to claim 1 or 2. [Explanation of symbols]

[0047] 100 Gate wiring region, 200 Cell region, 1 First active trench gate, 2 Gate wiring electrode, 3 First conductive portion, 4 Second active trench gate, 5 n + Mold source layer, 6 p + 1. Type contact layer, 7 emitter electrode, 8 second conductive portion, 9 trench gate insulating film, 10 interlayer insulating film, 11 n-type drift layer, 12 p-type collector layer, 13 collector electrode, 14 p-type base layer, 15 dummy trench gate, 17 third conductive portion, 18 fourth conductive portion, 19 fifth conductive portion, 20 electrode connection wiring, 21 first trench, 22 second trench, 23 electrode isolation insulating film, 24 first upper electrode, 25 first lower electrode, 26 second upper electrode, 27 second lower electrode.

Claims

1. a semiconductor substrate; an emitter electrode and a gate wiring electrode provided on the upper surface of the semiconductor substrate; a first conductivity type source layer disposed in a surface layer portion on the upper surface side of the semiconductor substrate and connected to the emitter electrode; a base layer of a second conductivity type disposed below the source layer; a collector electrode provided on the lower surface of the semiconductor substrate; a plurality of first active trench gates extending in a first direction and facing the source layer and the base layer via a trench gate insulating film; second active trench gates extending in a second direction intersecting the first direction and connecting adjacent first active trench gates; Equipped with Each of the plurality of first active trench gates has a portion that is wider than other portions, the gate wiring electrode extends in the second direction and is connected to the wide portions of the plurality of first active trench gates; the second active trench gate is disposed below the gate wiring electrode; a connection portion between the first active trench gate and the second active trench gate has a T-shape in plan view; Semiconductor device.

2. the second active trench gate is connected to an end of the first active trench gate; The semiconductor device according to claim 1 .

3. a dummy trench gate extending in the first direction and connected to the emitter electrode is provided between the first active trench gates; 3. The semiconductor device according to claim 1.

4. a first trench extending in the first direction and embedded with a first lower electrode serving as the first active trench gate and a first upper electrode provided on the first lower electrode with an electrode isolation insulating film interposed therebetween; a second trench extending in the first direction and embedded with a second lower electrode serving as the first active trench gate and a second upper electrode provided on the second lower electrode with an electrode isolation insulating film interposed therebetween; Equipped with the first trenches and the second trenches are alternately provided in the second direction, further comprising an electrode connection wiring extending in the second direction, spanning the second trench, and connecting the first upper electrodes adjacent to each other across the second trench; the electrode connection wiring is connected to the gate wiring electrode; 3. The semiconductor device according to claim 1.

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