Soft start circuit and DC-DC converter

Abstract

To provide a soft start circuit which can suppress overshoot of output voltage in recovering from an abnormal state in which output voltage drops.SOLUTION: In a soft start circuit of a DC power supply device comprising: an error amplifier circuit which uses feedback voltage according to output voltage and predetermined voltage as input; a switching element for drive provided between a voltage input terminal and a voltage output terminal; and a control circuit which controls the switching element for drive on the basis of output of the error amplifier circuit, which generates soft start voltage for controlling conduction of the switching element for drive when voltage of the voltage input terminal rises in the DC power supply device, the soft start circuit comprises state detection means which can detect a state in which the output voltage of the error amplifier circuit exceeds a predetermined potential, and is constituted to generate the soft start voltage according to detection of recovery from the state in which the output voltage of the error amplifier circuit exceeds the predetermined potential by the state detection means.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a soft start circuit for a DC power supply and a DC-DC converter, and relates to a technique that is effective when applied to, for example, a switching regulator type DC-DC converter. [Background technology]

[0002] A switching regulator DC-DC converter is a power supply device that supplies a DC power voltage. Among switching regulator DC-DC converters, there is a DC-DC converter that controls the output voltage using a PWM control method (see, for example, Patent Document 1). Furthermore, some DC-DC converters are equipped with a soft-start circuit that suppresses inrush current at startup and prevents overshooting of the output voltage (see, for example, Patent Document 2). Furthermore, some DC-DC converters are provided with an output low voltage protection circuit that detects when the output voltage drops below a predetermined potential and stops the output. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-044938 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-100497 Summary of the Invention [Problem to be solved by the invention]

[0004] In an on-board electronic control system equipped with a battery-powered DC-DC converter, the input voltage may drop below the DC-DC converter's output voltage during cranking. There is a demand for DC-DC converters equipped with low-voltage protection circuits to continue outputting even in such cases, but this can lead to the following problems. Figure 6 is a timing chart showing the changes in the main voltages and signals of a DC-DC converter using a typical PWM control method when the input voltage drops, where VIN is the input voltage, VOUT is the output voltage, COMP is the output of the error amplifier (amplification circuit), RAMP is the waveform signal (triangular wave) that is compared with the output of the error amplifier, and PWM is the drive signal waveform (drive pulse) of the switching element.

[0005] As shown in Figure 6, when the input voltage VIN of the DC-DC converter drops, the output voltage VOUT also drops accordingly, causing the COMP voltage to rise above the maximum RAMP voltage. After that, at timing t1, the input voltage VIN starts to rise, and the output voltage VOUT also rises along with the input voltage VIN. When the output voltage VOUT rises to the set voltage at timing t2, the COMP voltage begins to drop, but because the signal for duty control of the drive pulse according to the input / output voltage difference cannot be output immediately, VOUT continues to rise above the set voltage. Then, when the COMP voltage drops to a voltage at which duty control can be performed, the output voltage VOUT stops increasing, and the converter output is controlled to the set voltage.

[0006] As described above, conventional DC-DC converters using a general PWM control method have the problem that the output voltage VOUT overshoots when it returns from a state where it cannot be controlled to the set voltage.In Figure 6, the drive switch transistor (M1 in the figure) is controlled to be on during the high-level period of the PWM pulse, so during the period T1 when the COMP voltage is higher than the maximum voltage of RAMP, the drive switch M1 is kept on for a long time.

[0007] In order to solve the problem of the occurrence of overshoot, the inventors of the present invention came up with and studied a circuit configuration as shown in FIG. In the circuit shown in FIG. 7, VO is the terminal to which the output voltage VOUT is applied, AMP is an error amplifier that amplifies the potential difference between the voltage VFB obtained by resistively dividing VOUT and the reference voltage VREF, CLP1 is a clamping circuit that clamps the potential of the terminal SS, and CLP2 is a clamping circuit that clamps the voltage COMP supplied from the error amplifier AMP to the subsequent PWM comparator.

[0008] The SS clamping circuit CLP1 has an offset between its input terminals and clamps the potential of the terminal SS to a potential near the voltage VFB when the voltage VFB decreases due to a decrease in the output voltage VOUT. Thereby, at the rising of the input voltage VIN, it has a soft-start function of preventing the overshoot of the output voltage VOUT by suppressing the rapid change of the output of the error amplifier AMP. Also, although not shown, an output low-voltage protection circuit is provided that detects the low-voltage state of the output voltage VOUT and stops the output.

[0009] However, in the circuit shown in FIG. 7, when the voltage of the VO terminal drops below the detection voltage VLVP of the output low-voltage protection circuit under the condition of entering an abnormal state where the output voltage VOUT drops and clamps the SS terminal voltage, and when the abnormal state returns within the delay time (TDLY) of low-voltage detection, even if the voltage of the VO terminal rises due to the soft-start operation, the output may stop due to the detection of the low-voltage state of the output. Here, the condition for the output not to stop by the output low-voltage protection circuit is that if the time required for soft start is Tss, then Tss < TDLY. Note that if the delay time TDLY is increased, when an abnormal state of the output (overcurrent state of the output due to a short circuit) occurs, the time until the abnormality is detected and the output is stopped becomes longer, and there is a risk that current continues to flow through the driving switch transistor and the IC overheats and the IC is damaged. Therefore, the delay time TDLY cannot be increased too much.

[0010] The present invention has been made paying attention to the above problems, and its object is to provide a soft-start circuit that can suppress the overshoot of the output voltage when returning from an abnormal state where the output voltage decreases. Another object of the present invention is to provide a DC-DC converter in which the output is not stopped due to the detection of an output low voltage state at the timing when the output voltage recovers from an abnormal state of output voltage drop within the detection delay time for the output low voltage. [Means for solving the problem]

[0011] In order to achieve the above object, the present invention provides: In a DC power supply device including an error amplifier circuit that receives as input a feedback voltage corresponding to an output voltage and a predetermined first reference voltage, a drive switching element provided between a voltage input terminal and a voltage output terminal, and a control circuit that controls the drive switching element based on the output of the error amplifier circuit, a soft start circuit that generates a soft start voltage for controlling the conduction of the drive switching element when the voltage of the voltage input terminal rises, a state detection means capable of detecting a state in which the output voltage of the error amplifier circuit exceeds a predetermined potential; The soft start voltage is generated in response to the state detection means detecting that the output voltage of the error amplifier circuit has returned from a state in which it exceeded a predetermined potential.

[0012] The soft-start circuit configured as described above generates a soft-start voltage in response to detecting that the output voltage of the error amplifier circuit has returned from a state where it exceeded a predetermined potential, and controls the conduction of the drive switching element so that the output voltage rises slowly using the soft-start voltage. This makes it possible to suppress overshoot of the output voltage when the output voltage returns from an abnormal state where it drops. [Effects of the Invention]

[0013] The soft-start circuit of the present invention can suppress output voltage overshoot when recovering from an abnormal state in which the output voltage drops. Also, the DC-DC converter of the present invention has the advantage that the output is not stopped due to the detection of an output low voltage state when recovering from an abnormal state in which the output voltage drops within the detection delay time for the output low voltage. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a circuit diagram showing an embodiment in which the present invention is applied to a switching regulator type DC-DC converter. [Figure 2] 1 is a circuit diagram showing an example of a recovery circuit included in a DC-DC converter according to an embodiment of the present invention; [Figure 3] 10 is a timing chart showing changes in signals and potentials of various parts when the FB voltage drops to a potential slightly higher than the low voltage detection level in the DC-DC converter of the embodiment. [Figure 4] 6 is a timing chart showing changes in signals and potentials of various parts when the FB voltage drops to a potential lower than the low voltage detection level in the DC-DC converter of the embodiment. [Figure 5] 10A and 10B are timing charts showing the relationship between the error amplifier output and the waveform signal (triangular wave) and the change in the PWM drive pulse when the FB voltage drops to a potential lower than the low voltage detection level and then recovers in the DC-DC converter of the embodiment, where (A) is a timing chart when the output current capacity of the error amplifier is temporarily increased, and (B) is a timing chart when the output current capacity of the error amplifier is not temporarily increased. [Figure 6] 1 is a timing chart showing the changes in signals and potentials of various parts when the output voltage drops due to a temporary drop in the input voltage in a conventional switching regulator type DC-DC converter. [Figure 7]1 is a circuit diagram showing the configuration of a DC-DC converter having a function of preventing an over-short circuit of the output voltage immediately after recovery from a reduced output state, which was studied prior to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. FIG. 1 shows an embodiment of a switching regulator type DC-DC converter to which the present invention is applied.

[0016] The DC-DC converter of this embodiment includes a coil L1 as an inductor, a drive switch transistor M1 consisting of an N-channel MOSFET (insulated gate field effect transistor) connected between a voltage input terminal IN to which a DC input voltage VIN is applied and one terminal of the coil L1 and for supplying a drive current to the coil L1, and a rectifier switch transistor M2 consisting of an N-channel MOSFET connected between one terminal of the coil L1 and a ground point. Also, a smoothing capacitor C1 is connected between the other terminal (output terminal OUT) of the coil L1 and the ground point, and a stabilizing capacitor C0 is connected between the voltage input terminal IN and the ground point.

[0017] The DC-DC converter also includes a switching control circuit 10 that generates signals for controlling the on / off of the switch transistors M1 and M2, driver circuits DRV1 and DRV2 that drive the switch transistors M1 and M2 on / off based on the switching control signals generated by the control circuit 10, and an internal power supply circuit 20 that generates an operating voltage for the internal circuit based on an input voltage VIN. Although not particularly limited, in this embodiment, the elements constituting the switching control circuit 10 and the driver circuits DRV1 and DRV2, and the switch transistors M1 and M2 are formed on a single semiconductor chip to form a semiconductor integrated circuit (power supply control IC). The coil L1, capacitor C0, and smoothing capacitor C1 are connected as external elements to external terminals provided on the power supply control IC.

[0018] In the DC-DC converter of this embodiment, drive pulses that complementarily turn on and off the switch transistors M1 and M2 are generated by the driver circuits DRV1 and DRV2 and applied to the gate terminals of M1 and M2. Under normal operating conditions, when the drive transistor M1 is turned on, a DC input voltage VIN is applied to the coil L1, causing a current to flow toward the output terminal OUT and charging the smoothing capacitor C1. When the switch transistor M1 is turned off, the rectifying switch transistor M2 is turned on instead, causing a current to flow through the coil L1 via the turned-on transistor M2. As a result, an output voltage VOUT of a preset potential is output from the output terminal OUT.

[0019] The switching control circuit 10 includes a voltage divider circuit 11 made up of resistors R1 and R2 connected in series between a terminal VO to which a voltage VOUT output from an output terminal OUT is applied and a ground point, and an error amplifier 12 that receives as inputs a voltage VFB generated by the voltage divider circuit 11 and a reference voltage VREF1, and outputs a voltage corresponding to the potential difference between VFB and VREF1. The switching control circuit 10 also includes a waveform generating circuit 13 that generates a waveform signal of a predetermined frequency such as a triangular wave, a PWM comparator 14 that compares the generated triangular wave with the output of the error amplifier 12 to generate a control pulse, and a logic circuit 15 that generates a signal for driving and controlling the driver circuits DRV1 and DRV2 based on the generated control pulse.

[0020] Furthermore, the switching control circuit 10 includes a low-voltage protection circuit 16 that detects a low-voltage state in which the output voltage VOUT has dropped below a predetermined potential VLVP based on the voltage VFB generated by the voltage division circuit 11 and stops the output, and a recovery circuit 17 having a soft-start function that raises the output voltage VOUT while preventing an overshoot of the output when recovering from the low-voltage state of the output. Note that VLVP < VREF1. When the low-voltage protection circuit 16 detects the low-voltage state of the output, a shutdown signal SD is supplied to the logic circuit 15, and the logic circuit 15 stops the output by maintaining the driving switch transistor M1 and the rectifying transistor M2 in the off state.

[0021] The error amplifier 12 used has one inverting input terminal (-) and two non-inverting input terminals (+). The voltage VFB generated by the voltage division circuit 11 is input to the inverting input terminal (-), the reference voltage VREF1 is applied to one of the non-inverting input terminals (+), and the recovery circuit 17 is connected to the other non-inverting input terminal (+). In addition, the converter power supply control IC constituting the DC-DC of the present embodiment is provided with an external terminal SS to which an external capacitor C5 for setting the soft-start time is connected, and the above recovery circuit 17 is connected to this terminal SS. Note that the capacitor C2 and the resistor R3 connected in series between the output terminal of the error amplifier 12 and the ground point constitute a phase compensation circuit.

[0022] FIG. 2 shows a specific circuit configuration example of the above recovery circuit 17 together with the error amplifier 12. The circuit excluding the voltage division circuit 11 and the error amplifier 12 from the configuration shown in FIG. 2 is the recovery circuit 17. As shown in FIG. 2, the recovery circuit 17 includes an amplifier AMP1 for soft start and an amplifier AMP2 that constitutes a clamp circuit for clamping the output voltage of the error amplifier 12. The output of the error amplifier 12 is input to the non-inverting input terminal (+) of the amplifier AMP2, and a constant voltage VCLP that gives a clamp level is input to the inverting input terminal (-).

[0023] Furthermore, a MOS transistor M4 is connected between the output terminal of the error amplifier 12 and the ground, and the output voltage of the amplifier AMP2 is applied to the gate terminal of M4. As a result, when the output voltage of the error amplifier 12 exceeds the voltage VCLP, the amplifier AMP2 turns on the transistor M4 to clamp the voltage COMP supplied from the error amplifier 12 to the PWM comparator in the subsequent stage to the voltage VCLP. Therefore, the amplifier AMP2 and the transistor M4 form a clamp circuit (referred to in this specification as a COMP clamp circuit) that clamps the output voltage of the error amplifier 12. Note that VCLP>VREF1.

[0024] Amplifier AMP2 also functions as a comparator that compares the output voltage of error amplifier 12 with voltage VCLP. When the output voltage of error amplifier 12 reaches voltage VCLP, the output signal of amplifier AMP2 rises, and this signal is fed back to error amplifier 12 and amplifier AMP1 to turn the amplifier operation on and off. Of these, a one-shot pulse generating circuit 18 is provided to input the output signal of amplifier AMP2 to turn on and off error amplifier 12, and a one-shot pulse OSP having a predetermined pulse width is generated in synchronization with the falling edge of the output signal of amplifier AMP2, and this pulse signal is configured to temporarily increase the output current capacity of error amplifier 12. This function can be realized, for example, by providing two current sources that supply the operating current for error amplifier 12, and configuring so that only one current source is turned on in the normal operating state, and the other current source is turned on when the one-shot pulse OSP is generated.

[0025] The amplifier AMP1 for soft start has one non-inverting input terminal (+) and two inverting input terminals (-). The external terminal SS is connected to the non-inverting input terminal (+). The voltage VFB generated by the voltage divider circuit 11 is input to one of the inverting input terminals (-). The reference voltage VREF2 is applied to the other inverting input terminal (-). <VREF2<VREF1である。 Also, a constant current source CC0 and a MOS transistor M3 are connected in series between an internal power supply voltage terminal VDD and a ground point, and a connection node N1 between the constant current source CC0 and the transistor M3 is connected to an external terminal SS.

[0026] Thereby, when VFB < VREF2, the amplifier AMP1 operates the transistor M3 so that the voltage VSS of the terminal SS matches VREF2, and fixes VSS to VREF2. Also, when VFB > VREF2, the amplifier AMP1 operates the transistor M3 so that the voltage VSS of the terminal SS matches the output feedback voltage VFB, and fixes VSS to VFB. Therefore, a kind of clamp circuit (referred to as an SS clamp circuit in this specification) is constituted by the constant current source CC0, the transistor M3, and the amplifier AMP1. Also, the voltage VSS of the terminal SS becomes a soft start voltage for slowly rising the output voltage when power is turned on.

[0027] Also, an output signal of an amplifier AMP2 of a COMP clamp circuit is supplied to the amplifier AMP1 as an on / off control signal ON / OFF, and the amplifier AMP1 operates only during the period when the output signal of the amplifier AMP2 is at a high level and the COMP clamp circuit clamps the output of the error amplifier 12. Therefore, a soft start circuit is constituted by the SS clamp circuit and the amplifier AMP2 of the COMP clamp circuit that controls its operation. Also, the amplifier AMP2 functions as state detection means capable of detecting a state where the output voltage exceeds a predetermined potential.

[0028] On the other hand, the error amplifier 12 has a voltage VFB generated by a voltage dividing circuit 11 input to an inverting input terminal (−), the voltage VSS of the external terminal SS input to one of two non-inverting input terminals (+), and a reference voltage VREF1 applied to the other inverting input terminal (−). Thereby, the error amplifier 12 operates to output a voltage corresponding to the potential difference between VFB and VREF1 when VSS > VREF1, and output a voltage corresponding to the potential difference between VFB and VSS when VSS < VREF1. In the circuit of FIG. 2, a capacitor C3 is connected between the output terminal of the amplifier AMP1 and the ground point, and a capacitor C4 is connected between the output terminal of the amplifier AMP2 and the ground point.

[0029] Next, the operation of the recovery circuit 17 when an abnormal state occurs in which the output voltage VOUT decreases and then VOUT recovers will be described using the timing charts of FIGS. 3 to 5. Note that FIG. 3 shows the changes in the signals and potentials of each part when the FB voltage decreases to a potential slightly higher than the reference voltage VREF2 in the DC-DC converter of the present embodiment, and FIG. 4 shows the changes in the signals and potentials of each part when the FB voltage decreases to a potential lower than the low voltage detection level VLVP.

[0030] In a PWM type DC-DC converter, as described above, when the output voltage VOUT significantly decreases, the output voltage COMP of the error amplifier 12 rises above the maximum voltage of the triangular wave signal RAMP and the output voltage cannot be controlled. In the DC-DC converter of the present embodiment (FIG. 2), when the COMP voltage rises above the clamp voltage VCLP by the amplifier AMP2, it enters a mode of controlling the voltage VSS of the SS terminal according to the voltage VFB obtained by dividing the output voltage VOUT. At this time, if VREF2 ≦ VFB < VREF1, the voltage VSS of the SS terminal is controlled by the amplifier AMP1 of the SS clamp circuit so that VSS = VFB. On the other hand, if VFB < VREF2, the voltage VSS is controlled so that VSS = VREF2 voltage.

[0031] 3, when the FB voltage VFB drops to the reference voltage VREF2 (e.g., 0.8 V) or a potential slightly higher than that, the output voltage COMP of the error amplifier 12 rises as VFB drops, and when COMP rises to a clamp voltage VCLP (e.g., 1.6 V) (timing t1), COMP is clamped to VCLP by the amplifier AMP2 of the COMP clamp circuit. At this time, the output (ON / OFF) of the amplifier AMP2 goes high, activating the amplifier AMP1 of the SS clamp circuit, turning on the transistor M3 and extracting the charge from the capacitor C5, causing the voltage VSS of the SS terminal to drop rapidly and be clamped to VSS=VFB.

[0032] After that, when the abnormal state (low output voltage state) is resolved and the FB voltage VFB begins to rise, the error amplifier 12 outputs a voltage according to the potential difference between VFB and VSS, causing COMP to begin to fall, and the downstream PWM comparator begins generating duty-controlled pulses, causing the output voltages VOUT and VFB to rise. Then, the output (ON / OFF) of amplifier AMP2 in the COMP clamp circuit changes to low level, and the operation of amplifier AMP1 in the SS clamp circuit is stopped (timing: t2). This turns off transistor M3 and charges external capacitor C5 at the SS terminal, causing voltage VSS to rise. Note that immediately after VFB starts to rise, VFB temporarily becomes higher than VSS because voltage COMP drops and the signal for duty control of the drive pulse according to the input / output voltage difference cannot be output immediately.

[0033] Then, afterwards, when the VFB slowly rises and reaches VREF1 (e.g., 1.2V), the error amplifier 12 outputs a voltage corresponding to the potential difference between VFB and VREF1, so that the output voltage VOUT is controlled to become a predetermined set voltage. Note that even after the timing: t3 when the output voltage VOUT reaches a predetermined voltage, the operation of the amplifier AMP1 stops and the transistor M3 is turned off. Therefore, the voltage VSS of the SS terminal continues to rise, and when the externally connected capacitor C5 of the SS terminal reaches a fully charged state at the timing: t4, it then maintains a constant voltage.

[0034] As shown in FIG. 4, when the voltage VFB drops to a potential lower than the low-voltage detection level VLVP (e.g., 0.4V) and then recovers, as the FB voltage VFB drops, the output voltage COMP of the error amplifier 12 rises and is clamped to COMP = VCLP by the amplifier AMP2 of the COMP clamp circuit (timing: t1). Also, at this time, when the output of the amplifier AMP2 becomes a high level, the amplifier AMP1 of the SS clamp circuit is put into an operating state, the transistor M3 is turned on, the charge of the capacitor C5 is extracted, and the voltage VSS of the SS terminal rapidly drops and is clamped to VSS = VREF2.

[0035] Afterwards, at the timing: t2, when the abnormal state (low-voltage state of the output) is eliminated and returns, the VFB once rises until the output voltage becomes VFB > VSS, and then afterwards, VFB slowly rises in the same manner as in the case of FIG. 3. At this time, if it takes time for VFB to rise, there is a risk that the low-voltage protection circuit 16 will detect the low-voltage state and stop the output. Here, the condition for the low-voltage protection circuit 16 not to detect the low-voltage state is that if the period from timing: t1 - t2 is T1 and the delay time TDLY (e.g., 1.0 ms) by the low-voltage protection circuit 16, then T1 < TDLY. Therefore, in the DC-DC converter of this embodiment, immediately after the release of the low-voltage state, VFB is once raised to VREF2 so as not to detect the low-voltage state.

[0036] This shortens T1, avoids detection of a low voltage state by low voltage protection circuit 16, and allows normal operation to be restored without stopping the output. Also, by temporarily increasing the output current capability of error amplifier 12, it is possible to shorten the time it takes for output COMP of error amplifier 12 to drop to a level at which the output voltage can be controlled (a level lower than the maximum value of the triangular wave signal input to the PWM comparator), thereby improving the responsiveness of duty control by the PWM comparator and preventing overshoot of the output voltage.

[0037] 5A shows the relationship between the output COMP of error amplifier 12 and the waveform signal (triangular wave) RAMP and the change in the PWM drive pulse when the FB voltage, which is proportional to the output voltage VOUT, drops to a potential lower than the low voltage detection level VLVP and then recovers in the DC-DC converter of this embodiment. Also, FIG. 5B shows the relationship between the output COMP of error amplifier 12 and the waveform signal (triangular wave) RAMP and the change in the PWM drive pulse when the output current capability of error amplifier 12 is not temporarily increased immediately after the low voltage state is released. Comparing (A) and (B) in FIG. 5, it can be seen that in the DC-DC converter of this embodiment, which is configured to temporarily increase the output current capability of the error amplifier 12, it is possible to shorten the time T2 required for the output COMP of the error amplifier 12 to fall to a level at which appropriate duty control is possible.

[0038] Although the invention made by the present inventor has been specifically described above based on the embodiments, the present invention is not limited to the above embodiments. For example, in the above embodiments, the output of amplifier AMP1 constituting the SS clamp circuit is input to the gate terminal of transistor M3, which is connected in series with constant current source CC0 constituting the soft start circuit. However, if the IC has an external terminal (chip enable terminal) for inputting an enable signal to put the IC into an operating state, a signal obtained by logically ORing the output of amplifier AMP1 and the signal of the enable terminal may be input to the gate terminal of transistor M3. In the above embodiment, the low voltage protection circuit 16 detects the low voltage state of the output voltage based on the feedback voltage VFB, but the low voltage state of the output voltage may be detected by directly monitoring the output voltage.

[0039] Furthermore, in the above embodiment, the transistors M1 and M2 are on-chip elements, but the IC may be configured so that they are used as external elements. Furthermore, in the above embodiment, an example has been described in which the present invention is applied to a step-down DC-DC converter, but the present invention is not limited to this, and the soft-start circuit and the like can also be applied to step-up or inverting DC-DC converters that generate negative voltages, as well as linear regulators. [Explanation of symbols]

[0040] 10... Switching control circuit, 11... Voltage divider circuit, 12... Error amplifier, 13... Waveform generation circuit, 14... PWM comparator (state detection means), 15... Logic circuit, 16... Low voltage protection circuit, 17... Recovery circuit, 18... One-shot pulse generation circuit, DRV1, DRV2... Driver circuit, M1... Drive switch transistor (drive switching element), M2... Synchronous rectification switch transistor (rectification switching element), AMP1... Amplifier constituting soft start circuit, AMP2... Amplifier constituting clamp circuit

Claims

1. a soft start circuit for generating a soft start voltage for controlling the conduction of the drive switching element when the voltage of the voltage input terminal rises in a DC power supply device comprising: an error amplifier circuit to which a feedback voltage corresponding to an output voltage and a predetermined first reference voltage are input; a drive switching element provided between a voltage input terminal and a voltage output terminal; and a control circuit for controlling the drive switching element based on the output of the error amplifier circuit; a state detection means capable of detecting a state in which the output voltage of the error amplifier circuit exceeds a predetermined potential; a soft start circuit that generates the soft start voltage in response to detection by the state detection means that the output voltage of the error amplifier circuit has returned from a state in which it exceeded a predetermined potential.

2. 2. The soft start circuit according to claim 1, wherein the state detection means is a clamp circuit that fixes the output voltage of the error amplifier circuit to a predetermined potential when the output voltage of the error amplifier circuit reaches the predetermined potential.

3. a constant current source, a capacitor charged by the current of the constant current source, a transistor for discharging the charge of the capacitor, and a differential amplifier circuit having as inputs a charge voltage of the capacitor, the feedback voltage, and a second reference voltage lower than the first reference voltage; The charging voltage of the capacitor is input to the error amplifier circuit, The differential amplifier circuit When the feedback voltage drops to a level close to the second reference voltage, the transistor is controlled to make the charging voltage of the capacitor equal to the feedback voltage; 3. The soft start circuit according to claim 2, wherein when the feedback voltage drops below the second reference voltage, the soft start circuit controls the transistor so as to make the charging voltage of the capacitor equal to the second reference voltage.

4. A DC-DC converter comprising: an error amplifier circuit receiving as input a feedback voltage corresponding to an output voltage and a predetermined first reference voltage; a drive switching element provided between a voltage input terminal and a voltage output terminal; a control circuit controlling the drive switching element based on the output of the error amplifier circuit; and a soft start circuit generating a soft start voltage for controlling the conduction of the drive switching element when the voltage at the voltage input terminal rises, a state detection means for detecting a state in which the output voltage of the error amplifier circuit exceeds a predetermined potential, and the soft-start circuit generates the soft-start voltage in response to the state detection means detecting that the output voltage of the error amplifier circuit has returned from a state in which it exceeds the predetermined potential.

5. 5. The DC-DC converter according to claim 4, wherein the state detection means is a clamp circuit that fixes the output voltage of the error amplifier circuit to a predetermined potential when the output voltage of the error amplifier circuit reaches a predetermined potential.

6. The soft start circuit comprises: a constant current source, a capacitor charged by the current of the constant current source, a transistor for discharging the charge of the capacitor, and a differential amplifier circuit having as inputs a charge voltage of the capacitor, the feedback voltage, and a second reference voltage lower than the first reference voltage; The charging voltage of the capacitor is input to the error amplifier circuit, when the feedback voltage drops to a level close to the second reference voltage, the differential amplifier circuit controls the transistor so that the charging voltage of the capacitor matches the feedback voltage; 6. The DC-DC converter according to claim 5, wherein when the feedback voltage drops below the second reference voltage, the transistor is controlled so as to make the charging voltage of the capacitor equal to the second reference voltage.

7. 7. The DC-DC converter according to claim 6, wherein the differential amplifier circuit is configured to operate only while the state detection means fixes the output voltage of the error amplifier circuit to the predetermined potential after the output voltage of the error amplifier circuit has reached a predetermined potential.

8. The error amplifier circuit the charging voltage of the capacitor, the feedback voltage, and the first reference voltage are input; When the feedback voltage is higher than the first reference voltage, a voltage corresponding to a difference between the feedback voltage and the first reference voltage is output; 8. The DC-DC converter according to claim 7, wherein when the feedback voltage is lower than the first reference voltage, the DC-DC converter is configured to output a voltage corresponding to a difference voltage between the feedback voltage and a charging voltage of the capacitor.

9. 9. The DC-DC converter according to claim 8, wherein the state detection means is configured so that, after the output voltage of the error amplifier circuit reaches a predetermined potential and the output voltage of the error amplifier circuit is fixed at the predetermined potential, the output current capability of the error amplifier circuit is temporarily increased immediately after the output voltage of the error amplifier circuit falls below the predetermined potential.

10. 10. The DC-DC converter according to any one of claims 4 to 9, wherein the control circuit comprises: a PWM comparator that compares the output voltage of the error amplifier circuit with a waveform signal of a predetermined cycle to generate a duty-controlled pulse signal that controls the on / off of the drive switching element; and a low-voltage detection circuit that detects a low-voltage state in which the output voltage is lower than a predetermined voltage based on the feedback voltage or the output voltage, and is configured to fix the drive switching element to an off state and stop output when the low-voltage detection circuit detects a low-voltage state of the output.

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