TS synthesizer and broadcasting system

Abstract

To provide a TS synthesizer and a broadcasting system that can synchronize the internal SF phase between TS synthesizers without relying on an SF synchronization signal generator.SOLUTION: A TS synthesizer is a redundantly configured TS (Transport Stream) synthesizer, and includes generating means for generating an internal phase using a clock signal within the entrusted station, and setting means for setting the internal phase generated by the generating means of the TS synthesizing device that has been started first among multiple redundantly configured TS synthesizer as the internal phase to be used by the device itself.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present disclosure relates to a TS synthesizing device and a broadcasting system that synthesizes TS signals. [Background technology]

[0002] Satellite broadcasting uses the ISDB (Integrated Services Digital Broadcasting)-S format. A transport stream (TS) signal structured for satellite broadcasting is sent from a signal processing device (hereinafter referred to as a transmitting signal processing device) of a broadcasting company (hereinafter referred to as a commissioned station) and transmitted to an uplink station (hereinafter referred to as a commissioned station). At the commissioned station, a TS synthesizer synthesizes the TS signals from multiple commissioned stations. The combined TS signal is then transmitted from the transmission equipment to a broadcasting satellite. Hereinafter, the TS signal will be referred to as TS.

[0003] The clock signal at the entrusting station and the clock signal at the entrusted station must be synchronized in frequency. If the synchronization between the entrusting station and the entrusted station is lost, an overflow or underflow occurs in the input buffer of the TS synthesizer. When an overflow or underflow occurs, video freezes or audio mutes. Hereinafter, video freezes and the like are referred to as video noise. Audio mutes and the like are referred to as audio noise.

[0004] The transmitting signal processing device generates a TS with a superframe (hereinafter referred to as SF) structure synchronized with the clock signal at the entrusted station and transmits the generated TS to the entrusted station. If the entrusted station uses the pseudo-synchronization method, a TS pseudo-synchronization device is installed. The TS pseudo-synchronization device regenerates (reconstructs) the TS transmitted by the transmitting signal processing device into a TS synchronized with the clock signal at the entrusted station and outputs it to the TS synthesis device.

[0005] The SF phase is generated in the trustee station. The SF phase is used for the signal output operation of the device. Hereinafter, the SF phase held by each device in the trustee station is referred to as the internal SF phase.

[0006] In order to ensure stable operation, the entrusted station is provided with two systems: a working system (N system) and a backup system (E system). Therefore, the entrusted station has a TS synthesizer for the N system and a TS synthesizer for the E system. For example, when a fault occurs in the N system, the N system and the E system are switched over, and the E system becomes the working system. For example, Patent Document 1 describes an example in which two TS synthesizers are used as a redundant configuration. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-070052 Summary of the Invention [Problem to be solved by the invention]

[0008] A typical redundant configuration of TS synthesizers uses a reference synchronization configuration to synchronize the internal SF phases of the two TS synthesizers. In a reference synchronization configuration, the internal SF phases of the two TS synthesizers are synchronized based on the SF phase generated by the SF synchronization signal generator.

[0009] However, the SF synchronization signal generator is not configured redundantly. Therefore, if the SF synchronization signal generator fails, a phase shift in the internal SF phase may occur between the N-system TS synthesizer and the E-system TS synthesizer, causing synchronization to be lost. More precisely, if either the N-system TS synthesizer or the E-system TS synthesizer is restarted after the SF synchronization signal generator fails, a phase shift in the internal SF phase may occur between the N-system TS synthesizer and the E-system TS synthesizer, causing synchronization to be lost. This disrupts the continuity between the TS from the N-system TS synthesizer and the TS from the E-system TS synthesizer. As a result, one SF worth of packets may be duplicated or missing immediately after the system switchover. This duplicated or missing packets may cause video or audio noise.

[0010] Fig. 12 is an explanatory diagram showing an example in which a phase shift occurs between the internal SF phases of two TS synthesizers. Fig. 12 shows the SF phase output by the SF synchronization signal generator, the internal SF phase of the TS synthesizer for system 1, and the internal SF phase of the TS synthesizer for system 2.

[0011] When the TS synthesizer for System 1 starts up, it inputs the SF phase generated by the SF synchronization signal generator and synchronizes its internal SF phase with the input SF phase. Just like the TS synthesizer for System 1, when the TS synthesizer for System 2 starts up, it inputs the SF phase generated by the SF synchronization signal generator and synchronizes its internal SF phase with the input SF phase. As a result, the internal SF phases of the TS synthesizer for System 1 and the TS synthesizer for System 2 are synchronized.

[0012] After that, the SF synchronization signal generator is restarted, for example, due to a failure or maintenance. The TS synthesizer maintains an internal SF phase synchronized with the SF phase input at startup. Therefore, the TS synthesizer for system 1 and the TS synthesizer for system 2 can maintain synchronized internal SF phases as long as there is no problem with the clock. However, a phase shift occurs between the SF phase generated by the SF synchronization signal generator and the internal SF phases of the TS synthesizer for system 1 and the TS synthesizer for system 2. Specifically, the SF synchronization signal generator outputs an internally generated SF phase without inputting an external SF phase at startup (or restart). Therefore, the SF phase output by the SF synchronization signal generator after restart does not match the SF phase output before restart. This causes a phase shift to occur between the SF phase output by the SF synchronization signal generator and the internal SF phase of the TS synthesizer.

[0013] If one of the TS synthesizers restarts after the SF synchronization signal generator restarts, a phase shift occurs in the internal SF phases of the two TS synthesizers. For example, after the SF synchronization signal generator restarts, only the TS synthesizer for system 1 restarts. Then, when the TS synthesizer for system 1 starts up, it synchronizes its internal SF phase with the SF phase generated by the SF synchronization signal generator after the restart. On the other hand, the TS synthesizer for system 2 synchronizes its internal SF phase with the SF phase generated by the SF synchronization signal generator before the restart. As a result, a phase shift (phase difference) occurs between the internal SF phase of the TS synthesizer for system 1 and the internal SF phase of the TS synthesizer for system 2.

[0014] An object of the present disclosure is to provide a TS synthesizer and a broadcasting system that can synchronize the internal SF phase between TS synthesizers without relying on an SF synchronization signal generator. [Means for solving the problem]

[0015] The TS synthesizing device according to the present disclosure is a redundantly configured TS (Transport Stream) synthesizing device that includes a generating means for generating an internal phase using a clock signal within a trustee station, and a setting means for setting the internal phase generated by the generating means of the TS synthesizing device that was started first among a plurality of redundantly configured TS synthesizing devices as the internal phase to be used by the device itself.

[0016] The broadcasting system according to the present disclosure includes a clock signal generating unit that generates a clock signal and a TS synthesizing device that synthesizes TSs (Transport Streams), and the TS synthesizing device includes a generating means that generates an internal phase using the clock signal generated by the clock signal generating unit, and a setting means that sets the internal phase generated by the generating means of the TS synthesizing device that was started first among multiple redundantly configured TS synthesizing devices as the internal phase to be used by the device itself. [Effects of the Invention]

[0017] According to the present disclosure, the internal SF phases of TS synthesizers can be synchronized with each other. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a system configuration diagram showing a system including a trustee station and a trustee station having a TS synthesizing device with a general redundant configuration. [Figure 2] FIG. 1 is a block diagram showing an example of the configuration of a general TS synthesizing device. [Figure 3] 1 is a system configuration diagram showing a system including a trustee station and a trustee station having a redundantly configured TS synthesizing device according to the present disclosure. [Figure 4] 1 is a block diagram showing an example of the configuration of a TS synthesizing device according to the present disclosure. [Figure 5] FIG. 10 is an explanatory diagram showing a specific example of an SF phase. [Figure 6] FIG. 10 is a flow chart showing an example of the operation of the TS synthesizing device. [Figure 7] FIG. 10 is a timing diagram showing an example of setting an internal SF phase of a TS synthesizer. [Figure 8] FIG. 10 is a timing diagram showing an example of setting an internal SF phase of a TS synthesizer. [Figure 9] FIG. 10 is an explanatory diagram showing an example of control for pulling in an internal SF phase from a TS synthesizer of another system. [Figure 10] FIG. 1 is a block diagram showing the main parts of a TS synthesizing device. [Figure 11] 1 is a block diagram showing the main parts of a broadcasting system. [Figure 12] FIG. 10 is an explanatory diagram showing an example in which a phase shift occurs between the internal SF phases of two TS synthesizers. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0020] Fig. 1 is a system configuration diagram showing a system including a consigned station and a commissioned station, each having a typical redundantly configured TS synthesizing device. Fig. 1 shows a consigned station 100, commissioned stations 200 and 210, and a transmission facility 300. The transmission facility 300 transmits the TS received from the consigned station 100 to a broadcasting satellite.

[0021] The entrusted station 100 is provided with an N-system TS pseudo synchronizer 101, an E-system TS pseudo synchronizer 102, a clock signal generator 110, an SF synchronization signal generator 120, an N-system TS synthesizer 130, and an E-system TS synthesizer 131.

[0022] The TS pseudo-synchronizers 101 and 102 reconstruct the TS transmitted by the entrusted station 200 into a TS synchronized with the clock signal in the entrusted station, and output the reconstructed TS to the TS synthesizers 130 and 131 .

[0023] The clock signal generator 110 generates a clock signal and supplies the clock signal to the TS pseudo synchronizers 101 and 102, the SF synchronization signal generator 120, and the TS synthesizers 130 and 131. The dotted lines in Fig. 1 indicate the supply of the clock signal.

[0024] The SF synchronization signal generator 120 generates an SF phase signal based on the clock signal. The SF phase signal is supplied to the TS synthesizers 130 and 131.

[0025] The TS synthesizers 130 and 131 have a redundant configuration. A redundant configuration is one in which multiple devices are provided so that operation can continue even if one device fails. The TS synthesizers 130 and 131 select either the TS output by the N-system TS pseudo synchronizer 101 or the TS output by the E-system TS pseudo synchronizer 101. The TS synthesizers 130 and 131 then synthesize input TSs from multiple commissioned stations. The TS synthesizers 130 and 131 transmit the synthesized TS to the transmission equipment 300.

[0026] The entrusted station 200 is provided with an N-system transmitting side signal processing device (not shown) and an E-system transmitting side signal processing device (not shown). The N-system transmitting side signal processing device and the E-system transmitting side signal processing device generate TSs synchronized with a clock signal supplied within the entrusted station 200, and transmit the TSs to the entrusted station 100.

[0027] The entrusted station 210 has the same configuration as the entrusted station 200. Although two entrusted stations 200 and 210 are shown in Fig. 1, there may be three or more entrusted stations. When there are two or more entrusted stations, the entrusted station 100 has an N-system TS pseudo-synchronization device and an E-system TS pseudo-synchronization device corresponding to each entrusted station.

[0028] Fig. 2 is a block diagram showing an example of the configuration of the general TS synthesizer 130 shown in Fig. 1. The TS synthesizer 130 includes a TS multiplexing section 1301 and an internal SF phase generation section 1302. The TS synthesizer 131 shown in Fig. 1 is configured in the same way as the TS synthesizer 130. Note that the arrows in Fig. 2 simply indicate the direction of signal (data) flow, but do not exclude bidirectionality. This also applies to other block diagrams.

[0029] The TS multiplexing unit 1301 multiplexes a plurality of input TSs using the internal SF phase generated by the internal SF phase generating unit 1302 and outputs the multiplexed TSs.

[0030] The internal SF phase generation unit 1302 receives an SF phase signal generated by the SF synchronization signal generator 120 of the trustee station 100. The internal SF phase generation unit 1302 receives a clock signal generated by the clock signal generator 110 of the trustee station 100. The internal SF phase generation unit 1302 generates an internal SF phase using the clock signal based on the SF phase signal. That is, the internal SF phase generation unit 1302 synchronizes the internal SF phase with the SF phase generated by the SF synchronization signal generator 120.

[0031] 1 and 2, a reference synchronization configuration is employed to synchronize the internal SF phases of the two TS synthesizers 130 and 131. In the reference synchronization configuration, the internal SF phases of the two TS synthesizers 130 and 131 are synchronized based on the SF phase generated by the SF synchronization signal generator 120.

[0032] However, the SF synchronization signal generator 120 is not configured redundantly. Therefore, if the SF synchronization signal generator 120 fails, it may become impossible to synchronize the internal SF phases of the TS synthesizers 130 and 131. As a result, depending on the timing of system switching of the TS synthesizers, duplication or loss of packets for one SF may occur, which may result in video noise or audio noise.

[0033] FIG. 3 is a system configuration diagram showing a system including a trustee station and a trustee station, each having a TS synthesizing device with a redundant configuration according to this embodiment.

[0034] The configuration of this embodiment shown in Fig. 3 differs from the configuration of the entrusted station 100 shown in Fig. 1 in that the entrusted station 100A does not include an SF synchronization signal generator 120. Furthermore, the entrusted station 100A includes TS synthesizers 140 and 141 instead of the general TS synthesizers 130 and 131 shown in Fig. 1.

[0035] 4 is a block diagram showing an example of the configuration of the TS synthesizing device 140 of this embodiment. The TS synthesizing device 140 includes a TS multiplexing unit 1401, an internal SF phase generating unit 1402, and an internal SF phase setting unit 1403. The TS synthesizing device 141 shown in FIG. 3 is configured similarly to the TS synthesizing device 140.

[0036] The TS multiplexing unit 1401 multiplexes and outputs a plurality of input TSs using the internal SF phase set by the internal SF phase setting unit 1403 .

[0037] The internal SF phase generator 1402 receives the clock signal generated by the clock signal generator 110 of the trustee station 100A. The internal SF phase generator 1402 generates an internal SF phase using the clock signal. As an example, the internal SF phase generator 1402 is realized by a counter circuit.

[0038] 5 is an explanatory diagram showing a specific example of the SF phase. In this embodiment, the SF phase is expressed by counting up the count value of a counter based on the clock signal output from the clock signal generating device 110.

[0039] The internal SF phase generator 1402 sets the count value to 0 when the TS synthesizer 140 is started up. The internal SF phase generator 1402 counts up the count value (i.e., adds 1) at a clock timing of, for example, 56.61 MHz. When the count value reaches 626,687, the internal SF phase generator 1402 increments the SF number and resets the count value. Thereafter, the internal SF phase generator 1402 counts up again from the count value 0. The count value at this time corresponds to the SF phase.

[0040] The internal SF phase setting unit 1403 sets the internal SF phase to be used by its own device (i.e., the TS synthesizer 140). The internal SF phase setting unit 1403 sets the internal SF phase generated by the TS synthesizer that started up first among multiple redundantly configured TS synthesizers (e.g., the TS synthesizers 140 and 141) as the internal SF phase to be used by its own device. The internal SF phase setting unit 1403 may be realized by hardware (e.g., an electronic circuit, etc.), or may be realized by a combination of hardware and software (e.g., a combination of an electronic circuit and a program that controls it, etc.).

[0041] For example, the internal SF phase setting unit 1403 transmits and receives packets with its own count value set to TS synthesizers of other systems. The internal SF phase setting unit 1403 also determines the TS synthesizer that started first based on the count value extracted from the received packet.

[0042] For example, the internal SF phase setting unit 1403 determines that its own device (i.e., the TS synthesizer 140) has started up before the TS synthesizer of the other system (i.e., the TS synthesizer 141). In this case, the internal SF phase setting unit 1403 sets the internal SF phase generated by the internal SF phase generation unit 1402 of its own device as the internal SF phase to be used by its own device.

[0043] For example, the internal SF phase setting unit 1403 determines that its own device (i.e., the TS synthesizer 140) is running simultaneously with a TS synthesizer of another system (i.e., the TS synthesizer 141). In this case, the internal SF phase setting unit 1403 sets the internal SF phase generated by the internal SF phase generation unit 1402 of its own device as the internal SF phase to be used by its own device.

[0044] For example, the internal SF phase setting unit 1403 determines that a TS synthesizer of another system (i.e., the TS synthesizer 141) has started up before its own system (i.e., the TS synthesizer 140). In this case, the internal SF phase setting unit 1403 sets the internal SF phase generated by the internal SF phase generation unit 1402 of the TS synthesizer of the other system as the internal SF phase to be used in its own system. In other words, the internal SF phase setting unit 1403 synchronizes the internal SF phase of its own system with the internal SF phase generated and used by the TS synthesizer of the other system.

[0045] In this embodiment, when synchronizing the internal SF phase of the TS synthesizer of the other system with the internal SF phase of the own system, the count value of the own system is synchronized with the count value of the TS synthesizer of the other system. Hereinafter, this operation is also referred to as pulling in the internal SF phase (or count value) of the TS synthesizer of the other system.

[0046] Next, the operation of the TS synthesizer of this embodiment will be described. Fig. 6 is a flow diagram showing an example of the operation of the TS synthesizer. TS synthesizer A and TS synthesizer B shown in Fig. 6 correspond to, for example, the TS synthesizer 140 and TS synthesizer 141 shown in Fig. 3. This also applies to Figs. 7 to 9. Fig. 6 shows an example of the operation of TS synthesizer A (TS synthesizer 140), but TS synthesizer B (TS synthesizer 141) also operates in the same way.

[0047] When the TS synthesizer A is started up, it transmits a start-up packet to the synthesizer B of the other system (step S1).

[0048] If the internal SF phase setting unit 1403 of the TS synthesizer A does not receive a startup packet from the TS synthesizer B (N in step S2) or a response packet (N in step S3) within a predetermined period (for example, 10 msec or 20 msec) after the transmission of the startup packet, it determines that the TS synthesizer B is not started. In other words, the internal SF phase setting unit 1403 determines that the TS synthesizer A started before the TS synthesizer B. In this case, the internal SF phase setting unit 1403 of the TS synthesizer A sets the internal SF phase generated by the internal SF phase generation unit 1402 of the TS synthesizer A as the internal SF phase to be used by the TS synthesizer A (step S4). Thereafter, the TS synthesizer A operates using the set internal SF phase.

[0049] If the internal SF phase setting unit 1403 of the TS synthesizer A does not receive a startup packet from the TS synthesizer B within a predetermined period (for example, 10 msec or 20 msec) after the transmission of the startup packet (N in step S2), but receives a response packet (Y in step S3), it determines that the TS synthesizer B is started up. In other words, the internal SF phase setting unit 1403 determines that the TS synthesizer B has started up before the TS synthesizer A. In this case, the internal SF phase setting unit 1403 of the TS synthesizer A pulls in the internal SF phase generated and used by the internal SF phase generation unit 1402 of the TS synthesizer B, and sets it as the internal SF phase to be used by the TS synthesizer A (step S5). Thereafter, the TS synthesizer A operates with the set internal SF phase.

[0050] If the internal SF phase setting unit 1403 of the TS synthesizer A receives a startup packet from the TS synthesizer B within a predetermined period (for example, 10 msec or 20 msec) from the transmission of the startup packet (Y in step S2), it determines that the TS synthesizer B started up at approximately the same time as the TS synthesizer A. In this case, the internal SF phase setting unit 1403 of the TS synthesizer A compares the count value of the TS synthesizer A with the count value of the TS synthesizer B (step S6).

[0051] Next, if the count value of TS synthesizer A is greater than the count value of TS synthesizer B (Y in step S6), the internal SF phase setting unit 1403 determines that TS synthesizer A started earlier than TS synthesizer B. In this case, the internal SF phase setting unit 1403 of TS synthesizer A sets the internal SF phase generated by the internal SF phase generation unit 1402 of TS synthesizer A as the internal SF phase to be used by TS synthesizer A (step S7). Thereafter, TS synthesizer A operates with the set internal SF phase.

[0052] Furthermore, if the count value of TS synthesizer A is the same as the count value of TS synthesizer B (Y in step S6), the internal SF phase setting unit 1403 determines that TS synthesizer A and TS synthesizer B are running simultaneously. If the count value of TS synthesizer A and the count value of TS synthesizer B are the same, it means that the internal SF phases are already synchronized. In this case, the internal SF phase setting unit 1403 of TS synthesizer A sets the internal SF phase generated by the internal SF phase generation unit 1402 of TS synthesizer A as the internal SF phase to be used by TS synthesizer A (step S7). Thereafter, TS synthesizer A operates using the internal SF phase that has been set.

[0053] On the other hand, if the count value of TS synthesizer A is smaller than the count value of TS synthesizer B (N in step S6), the internal SF phase setting unit 1403 determines that TS synthesizer B started up earlier than TS synthesizer A. In this case, the internal SF phase setting unit 1403 of TS synthesizer A pulls in the internal SF phase generated and used by the internal SF phase generation unit 1402 of TS synthesizer B, and sets it as the internal SF phase to be used by TS synthesizer A (step S8). Thereafter, TS synthesizer A operates with the set internal SF phase.

[0054] 7 is a timing diagram showing an example of setting the internal SF phase of a TS synthesizer, in which TS synthesizer A starts up before TS synthesizer B. In FIG.

[0055] In this embodiment, five types of packets are transmitted and received between TS synthesizers: a startup packet, a response packet, a synchronization packet, a response synchronization packet, and an SF phase packet. A startup packet is a packet that is transmitted to a TS synthesizer of another system at startup. A response packet is a packet that is transmitted as a response when a startup packet is received. A synchronization packet is a packet that is transmitted when synchronizing the internal SF phase with a TS synthesizer of another system. A response synchronization packet is a packet that is transmitted as a response when a synchronization packet is received. An SF phase packet is a packet that is transmitted at predetermined intervals after the internal SF phase has been set. All of these packets comply with the packet format of MPEG-2 TS (MPEG-2 Transport Stream) specified in ISO / IEC 13818-1.

[0056] When the TS synthesizer A is started, it performs clock locking to synchronize with the clock signal supplied from the clock signal generator 110. When clock locking is complete, the internal SF phase generator 1402 of the TS synthesizer A generates an internal SF phase.

[0057] Next, TS synthesizer A (for example, the internal SF phase setting unit 1403) transmits a startup packet to TS synthesizer B. At this time, TS synthesizer B has not yet started up (or clock locking after startup has not been completed). Therefore, TS synthesizer B cannot transmit a response packet in response to the startup packet.

[0058] The internal SF phase setting unit 1403 of the TS synthesizer A does not receive a response packet from the TS synthesizer B within a predetermined period of time after the transmission of the startup packet, so it sets the internal SF phase generated at startup to the internal SF phase to be used. The TS synthesizer A then starts operating using the internal SF phase that it set. Thereafter, the TS synthesizer A (for example, the internal SF phase setting unit 1403) transmits an SF phase packet in which its own internal SF phase (count value) is set to the TS synthesizer B at predetermined intervals.

[0059] Next, TS synthesizer B, which has completed clock locking after startup, transmits a startup packet to TS synthesizer A. Upon receiving the startup packet, TS synthesizer A (for example, the internal SF phase setting unit 1403) transmits a response packet to TS synthesizer B. TS synthesizer A also stops transmitting the SF phase packet and prepares to receive a synchronization packet from TS synthesizer B.

[0060] The synchronization packet and response synchronization packet transmitted and received between TS synthesizers include an SF synchronization counter and an SF response synchronization counter. When the internal SF phase setting unit 1403 of TS synthesizer B receives the response packet, it sets the count value of the TS synthesizer B in the SF synchronization counter of the synchronization packet. Then, TS synthesizer B (for example, the internal SF phase setting unit 1403) transmits the synchronization packet to TS synthesizer A.

[0061] When the internal SF phase setting unit 1403 of the TS synthesizer A receives a synchronization packet, it sets the SF synchronization counter value of the synchronization packet to the SF synchronization counter of the response synchronization packet. The internal SF phase setting unit 1403 of the TS synthesizer A also sets the count value of the TS synthesizer A to the SF response synchronization counter of the response synchronization packet. The TS synthesizer A then transmits the response synchronization packet to the TS synthesizer B. Thereafter, the TS synthesizer A transmits an SF phase packet to the TS synthesizer B at predetermined intervals. The SF phase packet is used, for example, to determine whether or not a phase shift has occurred in the internal SF phase between the TS synthesizers.

[0062] When the internal SF phase setting unit 1403 of the TS synthesizer B receives the response synchronization packet, it sets the count value of the TS synthesizer B based on the value of the SF response synchronization counter included in the response synchronization packet. In other words, the internal SF phase setting unit 1403 controls the pulling in of the internal SF phase (count value) of the TS synthesizer A. After pulling in the internal SF phase of the TS synthesizer A, the TS synthesizer B counts the count value based on the clock signal until pulling in control is performed again. Pulling in control is performed again when the TS synthesizer is restarted or when the internal SF phase is misaligned due to a misalignment of the reference clocks between the two systems, etc. Thereafter, the TS synthesizer B transmits an SF phase packet to the TS synthesizer A at predetermined intervals.

[0063] Fig. 8 is a timing diagram showing an example of setting the internal SF phase of a TS synthesizer. Fig. 8 shows an example in which TS synthesizer A and TS synthesizer B start up at approximately the same time.

[0064] When TS synthesizer A and TS synthesizer B start up at approximately the same time, they transmit startup packets to each other at approximately the same time. Then, TS synthesizer A and TS synthesizer B receive the startup packets within a predetermined period (for example, 10 msec or 20 msec) after transmitting their respective startup packets. In this case, TS synthesizer A and TS synthesizer B determine that they started up at approximately the same time as a TS synthesizer in another system.

[0065] When the internal SF phase setting unit 1403 of the TS synthesizer A receives the startup packet within a predetermined period of time from the transmission of the startup packet, it sets the count value of the SF synchronization counter of the synchronization packet to the TS synthesizer A. Then, the TS synthesizer A transmits the synchronization packet to the TS synthesizer B.

[0066] As with the TS synthesizer A, when the internal SF phase setting unit 1403 of the TS synthesizer B receives a startup packet within a predetermined period of time after the transmission of the startup packet, it sets the count value of the SF synchronization counter of the synchronization packet to that of the TS synthesizer B. Then, the TS synthesizer B transmits the synchronization packet to the TS synthesizer A.

[0067] Next, upon receiving the synchronization packet, the internal SF phase setting unit 1403 of the TS synthesizing device A sets the SF synchronization counter value of the synchronization packet to the SF synchronization counter of the response synchronization packet. Also, the internal SF phase setting unit 1403 of the TS synthesizing device A sets the count value of the TS synthesizing device A to the SF response synchronization counter of the response synchronization packet. Then, the TS synthesizing device A transmits the response synchronization packet to the TS synthesizing device B.

[0068] Similar to the TS synthesizer A, when the internal SF phase setting unit 1403 of the TS synthesizer B receives a synchronization packet, it sets the SF synchronization counter of the response synchronization packet to the value of the SF synchronization count of the synchronization packet. Also, the internal SF phase setting unit 1403 of the TS synthesizer B sets the SF response synchronization counter of the response synchronization packet to the count value of the TS synthesizer B. Then, the TS synthesizer B transmits the response synchronization packet to the TS synthesizer A.

[0069] Next, upon receiving the response synchronization packet, the internal SF phase setting unit 1403 of TS synthesizer A compares the count value of TS synthesizer A with the count value of TS synthesizer B based on the value of the SF response synchronization counter included in the response synchronization packet. If the count value of TS synthesizer B is larger than the count value of TS synthesizer A, the internal SF phase setting unit 1403 of TS synthesizer A performs control to pull in the internal SF phase (count value) of TS synthesizer B. On the other hand, if the count value of TS synthesizer A is larger than the count value of TS synthesizer B or if the values ​​are the same, TS synthesizer A uses the internal SF phase generated by TS synthesizer A as is.

[0070] As with TS synthesizer A, when the internal SF phase setting unit 1403 of TS synthesizer B receives a response synchronization packet, it compares the count value of its own TS synthesizer B with the count value of its own TS synthesizer A based on the value of the SF response synchronization counter included in the response synchronization packet. If the count value of TS synthesizer A is larger than that of TS synthesizer B, the internal SF phase setting unit 1403 of TS synthesizer B performs control to pull in the internal SF phase (count value) of TS synthesizer A. On the other hand, if the count value of TS synthesizer B is larger than or the same as that of TS synthesizer A, TS synthesizer B uses the internal SF phase generated by TS synthesizer B as is.

[0071] In this embodiment, the TS synthesizer is configured to compare its own count value with the count value of a TS synthesizer in another system and synchronize with the one with the larger count value. However, the TS synthesizer may also be configured, for example, to compare its own count value with the count value of a TS synthesizer in another system and synchronize with the one with the smaller count value.

[0072] Next, the control of pulling in the internal SF phase from a TS synthesizer of another system will be described. Fig. 9 is an explanatory diagram showing an example of the control of pulling in the internal SF phase from a TS synthesizer of another system. Fig. 9 shows the control of TS synthesizer B pulling in the internal SF phase (count value) of TS synthesizer A.

[0073] The TS synthesizer B sets the count value k of the TS synthesizer B in the SF synchronization counter of the synchronization packet. s Then, TS synthesizer B transmits the synchronization packet to TS synthesizer A.

[0074] The TS synthesizer A receives the synchronization packet sent by the TS synthesizer B. When the TS synthesizer B generates the synchronization packet (i.e., when the count value k s The time from the time when the TS synthesizer A receives the synchronization packet is called the transmission delay t s Let's say.

[0075] Next, the TS synthesizer A adds the value of the SF synchronization counter of the synchronization packet (count value k s ) is set in the SF response synchronization counter of the response synchronization packet. a Then, the TS synthesizer A transmits a response synchronization packet to the TS synthesizer B. The time from when the TS synthesizer A receives the synchronization packet to when the TS synthesizer A generates the response synchronization packet (i.e., the count value k a The time period from the time of the first transfer to the time of the second transfer) is defined as the processing delay α.

[0076] The TS synthesizer B receives the response synchronization packet sent by the TS synthesizer A. When the TS synthesizer A generates the response synchronization packet (i.e., when the count value k a The time from the time when the TS synthesizer B receives the response synchronization packet is called the transmission delay t a Let's say.

[0077] The TS synthesizer B extracts the value of the SF response synchronization counter from the received response synchronization packet. Next, the TS synthesizer B controls the pulling in of the internal SF phase of the TS synthesizer A. The period from when the TS synthesizer B receives the response synchronization packet to when it starts the control to pull in the internal SF phase of the TS synthesizer A is defined as the processing delay β. The count value of the TS synthesizer B at the time when it starts the control to pull in the internal SF phase of the TS synthesizer A is defined as kb Let's say.

[0078] The count value set in the SF response synchronization counter of the response synchronization packet by the TS synthesizer A is k s However, the control of the TS synthesizer B to pull in the internal SF phase (count value) of the TS synthesizer A is performed by the count value k s After the setting, the processing delay α and the transmission delay t a , and then starts after a processing delay β. Therefore, when the control to pull in the internal SF phase of the TS synthesizer A starts, the count value of the TS synthesizer A is k s The value is counted up from

[0079] Therefore, TS synthesizer B calculates the count value of TS synthesizer A (hereinafter referred to as count value K) at the time when it starts control to pull in the internal SF phase of TS synthesizer A. Then, TS synthesizer B sets the calculated count value K as the count value of its own device. Count value K is calculated, for example, as follows:

[0080] If the cable length between TS synthesizers A and B is the same, the transmission delay t s and the transmission delay t a Therefore, the value of t is considered to be the same as that of t. s =t a Let's say.

[0081] The transmission / reception delay from the time the startup packet is sent to the time the pull-in control starts is t sa Then, t sa =t s +α+t a +β=2t+α+β. Then, t=(t sa -α-β) / 2.

[0082] In addition, the transmission and reception delay t sa The count value in the TS synthesizer B is k s From a certain point on, k b Therefore, t sa =kb -k s This becomes:

[0083] From the above, the count value K of the TS synthesizer A can be calculated as follows. K=k a +t+β =k a +{(t sa -α-β) / 2}+β =k a +{(k b -k s ) / 2}-(α-β) / 2

[0084] Therefore, the count value K is k a ,k b ,k s , α, β, where α and β are known design values.

[0085] The internal SF phase setting unit 1403 of the TS synthesizer B sets the count value k b and the count value k extracted from the response synchronization packet s ,k a and the known values ​​of processing delays α and β, the count value K of TS synthesizer A is calculated. Then, the internal SF phase setting unit 1403 of TS synthesizer B sets the calculated count value K as the count value of TS synthesizer B. By performing such an operation, TS synthesizer B can pull in the internal SF phase of TS synthesizer A.

[0086] As described above, a typical redundantly configured TS synthesizer employs a reference synchronization configuration that uses the SF synchronization signal generator 120. However, the SF synchronization signal generator 120 is not configured redundantly. Therefore, if the SF synchronization signal generator 120 fails, the internal SF phases of the TS synthesizers may not be synchronized.

[0087] In this embodiment, the TS synthesizer 140 and the TS synthesizer 141 are configured to synchronize their internal SF phases with each other. With this configuration, it is possible to complete the process of synchronizing the internal SF phases between the TS synthesizers. Furthermore, it is possible to eliminate the SF synchronization signal generator 120, which is not configured redundantly. As a result, it is possible to configure all devices redundantly within the entrusted station 100A.

[0088] 10 is a block diagram showing the main components of a TS synthesizer. The TS synthesizer 10 shown in FIG. 10 (implemented by TS synthesizers 140 and 141 in the embodiment) is a redundantly configured TS (Transport Stream) synthesizer, and includes: a generating means 11 (implemented by an internal SF phase generating unit 1402 in the embodiment) that generates an internal phase (e.g., corresponding to the internal SF phase in the embodiment) using a clock signal within a trusted station (equivalent to the trusted station 100A in the embodiment); and a setting means 12 (implemented by an internal SF phase setting unit 1403 in the embodiment) that sets the internal phase generated by the generating means 11 of the TS synthesizer 10 that started first among the multiple redundantly configured TS synthesizers 10 as the internal phase to be used within the TS synthesizer itself. This configuration allows the internal SF phases of TS synthesizers to be synchronized with each other without relying on an SF synchronization signal generating device. Furthermore, all devices within the trusted station can be configured redundantly.

[0089] 11 is a block diagram showing the main components of a broadcasting system. The broadcasting system 20 (corresponding to the entrusted station 100A) shown in FIG. 11 includes a clock signal generating unit 23 (implemented by a clock signal generating device 110 in the embodiment) that generates a clock signal, and TS synthesizers 21 and 22 (implemented by TS synthesizers 140 and 141 in the embodiment) that synthesize TSs (Transport Streams). Each TS synthesizer 21 and 22 includes a generating means 11 (implemented by an internal SF phase generating unit 1402 in the embodiment) that generates an internal phase (e.g., corresponding to the internal SF phase in the embodiment) using the clock signal generated by the clock signal generating unit 23, and a setting means 12 (implemented by an internal SF phase setting unit 1403 in the embodiment) that sets the internal phase generated by the generating means 11 of the TS synthesizer that started first among the multiple redundantly configured TS synthesizers 21 and 22 as the internal phase to be used in that device. This configuration allows the internal SF phases of the TS synthesizers to be synchronized with each other without relying on an SF synchronization signal generating device. Furthermore, all devices within the trustee station can be configured to be redundant.

[0090] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0091] Each drawing is merely an example for describing one or more embodiments. Each drawing may relate not only to one particular embodiment, but also to one or more other embodiments. As will be understood by those skilled in the art, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings to create, for example, an embodiment not explicitly shown or described. Not all features or steps shown in any one drawing are necessary to describe an exemplary embodiment, and some features or steps may be omitted. The order of steps described in any drawing may be changed as appropriate. [Explanation of symbols]

[0092] 10,21,22,130,131,140,141 TS synthesizer 11 Generation means 12 Setting Method 20 Broadcasting System 23 Clock signal generator 100,100A Trustee 101,102 TS pseudo-synchronization device 110 Clock signal generator 120 SF Synchronization Signal Generator 200, 210 Commissioning station 300 Transmission Equipment 1301,1401 TS multiplex section 1302,1402 Internal SF phase generator 1403 Internal SF setting section

Claims

1. A redundantly configured TS (Transport Stream) synthesizing device, generating means for generating an internal phase using a clock signal in a trustee station; and a setting unit for setting the internal phase generated by the generating unit of the TS synthesizer that was started first among the plurality of redundantly configured TS synthesizers as the internal phase to be used in the device itself. A TS synthesis device characterized by:

2. When a response is received within a predetermined period of time after a startup packet is transmitted to the TS synthesizer of the other system at startup, the setting means sets the internal phase generated by the generating means of the TS synthesizer of the other system as the internal phase to be used in the own device.

2. The TS synthesizer according to claim 1.

3. The setting means sets the internal phase generated by the generating means of the own device as the internal phase to be used in the own device when a response is not received within a predetermined period of time after transmitting a startup packet to the TS synthesizing device of the other system at startup.

3. The TS synthesizing device according to claim 1.

4. The setting means When the startup packet is received from the TS synthesizer of the other system, a response synchronization packet including a count value indicating the internal phase used by the own device is transmitted; When the response synchronization packet is received, the internal phase used by the device is set based on the count value.

3. The TS synthesizer according to claim 2.

5. The setting means, when receiving the startup packet from the TS synthesizer of the other system within a predetermined period after transmitting the startup packet to the TS synthesizer of the other system at startup and then receiving the response synchronization packet, sets the internal phase to be used by the own device based on the smaller of the count value of the TS synthesizer of the other system and the count value of the own device.

5. The TS synthesizer according to claim 4.

6. a clock signal generating unit that generates a clock signal; a TS synthesizing device for synthesizing a TS (Transport Stream), The TS synthesizer comprises: a generating means for generating an internal phase using the clock signal generated by the clock signal generating unit; and a setting unit for setting the internal phase generated by the generating unit of the TS synthesizer that was started first among the plurality of TS synthesizers configured redundantly as the internal phase to be used in the device itself. A broadcasting system comprising:

7. When a response is received within a predetermined period of time after a startup packet is transmitted to the TS synthesizer of the other system at startup, the setting means sets the internal phase generated by the generating means of the TS synthesizer of the other system as the internal phase to be used in the own device.

7. The broadcasting system according to claim 6.

8. The setting means sets the internal phase generated by the generating means of the own device as the internal phase to be used in the own device when a response is not received within a predetermined period of time after transmitting a startup packet to the TS synthesizing device of the other system at startup.

8. The broadcasting system according to claim 6 or 7.

9. The setting means When the startup packet is received from the TS synthesizer of the other system, a response synchronization packet including a count value indicating the internal phase used by the own device is transmitted; When the response synchronization packet is received, the internal phase used by the device is set based on the count value. The broadcasting system according to claim 7.

10. The setting means, when receiving the startup packet from the TS synthesizer of the other system within a predetermined period after transmitting the startup packet to the TS synthesizer of the other system at startup and then receiving the response synchronization packet, sets the internal phase to be used by the own device based on the larger of the count value of the TS synthesizer of the other system and the count value of the own device.

10. The broadcasting system according to claim 9.

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