Memory system, memory controller, and data read-out method

Abstract

To provide a memory system capable of improving responsiveness to host accesses.SOLUTION: According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller has a speculative read-out mode in which data expected to be requested by a host is read from the nonvolatile memory in advance. The memory controller records a physical address of the nonvolatile memory where the data most recently read by the host is stored. When the host requests a data read, the memory controller determines whether to transition to the speculative read-out mode based on the physical address of the nonvolatile memory where the requested data is stored and the recorded physical address. In response to the transition to the speculative read-out mode, the memory controller reads data from the nonvolatile memory within a range determined based on the physical address associated with a logical address specified by the host.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION Embodiments of the present invention relate to a memory system, a memory controller, and a method for reading data. [Background technology]

[0002] For example, a memory controller that controls a NAND-type flash memory has a function of converting an address specified by a host (hereinafter referred to as a logical address) into an address of the flash memory (hereinafter referred to as a physical address) using an FTL (Flash Translation Layer).

[0003] Conversion from logical addresses to physical addresses is performed using a conversion table created based on write results from the host and processing results within the memory system. This conversion table is stored in flash memory within the memory system. A memory controller that only has volatile memory with insufficient capacity to cache the entire conversion table must partially read the conversion table from flash memory to volatile memory as needed. This reading reduces responsiveness to accesses from the host. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2018 / 0321987 [Patent Document 2] US Patent Application Publication No. 2022 / 0091984 [Patent Document 3] US Patent Application Publication No. 2018 / 0067684 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a memory system, a memory controller, and a data read method that can improve responsiveness to access from a host. [Means for solving the problem]

[0006] According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is connectable to a host and controls the nonvolatile memory. The memory controller has a speculative read mode in which data expected to be requested by the host is read from the nonvolatile memory in advance. The memory controller records a physical address indicating a physical location in the nonvolatile memory where data most recently requested to be read by the host is stored. When the host requests data to be read, the memory controller determines whether to transition to the speculative read mode based on the physical address in the nonvolatile memory where the requested data is stored and the recorded physical address. If it determines that the mode should be transitioned to the speculative read mode, the memory controller transitions to the speculative read mode and reads data from the nonvolatile memory within a range determined based on the physical address associated with the logical address specified by the host. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system according to a first embodiment. [Figure 2] 5 is a diagram for explaining a data read procedure in a normal mode of the memory system according to the first embodiment. FIG. [Figure 3] 3 is a diagram showing an example of reading data when data to be read consecutively is stored scatteredly in a flash memory in the memory system of the first embodiment; FIG. [Figure 4] FIG. 2 is a diagram showing an example in which data scattered in a logical address space is stored contiguously in a physical address space in the memory system of the first embodiment. [Figure 5]FIG. 10 is a diagram showing an example in which both logical addresses and physical addresses become consecutive by writing a large amount of data at once in the memory system of the first embodiment. [Figure 6] FIG. 2 is a diagram showing an example of the data structure of each page in a flash memory in the memory system of the first embodiment. [Figure 7] 10 is a diagram showing an example in which the memory controller determines whether data read from the flash memory performed in response to a read command from the host in the memory system of the first embodiment is for consecutive physical addresses. FIG. [Figure 8] FIG. 10 is a diagram showing an example of data read from a flash memory by a memory controller when it is determined to transition to a speculative read mode in the memory system of the first embodiment. [Figure 9] 4 is a diagram for explaining a data read procedure in a speculative read mode of the memory system according to the first embodiment; [Figure 10] 10 is a flowchart showing an operation procedure when the memory system of the first embodiment receives a read command from the host in normal mode. [Figure 11] 10 is a flowchart showing an operation procedure when the memory system of the first embodiment receives a read command from the host in the speculative read mode. [Figure 12] FIG. 10 is a diagram for explaining a transition determination to a speculative read mode in the memory system according to the second embodiment. [Figure 13] FIG. 10 is a diagram for explaining additional speculative reading in a speculative read mode of the memory system according to the second embodiment. [Figure 14] 10A and 10B are diagrams for explaining updates of a reference physical address and a determination range in the memory system according to the third embodiment. [Figure 15] 13 is a diagram for explaining an example of a determination of validity / invalidity of speculatively read data by a memory controller of a memory system according to a fourth embodiment. [Figure 16]FIG. 13 is a diagram showing an example of a verification logical address in a ring buffer structure in the memory system according to the fifth embodiment. [Figure 17] FIG. 13 is a diagram showing an example of speculatively read data in a RAM (cache memory) in the memory system of the sixth embodiment. [Figure 18] FIG. 13 is a first diagram for explaining a list showing the order in which blocks are written, which is held by a memory controller in a memory system according to the seventh embodiment. [Figure 19] FIG. 23 is a second diagram for explaining the list showing the order in which blocks are written, which is held by the memory controller in the memory system of the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings.

[0009] (First embodiment) First, the first embodiment will be described.

[0010] FIG. 1 is a block diagram showing an example of the configuration of a memory system 1 according to the first embodiment.

[0011] As shown in Fig. 1, the memory system 1 has a memory controller 11 and a flash memory 12. The memory system 1 may be a UFS (Universal Flash Storage) device in which the memory controller 11 and the flash memory 12 are configured as a single package, or may be an SSD (Solid State Drive). In Fig. 1, the memory system 1 is shown connected to a host 2. The memory system 1 may be, for example, a PCI Express TM (PCIe TM ) standard and is connected to host 2 via an interface compliant with the standard.

[0012] The memory controller 11 controls the flash memory 12. The memory controller 11 can be connected to the host 2. The memory controller 11 controls writing of data to the flash memory 12 and reading of data from the flash memory 12 in response to a command from the host 2. In order to preserve the data stored in the flash memory 12, the memory controller 11 may autonomously control writing of data to the flash memory 12 and reading of data from the flash memory 12, regardless of a command from the host 2.

[0013] The flash memory 12 is a non-volatile storage medium, and is, for example, a NAND-type flash memory.

[0014] The memory controller 11 includes a processor 111, a RAM (Random Access Memory) 112, a host interface circuit 113, an ECC (Error Correcting Code) circuit 114, and a memory interface circuit 115.

[0015] The processor 111 controls the operation of the entire memory system 1 by controlling each component of the memory controller 11. The processor 111 loads various programs from the flash memory 12 to the RAM 112 and executes them. The various programs include FTL for realizing various functions that the memory controller 11 should have, such as a function for converting logical addresses into physical addresses. The processor 111 is, for example, a CPU (Central Processing Unit).

[0016] The RAM 112 is a volatile storage medium and serves as a working area for the processor 111, for example, to temporarily store various programs and various data.

[0017] The host interface circuit 113 is, for example, an NVM Express TM (NVMe TM) standard compliant protocol to communicate with host 2.

[0018] The ECC circuit 114 adds an error correction code to data to be written to the flash memory 12. Furthermore, the ECC circuit 114 uses the error correction code added to data read from the flash memory 12 to perform error correction processing to detect and correct errors contained in the read data.

[0019] The memory interface circuit 115 controls writing of data to the flash memory 12 and reading of data from the flash memory 12 based on instructions from the processor 111 .

[0020] In the memory system 1 of the first embodiment having the above configuration, the memory controller 11 has two modes, a normal mode and a speculative read mode, for reading data from the flash memory 12. First, with reference to FIG. 2, a data read procedure in the normal mode of the memory system 1 of this embodiment will be described.

[0021] In normal mode, when a read command is received from the host 2 (1), the memory controller 11 first converts the logical address specified by the host 2 into a physical address. Specifically, the FTL 110 reads the conversion table 151, which records the correspondence between logical addresses and physical addresses, from the flash memory 12 to the RAM 112 (2), and converts the logical address specified by the host 2 into a physical address based on the conversion table 151 (3).

[0022] Once the physical address corresponding to the logical address specified by the host 2 is obtained, the memory controller 11 uses the physical address to read the data requested by the host 2 (user data 152) from the flash memory 12 and transmits it to the host 2 (4).

[0023] Here, it is assumed that in the memory system 1 of the first embodiment, the capacity of the RAM 112 is insufficient to cache the entire conversion table 151. More specifically, it is assumed that the capacity that can be secured in the RAM 112 for caching the conversion table 151 is insufficient to cache the entire conversion table 151.

[0024] To this end, the FTL 110 partially reads the conversion table 151 from the flash memory 12 to the RAM 112. If the portion of the conversion table 151 required to convert the logical address specified by the host 2 into a physical address is cached in the RAM 112, the FTL 110 can convert the logical address specified by the host 2 into a physical address using the portion of the conversion table 151 cached in the RAM 112, without reading the conversion table 151 from the flash memory 12. On the other hand, if the required portion of the conversion table 151 is not cached in the RAM 112, the FTL 110 reads the required portion of the conversion table 151 from the flash memory 12 to replace the portion cached in the RAM 112 ((2) in FIG. 2), and converts the logical address specified by the host 2 into a physical address. Reading the conversion table 151 in this way reduces responsiveness to accesses from the host 2.

[0025] Note that, here, the RAM 112 built into the memory controller 11 is exemplified as a storage medium for caching the conversion table 151, but this is not limiting, and for example, the memory system 1 may be equipped with a DRAM (Dynamic RAM) accessible from the memory controller 11, and the FTL 110 may cache the conversion table 151 in the DRAM. In this case, too, it is assumed that the capacity that can be secured in the DRAM for caching the conversion table 151 is insufficient to cache the entire conversion table 151.

[0026] Next, the speculative read mode will be explained. The speculative read mode is a mode prepared to improve responsiveness to access from the host 2.

[0027] First, the prerequisites for the memory system 1 of the first embodiment to allow the memory controller 11 to read data from the flash memory 12 in speculative read mode will be described.

[0028] The flash memory 12 is a write-once memory. Therefore, even if data is read consecutively, if the host 2 writes this data while writing other data, the data will be stored in a discontinuous and scattered manner in the flash memory 12.

[0029] In this case, as shown in FIG. 3, even if the host 2 requests consecutive reads of this data, the FTL 110 will obtain non-consecutive physical addresses from the conversion table 151. As a result, the memory controller 11 will read data from the flash memory 12 based on the non-consecutive physical addresses.

[0030] Therefore, in the memory system 1 of the first embodiment, the host 2 is required to specify the logical addresses of the data that the host 2 will read consecutively, for example, at any timing after the data is written. This instruction is given, for example, by the NVMe TM All you need to do is use one of the commands provided in the standard, the uses of which can be defined by the vendor.

[0031] Upon receiving this instruction, the memory controller 11 reads the data stored discontinuously and scatteredly in the flash memory 12, invalidates the original data, and rewrites it to the flash memory 12 so that the physical addresses are continuous.

[0032] Furthermore, when the memory controller 11 rewrites data to the flash memory 12 so that the physical addresses are consecutive in accordance with instructions from the host 2, the memory controller 11 treats the data in the block of the flash memory 12 into which the data was written as data that is prohibited from being updated. Alternatively, when an update of data occurs in that block, the memory controller 11 moves all of the data in the block including the updated data to another block, thereby maintaining the consecutive physical addresses.

[0033] In other words, the speculative read mode is a mode that is prepared on the assumption that data exists that has consecutive logical addresses and consecutive physical addresses.

[0034] 4, when a data read command is received from the host 2 with non-consecutive logical addresses sequentially specified, it cannot be said that there is no possibility that the data is stored contiguously in the flash memory 12. However, the memory system 1 of the first embodiment does not assume the application of the speculative read mode to reading data whose physical addresses are only contiguous.

[0035] Furthermore, when the host 2 writes a large amount of data at once, the logical addresses are consecutive and the physical addresses are consecutive, as shown in Figure 5. Therefore, there is no need to rewrite the data in response to a command from the host 2, as described above.

[0036] Furthermore, in the memory system of the first embodiment, when writing data to the flash memory 12, the memory controller 11 writes logical address information including a logical address specified by the host 2 to the flash memory 12 together with the data.

[0037] The flash memory 12 has a plurality of blocks, each including a plurality of pages. The memory controller 11 writes data to the flash memory 12 and reads data from the flash memory 12 in units of pages. Figure 6 shows an example of the data structure of each page in the flash memory 12 in the memory system 1 of the first embodiment.

[0038] 6, each page in the flash memory 12 includes an area where user data 152 is stored and an area where logical address information 153 is stored. When the memory controller 11 receives a write command from the host 2, it writes the data received from the host 2 (user data 152) and logical address information 153 including the logical address specified by the host 2 into the flash memory 12 in page units as a data structure having the data structure shown in FIG.

[0039] In other words, in the memory system 1 of the first embodiment, when data is read from the flash memory 12, the logical address associated with the physical address of the flash memory 12 in which this data is stored can be obtained without referring to the conversion table 151.

[0040] Next, a determination condition for determining whether the memory controller 11 should transition from the normal mode to the speculative read mode will be described.

[0041] When the memory system 1 is powered on or reset, the memory controller 11 starts operating in normal mode. When the memory controller 11 reads data from the flash memory 12 in response to a read command from the host 2, it records the physical address of the flash memory 12 where that data is stored. In other words, the memory controller 11 records the physical address of the flash memory 12 where the data most recently read from the flash memory 12 is stored (only when the data is read in response to a read command from the host 2). The memory controller 11 uses this physical address as the reference physical address.

[0042] In addition, when the memory controller 11 receives a read command from the host 2 and converts the specified logical address into a physical address using the FTL 110, it determines whether the obtained physical address is a consecutive physical address that is larger than the reference physical address by the unit of data read by the host 2.

[0043] FIG. 7 is a diagram showing an example in which the memory controller 11 determines whether data read from the flash memory 12 in response to a read command from the host 2 is from consecutive physical addresses.

[0044] 7, first, the physical address recorded in the first read is compared with the physical address targeted in the second read, and it is determined that the second read is for a physical address consecutive to the reference physical address (consecutive). Next, the physical address recorded in the second read is compared with the physical address targeted in the third read, and it is determined that the third read is not for a physical address consecutive to the reference physical address (non-consecutive).

[0045] The memory controller 11 determines to transition from the normal mode to the speculative read mode when the physical address to be read is a physical address consecutive to the reference physical address for a predetermined number of times. This number may be a predetermined fixed number, or may be a number that can be appropriately specified for system performance tuning, for example. This number can be specified, for example, in the case of NVMe TM This can be achieved by issuing one of the commands provided in the standard, the purpose of which can be arbitrarily defined by the vendor, from host 2.

[0046] Even after transitioning to the speculative read mode, the memory controller 11 continues to determine whether the physical address to be read is a physical address consecutive to the reference physical address. If the physical addresses are not consecutive, the memory controller 11 determines to transition from the speculative read mode to the normal mode.

[0047] FIG. 8 is a diagram showing an example of data read from the flash memory 12 by the memory controller 11 when it is determined to transition to the speculative read mode.

[0048] When the memory controller 11 determines to transition to the speculative read mode, it determines the speculative read range 131 based on the physical address of the read target, and reads the data in the speculative read range 131 from the flash memory 12. The data in the speculative read range 131 is data that is predicted to be requested by the host 2. The width of the speculative read range 131 may be a predetermined value, or may be a value that can be appropriately specified by tuning the performance of the system, for example. This value can be specified, for example, in the case of NVMe TM This can be achieved by issuing one of the commands provided in the standard, the purpose of which can be arbitrarily defined by the vendor, from host 2.

[0049] As described above, logical address information 153 is stored in each page in the flash memory 12 together with user data 152. The memory controller 11 caches the user data 152 in the speculative read range 131 read from the flash memory 12 in the RAM (cache memory) 112, and also caches the logical address included in the logical address information 153 in the RAM 112 as a verification logical address 154.

[0050] Next, with reference to FIG. 9, a data read procedure in the speculative read mode of the memory system 1 of the first embodiment will be described.

[0051] In the speculative read mode, the memory controller 11 speculatively reads data predicted to be requested by the host 2 (1). Specifically, data is read from consecutive physical addresses that are larger than the reference physical address by the unit of data read by the host 2. As described above, in the memory system 1 of the first embodiment, when user data 152 is read from the flash memory 12, the memory controller 11 can obtain a logical address that is associated with the physical address of the flash memory 12 where the user data 152 is stored. In addition to the user data 152, the memory controller 11 also caches this logical address (verification logical address 154) in the RAM 112.

[0052] When a read command is received from the host 2 (2), the memory controller 11 compares (3) the logical address specified by the host 2 with the logical address cached in the RAM 112. If the logical address specified by the host 2 matches the logical address cached in the RAM 112, the memory controller 11 transmits the user data 152 cached in the RAM 112 to the host 2 (4).

[0053] Furthermore, if the logical address specified by the host 2 matches the logical address cached in the RAM 112, the memory controller 11 determines that this read is for a physical address consecutive to the reference physical address (consecutive). In this case, the memory controller 11 continues the speculative read mode. If the speculative read mode is continued, the memory controller 11 updates the reference physical address to the physical address that is the target of this read. Then, the memory controller 11 reads data from consecutive physical addresses that are larger than the reference physical address by the unit of data read by the host 2. In other words, the memory controller 11 performs speculative reading of data that is predicted to be requested by the host 2.

[0054] The memory controller 11 deletes the data sent to the host 2 and the logical address corresponding to this data from the RAM 112, and caches in the RAM 112 the speculatively read data and the logical address corresponding to this data.

[0055] In addition, if the logical address specified by the host 2 does not match the logical address cached in the RAM 112, the memory controller 11 does not continue the speculative read mode, but transitions from the speculative read mode to the normal mode.

[0056] As described above, in the memory system 1 of the first embodiment, the memory controller 11 has a speculative read mode. The memory controller 11 adaptively switches between the normal mode and the speculative read mode depending on the status of issuance of a read command by the host 2. By having the speculative read mode, the memory system 1 of the first embodiment is expected to reduce the number of times that the conversion table 151 is read from the flash memory 12. Furthermore, in the memory system 1 of the first embodiment, it is expected that reading of the user data 152 from the flash memory 12 at the timing of receiving a read command from the host 2 can be substituted by reading of the user data 152 from the RAM 112.

[0057] That is, the memory system 1 of the first embodiment can improve the responsiveness to access from the host 2.

[0058] FIG. 10 is a flowchart showing an operation procedure when the memory system 1 of the first embodiment receives a read command from the host 2 in the normal mode.

[0059] When the memory controller 11 receives a read command from the host 2 (S101), it converts the logical address specified by the host 2 into a physical address using the conversion table 151 and executes a normal read to read data from the flash memory 12 (S102). The memory controller 11 transmits the read data to the host 2 (S103).

[0060] The memory controller 11 determines whether the target physical address of the previous read command and the target physical address of the current read command are consecutive (S104). If they are consecutive (S104: Yes), the memory controller 11 then determines whether the number of consecutive occurrences has reached a set number (S105). If it has reached that number (S105: Yes), the memory controller 11 transitions from the normal mode to the speculative read mode (S106).

[0061] When transitioning to the speculative read mode, the memory controller 11 sets the target physical address of the current read command as the reference physical address (S107), executes the speculative read based on the reference physical address (S108), and terminates the processing when a read command is received from the host 2.

[0062] On the other hand, if the target physical address of the previous read command and the target physical address of the current read command are not consecutive (S104: No), or if the number of consecutive addresses has not reached the set number (S105: No), the memory controller 11 does not transition to the speculative read mode and terminates the processing when it receives a read command from the host 2.

[0063] FIG. 11 is a flowchart showing an operation procedure when the memory system 1 of the first embodiment receives a read command from the host 2 in the speculative read mode.

[0064] When the memory controller 11 receives a read command from the host 2 (S201), it determines whether the logical address specified by the host 2 matches the logical address cached by the speculative read (S202). If they match (S203: Yes), the memory controller 11 transmits the data cached by the speculative read to the host 2 (S203).

[0065] Furthermore, if the logical address specified by the host 2 matches the logical address cached by the speculative read, the memory controller 11 continues the speculative read mode. The memory controller 11 updates the reference physical address to the target physical address of the current read command (S204), and executes the speculative read based on the reference physical address (S205).

[0066] On the other hand, if the logical address specified by the host 2 does not match the logical address cached by the speculative read (S202: No), the memory controller 11 does not continue the speculative read mode and transitions from the speculative read mode to the normal mode (S206). After transitioning to the normal mode, the memory controller 11 converts the logical address specified by the host 2 into a physical address using the conversion table 151 and executes a normal read to read data from the flash memory 12 (S207).

[0067] In a storage device having an FTL, the smaller the user data size (hereinafter referred to as logical block size) assigned to each logical address, the larger the amount of time spent reading the conversion table in reading the user data. When the logical block size is 16 KiB for a 4-byte logical address, the ratio of the time spent reading the conversion table is only 0.24‰, whereas when the logical block size is 4 KiB for a 4-byte logical address, at least 0.98‰ is spent reading the conversion table. Therefore, the smaller the user data size assigned to each logical address, the greater the effect obtained by the memory system 1 of the first embodiment.

[0068] As described above, the memory system 1 of the first embodiment can improve responsiveness to access from the host 2 by reducing the number of times the conversion table 151 is read in the speculative read mode.

[0069] (Second embodiment) Next, a second embodiment will be described, in which the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

[0070] The memory system 1 of the second embodiment is an improvement over the memory system 1 of the first embodiment in determining whether to transition to the speculative read mode.

[0071] Although the data in the flash memory 12 is sorted in the order of access from the host 2, if the host 2 is a computer that operates in multithreading, the reproducibility of the read order may be lost. However, it is expected that the loss of order will be a local swap, such as a front-to-back swap.

[0072] Therefore, in the memory system 1 of the second embodiment, the physical addresses determined to have been read consecutively are not limited to a single physical address that is larger by the unit of data read by the host 2, as in the memory system 1 of the first embodiment, but are determined to have a range before and after that. Next, when a physical address range within that range is read, it is determined that the physical addresses have been read consecutively.

[0073] The reference physical address is updated only if the physical address to be read is larger than the reference physical address. The determination range is set to the area before and after the updated reference physical address. The size of the determination range is set to the same as the size of the cache secured in the RAM 112, for example. The width of this determination range can be set arbitrarily, for example, by issuing a command from the host 2.

[0074] FIG. 12 is a diagram for explaining a transition determination to the speculative read mode in the memory system 1 of the second embodiment.

[0075] In the memory system 1 of the second embodiment, similarly to the memory system 1 of the first embodiment, the memory controller 11 transitions to the speculative read mode when consecutive reads of physical addresses are performed a preset number of times. In Fig. 12, it is assumed that the number of times used as the criterion for transitioning to the speculative read mode is set to four.

[0076] 11, first, a determination range having a width equal to, for example, the cache size is set based on the physical address (reference physical address) recorded in the first read. The second read is not for a physical address consecutive to the reference physical address, so it is determined to be non-consecutive in the memory system 1 of the first embodiment. In contrast, in the memory system 1 of the second embodiment, it is determined to be consecutive because it falls within the determination range having a width equal to, for example, the cache size. However, because it is not a physical address larger than the reference physical address, the reference physical address is not updated. Therefore, the determination range is not updated either.

[0077] The third read is also determined to be consecutive because it falls within the judgment range, which has a width equal to the cache size. Since the third read is at a physical address larger than the base physical address, the base physical address is updated, and the judgment range is also updated accordingly.

[0078] The fourth read is determined to be non-contiguous because it does not fall within a determination range having a width equal to the cache size, for example. Although not shown in FIG. 12, in this case, the reference physical address is updated, and the determination range is also updated accordingly. The next read is the second read. If the fourth read is determined to be contiguous, the memory controller 11 transitions from normal mode to speculative read mode.

[0079] FIG. 13 is a diagram for explaining additional speculative reading in the speculative read mode of the memory system 1 of the second embodiment.

[0080] When the mode shifts to the speculative read mode, the memory controller 11 reads data in a determination range determined based on the reference physical address from the flash memory 12 and caches it in the RAM 112 (speculative read). If the determination range is updated along with the update of the reference physical address, the memory controller 11 deletes cached data that falls within the previous determination range but is outside the current determination range from the RAM 112. In addition, the memory controller 11 reads data that falls within the current determination range but does not overlap with the previous determination range from the flash memory 12 and caches it in the RAM 112.

[0081] 12, the reference physical address is updated in the first read, and the judgment range is updated accordingly. Specifically, data corresponding to a portion of the previous judgment range that is outside the current judgment range is deleted from RAM 112, and data corresponding to a portion of the current judgment range that does not overlap with the previous judgment range is read.

[0082] The second read is a read that targets the part of the determination range that was added in the first read. In this way, the memory system 1 of the second embodiment takes into consideration the case where the host 2 is a computer that operates in multithreading, and focuses on the fact that although there is a possibility that the reproducibility of the read order will be lost, it can be expected that this will be a local replacement, and provides a certain degree of width to the determination range.

[0083] As a result, the memory system 1 of the second embodiment can increase the possibility that the speculative read mode will continue even if the reproducibility of the read order is lost, and can further improve responsiveness to access from the host 2.

[0084] (Third embodiment) Next, a third embodiment will be described. Here, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

[0085] The memory system 1 of the third embodiment is an improvement over the method of updating the determination range in the memory system 1 of the second embodiment.

[0086] In the memory system 1 of the second embodiment, if the physical address to be read is larger than the reference physical address, the address is uniformly updated. In this case, if an extremely large physical address is read, the possibility increases that a smaller physical address that has not yet been read will be determined to be non-consecutive.

[0087] Therefore, in the memory system 1 of the third embodiment, an update range is further set based on the reference physical address, and the reference physical address and the determination range are updated only in the case of a read that targets this update range.

[0088] FIG. 14 is a diagram for explaining the update of the reference physical address and the determination range in the memory system 1 of the third embodiment.

[0089] In Figure 14, the second and third reads are performed for the judgment range set in the first read, but both are outside the update range, and the reference physical address and judgment range are not updated.

[0090] In this way, in the memory system 1 of the third embodiment, when the reproducibility of the read order is lost and an extremely large physical address within the judgment range becomes the read target, the judgment range is not updated, thereby increasing the likelihood that the speculative read mode will continue and further improving responsiveness to accesses from the host 2.

[0091] (Fourth embodiment) Next, a fourth embodiment will be described. Here, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

[0092] The memory system 1 of the fourth embodiment is an example showing a method for eliminating the prohibition on updating data within a block of the flash memory 12 into which data that is read continuously by the host 2 has been written, or the restriction on data movement in block units that accompanies data updates, which was assumed in the memory system 1 of the first embodiment.

[0093] The validity or invalidity of each piece of data in the flash memory 12 is managed by the memory controller 11, more specifically, the FTL 110, as a correspondence table.

[0094] The memory controller 11 references this correspondence table before outputting speculatively read data to the host 2. This prevents invalidated user data 152 in a block from being output to the host 2.

[0095] Even if the speculatively read data contains data that matches the logical address specified by the host 2, if that data is invalidated in the correspondence table, the memory controller 11 determines that there is no data that can be output from the speculatively read data and terminates the speculative data read. The memory controller 11 transitions from the speculative read mode to the normal mode and resumes determining the continuity of the read by the host 2.

[0096] Furthermore, when the memory controller 11 finds from the correspondence table that the data at the lower limit of the determination range is invalid, it continues speculative reading until the lower limit becomes valid data, and updates the determination range and update range.

[0097] The correspondence table is assumed to be a table associated with physical blocks in the flash memory 12. Because the correspondence table is associated with physical addresses, it has no correlation with the access pattern of logical addresses. Although the correspondence table needs to be read from the flash memory 12 to the RAM 112, the information only indicates whether it is valid or invalid, and the amount of data is sufficiently small compared to the conversion table 151 that converts logical addresses to physical addresses.

[0098] FIG. 15 is a diagram for explaining an example of the determination by the memory controller 11 as to whether speculatively read data is valid or invalid.

[0099] In the example of FIG. 15, the memory controller 11 can determine from the correspondence table that the sixth logical address F from the top that has been speculatively read has already been invalidated.

[0100] Also, as in the case of logical address C, there may be cases where data at the same logical address within the same block is speculatively read, but one of the data is always invalidated. Therefore, even in the example of Figure 15, if the memory controller 11 continues to refer to the correspondence table for the determination range (speculative read range 131), it will eventually be able to obtain valid data from the speculatively read data. In other words, if the memory controller 11 finds that data matching the logical address specified by the host 2 is cached but is marked invalid in the correspondence table, it checks whether data at the same logical address is separately cached.

[0101] 15, the two pieces of data before logical address A have already been invalidated, and the range of these pieces of data does not become the lower limit of the determination range for speculative reads. If these pieces of data were to be set as the lower limit of the determination range, the memory controller 11 would continue speculative reads up to the position of logical address A.

[0102] As described above, the memory system 1 of the fourth embodiment eliminates the prohibition on updating data within a block of the flash memory 12 into which data that is continuously read by the host 2 has been written, or the restriction on data movement in block units that accompanies data updates, which was assumed in the memory system 1 of the first embodiment.

[0103] (Fifth embodiment) Next, a fifth embodiment will be described. Here, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

[0104] The memory system 1 of the fifth embodiment is an improvement over the method of referring to the verification logical address 154 in the memory system 1 of the fourth embodiment.

[0105] In the memory system 1 of the fourth embodiment, in consideration of the case where an update occurs within the same block, as in the case of logical address C in Fig. 15, even if the logical address initially found is invalid, it is necessary to perform reference processing again to find a valid logical address, or to continue reference processing until all of the verification logical addresses 154 have been referenced. Therefore, in the memory system 1 of the fourth embodiment, the processing time increases as the number of reference processing operations increases. Furthermore, the control mechanism becomes more complex due to the increased control required for the re-reference.

[0106] Therefore, the memory system 1 of the fifth embodiment is provided with a mechanism that can determine whether data is valid or invalid based only on the first matching logical address, thereby eliminating the need for the repeated reference process that is required in the memory system 1 of the fourth embodiment.

[0107] In the memory system 1 of the fifth embodiment, the verification logical address 154 has a ring buffer structure. Fig. 16 is a diagram showing an example of the verification logical address 154 of the ring buffer structure in the memory system 1 of the fifth embodiment.

[0108] The memory controller 11 holds information about the beginning and end of the ring buffer. When the determination range is updated, the memory controller 11 overwrites the logical address information (starting at the ring buffer) corresponding to the smallest physical address. When referencing the logical address information, the memory controller 11 starts referencing in descending order from the position with the largest physical address (the end of the ring buffer).

[0109] As a result, if there are identical logical addresses within the determination range, the logical address that was referenced first, i.e., the one with the largest physical address, is determined to be the most recent logical address-physical address correspondence. This is because, due to the characteristics of the flash memory 12, the data with the largest physical address is the most recent data.

[0110] In this way, in the memory system 1 of the fifth embodiment, it is possible to determine whether data is valid or invalid based only on the first matching logical address, thereby improving responsiveness to access from the host 2 compared to the memory system 1 of the fourth embodiment.

[0111] (Sixth embodiment) Next, a sixth embodiment will be described. Here, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

[0112] In the memory system 1 of the fourth embodiment, data that is invalid in the correspondence table is also speculatively read from the flash memory 12, but in the memory system 1 of the sixth embodiment, data that is invalid in the correspondence table is not read.

[0113] FIG. 17 is a diagram showing an example of speculatively read data in the RAM (cache memory) 112 in the memory system 1 of the sixth embodiment.

[0114] 17, it is assumed that eight pieces of user data 152 can be cached in the RAM 112. It is also assumed that 15 pieces of data can be written to one block of the flash memory 12, and the start point of the determination range is the sixth physical address.

[0115] In this case, the correspondence table indicates that the sixth, eighth, and eleventh data are invalid, so the memory controller 11 speculatively reads the eight pieces of data, from the sixth to the fifteenth, excluding the eighth and eleventh data, from the flash memory 12 to the RAM 112.

[0116] As described above, in the memory system 1 of the sixth embodiment, all cached user data 152 is valid, and therefore, unlike the memory system 1 of the fourth embodiment, it is possible to refer to the logical address of the speculative read range and output the first one found to the host.

[0117] In addition, since unnecessary data is not read into the RAM 112, the freed-up portion can be used for further speculative reading. Regarding the range of consecutive reads, even if additional data is read into the cache memory, it is determined to be consecutive.

[0118] As described above, the memory system 1 of the sixth embodiment can improve the responsiveness to access from the host 2 compared to the memory system 1 of the fourth embodiment.

[0119] (Seventh embodiment) Next, a seventh embodiment will be described. Here, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

[0120] In the memory systems 1 of the first to sixth embodiments, speculative reading is completed within one block of the flash memory 12, and if the reading range moves to another block, the speculative reading must be temporarily stopped.

[0121] Therefore, in the memory system 1 of the seventh embodiment, even when the read block is switched, speculative read can be continued.

[0122] In the memory system 1 of the seventh embodiment, the memory controller 11 holds a list indicating the stroke order of the blocks. Figures 18 and 19 are diagrams for explaining the list indicating the stroke order of the blocks held by the memory controller 11 in the memory system 1 of the seventh embodiment.

[0123] The list is designed to connect all blocks in the flash memory 12. However, only blocks in which valid data is written are connected. In the examples of Figures 18 and 19, five blocks are connected.

[0124] When the memory controller 11 has written all the data in a block, it connects the written block to the end of this list. If all the data in a block becomes invalid, the memory controller 11 removes that block from the list.

[0125] The memory controller 11 speculatively reads data from within a block of the flash memory 12, and when the read range reaches the end of the block, it resumes speculative reading from the beginning of the block connected next to the block that was speculatively read in the write order list. In the examples of Figures 18 and 19, the read range reaches the end of block 3, and speculative reading is resumed from the beginning of block 4, which is connected next to block 3, based on the list.

[0126] In the case of a block at the end of the list, the memory controller 11 terminates the speculative read when it reaches the end of the block.

[0127] As a result, in the memory system 1 of the seventh embodiment, speculative reading can be continued even if the data to be read is written continuously across blocks. In the case of a flash memory 12 with a small block size of about 10 MiB, block spanning is likely to occur, so the memory system 1 of the seventh embodiment can fully obtain the effect of speculative reading compared to the memory systems 1 of the first to sixth embodiments.

[0128] Furthermore, it is possible that data areas that are frequently speculatively read may be written across blocks depending on the write command from the host 2. In this case, by employing the mechanism of the memory system 1 of the seventh embodiment, it becomes possible to fully obtain the effect of speculative reading.

[0129] As described above, in the memory system 1 of the seventh embodiment, even if the block size of the flash memory 12 is small, it becomes easier to continue speculative reads, and the effects of speculative reads can be obtained continuously. For example, if the block size of the flash memory 12 is 10 MiB and four consecutive 4 KiB reads are performed before transitioning to speculative reads, in the memory systems 1 of the first to sixth embodiments, 0.39 ‰ is read in normal mode. In contrast, in the memory system 1 of the seventh embodiment, speculative reads are also possible for this 0.39 ‰ worth of data.

[0130] In this way, the memory system 1 of the seventh embodiment can improve the responsiveness to access from the host 2 compared to the memory systems 1 of the first to sixth embodiments.

[0131] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are within the scope of the invention. and summary, as well as the inventions described in the claims and their equivalents. [Explanation of symbols]

[0132] 1...memory system, 2...host, 11...memory controller, 12...flash memory, 110...FTL, 111...processor, 112...RAM, 113...host interface circuit, 114...ECC circuit, 115...memory interface circuit, 131...speculative read range, 151...conversion table, 152...user data, 153...logical address information, 154...logical address for verification.

Claims

1. a non-volatile memory; a memory controller connectable to a host and controlling the nonvolatile memory; Equipped with The memory controller a speculative read mode for reading data that is predicted to be requested by the host from the nonvolatile memory in advance; recording a physical address indicating a physical location in the nonvolatile memory where the data most recently requested to be read by the host is stored; When a data read request is received from the host, a determination is made as to whether or not to transition to the speculative read mode based on a physical address of the nonvolatile memory where the requested data is stored and the recorded physical address; When it is determined that the mode should be shifted to the speculative read mode, the mode is shifted to the speculative read mode, and data within a range determined based on a physical address associated with the logical address specified by the host is read from the nonvolatile memory. Memory system.

2. 2. The memory system of claim 1, wherein the memory controller determines that the speculative read mode should be entered when the physical address of the nonvolatile memory where the data requested by the host is stored is larger than the recorded physical address by a size of the unit of data read by the host for a predetermined number of consecutive times.

3. 2. The memory system of claim 1, wherein the memory controller determines that the speculative read mode should be entered when the physical address of the nonvolatile memory where the data requested by the host is stored is within a range determined based on the recorded physical address for a predetermined number of consecutive times.

4. The memory controller determining whether the physical address of the nonvolatile memory where the data requested by the host is stored is greater than the recorded physical address; If the address is large, updating the recorded physical address to a physical address in the nonvolatile memory where the data requested by the host is stored; 4. The memory system of claim 3, wherein if the address is not large, updating of the recorded physical address is omitted.

5. If the physical address of the nonvolatile memory where the data requested by the host is stored is greater than the recorded physical address, further determining whether or not a difference between a physical address of the nonvolatile memory where the data requested by the host is stored and the recorded physical address is equal to or less than a threshold value; If it is below the threshold, updating the recorded physical address to a physical address in the nonvolatile memory where the data requested by the host is stored; If the threshold is exceeded, skip updating the recorded physical address.

5. The memory system of claim 4.

6. the non-volatile memory has a plurality of blocks, each containing a plurality of pages; The memory controller When a data write request is received from the host, the logical address designated by the host is stored in a first area of ​​the page, and data received from the host is written to the nonvolatile memory so as to be stored in a second area of ​​the page; determining whether to continue the speculative read mode based on a logical address specified by the host and a logical address read from the nonvolatile memory together with data predicted to be requested by the host during the speculative read mode; 10. The memory system of claim 1.

7. 7. The memory system of claim 6, wherein, when the host requests data reading during the speculative read mode, the memory controller determines to continue the speculative read mode if a logical address specified by the host matches a logical address read from the non-volatile memory together with data predicted to be requested by the host.

8. the memory controller, in the speculative read mode, reads from the nonvolatile memory data stored at a location indicated by an address that is larger than a physical address associated with a logical address specified by the host by a size of a unit of data read by the host; 7. The memory system of claim 6.

9. The memory controller, in the speculative read mode, determining whether a physical address associated with the logical address designated by the host is greater than the recorded physical address; If the address is large, updating the recorded physical address to a physical address associated with the logical address designated by the host; reading, from the nonvolatile memory, data in a portion of a range determined based on the updated physical address that does not overlap with a range determined based on the pre-update physical address; If the address is not large, skip updating the recorded physical address.

7. The memory system of claim 6.

10. If the physical address associated with the logical address specified by the host is greater than the recorded physical address, further determining whether or not a difference between a physical address associated with the logical address specified by the host and the recorded physical address is equal to or less than a threshold value; If it is below the threshold, updating the recorded physical address to a physical address associated with the logical address designated by the host; reading, from the nonvolatile memory, data in a portion of a range determined based on the updated physical address that does not overlap with a range determined based on the pre-update physical address; If the threshold is exceeded, skip updating the recorded physical address.

10. The memory system of claim 9.

11. The memory controller managing a correspondence table indicating whether each piece of data stored in the nonvolatile memory is valid or invalid; In the speculative read mode, if data at a logical address specified by the host has been read from the nonvolatile memory in advance as data predicted to be requested by the host, the read data is determined to be valid or invalid based on the correspondence table, and if valid, the read data is transmitted to the host.

10. The memory system of claim 1.

12. The memory controller reading data that is predicted to be requested by the host into a cache memory having a ring buffer structure; referring to the cache memory in descending order of physical addresses and searching for data at the logical address specified by the host; 12. The memory system of claim 11.

13. The memory controller managing a correspondence table indicating whether each piece of data stored in the nonvolatile memory is valid or invalid; When reading data that is predicted to be requested by the host from the nonvolatile memory, it is determined whether the data to be read is valid or invalid based on the correspondence table, and if the data is valid, it is read from the nonvolatile memory.

10. The memory system of claim 1.

14. 14. The memory system of claim 13, wherein the memory controller further reads data predicted to be requested by the host from the nonvolatile memory if the data to be read is invalid.

15. the non-volatile memory has a plurality of blocks, each containing a plurality of pages; The memory controller managing a list indicating the order in which the plurality of blocks were used to write the host data; The reading of data predicted to be requested by the host can be continued across two blocks based on the list.

10. The memory system of claim 1.

16. A memory controller connectable to a host and controlling a nonvolatile memory, a speculative read mode for reading data that is predicted to be requested by the host from the nonvolatile memory in advance; recording a physical address indicating a physical location in the nonvolatile memory where the data most recently requested to be read by the host is stored; When a data read request is received from the host, a determination is made as to whether or not to transition to the speculative read mode based on a physical address of the nonvolatile memory where the requested data is stored and the recorded physical address; When it is determined that the mode should be shifted to the speculative read mode, the mode is shifted to the speculative read mode, and data within a range determined based on a physical address associated with the logical address specified by the host is read from the nonvolatile memory. Memory controller.

17. A data reading method for a memory system comprising: a nonvolatile memory; and a memory controller connectable to a host and controlling the nonvolatile memory, wherein the memory controller has a speculative read mode in which data predicted to be requested by the host is read from the nonvolatile memory in advance, the method comprising: The memory controller: recording a physical address indicating a physical location in the nonvolatile memory where the data most recently requested to be read by the host is stored; When a data read request is received from the host, a determination is made as to whether or not to transition to the speculative read mode based on a physical address of the nonvolatile memory where the requested data is stored and the recorded physical address; When it is determined that the mode should be shifted to the speculative read mode, the mode is shifted to the speculative read mode, and data within a range determined based on a physical address associated with the logical address specified by the host is read from the nonvolatile memory. Data reading method.

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