Nonlinear analog control of multiphase electrical circuit

Abstract

To provide a nonlinear analog control of a multiphase electrical circuit.SOLUTION: The subject matter of the present invention is a multiphase electrical circuit for supplying a power to a target load. The multiphase electrical circuit comprises: a power cell comprising N power supply branches converging toward an output node; and a control circuit comprising a voltage regulation circuit configured to generate an alternating binary regulation signal based on a combination of an output voltage and a noise voltage, and a dispersion circuit configured to generate, for each power supply branch, at least one dedicated actuation signal based on the regulation signal. A plurality of operating signal is shifted each other in accordance with a phase shift changed with time.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to polyphase electrical circuits for space applications, and more particularly to implementing nonlinear analog control of polyphase circuits. [Background technology]

[0002] Power supply systems incorporate multi-phase converters to improve energy efficiency, optimize voltage regulation, and manage loads in a more balanced manner. Multi-phase converters operate with electrical signals distributed across multiple phases, allowing for balanced load sharing. These converters are versatile and can convert between DC and AC voltages, as well as adjust voltage or current to address the specific needs of electrical devices.

[0003] In the context of a multi-phase converter, a "phase" should be understood to mean an individual power supply branch of an electrical circuit that converts electrical energy. A multi-phase converter uses several, typically two, three, or more, independently operating phases to convert energy. Each phase operates at a time shift relative to the others, resulting in a time sequence in which each phase continuously contributes to the converter's total output. This approach distributes the electrical load and reduces current fluctuations, which can improve efficiency and reduce current ripple. For example, in a two-phase converter, two phases operate alternately to reduce voltage. Similarly, a three-phase converter uses three phases operating sequentially.

[0004] A multi-phase converter generally comprises power cells formed by a number of phases and a control circuit configured to control the activation and deactivation of the various phases in order to achieve an operating time shift between the phases.

[0005] As computing units' power requirements increase, voltage regulator modules (VRMs) must supply more current while improving responsiveness to load transistors. For this purpose, the use of multiphase or multiphase series-capacitor topologies is favored. Combining these topologies with nonlinear control optimizes the performance of these converters. However, applying effective nonlinear control to multiphase or multiphase series-capacitor converters can be complex, especially in applications that do not include a digital controller such as a microprocessor, FPGA, or processor.

[0006] More specifically, in the context of space applications, implementing control circuits using digital controllers results in circuits with reduced technical robustness. Indeed, conventional digital control circuits often exhibit limitations in terms of reliability in the harsh space environment. Currently available solutions are often based on conventional digital control circuits that are not optimized for space-specific constraints, particularly radiation tolerance, reliability, and stability.

[0007] Furthermore, the present invention addresses the problem of variations in the operating frequency of the control signals of the various phase-shifted phases. Indeed, if the control circuit is not controlled by a fixed clock frequency, it becomes difficult to generate phase-shifted control signals at uncertain frequencies. In this case, the control circuit must phase-shift the control signals based on a single input signal without first knowing when the next phase will be triggered. This is referred to as a "nonlinear" control circuit design.

[0008] For purposes of describing the present invention, the term "power supply branch" is used to refer to an electrical phase of a polyphase circuit. Summary of the Invention [Problem to be solved by the invention]

[0009] To overcome the limitations of existing solutions, the present invention proposes a multi-phase electric circuit with a non-linear analog phase control circuit. The non-linearity of the control circuit allows the main signal to be phase-shifted over multiple phases without knowing its duration. In addition, the architecture proposed by the present invention allows improving the stability of operation of the multi-phase circuit regardless of the output load, which can be adjusted depending on the intended application.

[0010] The analog implementation of the control circuit according to the present invention ensures that the multiphase circuit is suitable for harsh environments, more particularly the space environment, which provides superior reliability for digital microcontrollers subject to environmental constraints in space applications. [Means for solving the problem]

[0011] The subject of the present invention is a polyphase electric circuit configured to generate an output current or output voltage for powering a target load, said polyphase electric circuit comprising: a power cell, an input node for supplying an input voltage; 〇The ground and an output node for providing said output voltage; N power delivery branches converging towards an output node, where N is a natural number greater than 1, each power delivery branch having: a central node isolated from the input node by at least one first switch and from ground by at least one second switch; N power supply branches, each of which comprises: a power cell comprising: a control circuit, A voltage regulation circuit configured to generate an alternating binary regulation signal based on a combination of an output voltage and an alternating noise voltage, said noise voltage being determined by the voltage regulation circuit to: ■ the potential of the central node of the selected power supply branch, or ■ Input voltage a voltage regulation circuit generated based on a distributed circuit configured to generate, for each power supply branch, at least one dedicated actuation signal based on the adjustment signal, the actuation signals being phase shifted relative to one another according to a time-varying phase shift; a control circuit comprising: Equipped with.

[0012] According to a particular aspect of the invention, the voltage regulation circuit comprises a comparator for comparing the intermediate signal with a predetermined reference voltage, the intermediate signal having a DC component corresponding to the output voltage and an AC component corresponding to the noise voltage.

[0013] According to a particular aspect of the present invention, a voltage regulation circuit includes a divider bridge including a pair of resistors separated by a third switch and configured to generate a fraction of an input voltage when the third switch is on, the third switch being controlled by a regulation signal.

[0014] According to a particular aspect of the invention, the voltage regulation circuit comprises N diodes, each having an anode connected to a central node of a power supply branch associated with said diode, and having a cathode connected to a common node isolated from ground by a fourth switch controlled by a regulation signal.

[0015] According to a particular aspect of the invention, a distributed circuit comprises a chain of N D-type flip-flops, all synchronized according to an adjustment signal and mounted such that the output of a flip-flop of rank i=1 to N-1 is connected to the input of the next flip-flop of rank i+1.

[0016] According to a particular aspect of the invention, the distributed circuit further comprises an OR-type logic cell having a first input connected to the output of the flip-flop of rank N, a second input receiving an initialization signal, and an output connected to the input of the flip-flop of rank i=1.

[0017] According to a particular aspect of the invention, the distributed circuit further comprises N AND type logic cells, each AND type cell having a first input for receiving the output of an associated D type flip-flop, a second input for receiving an adjustment signal, and an output for providing an activation signal to an associated power supply branch.

[0018] According to a particular aspect of the present invention, the control circuit further comprises a protection circuit interposed between the voltage regulation circuit and the distribution circuit and configured to limit the duration for setting the regulation signal to a high or low state to a predetermined threshold.

[0019] According to a particular aspect of the invention, the control circuit further comprises a dead time circuit inserted between the distribution circuit and the power cells and configured to generate, for each power supply branch, a first actuation signal and a second supplemental actuation signal, wherein each transition edge of the second actuation signal is shifted in time with respect to the first actuation signal.

[0020] According to a particular aspect of the invention, each power supply branch comprises an associated element inductor attached between the central node and the output node, each power supply branch being configured to generate an element current through the associated element inductor.

[0021] Further features and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0022] [Figure 1] 1 shows a polyphase electric circuit according to a first embodiment of the present invention; [Figure 2a] 1 shows a first example of a power cell of a polyphase electric circuit according to the invention; [Figure 2b] 2 shows a second example of a power cell of a polyphase electric circuit according to the invention; [Figure 3a] 1 shows a first example of a voltage regulation circuit for a polyphase electric circuit according to the present invention; [Figure 3b] 2 shows a second example of a voltage regulation circuit for a polyphase electric circuit according to the present invention. [Figure 4] 1 shows a control signal distribution circuit for a polyphase electrical circuit according to the present invention; [Figure 5] 3 shows a timing diagram of the internal and external signals of the control circuit of the polyphase electric circuit according to the present invention; [Figure 6] 2 shows a polyphase electric circuit according to a second embodiment of the present invention; [Figure 7a] 4 shows an example of an implementation of a protection circuit in a polyphase electric circuit according to a second embodiment of the present invention. [Figure 7b] 10 shows a RESET signal generating circuit in a polyphase electric circuit according to a second embodiment of the present invention. [Figure 7c] 10 shows a SET signal generating circuit in a polyphase electric circuit according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] 1 shows a multi-phase electric circuit D1 according to a first embodiment of the present invention. The multi-phase electric circuit D1 comprises a power cell 1 and a control circuit 2. The power circuit 1 outputs an output current I to a load 3 to be powered. out The control circuit 2 is formed by N power supply branches (index i=1 to N) configured to generate differential signals CMD which are phase shifted relative to one another according to a time-varying phase shift. i (i=1 to N). iis dedicated to the power supply branch with the same index i to trigger said power supply branch to supply power to the load 3 for a certain duration, and the activated power supply branch then becomes conductive.

[0024] Power cell 1 is connected to the input voltage V in an input node 12 for supplying the output voltage V out and N power supply branches converging towards the output node 11. A powered load 3 is connected between the output node 11 and ground GND. The power cell 1 comprises: - output current I through the powered load 3 out and, - output voltage V at the terminals of load 3 out The output voltage V propagates to the control circuit 2 via the first feedback loop. out and, at least one noise voltage V reinjected into the control circuit 2 via a second feedback loop; m1 From V mN and Generate.

[0025] The control circuit 2 includes a voltage regulation circuit 21 and a distribution circuit 22. The voltage regulation circuit 21 regulates the output voltage V out and at least one noise voltage V reinjected through a second feedback loop. m1 From V mN The adjustment signal V is generated based on the combination of the selected noise voltage AC component and the selected noise voltage AC component. reg The adjustment signal V reg is a binary and periodic digital signal for the distribution circuit 22.

[0026] The distribution circuit 22 generates, for each power supply branch, a regulated signal V regThe actuation signals are configured to generate dedicated actuation signals CMD1, CMD2, CMD3 based on the adjustment signal V. The actuation signals are phase shifted relative to one another by a time-varying phase shift. reg is a multiple actuation signal CMD i With source signals generated with a variable phase shift, the power supply branches of the power cell 1 can be operated sequentially without the need for a synchronous clock signal.

[0027] Output voltage V out and noise voltage V mi to the control circuit 2, a stable polyphase electric circuit D1 can be obtained, regardless of the required operating frequency of the power supply branches.

[0028] Noise voltage V mi is in phase with the conduction of each of the power supply branches to achieve operation that is load independent and can be adjusted according to the intended application. reg can generate the adjustment signal V reg reproduces the time-dependent variation of the current flowing through the relevant power supply branch.

[0029] 2a shows a first example of a power cell 2 of a multi-phase electric circuit D1 according to the invention. In this illustrative and non-limiting example, the power cell 2 receives a DC input voltage V in The output voltage V is lower than the input voltage out This is a multiphase buck converter for converting an output voltage V out is measured at the output node 11. The power cell 2 has multiple power supply branches PH1 to PH2 that converge towards the output node 11. N The target load 3 comprises, for example, a load capacitor C connected in parallel between the output node 11 and ground GND. out and the load resistance R load It consists of:

[0030] Each power supply branch PH i is the first switch Q i1 and the second switch Qi2 and the central node 13 and the associated element inductor L attached between the central node 13 and the output node 11. i Each power supply branch PH i , the central node 13 has at least a first associated switch Q i1 Each power supply branch PH i , the central node 13 has at least a second associated switch Q i2 The first switch Q is isolated from ground GND. i1 Power Supply Branch PH i The associated activation signal CMD i The second switch Q is controlled by i2 Power Supply Branch PH i Supplementary actuation signal CMD related to i For example, the actuation signal CMD i When is in a high state, the first switch Q i1 is in the on state, and the second switch Q i2 is in the OFF state. This allows the power supply branch PH i through the input node 12 to the output node 11, the associated central node 13 and the associated element inductor L i Conversely, the current flows through the actuation signal CMD i When is in a low state, the first switch Q i1 is in the off state, and the second switch Q i2 is in the ON state, which connects the central node 13 to ground GND and the power supply branch PH i The current stops flowing. i are phase shifted so that each power supply branch operates at a time shift relative to the other branches, which helps distribute the load and reduce current fluctuations, thereby reducing current ripple and energy losses. i By spreading the load across the converter, it is able to better manage current fluctuations.

[0031] 2b shows a second example of a power cell 2 of a multi-phase electric circuit D1 according to the present invention. In this illustrative and non-limiting example, the power cell 2 is connected to a DC input voltage V in The output voltage V is lower than the input voltage out The power cell 2 according to the second example incorporates all of the features and advantages described with respect to the first example. The power cell 2 according to the second example differs from the first example in the following ways: Each power supply branch PH i (i=1 to N-1) is the first switch Q i1 and an intermediate capacitor C mounted in series between the fly In addition, each power supply branch PH i (i=1 to N-1), the intermediate capacitor C fly and the first switch Q i1 The common node between the power supply branch PH i+1 The first switch Q (i+1)1 The last power supply branch of rank i=N is connected to the intermediate capacitor C fly Only the first power supply branch PH1 has its first switch Q 11 The power cell 2 according to the second example is more technically robust than the first example. This is because the first and second switches Q i1 and Q i2 The terminal voltage of is the input voltage V in This is because it is lower than

[0032] 3a shows a first example of a voltage regulation circuit 21 of the control circuit 2 according to the invention. The voltage regulation circuit 21 regulates the output voltage V out and noise voltage V noise Based on the combination of alternating binary adjustment signals V reg is configured to generate

[0033] In a first example, the voltage regulation circuit 21 includes a resistive divider bridge formed by a pair of resistors R4, R6 separated by a switch Q1. The resistive divider bridge R4, R6 divides the input voltage V in The third switch Q1 is configured to generate a portion of the regulation signal V via a feedback loop inside the voltage regulation circuit 21. reg It is controlled by the adjustment signal V reg The divider bridge R4, R6, controlled by the adjustment signal V reg and the noise voltage V noise The resistor divider bridge generates the activated power supply branch PH when switch Q1 is on. i The noise voltage V is equal to the voltage that can be measured at the center node 13 of noise The synchronized noise voltage V noise The introduction of the voltage regulator 21 ensures that the currents flowing through the various power supply branches are equal. This ensures the stability of the converter D1 without measuring the currents. Furthermore, the voltage regulator circuit 21 regulates the output voltage V propagated from the output node 11 through the first feedback loop of the multiphase electrical circuit D1 described in FIG. out Receives the internally generated noise voltage V noise and the output voltage V out The combination with the intermediate voltage V int The voltage regulation circuit 21 generates the intermediate signal V int and a given reference voltage V ref The output signal of the comparator COMP is a signal corresponding to the adjustment signal V reg which is a periodic binary signal.

[0034] The voltage regulation circuit 21 regulates the output voltage V out and an output node that supplies an intermediate signal V int The resistor R2 is connected between the non-inverting input of the comparator COMP corresponding to the output voltage V out The DC component of can be superimposed on the non-inverting input of the comparator COMP.

[0035] On the one hand, the voltage regulation circuit 21 regulates the output voltage V out On the other hand, the node supplying the noise voltage V noise The capacitor C2 is connected between the node supplying the noise voltage V noise is integrated at least through resistor R4 to produce the output voltage V out and noise voltage V noise A triangular wave signal is obtained between the

[0036] On the one hand, the voltage regulation circuit 21 regulates the output voltage V out and on the other hand, the output node that supplies the intermediate signal V int The capacitor C1 functions as a high-pass filter. noise The AC component of the output voltage V can be superimposed on the non-inverting input of the comparator COMP. out and the DC component corresponding to the noise voltage V noise and an intermediate signal V int The impedance of capacitor C1 is lower than the impedance of resistor R2 at the operating frequency. This means that the noise voltage V noise and the intermediate signal V int Prevents voltage drop between

[0037] The voltage regulation circuit 21 generates a triangular intermediate signal V synchronized with the currents in the branches at the input of a comparator COMP with two tripping thresholds. int is generated internally. int reproduces the shape of the current through the inductor of the power supply branch in the conducting state, which results in a frequency f determined by the time constant R4·C2 and by the values ​​of the two hysteresis thresholds of the comparator COMP. reg In this case, the binary periodic adjustment signal V reg is generated.

[0038] Optionally, the voltage regulation circuit 21, on the other hand, regulates the noise voltage V noise and on the other hand the output of the voltage divider bridge R4, R6. In this case, the frequency f reg is determined by the time constant (R4+R5) C2, which is the value of the two hysteresis thresholds of the comparator COMP. By adding resistor R5, the frequency f reg This increases the degree of freedom in dimensioning.

[0039] 3b shows a second example of a voltage regulation circuit 21 of the control circuit 2 according to the invention. The voltage regulation circuit 21 regulates the output voltage V out and noise voltage V noise Based on the combination of alternating binary adjustment signals V reg is configured to generate

[0040] In the second example, the voltage regulation circuit 21 includes N diodes D i (N is the power supply branch PH i In this example, N=3 is considered. Each diode D of rank i i is the diode D i Electricity Supply Branch PH related to i The diode D has an anode connected to the center node 13 of the diode D. i The cathodes of the voltage regulators 21 and 22 are connected to a common node 211. The common node 211 is isolated from the ground GND by a switch Q2. The switch Q2 supplies a regulation signal V reg Power supply branch PH i In any one of the first switch Q i1 When is on, the central node 13 is connected to a non-zero central voltage V mi The corresponding diode D i Since a positive voltage is applied to the other diode D, it becomes conductive. j (j≠i) is in the off state. Therefore, the central voltage V mi is the noise voltage V noiseThis noise signal propagates towards the common node 211 to form the activated power supply branch PH i The element inductor L i The image of the current through the inductor L can be added to the regulation loop. i is the same, the inductor L i Activating switch Q2 ensures that common node 211 is grounded when all power supply branches are shut down.

[0041] Furthermore, the voltage regulation circuit 21 regulates the output voltage V propagated from the output node 11 through the first feedback loop of the multi-phase electric circuit D1 described in FIG. out Receives the internally generated noise voltage V noise and the output voltage V out The combination with the intermediate voltage V int The noise voltage V noise is the output voltage V out The intermediate signal V propagates towards the common node. int is the output voltage V out and the DC component corresponding to the noise voltage V noise and AC components corresponding to

[0042] The voltage regulation circuit 21 regulates the intermediate signal V int and a given reference voltage V ref The output signal of the comparator COMP is a signal corresponding to the adjustment signal V reg which is a periodic binary signal.

[0043] In general, the voltage regulator circuit 21 regulates the output voltage V out and the DC component corresponding to the noise voltage V noise and an intermediate voltage V int from the periodic binary adjustment signal V reg This combination ensures that the currents flowing through the various power supply branches are equal, thereby improving the stability of the converter D1.

[0044] Alternatively, according to a particular embodiment, N diodes D i is replaced by N switches controlled by external signals. In one example, the switches are made of transistors. In this case, switch Q2 can be omitted.

[0045] 4 shows a distribution circuit 22 of the control circuit 2 according to the present invention. The distribution circuit 22 distributes the regulated signal V generated by the voltage regulation circuit 21. reg The distribution circuit 22 receives each power supply branch PH i Regarding the adjustment signal V reg Dedicated activation signal CMD from i The actuation signal CMD is generated. i are phase shifted relative to one another without the need for an external clock signal of a fixed frequency. The distributed circuit 22 comprises a chain of N D-type flip-flops, N being the power supply branch PH i As a non-limiting example, consider an example of three power supply branches, and therefore three D-type flip-flops, denoted 221, 222, and 223. The flip-flops 221, 222, and 223 all receive the regulation signal V reg The flip-flops 221, 222, and 223 are synchronized by the outputs s of the flip-flops of rank i=1 to N-1. i is attached to the input of the next flip-flop of rank i+1. A chain of N flip-flops forms a shift register.

[0046] The distribution circuit 22 comprises an OR logic cell 230 having a first input connected to the output s3 of the last flip-flop 223, a second input receiving the initialization signal Init1, and an output connected to the input of the flip-flop of rank i=1. The logic cell 230 is used to initialize the chain of flip-flops by injecting a high logic state at the input of the first flip-flop of rank i=1 when the initialization signal Init1 is in a high logic state. In an initialization step prior to the operation of the converter, the initialization signal Init1 is in a high logic state "1" so as to obtain a logic value "1" at the input of the flip-flop 221 of rank i=1. The inputs and outputs of the other flip-flops in the chain are in a low logic state "0". Initially, the output of the flip-flop 221 of rank i=1 is in a low logic state "0". The distribution circuit 22 further comprises N AND logic cells. In the illustrated example, these are three AND cells, designated 231, 232, and 233. Each AND cell has a first input that receives the output of an associated D-type flip-flop. Each AND cell receives an adjustment signal V reg Each AND cell has a second input that receives an activation signal CMD i The relevant power supply branch PH i The first AND cell 231 receives the output signal s1 from the flip-flop 221 and generates an activation signal CMD1 for controlling the power supply branch PH1 of rank i=1. The second AND cell 232 receives the output signal s2 from the flip-flop 222 and generates an activation signal CMD2 for controlling the power supply branch PH2 of rank i=2. The third AND cell 233 receives the output signal s3 from the flip-flop 223 and generates an activation signal CMD3 for controlling the power supply branch PH3 of rank i=3.

[0047] In general, the power supply branch PH i is the associated actuation signal CMD i is in a high logic state "1", it supplies current to the load circuit. iis the output signal s of the associated flip-flop i and the adjustment signal V reg and are simultaneously in a high logic state "1".

[0048] The following describes the temporal changes in the output signals s1, s2, and s3 in a control cycle Cyc including three consecutive stages E1, E2, and E3, as shown in the timing chart of Fig. 5. Fig. 5 shows a timing chart of the internal and external signals of the control circuit 3 to explain the operation of the distribution circuit 22.

[0049] The first step E1 is to adjust the regulation signal V reg The first D-type flip-flop 222 is triggered by the first rising edge FM1 on the input of the first flip-flop 221. Said rising edge causes the high logic state "1" to be transmitted from the input of the first flip-flop 221 to its output s1. Thus, the high logic state "1" is obtained only at the first output s1. The high logic state "1" of the first output s1 is also transmitted to the input of the second flip-flop 222. The high logic state "1" at the output s1 is maintained as long as there is no rising edge following the first rising edge FM1. The output signals s2 and s3 of the other D-type flip-flops in the chain are maintained in the low logic state "0". Thus, at the start of step E1, the following configuration is obtained: the output signal s1 of the flip-flop 221 and the adjustment signal V reg and are simultaneously in the high logic state "1", which generates a high state pulse in the actuation signal CMD1 while keeping the other actuation signals CMD2 and CMD3 in the low logic state. Only the power supply branch PH1 of rank i=1 is in the conducting state and injects the power supply current towards the target load 3.

[0050] The second step E2 is to adjust the regulation signal V regThe OR logic cell 230 receives two low logic states "0" at its two inputs. The output s1 of the flip-flop 221 transitions to the low logic state "0". The high logic state "1" at the output s2 is maintained as long as there is no rising edge following the rising edge FM2. The output signals s1 and s3 of the other D-type flip-flops in the chain are maintained in the low logic state "0". Thus, at the start of step E2, the following configuration is obtained: the output signal s2 of the flip-flop 222 and the adjustment signal V reg and are simultaneously in the high logic state "1", which generates a high state pulse in the actuation signal CMD2 while keeping the other actuation signals CMD1 and CMD3 in the low logic state. Only the power supply branch PH2 of rank i=2 is in the conducting state and injects a power supply current towards the target load 3.

[0051] The third step E3 is to adjust the regulation signal V reg The rising edge FM3 on the third flip-flop 223 passes the signal from its input to its output s 232. The rising edge FM3 causes the second flip-flop 222 to transmit a high logic state "1" to its input. Thus, a high logic state "1" is obtained only at the third output s3. The high logic state "1" of the third output s3 is also transmitted to the input of the first flip-flop 221 via the OR logic cell 230. The high logic state "1" at the output s3 is maintained as long as there is no rising edge following the rising edge FM3. Similarly, the rising edge FM3 propagates a low logic state "0" from the input of the second flip-flop 222 to its output s2. The same applies to the output s1 of the flip-flop 221. Thus, the output signals s1 and s2 of the other D-type flip-flops in the chain are maintained in the low logic state "0". Thus, at the start of step E3, the following configuration is obtained: The output signal s3 of the flip-flop 223 and the adjustment signal V reg and are simultaneously in the high logic state "1", which generates a high state pulse in the actuation signal CMD3 while keeping the other actuation signals CMD1 and CMD2 in the low logic state. Only the power supply branch PH3 of rank i=3 is in the conducting state and injects the power supply current towards the target load 3.

[0052] Thus, the distribution circuit 22 determines the predetermined value of the target phase shift and the adjustment signal V reg Without prior knowledge of the frequency of the phase-shifted differential signal CMD i The number of flip-flops and AND logic cells is determined by the power supply branch PH i The adjusting signal V that synchronizes the chain of flip-flops is equal to the number of reg The frequency of the power supply branch PH of the converter D1 is divided by the number of power supply branches N. i The respective switching frequencies f CMD is related to the following relationship: f CMD =f reg Controlled by / N, f reg is the adjustment signal V reg is the frequency of the power supply branch PH i is the number of

[0053] The control circuit 2 controls the second switch Q i2 To control the actuation signal CMD i The signal generating means may include, for example, an inverter circuit.

[0054] 6 shows a polyphase electric circuit D1 according to a second embodiment of the present invention. In the second embodiment, the control circuit 2 further comprises a protection circuit 23 inserted between the voltage regulation circuit 21 and the distribution circuit 22. The protection circuit 23 protects the regulated signal V from the voltage regulation circuit 21. reg and sends the master signal V CMD Generates the master signal V CMD Compared with the first embodiment, the adjustment signal V reg Instead of V, it serves as the clock signal for the daisy-chained D-type flip-flops. reg The duration of setting the state to high or low is determined by a predetermined threshold T ON,max The protection circuit 23 is configured to limit the power supply branch PH i The maximum conduction time T ON,max By controlling , it is possible to induce a controlled temporary imbalance in the currents flowing through the power supply branches of the converter at the current transition edges. Although this imbalance should generally be avoided, it has been found to improve the response time of the converter if allowed for a controlled duration.

[0055] As an example, a D-type flip-flop employed in SET / RESET mode can be used to implement the protection circuit 23, as shown in Figure 7a. The SET signal is connected to the master signal V CMD The RESET signal is set to a high state by the master signal V CMD The master signal V returns to a low state. In the event of a conflict, the RESET signal takes priority. Figure 7b shows the RESET signal generation circuit in the protection circuit 23. CMD is the circuit T on_gen is input, and the maximum operating time is TON,max It allows you to set the circuit T on_gen is the resistance R 23 and capacitor C 23 The RC filter is connected to the master signal V CMD A voltage of is applied to the circuit T on_gen is the diode D 23 Further provided with a diode D 23 The anode of the resistor R 23 and capacitor C 23 Diode D is connected to the common node between 23 The cathode of the resistor R 23 connected to the other pole of the circuit T on_gen The output signal of resistor R 23 and capacitor C 23 and propagates to the first input of the AND logic cell. The second input of the AND logic cell receives a complementary regulation signal V (e.g., provided from the negative output of the comparator COMP). reg The RESET signal is generated by the memory cell to a D-type flip-flop of the protection circuit 23.

[0056] Figure 7c shows the SET signal generation circuit in the protection circuit 23. It receives the already generated RESET signal at one input and the regulation signal V at the other input. reg It includes an AND cell that receives

[0057] Preferably, according to a second embodiment illustrated in Fig. 6, the control circuit 2 further comprises a dead time circuit 24 inserted between the distribution circuit 22 and the power cell 1. The dead time circuit 24 controls the first CMD i Activation signal and second CMD barre,i and a complementary actuation signal CMD. barre,i The transition edges of the power supply branch PH i The first switch Q i1 and the second switch Q i2This can avoid the problem of mutual conduction between the

[0058] The implementation of the dead time circuit 24 is independent of the implementation of the protection circuit 23 in the control circuit 2 according to the invention. According to a third embodiment, the control circuit 2 comprises the above-mentioned voltage regulation circuit 21, the protection circuit 23 and the distribution circuit 22. According to a fourth embodiment, the control circuit 2 comprises the above-mentioned voltage regulation circuit 21, the distribution circuit 22 and the dead time circuit 24.

[0059] The present invention is applicable to several types of multi-phase circuits, particularly power converters such as DC / DC, AC / AC, AC / DC, and DC / AC, and switched-mode power supplies (SMPS). The solution is useful for any multi-phase, multi-level, or hybrid converter that uses nonlinear control. In addition, direct current to alternating current (DC-AC) inverters in solar power, wind power, and energy storage systems can also benefit from the generation of control according to the present invention. [Explanation of symbols]

[0060] 1 power cell 2. Control circuit 3 Target Load 11 Output Nodes 12 Input Nodes 13 Central Node 21 Voltage Regulator Circuit 22 Distributed circuit 23 Protection circuit 24 Dead Time Circuits 211 Common Node 221, 222, 223 D-type flip-flops CMD1, CMD2, CMD3 activation signals COMP comparator D1 Polyphase Electrical Circuit D1, D2, D3 diodes GND Ground I1, I N Element Current Init1 initialization signal I out Output Current L1, L N Element Inductor PH1, PH N Power Supply Branch Q1 Third Switch Q 11 , Q N1 First Switch Q 12 , Q N2 Second Switch Q2 4th switch R4, R6 resistance V in Input voltage V int Intermediate signal V noise Noise Voltage V out Output Voltage V reg adjustment signal

Claims

1. Output current (I) for supplying power to the target load (3) ｏｕｔ ) or output voltage (V ｏｕｔ ), wherein the polyphase electric circuit (D1) is configured to generate - a power cell (1), Input voltage (V ｉｎ an input node (12) for supplying 〇Ground (GND) and The output voltage (V ｏｕｔ an output node (11) for providing N power supply branches (PH) converging towards the output node (11) １ , P.H. Ｎ ), where N is a natural number greater than 1, and each power supply branch (PH １ , P.H. Ｎ )but, At least one first switch (Q １１ , Q Ｎ１ ) and separated from the input node (12) by at least one second switch (Q １２ , Q Ｎ２ a central node (13) separated from said ground (GND) by N power supply branches (PH １ , P.H. Ｎ )and a power cell (1) comprising: a control circuit (2), The output voltage (V ｏｕｔ ) and alternating noise voltage (V ｎｏｉｓｅ ) based on the combination of an alternating binary adjustment signal (V ｒｅｇ a voltage regulation circuit (21) configured to generate the noise voltage (V ｎｏｉｓｅ ) is adjusted by the voltage adjustment circuit (21), ■ Selected power supply branch (PH １ , P.H. Ｎ ) the potential of the central node (13) of ■ The input voltage (V ｉｎ ) a voltage regulation circuit (21) generated based on For each power supply branch, the regulation signal (V ｒｅｇ ) based on at least one dedicated actuation signal (CMD １ , C.M.D. ２ , C.M.D. ３ a distribution circuit (22) configured to generate a plurality of said actuation signals, wherein the actuation signals are phase shifted relative to one another according to a time-varying phase shift; a control circuit (2) comprising: A polyphase electric circuit (D1) comprising:

2. The voltage regulation circuit (21) regulates the intermediate signal (V ｉｎｔ a comparator (COMP) for comparing the intermediate signal (V ｉｎｔ ) is the output voltage (V ｏｕｔ ) and the DC component corresponding to the noise voltage (V ｎｏｉｓｅ 2. The polyphase electric circuit (D1) of claim 1, further comprising a comparator (COMP) having an AC component corresponding to the phase difference between the phases of the input and output of the polyphase electric circuit (D1).

3. The voltage regulation circuit (21) is connected to a third switch (Q １ ) when the third switch is on, the input voltage (V ｉｎ ), wherein the third switch (Q １ ) is the adjustment signal (V ｒｅｇ 3. A polyphase electric circuit (D1) according to claim 1 or 2, comprising a divider bridge controlled by a

4. The voltage regulation circuit (21) includes N diodes (D １ , D ２ , D ３ ), and each diode (D １ , D ２ , D ３ ) has its anode connected to the central node (13) of the power supply branch associated with said diode, and its cathode connected to the regulating signal (V ｒｅｇ ) controlled by a fourth switch (Q ２ ) connected to a common node (211) separated from the ground (GND) by N diodes (D １ , D ２ , D ３ 3. A polyphase electric circuit (D1) according to claim 1 or 2, comprising:

5. The distribution circuit (22) is connected to the adjustment signal (V ｒｅｇ 5. A polyphase electric circuit (D1) according to any one of claims 1 to 4, comprising a chain of N D-type flip-flops (221, 222, 223) synchronized according to the following formula:

6. 6. The polyphase electric circuit (D1) of claim 5, wherein the distribution circuit (22) further comprises an OR-type logic cell having a first input connected to the output of the flip-flop of rank N, a second input receiving an initialization signal (Init1), and an output connected to the input of the flip-flop of rank i=1.

7. The distributed circuit (22) comprises N AND-type logic cells, each AND-type cell having a first input receiving the output of an associated D-type flip-flop, and a second input receiving the adjustment signal (V ｒｅｇ a second input for receiving said actuation signal (CMD １ , C.M.D. ２ , C.M.D. ３ 7. A polyphase electric circuit (D1) according to claim 5 or 6, further comprising N AND-type logic cells having outputs for supplying a power supply branch to an associated power supply branch.

8. The control circuit (2) is inserted between the voltage adjustment circuit (21) and the distribution circuit (22), and the adjustment signal (V ｒｅｇ 8. The polyphase electric circuit (D1) according to any one of claims 1 to 7, further comprising a protection circuit (23) configured to limit the duration for setting the first or second input of the multi-phase electric circuit (D1) to a predetermined threshold.

9. The control circuit (2) is inserted between the distribution circuit (22) and the power cell (1) and for each power supply branch, outputs a first activation signal (CMD １ , C.M.D. ２ , C.M.D. ３ ) and second (CMDN １ , C.M.D.N. ２ , C.M.D.N. ３ 9. The polyphase electric circuit (D1) according to claim 1, further comprising a dead time circuit (24) configured to generate a supplementary actuation signal of the second actuation signal, wherein each transition edge of the second actuation signal is shifted in time with respect to the first actuation signal.

10. Each power supply branch (PH １ , P.H. Ｎ ) has an associated element inductor (L) attached between the central node (13) and the output node (11). １ , L Ｎ ) and each power supply branch (PH １ , P.H. Ｎ ) through the associated element inductor １ , I Ｎ ) and an associated element inductor (L １ , L Ｎ 10. A polyphase electric circuit (D1) according to any one of claims 1 to 9, comprising:

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