Device surface termination using superconducting structure and alloy

Abstract

To provide a superconducting structure that reduces the risk of damage to contact between superconductors in a quantum circuit, and a method for manufacturing the same.SOLUTION: A method of manufacturing a superconductor device (superconducting structure 200) includes providing a first metal layer 204 on a substrate 202, eliminating oxidation of the top surface of the first metal layer, and depositing a second metal layer 208 on the first metal layer, thereby creating a superconducting alloy 206 of the first and second metal layers between the first and second metal layers, with no oxide layer between the superconducting alloy and the first metal layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to quantum computing, and more particularly to superconducting structures and methods for making same. [Background technology]

[0002] Superconducting quantum computing is the implementation of quantum computers in superconducting electronic circuits. Quantum computing studies the application of quantum phenomena to information processing and communication. Various models of quantum computing exist, with the most widespread model involving the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states, which may be a quantum superposition of both states. A quantum gate is a generalization of a logic gate, but a quantum gate describes the transformation that one or more qubits will undergo after the gate is applied to them, given their initial state. Various quantum phenomena, such as superposition and entanglement, have no analogues in the classical computing world and therefore may involve special structures, techniques, and materials. Summary of the Invention

[0003] According to one embodiment, a superconductor device includes a first metal layer on a substrate. A second metal layer is on the first metal layer. A superconducting alloy of the first metal layer and the second metal layer is between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

[0004] In one embodiment, the first metal layer is niobium (Nb), the second metal layer is aluminum (Al), and the superconducting alloy is Al 3 Nb.

[0005] In one embodiment, the orientation of the crystal grains of the superconducting alloy is substantially aligned with the (002) plane parallel to the surface of the substrate metal layer.

[0006] In one embodiment, the electrode is on the second metal layer.

[0007] In one embodiment, the electrodes are Josephson junction electrodes.

[0008] In one embodiment, the superconducting alloy serves to protect the first metal layer from oxidation or contamination that may affect the performance of the superconductor device.

[0009] According to one embodiment, a method for fabricating a superconductor device includes providing a first metal layer on a substrate. Oxidation of an upper surface of the first metal layer is rejected. A second metal layer is deposited on the first metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

[0010] In one embodiment, eliminating oxidation of the top surface of the first metal layer includes placing a second metal layer over the first metal layer after deposition of the first metal layer and before exposing the top surface of the first metal layer to air.

[0011] In one embodiment, eliminating oxidation of the top surface of the first metal layer further comprises maintaining the superconductor device in a vacuum between deposition of the first metal layer and deposition of the second metal layer.

[0012] In one embodiment, eliminating oxidation of the top surface of the first metal layer includes exposing the top surface of the first metal layer to air to remove all oxidation from the first metal layer, followed by cleaning the top surface of the first metal layer, and then depositing a second metal layer over the first metal layer.

[0013] In one embodiment, the second metal layer is etched away after the formation of the superconducting alloy.

[0014] In one embodiment, creating the superconducting alloy includes annealing the first metal layer and the second metal layer at a predetermined temperature.

[0015] In one embodiment, the superconducting alloy creates an electrical pathway from the first metal layer to the second metal layer.

[0016] In one embodiment, the lattice orientation of the superconducting alloy is (002), (112), or (101), depending on the temperature at which the first and second metal layers are annealed to create the superconducting alloy.

[0017] In one embodiment, an electrode is deposited on the second metal layer.

[0018] In one embodiment, the electrodes are Josephson junction electrodes.

[0019] In one embodiment, the second metal layer is removed and an electrode is deposited on top of the superconducting alloy.

[0020] According to one embodiment, a method for fabricating a superconductor device includes providing a first metal layer on a substrate. An initial oxide layer is provided on top of the first metal layer. A second metal layer is deposited on the initial oxide layer. A superconducting alloy of the first and second metal layers is created between the first and second metal layers. The initial oxide layer is transferred to the top surface of the superconducting alloy during the creation of the superconducting alloy.

[0021] In one embodiment, the initial oxide and second metal layer on the top surface of the superconducting alloy are removed. An electrode is deposited on the superconducting alloy.

[0022] These and other features will become apparent from the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings.

[0023] The drawings are of exemplary embodiments. The drawings do not depict all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more effective illustration. Some embodiments may be practiced with additional components or steps, or without all components or steps shown, or both. When the same number appears in different drawings, the number refers to the same or similar components or steps. [Brief explanation of the drawings]

[0024] [Figure 1] (A) shows a first superconductor layer on a substrate, and (B) shows a residual oxide layer on the first superconductor layer. [Figure 2] 1 is a simplified cross-sectional view of a superconducting structure consistent with example embodiments. [Figure 3] (A) shows a semiconductor structure prior to the formation of a superconducting alloy between the metal layers consistent with an example embodiment; (B) illustrates the semiconductor structure after a superconducting alloy has been formed between the first metal layer and the second metal layer consistent with an example embodiment; (C) shows a semiconductor structure including an electrode on the second metal layer consistent with an example embodiment; and (D) shows a semiconductor structure including an electrode directly on the superconducting alloy consistent with an example embodiment. [Figure 4] FIG. 10 illustrates the formation of superconducting alloys with different orientations based on annealing temperature, consistent with example embodiments. [Figure 5] 1A-1D illustrate different processing steps for fabricating a superconducting structure including an initial oxide layer between a first metal layer and a second metal layer, consistent with an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0025] Overview In the following detailed description, numerous specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it will be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, or circuits, or combinations thereof, have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0026] In one aspect, spatially related terms such as "front," "back," "top," "bottom," "beneath," "below," "lower," "above," "upper," "side," "left," "right," etc. are used in relation to the orientation of the figures being described. Because components of the disclosed embodiments may be positioned in many different orientations, the directional terms are used for illustrative purposes and are in no way limiting. As such, it will be understood that the spatially related terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, for example, the term "below" can encompass both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced in other directions) and the spatial relationship descriptors used herein should be interpreted accordingly.

[0027] As used herein, the terms "lateral" and "horizontal" describe an orientation parallel to the first surface of the chip.

[0028] As used herein, the term "vertical" describes an orientation that is disposed perpendicular to the first surface of the chip, chip carrier, or semiconductor body.

[0029] As used herein, the terms "coupled" and / or "electrically coupled" do not mean that elements must be directly coupled together - intervening elements may be present between the "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low ohmic electrical connection between the elements electrically connected together.

[0030] Although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the example embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Example embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations due, for example, to manufacturing techniques and / or tolerances, may be expected. As such, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of the regions of a device and are not limiting in scope.

[0032] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the spirit and scope as defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

[0033] As used herein, certain terms are used to indicate what may be considered idealized behavior, such as "lossless," "superconductor," or "superconducting," and are intended to encompass functionality that may not be strictly ideal but is within acceptable margins for a given application. For example, certain levels of loss or tolerance may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms.

[0034] The concepts herein relate to quantum technologies and quantum chips. With respect to quantum technologies, electromagnetic energy associated with a qubit may be stored, for example, in so-called Josephson junctions and in the capacitive and inductive elements used to form the qubit. Other examples may include spin qubits or topological qubits coupled to resonators, microfabricated ion traps, etc. Other types of superconducting components are similarly supported by the teachings herein, including (without limitation) circulators, isolators, amplifiers, filters, active control electronics such as rapid single flux quantum (RSFQ), etc.

[0035] In one example, to read out the qubit state, a microwave signal is applied to a microwave readout cavity that couples to the qubit at the cavity frequency. The transmitted (or reflected) microwave signal passes through a number of adiabatic stages and low-noise amplifiers used to block or reduce noise and improve the signal-to-noise ratio. The amplitude and / or phase of the return / output microwave signal carries information about the qubit state, such as whether the qubit is detuned to a ground state or an excited state. The microwave signal carrying quantum information about the qubit state is typically weak (e.g., on the order of a few microwave photons). Various circuits and techniques may be used to measure this weak signal. For example, low-noise quantum-limited amplifiers (QLAs), such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPAs), may be used as preamplifiers at the output of a quantum system to boost the quantum signal while adding a minimal amount of noise, as dictated by quantum mechanics, to improve the signal-to-noise ratio of the output chain. In addition to Josephson amplifiers, certain Josephson microwave components that use Josephson amplifiers or Josephson mixers, such as Josephson circulators, Josephson isolators, and Josephson mixers, may be used in scalable quantum processors. Thus, Josephson junctions are key circuit elements in superconducting quantum computers. A Josephson junction may contain a thin layer of insulator, sometimes referred to as a barrier or tunnel barrier, between two layers of superconductor. The Josephson junction acts as a superconducting tunnel junction.

[0036] A qubit system may include one or more readout resonators coupled to the qubit. The readout resonator may be a transmission line that includes a capacitive connection to ground on one side and is shorted to ground on the other side, such as for a quarter-wave resonator, or may have a capacitive connection to ground, such as for a half-wave resonator, that results in oscillation in the transmission line at a resonant frequency of oscillation that is near the frequency of the qubit. For example, the readout resonator may act on a pulse coming from a control / measurement device at the readout resonator frequency. The pulse acts as a measurement that decoheres the qubit and collapses the pulse into a "one" or "zero" state, thereby signaling a phase shift for the measurement pulse.

[0037] Between the qubits, there may be coupling resonators that allow different qubits to be coupled together to realize quantum logic gates. Coupling resonators are typically structurally similar to readout resonators in that they are transmission lines with capacitive connections to ground on both sides, which also result in oscillation within the coupling resonator. When qubits are implemented as transmons, each side of the coupling resonator is coupled (e.g., capacitively or inductively) to a corresponding qubit by being appropriately close to the qubit (e.g., a capacitor). Two qubits are coupled together through the coupling resonators because each side of the coupling resonator has a coupling with a different qubit. In this way, there is an interdependence between the states of the coupled qubits, which allows the coupling resonator to use the state of one qubit to control the state of the other qubit. Entanglement occurs when the interaction between two qubits is such that the states of the two cannot be determined independently but can only be determined relative to the entire system. In this way, the states of the two qubits are linked together such that a measurement of one of the qubits disrupts the state of the other qubit.

[0038] Typical materials for making interconnects include, but are not limited to, niobium (Nb), aluminum (Al), niobium nitride (NbN), titanium nitride (TiN), niobium titanium nitride (NbTiN), etc., and are sometimes referred to herein as superconductors. It will be understood that other suitable materials having superconducting properties may be used as well.

[0039] Applicant has recognized that improvements can be made to superconductor device structures and their fabrication to increase the computational power and reliability of quantum computers in general, and superconducting structures in particular. Achieving low error rates and greater reliability relates, among other aspects, to precisely manipulating the states of qubits and performing sequential operations that provide consistent results and do not simply provide unreliable data. Quantum technology is still an evolving field, and providing structures with highly predictable and even ideal performance is challenging.

[0040] In one aspect, the teachings herein are based on Applicant's insight that protecting certain interfaces of superconductors used in superconducting quantum circuits from oxidation can improve the decoherence and signal integrity of superconducting qubits. Applicant further recognizes that the direct application of conventional integrated circuit techniques for protecting materials from oxidation to superconducting quantum circuits may be ineffective due to unique challenges presented by quantum circuits that are not present in classical computing architectures. Accordingly, embodiments of the present disclosure are further based on the recognition that issues unique to quantum circuits have been considered when evaluating the applicability of conventional integrated circuit techniques for constructing superconducting quantum circuits, particularly for selecting materials and processes used to protect the superconducting materials of such circuits from oxidation.

[0041] The surface of a superconductor in a quantum circuit contains potentially lossy material due to oxide growth or surface contamination that degrades resonator quality. In this regard, FIG. 1(A) illustrates a first superconductor layer 104 on a substrate 102. A surface oxide 106 may grow naturally, and is therefore sometimes referred to herein as a native oxide. As illustrated in FIG. 1(B), there is a residual oxide 107 that remains when another superconductor layer 108 is placed on top (e.g., in the formation of a Josephson junction).

[0042] Contacts between superconductor elements, such as capacitor pads and Josephson junction electrodes that may be implemented by superconductor layers 104 and 108, are important for good qubit performance. However, residual oxide or surface contamination 107 in the contact areas can degrade qubit coherence. For example, semiconductor processes often involve separate chambers for different depositions, and vacuum is often broken, which can quickly result in the native oxide 107 discussed herein. One method for removing the native oxide 107 is to use in-situ cleaning (e.g., ion milling, sputter cleaning, vacuum baking, vapor HF, etc.). However, there are limitations to the level of cleanliness that can be achieved. For example, vapor HF is typically not performed in a vacuum (although it may be performed), so oxide removal sometimes continues in air before loading into the deposition chamber. Oxide formation is thus limited but not eliminated. Regarding ion milling, although it is performed in a vacuum, ion milling can also lead to some degree of redeposition because it is a sputter removal of oxide.

[0043] Thus, the teachings herein provide methods and systems for mitigating the loss of superconductor-to-superconductor contacts in quantum circuits. The techniques described herein may be implemented in numerous ways. Exemplary implementations are provided below with reference to the following figures.

[0044] Exemplary Superconducting Structures Reference is now made to Figure 2, which is a simplified cross-sectional view of a superconducting structure 200 consistent with an example embodiment. Superconducting structure 200 may be used to implement a variety of superconducting circuits, including, without limitation, Josephson junctions (JJs), superconducting capacitors, circulators, isolators, amplifiers, filters, etc. To facilitate this discussion, superconducting structures herein will sometimes be discussed in the context of JJs, while it will be understood that other superconducting structures are similarly supported.

[0045] The superconducting structure 200 may include a substrate 202. In various embodiments, the substrate 202 may comprise any suitable material or combination of materials, such as doped or undoped silicon, glass, a dielectric, etc. For example, the substrate may comprise a silicon-on-insulator (SOI) structure, e.g., with a buried insulator layer, or a bulk material substrate, e.g., with appropriately doped regions, typically referred to as wells. In another embodiment, the substrate may be silicon with a silicon oxide, nitride, or other insulating film thereon.

[0046] Other materials that may be used for the substrate include, without limitation, any of sapphire, aluminum oxide, germanium, gallium arsenide (GaAs) or other III-V periodic table compounds, indium phosphide (InP), silicon carbide (SiC), superconducting alloys of silicon and germanium, quartz, etc. Thus, as used herein, the term substrate 202 refers to a foundation upon which various superconducting structures may be built.

[0047] A first metal layer 204 is located on a substrate 202. In one embodiment, the first metal layer 204 is niobium (Nb). A second metal layer 208 is located on the first metal layer 204. In one embodiment, the second metal layer 208 is aluminum (Al). Between the first metal layer 204 and the second metal layer 208 is a superconducting alloy 206 of the first and second metal layers. For example, the superconducting alloy may be niobium aluminide AlNb. As used herein, the term niobium aluminide includes all stable aluminides present in the Nb-Al phase diagram. Niobium aluminide refers to any alloy of Al and Nb. Three phases are possible: AlNb, AlNb2, and NbAl (i.e., only three niobium aluminide phases exist in the binary Nb-Al equilibrium phase diagram). It should be noted that in embodiments with very thin films, unstable Al-Nb phases may form with crystal structures and compositions not found in the bulk phase.

[0048] In various embodiments, different grain orientations of AlNb may be formed based on temperature and time conditions, as discussed in more detail below. Significantly, no oxide layer is present between the first metal layer 204 and the superconducting alloy 206. Additionally, in one embodiment, no oxide layer is present between the second metal layer 208 and the superconducting alloy 206.

[0049] Superconducting circuit elements such as, without limitation, JJs, resonators, coupling pads, capacitors, gate electrodes, etc. are typically capped with a second conductor. In one embodiment, the second conductor (i.e., second metal layer 208) is deposited on the first conductor (i.e., first metal layer 204) before the first metal layer 204 is exposed to air to prevent oxidation on the first metal layer.

[0050] Alternatively or additionally, the top surface of first metal layer 204 is thoroughly cleaned before second metal layer 208 is deposited. The two conductive layers, including first metal layer 204 and second metal layer 208, are alloyed at their interface to create an electrical path from the base conductor (i.e., first metal layer 204), through superconducting alloy 206, and to the JJ electrode, represented in FIG. 2 by second metal layer 208. The lack of an oxide layer between metal layers 204 and 208 and superconducting alloy 206 improves the quality of the contact (e.g., the contact between the capacitor pad, represented by second metal layer 208, and the JJ 208 lead for loss reduction), thereby creating a more ideal JJ. In various embodiments, metal layer 208 may be a metal that is only used to create interface alloy 206, in which case the electrode is deposited later. Alternatively, the metal layer 208 may also be a single layer (or a double layer electrode) that is subsequently annealed to form the superconducting alloy 206. In some embodiments, the superconducting circuit is constructed prior to annealing to form the interfacial alloy 206.

[0051] Exemplary Processes for Superconducting Structures With the foregoing description of the exemplary superconducting structure 200, it may be helpful to discuss an exemplary process for fabricating the superconducting structure 200. To that end, FIGS. 3(A) through 3(D) illustrate various steps in the fabrication of a superconducting structure consistent with exemplary embodiments. More specifically, FIG. 3(A) illustrates a semiconductor structure 300A prior to the formation of a superconducting alloy between the metal layers consistent with exemplary embodiments. In various embodiments, the base first metal layer 304 is capped with a second metal layer 308 either (i) prior to atmospheric exposure or (ii) after atmospheric exposure, after which native metal oxide is substantially removed prior to the second metal layer 308 deposition, collectively referred to herein as native metal oxide elimination. For example, in various embodiments, the second metal layer 308 is placed on the first metal layer 304 before oxidation occurs (e.g., while in a controlled environment such as a vacuum, even when the chip goes from one deposition chamber to another), or by thorough cleaning of the top surface of the first metal layer 304 to remove all oxide on the first metal layer 304 before the second metal layer 308 is placed on top of the first metal layer 304.

[0052] In various embodiments, this cleaning of oxide from the top surface of the first metal layer 304 may use wet cleaning or dry cleaning (preferred). Such dry cleaning may include, without limitation, ion milling, pre-sputtering, or another suitable technique for removing oxide from the top of the first metal layer 304. In this manner, an oxide-free interface may be achieved. Thus, the interface between the first metal layer 304 and the second metal layer 308 is substantially free of oxide. A superconducting alloy is then formed between the two metal layers 304 and 308, as discussed in more detail below.

[0053] 3(B) illustrates the semiconductor structure 300B after a superconducting alloy 306 has been formed between the first metal layer 304 and the second metal layer 308, consistent with an example embodiment. In one embodiment, the superconducting alloy is formed using annealing. Other methods of creating the superconducting alloy 306 between the first metal layer 304 and the second metal layer 308 include, without limitation, increasing the pressure and / or bias by a predetermined amount during the deposition of the second metal layer 308.

[0054] In one embodiment, the first metal layer 304 is niobium (Nb) and the second metal layer 308 is aluminum (Al), and the resulting alloy 306 between these two metals is niobium aluminide AlNb(002), where (002) is the lattice orientation of the superconducting alloy 306 relative to the 110 plane of Nb and, in this case, the surface of the substrate.

[0055] In various embodiments, depending on the various superconductor structures to be fabricated, the second metal layer 308 may be retained or etched away using wet or dry (plasma) etching. In this manner, the unreacted second metal layer 308 may be left in place or removed, selectively leaving the exposed metal alloy 306, which now protects the first metal layer 304 from reaction with the ambient environment. By creating the metal alloy 306, the first metal layer 304 is protected from oxidation or other elements that may affect the performance of the superconductor device of the first metal layer 304, thereby improving device performance.

[0056] 3(C) and 3(D) illustrate semiconductor structures 300C and 300D, respectively, including an electrode 320 on the second metal layer 308 and an electrode 320 directly on the superconducting alloy 306, consistent with exemplary embodiments. For example, the junction electrode 320 may belong to a JJ. The JJ may be on a capacitor (i.e., formed by subtractive etching) or on a substrate connected to the capacitor by the junction electrode (i.e., Dolan shadow junction construction). A three-layer junction process may be used, for example, for the fabrication of JJ logic devices and integrated circuits. For example, the junction electrode 320 may have a thin layer of oxide on the electrode, which may be covered by another metal layer to provide a three-layer configuration (e.g., a JJ on a capacitor).

[0057] Referring now to FIG. 4, FIG. 4 illustrates the formation of a superconducting alloy 406 with different orientations based on annealing temperature, consistent with an example embodiment. For purposes of discussion, and not limitation, an original semiconductor structure 400A has a first metal layer 404 comprising niobium (Nb) and a second metal layer 408 comprising aluminum (Al) disposed on a substrate 402. X-ray diffraction intensity charts 400C and 400D (referring to structure 400B) show that at temperatures near 500° C., a superconducting alloy 406 forms at the interface between the niobium layer 404 and the aluminum layer 408. The superconducting alloy 406 (i.e., AlNb) has a lattice structure that may be oriented differently from the substrate based on different annealing temperatures. The desired orientation for optimal contact may be controlled by the annealing conditions.

[0058] Different temperatures produce different alloy thicknesses. For example, a thin layer of AlNb(002) forms below 400°C with long annealing times and grows over time. As the temperature is increased (e.g., 650°C), the superconducting alloy 406 begins to contain grains exhibiting different orientations (AlNb(112) and (101)) as the grains in the film become more randomly oriented. In some embodiments, similar results may be achieved with different combinations of temperature and time. For example, long annealing times but low temperatures, sometimes referred to herein as isothermal anneals, may also be used to achieve the superconducting alloy AlNb(002). Applicant has determined that annealing temperatures from 350°C to 500°C with respect to the Nb / Al interface produce superconducting alloy AlNb with 002 alignment relative to the underlying Nb 110 plane.

[0059] Note that Nb404 and Al408 form a superconducting alloy 406 above 350 C when in direct contact. Alloying Nb404 and Al408 forms an electrical path from Nb to Al through the Nb-Al alloy 406. In one embodiment, no oxygen is present at the interface between Nb404 and the Nb-Al alloy 406, and only a small amount of oxygen is present on the surface of the Al layer 408. Therefore, there are no residual Nb oxides to cause decoherence, which substantially enhances superconductor device performance.

[0060] The preceding discussion generally relates to avoiding an oxide layer between a first metal layer (e.g., Nb) and a second metal layer (e.g., Al). It should be noted that if native niobium oxide is present between the two metal layers, a superconducting alloy can still form, albeit less rapidly, under certain conditions. In this regard, reference is made to FIGS. 5(A) through 5(D), which provide different processing steps for fabricating a superconducting structure including an initial oxide layer between a first metal layer 504 and a second metal layer 508, consistent with exemplary embodiments. As illustrated in FIG. 5(A), a first metal layer 504 (e.g., Nb) is located on a substrate 502. A second metal layer (e.g., Al) 508 is located on the first metal layer 504. A native oxide layer (e.g., niobium oxide) 505 is located between metal layers 508 and 504.

[0061] FIG. 5(B) illustrates that during alloy formation (eg, by annealing), the native oxide 505 migrates away from the niobium surface to the surface of the superconducting alloy 506 and is represented by oxide layer 507.

[0062] 5(C) illustrates that a selective etch can remove second metal layer 508 and oxide layer 507. In various embodiments, both second metal layer 508 and oxide layer 507 may be removed simultaneously or separately by different etch steps. An electrode (e.g., Josephson) 520 may then be deposited on top of superconducting alloy 506. For example, a selective etch and aluminum JJ fabrication results in an electrical path from Nb to Al through a niobium oxide defect-free Nb-Al alloy.

[0063] Accordingly, Applicant has determined that while a superconducting alloy between metal layers without an oxide (e.g., niobium oxide) layer between the metal layers can be achieved without actively preventing and / or removing an oxide layer between first metal layer 504 and second metal layer 508, such processing requires substantially more fabrication time and / or temperature to create protective alloy 506. While the discussion herein may refer to the idealized term "oxide-free," it will be understood to include the meaning of being substantially free of oxygen, such as being very difficult to detect using known equipment.

[0064] conclusion The description of various embodiments of the present teachings has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was selected to best explain the principles of the embodiments, practical applications, or technical improvements to technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0065] While the foregoing describes what is believed to be the best mode and / or other example, it is understood that various modifications may be made, that the subject matter disclosed herein may be implemented in a variety of forms and examples, and that the teachings may be applied to numerous applications, only a few of which have been described herein. It is the intent of the appended claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0066] The components, steps, features, objects, benefits, and advantages discussed in this specification are merely exemplary. None of the above, or any discussion related thereto, shall limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, estimates, positions, dimensions, sizes, and other details set forth in this specification, including the appended claims, are approximate rather than precise. The above are intended to have a reasonable range consistent with the functions to which they relate and what is customary in the technical field to which they pertain.

[0067] Numerous other embodiments are also contemplated, including embodiments having fewer, additional, or different, or combinations of, components, steps, features, objects, advantages, and characteristics, as well as embodiments in which the components and / or steps are arranged and / or ordered differently.

[0068] While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" is meant merely as an example, rather than as best or optimal. Except as noted immediately above, nothing that has been described or illustrated is intended to, or should be construed as, creating a derogation of any disclosed component, step, feature, object, benefit, advantage, or equivalent, whether or not the above is recited in the claims.

[0069] The terms and phrases used herein will be understood to have their ordinary meanings consistent with such terms and phrases in relation to their corresponding fields of inquiry and study, unless a specific meaning is otherwise stated herein. Related terms, such as first and second, etc., may be used merely to distinguish one entity or act from another, without necessarily requiring or implying any actual relationship or order between such entities or acts. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements may not only include those elements, but may also include other elements not expressly listed or other elements inherent to such process, method, article, or apparatus. An element preceded by "a" or "an" does not, without further constraints, preclude the presence of additional identical elements in a process, method, article, or apparatus that includes the element.

[0070] The Abstract of the present disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, it will be appreciated that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the appended claims reflect, inventive subject matter lies in some features of a single disclosed embodiment. As such, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. 1. A method of manufacturing a superconductor device, comprising: Preparing the substrate; providing a first metal layer over the substrate; eliminating oxidation of a top surface of the first metal layer; depositing a second metal layer over the first metal layer; forming a superconducting alloy between the first metal layer and the second metal layer, wherein there is no oxide layer between the superconducting alloy and the first metal layer; the first metal layer is niobium (Nb); the second metal layer is aluminum (Al), The superconducting alloy is Al ３ Nb, method.

2. 2. The method of claim 1, wherein eliminating the oxidation of the top surface of the first metal layer comprises placing the second metal layer on the first metal layer after deposition of the first metal layer and before exposing the top surface of the first metal layer to air.

3. 3. The method of claim 2, wherein eliminating the oxidation of the top surface of the first metal layer further comprises maintaining the superconductor device in a vacuum between deposition of the first metal layer and deposition of the second metal layer.

4. 4. The method of claim 1, wherein eliminating the oxidation of the top surface of the first metal layer comprises depositing the second metal layer over the first metal layer after cleaning the top surface of the first metal layer to remove all oxide from the top surface of the first metal layer.

5. 5. The method of claim 1, further comprising etching away the second metal layer after forming the superconducting alloy.

6. 6. The method of claim 1, wherein creating the superconducting alloy comprises annealing the first metal layer and the second metal layer at a predetermined temperature.

7. 7. The method of claim 1, wherein the superconducting alloy creates an electrical path from the first metal layer to the second metal layer.

8. 8. The method of claim 1, wherein the lattice orientation of the superconducting alloy is (002), (112), or (101), depending on the temperature of annealing the first and second metal layers.

9. The method of claim 1 , further comprising depositing an electrode on the second metal layer.

10. The method of claim 9 , wherein the electrode is a Josephson junction electrode.

11. removing the second metal layer; depositing an electrode on said superconducting alloy; 11. The method of claim 1, further comprising:

12. 1. A method of manufacturing a superconductor device, comprising: Preparing the substrate; providing a first metal layer over the substrate; providing an initial oxide layer on a top surface of the first metal layer; depositing a second metal layer over the initial oxide layer; forming a superconducting alloy between the first metal layer and the second metal layer; transferring the initial oxide layer to a top surface of the superconducting alloy during the preparation of the superconducting alloy; Including, the first metal layer is niobium (Nb); the second metal layer is aluminum (Al), The superconducting alloy is Al ３ Nb, method.

13. removing the initial oxide and the second metal layer on the top surface of the superconducting alloy; depositing an electrode on said superconducting alloy; The method of claim 12 further comprising:

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