Image forming device and image processing method

Abstract

To enhance efficiency when a plurality of items of processing can be executed in parallel.SOLUTION: An image forming device 2 performs one core verification processing when one core 25 is used in performing subsequent stage development processing of data processing for printing data 81, and two core verification processing when performing parallel processing using two cores 25, determines the parallel number of the core 25 on the basis of the acquired verification result, and performs development processing for a remaining band. Thereby, the image forming device 2 can determine an appropriate parallel number according to the contents of the printing data 81, and can shorten a time to complete the development processing for the remaining band by performing the development processing using the core 25 of this parallel number. As a result, the image forming device 2 can reduce the time required for the printing processing based on the supplied printing data, namely, the waiting time of a user.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an image forming apparatus and an image processing method, and is suitable for application to, for example, an electrophotographic image forming apparatus (so-called printer). [Background technology]

[0002] Conventionally, a widely used image forming device receives print data from a higher-level device such as a computer, expands the print data in a control unit to generate raster data, generates a toner image based on the raster data in an image forming unit, and transfers and fixes this onto paper to perform the printing process.

[0003] Of these, the control unit has a configuration similar to that of a general information processing device, and includes, for example, a CPU (Central Processing Unit) that performs arithmetic processing, memory (also called main memory) that stores information, etc. Also, some image forming devices have been proposed that are equipped with multiple cores in the CPU of the control unit and execute multiple processes in parallel, thereby improving arithmetic processing capabilities and shortening processing time (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-233759 A (Fig. 1, etc.) Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, the control unit of an image forming apparatus may have a cache memory between the CPU and the memory (main memory) for the purpose of speeding up various processes, etc. This cache memory allows for faster access than the main memory, but often has a relatively small storage capacity due to cost and other issues.

[0006] In image forming devices, especially when the CPU has multiple cores, the cache memory capacity allocated to each core becomes even smaller, increasing the likelihood of a cache miss occurring. When this happens, the CPU must perform a process called cache out, which moves part of the cache memory to the main memory, and this process takes some time.

[0007] This creates a problem in that when an image forming device performs parallel processing using multiple cores, cache misses may occur more frequently than when processing is performed using a single core, which could actually increase the time required to complete the printing process.

[0008] The present invention has been made in consideration of the above points, and aims to propose an image forming apparatus and an image processing method that can improve efficiency when a plurality of processes can be executed in parallel. [Means for solving the problem]

[0009] In order to solve this problem, the image forming apparatus of the present invention is provided with a main memory that stores print data, a cache memory that stores part of the data stored in the main memory, a plurality of processing units that are capable of parallel processing and execute a generation process that generates image formation data based on a plurality of split data generated based on the print data, a parallel number determination unit that determines the parallel number of processing units when executing the generation process based on the print data or the split data, and a printing unit that prints the image formation data on a medium.

[0010] Furthermore, the image processing method of the present invention includes a verification step in which a generation process is performed to generate data suitable for printing processing based on a plurality of split data generated based on the print data while utilizing a cache memory that stores a portion of the print data stored in the main memory, and the verification step is performed for each of a plurality of different parallel numbers when a plurality of processing units are executed in parallel, and a parallel number determination step in which the parallel number of processing units is determined when executing the generation process for the remaining split data based on the results of the plurality of verification processes.

[0011] The present invention determines the number of parallel processes for processing units while using part of the print data as a verification process. As a result, the present invention can determine an appropriate number of parallel processes according to the characteristics of the print data, and can efficiently execute the generation process. [Effects of the Invention]

[0012] According to the present invention, it is possible to realize an image forming apparatus and an image processing method that can improve efficiency when a plurality of processes can be executed in parallel. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram showing the overall configuration of an image forming system; [Figure 2] FIG. 2 is a block diagram showing the functional configuration of a control unit. [Figure 3] FIG. 2 is a schematic diagram illustrating an overview of data processing by the image forming apparatus. [Figure 4] 10 is a flowchart showing a procedure of a deployment process. [Figure 5] 10 is a flowchart showing a procedure of one core verification process. [Figure 6] 10 is a schematic diagram illustrating some of the monitoring items and their values ​​in the deployment process. [Figure 7] 10 is a flowchart showing a two-core verification process procedure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

[0015] [1. Configuration of image forming device] As shown in Fig. 1, image forming system 1 according to this embodiment is configured such that image forming apparatus 2 and computer apparatus 3 are connected via network 4. Image forming apparatus 2, which serves as an information processing apparatus, is an electrophotographic color printer that can form monochrome or color images on paper, i.e., print. Incidentally, image forming apparatus 2 does not have an image scanner function for reading documents or a communication function using a telephone line, but is a single-function SFP (Single Function Printer) that has only a printing function.

[0016] The image forming apparatus 2 is configured around a control unit 11 that controls the entire image forming apparatus, and is connected to a non-volatile storage medium 12, a communication unit 13, a display operation unit 14, a printing unit 15, etc. The control unit 11 includes a CPU (Central Processing Unit) 21 that performs various arithmetic processing, a main memory 22 that temporarily stores various information, and a cache memory 23.

[0017] The CPU 21, which serves as a processing unit, is provided with three cores 25 (a first core 25A, a second core 25B, and a third core 25C) that perform arithmetic processing. Therefore, the CPU 21 can execute three arithmetic processes in parallel using the three cores 25. Hereinafter, the cores 25 are also referred to as processing units.

[0018] The main memory 22 is a volatile storage element, and is configured, for example, by a DRAM (Dynamic Random Access Memory). That is, compared to the cache memory 23 described later, the main memory 22 can achieve a relatively large capacity at low cost, but has a relatively slow access speed.

[0019] The cache memory 23 is a non-volatile storage element located between the CPU 21 and the main memory 22, and is configured, for example, by an SRAM (Static Random Access Memory). That is, compared to the above-mentioned main memory 22, the cache memory 23 has a relatively high access speed, but its capacity is kept relatively small due to its high cost.

[0020] The control unit 11 performs various processes by using the CPU 21 to execute various programs read from the nonvolatile storage medium 12 or the like while using the main memory 22 as a work area. Furthermore, in the control unit 11, when various arithmetic processes are performed by each core 25 of the CPU 21, a portion of the data stored in the main memory 22 is stored in advance in the cache memory 23. Then, the control unit 11 has the CPU 21 access the cache memory 23 instead of the main memory 22, thereby shortening the processing time.

[0021] For example, in the control unit 11, when an area of ​​information to be read by the CPU 21 is stored in the cache memory 23, the control unit 11 can read the information from the cache memory 23, thereby shortening the processing time compared to when the information is read from the main memory 22. Also, in the control unit 11, when an area to which information from the CPU 21 is to be written is stored in the cache memory 23, the control unit 11 can write the information to the cache memory 23, thereby shortening the processing time compared to when the information is written to the main memory 22.

[0022] On the other hand, if the area of ​​information to be accessed by the CPU 21 is not stored in the cache memory 23, the control unit 11 cannot immediately access the cache memory 23. In this case, the control unit 11 either causes the CPU 21 to directly access the main memory 22, or causes a process of writing back a portion of the area from the cache memory 23 to the main memory 22 (so-called cache out) and stores the other area in the cache memory 23, and then causes the CPU 21 to access the cache memory 23.

[0023] It is generally known that after a specific address in the main memory 22 is accessed, there is a high possibility that an address close to that address will be accessed. For this reason, when the CPU 21 accesses a specific address in the main memory 22, the control unit 11 stores information about an area close to that address in the cache memory 23.

[0024] The nonvolatile storage medium 12 is a nonvolatile storage medium such as an SSD (Solid State Drive) or an HDD (Hard Disk Drive), and stores various programs, various information, etc. In addition, compared to the main memory 22 and the cache memory 23, the nonvolatile storage medium 12 has a sufficiently large storage capacity, but an extremely slow access speed.

[0025] The communication unit 13 has a wired LAN interface conforming to standards such as IEEE (Institute of Electrical and Electronics Engineers) 802.3 (IEEE802.3u / ab / an / ae), etc. The communication unit 13 is connected to the network 4, and transmits and receives various information to and from the computer device 3 via the network 4.

[0026] The display operation unit 14 is configured as a touch panel that combines a display device such as a liquid crystal panel with an input device such as a touch sensor. The display operation unit 14 displays various information under the control of the control unit 11, and also receives operation inputs from the user and notifies the control unit 11 of the inputs.

[0027] Printing unit 15 includes, for example, a transport mechanism that transports paper along a predetermined transport path, an image forming unit that performs exposure processing using light from an LED (Light Emitting Diode) or the like to form a toner image using toner of each color, and a fixing unit that fixes the toner image to paper (none of which are shown). Based on the control of control unit 11, printing unit 15 performs a printing process to form (i.e., print) an image based on image data on paper.

[0028] 2, the control unit 11 forms a plurality of functional blocks such as an editing unit 31, one or two developing units 32, and a core processing determination unit 33. Furthermore, the control unit 11 forms functional blocks such as an operation efficiency calculation unit 35 and a parallel number determination unit 36 ​​within the core processing determination unit 33. The detailed functions and operations of each functional block will be described later.

[0029] The computer device 3 (FIG. 1) is, for example, a desktop, notebook, or tablet computer device, and is connected to a network 4. In addition to a predetermined operating system, the computer device 3 is provided with various applications such as document creation and spreadsheets, as well as a printer driver for executing printing processing by the image forming device 2, and can execute these appropriately based on user operation instructions.

[0030] Network 4 is configured by appropriately combining wired LAN, wireless LAN, etc., using various network devices such as routers and hubs (not shown), base stations, and LAN (Local Area Network) cables, and transmits various information between each connected device.

[0031] With this configuration, in the image forming system 1, print data is generated in the computer device 3 based on user operation, and when this print data is sent to the image forming device 2 via the network 4, an image based on the print data can be printed in the image forming device 2.

[0032] [2. Overview of data processing by image forming devices] Next, we will explain data processing in the image forming device 2. When print data is supplied from the computer device 3 to the image forming device 2, the image forming device 2 performs data processing based on the print data for each page, and the printing unit 15 performs printing processing.

[0033] 3, the image forming device 2 sequentially performs a first-stage editing process and a second-stage expansion process as data processing for one page. In the first-stage editing process, the editing unit 31 generates intermediate data 82 from print data 81. In the second-stage expansion process, the expansion unit 32 generates raster data 83 from the intermediate data 82.

[0034] Fig. 3(A) shows the flow of data between each processing block. Fig. 3(B) shows the content and division of each data block. Fig. 3(C) shows the expansion of each band of data by the preliminary expansion process, one-core expansion process, and two-core expansion process, which will be described later.

[0035] The print data 81 supplied from the computer device 3 generally includes a plurality of drawing objects. These drawing objects represent, for example, characters, figures, or images, and are composed of commands written in a predetermined printing language.

[0036] As an editing process, the editing unit 31 generates intermediate data 82 based on the drawing objects by analyzing commands and the like included in the supplied print data 81. At this time, the editing unit 31 divides the print data 81 into bands of a predetermined width in the sub-scanning direction (the transport direction of the paper on which printing is performed), and generates intermediate data 82 for each band. In the following, the print data 81 and intermediate data 82 corresponding to one band will also be referred to as divided data.

[0037] As a rendering process, the rendering unit 32 renders the intermediate data of each band to generate raster data 83 in bitmap format. When this raster data 83 is printed by the printing unit 15, it becomes an image corresponding to one band width on paper. Hereinafter, the raster data 83 will also be referred to as image formation data. Hereinafter, the compilation of the editing process and rendering process, which are processes performed to generate the raster data 83, or just the rendering process, will also be referred to as the generation process.

[0038] [3. Operational efficiency in deployment processing] When performing the above-described rendering process, the control unit 11 of the image forming apparatus 2 can set the number of cores 25 of the CPU 21 to be assigned to the rendering process to either 1 or 2. That is, the control unit 11 can either assign rendering process (thread) of one band to one core 25 and operate it (hereinafter referred to as 1-core rendering process), or assign rendering process (thread) of different bands to multiple cores 25 and operate them in parallel (hereinafter referred to as 2-core rendering process).

[0039] In this expansion process, when the CPU 21 uses the cache memory 23, there is a possibility that cache out may occur, as with other processes. In particular, when two-core expansion process is performed, if cache data in the same area is accessed from both cores 25 (i.e., expansion process), and if the two cores 25 are performing different processes and the cache memory 23 does not contain the data they need, cache out and cache write may occur alternately. This may result in a phenomenon in which the processing time per band in two-core expansion process is longer than in one-core expansion process, resulting in a decrease in operating efficiency.

[0040] Therefore, in the image forming device 2, when performing expansion processing in printing processing, verification processing is performed for the case where single-core expansion processing is performed and for the case where dual-core expansion processing is performed, and based on the obtained verification results, the number of cores that will perform expansion processing in parallel for the remaining bands (hereinafter referred to as the parallel number) is determined, and the expansion processing is performed.

[0041] [4. Expansion processing] Next, the latter stage of the data processing performed when the image forming device 2 performs print processing will be described in detail, focusing on the verification process and the determination of the number of parallel processes for the one-core and two-core development processes.

[0042] When the control unit 11 of the image forming device 2 receives print data 81 (Figure 3) from the computer device 3 (Figure 1) via the network 4, it first reads and executes a predetermined data processing program from the non-volatile storage medium 12 (Figure 1), thereby forming functional blocks such as the editing unit 31 (Figure 2).

[0043] Then, the control unit 11 performs editing processing based on the print data 81 using the editing unit 31, dividing the print data into multiple bands, generating intermediate data 82 for each band, and stores the intermediate data 82 in the main memory 22. Next, the control unit 11 reads out a decompression processing program from the non-volatile storage medium 12 and executes it using the first core 25A of the CPU 21, thereby starting the decompression processing procedure RT1 shown in Fig. 4 and proceeding to the first step SP1.

[0044] In step SP1, the control unit 11 generates two threads corresponding to the development unit 32, and proceeds to the next step SP2. At this time, the control unit 11 assigns one thread to the second core 25B and the other thread to the third core 25C.

[0045] In step SP2, the control unit 11 determines whether the rendering process has already been completed for one page of print data 81. If the result is negative, this means that there are bands of intermediate data 82 that have not yet been rendered, and therefore rendering must continue. In this case, the control unit 11 proceeds to the next step, SP3.

[0046] In step SP3, the control unit 11 causes the expansion unit 32 to perform a preliminary expansion process on one unexpanded band, thereby generating raster data 83 for that band, and then proceeds to the next step SP4. At this time, the control unit 11 starts the process from a state in which information about areas that are likely to be accessed during the expansion process has not yet been stored in the cache memory 23, so the expansion process may take a relatively long time. However, by performing this preliminary expansion process, the control unit 11 can store in the cache memory 23 information about areas that are likely to be accessed in the main memory 22 during subsequent expansion processes.

[0047] In step SP4, the control unit 11 performs one-core verification processing to acquire various pieces of information by executing a decompression process for one band using one thread (i.e., the decompression unit 32) using one core 25. Specifically, the control unit 11 starts a one-core verification processing procedure RT2 shown in Fig. 5 as a subroutine, and proceeds to the first step SP21.

[0048] In step SP21, similar to step SP2 of the rendering process procedure RT1 (FIG. 4), the control unit 11 determines whether rendering has been completed for one page of print data 81. If a negative result is obtained here, the control unit 11 proceeds to the next step SP22.

[0049] In step SP22, the control unit 11 starts a monitoring process for the cache memory 23, and proceeds to the next step SP23. At this time, as part of the monitoring process, the control unit 11 monitors items related to reading and writing from and to the cache memory 23, such as the number of data requests to the cache memory 23, the number of times necessary data was stored in the cache memory 23 (the so-called number of cache hits), and the number of cache outs, as shown in table T1 in Fig. 6. The control unit 11 also monitors, for example, the time required after the start of the expansion process.

[0050] In step SP23, the control unit 11 instructs one thread (i.e., the decompression unit 32) by one core 25 to perform decompression processing for one unprocessed band, and proceeds to the next step SP24. At this time, the CPU 21 performs the decompression processing only using, for example, the second core 25B (FIG. 1), and keeps the third core 25C waiting without performing any processing.

[0051] In step SP24, the control unit 11 ends monitoring of the cache memory 23 in response to the completion of the expansion process, and proceeds to the next step SP25. At this time, the control unit 11 tallies the values ​​obtained for each of the items that were being monitored, such as the number of cash-outs and the time required for the expansion process.

[0052] In step SP25, the control unit 11 determines whether valid data is included in the intermediate data 82 of the extracted band. Specifically, the control unit 11 tallies the amount of data of object information representing characters, figures, images, etc. in the intermediate data 82 and compares it with a predetermined reference data amount, compares the time required for processing with a predetermined reference time, and further compares the number of data requests to the cache memory 23 with a predetermined reference number of requests.

[0053] Then, the control unit 11 determines that valid data is included if the following three requirements are met: the data volume is equal to or greater than the reference data volume, the required time is equal to or greater than the reference time, and the number of data requests is equal to or greater than the reference request number. The control unit 11 also determines that valid data is not included if the data volume is less than the reference data volume, or the required time is less than the reference time, or the number of data requests is less than the reference request number, that is, if at least one of the requirements is not met.

[0054] If a negative result is obtained in step SP25, this indicates that the intermediate data 82 for that band does not contain enough valid data, and therefore an appropriate verification result could not be obtained for the expansion process by one core 25. In this case, the control unit 11 discards the verification result for that band and returns to step SP21, repeating the series of processes for the next band and obtaining a new verification result.

[0055] On the other hand, if a positive result is obtained in step SP25, this means that the intermediate data 82 of the band contains a sufficient amount of valid data, and therefore an appropriate verification result has been obtained for the decompression process by one core 25. In this case, the control unit 11 proceeds to the next step SP26.

[0056] In step SP26, the control unit 11 causes the operation efficiency calculation unit 35 (FIG. 2) of the core processing determination unit 33 to calculate multiple values ​​representing the operation efficiency in the one-core deployment process, stores the obtained operation efficiencies in the main memory 22, and proceeds to the next step SP27. At this time, the operation efficiency calculation unit 35 stores, as the operation efficiency, various values ​​obtained and calculated in the one-core verification process, such as the number of cash-outs and the time required for the deployment process.

[0057] On the other hand, if a positive result is obtained in step SP21, this means that the extraction process and the verification process cannot be performed because there are no bands left for which extraction process from the intermediate data 82 has not been completed. In this case, the control unit 11 proceeds to the next step SP27.

[0058] In step SP27, the control unit 11 ends the one-core verification processing procedure RT2, returns to step SP4 of the original decompression processing procedure RT1 (FIG. 4), and proceeds to the next step SP5.

[0059] In step SP5, the control unit 11 performs two-core verification processing, which acquires various information by executing a decompression process for each of the two bands using two threads (i.e., the decompression unit 32) using the two cores 25. Specifically, the control unit 11 starts a two-core verification processing procedure RT3 shown in Fig. 7 as a subroutine, and proceeds to the first step SP31. Overall, this two-core verification processing procedure RT3 is similar to the single-core verification processing procedure RT2 (Fig. 5) except that the number of cores 25 performing the decompression process is changed from one to two.

[0060] Specifically, the control unit 11 performs the same processes as steps SP21 and SP22 in steps SP31 and SP32, and then proceeds to the next step SP33. In step SP33, the control unit 11 instructs the two threads (i.e., the decompression units 32) of the two cores 25 to perform decompression processing in parallel for each of the two unprocessed bands, and then proceeds to the next step SP34. At this time, the CPU 21 causes, for example, the second core 25B and the third core 25C (FIG. 1) to perform decompression processing for different bands.

[0061] Thereafter, the control unit 11 performs the same processes as steps SP24 and SP25 in steps SP34 and SP35, and then proceeds to the next step SP36. In step SP36, the control unit 11 causes the operation efficiency calculation unit 35 (FIG. 2) of the core processing determination unit 33 to calculate multiple values ​​representing the operation efficiency in the two-core deployment process, stores the obtained operation efficiencies in the main memory 22, and proceeds to the next step SP37. At this time, the operation efficiency calculation unit 35 stores, as operation efficiencies, various values ​​obtained and calculated in the two-core verification process, such as the number of cash-outs and the time required for the deployment process.

[0062] In step SP37, the control unit 11 ends the two-core verification processing procedure RT3, returns to step SP5 of the original decompression processing procedure RT1 (FIG. 4), and proceeds to the next step SP6.

[0063] In step SP6, the control unit 11 determines the number of parallel processes to be used when performing the expansion process for the remaining bands using the parallel process number determination unit 36 ​​(FIG. 2), and then proceeds to the next step SP7. Specifically, if the number of cache-outs in the two-core verification process is less than twice the number of cache-outs in the one-core verification process, the parallel process number determination unit 36 ​​determines the number of parallel processes to be "2," and if the number is more than twice the number of cache-outs, the parallel process number determination unit 36 ​​determines the number of parallel processes to be "1." In other words, the parallel process number is determined so that the number of cache-outs per core is reduced.

[0064] In step SP7, the control unit 11 determines whether the rendering process has already been completed for one page of print data 81, just as in step SP2. If a negative result is obtained here, this indicates that there are bands of intermediate data 82 that have not yet been rendered, and therefore rendering processing must continue. In this case, the control unit 11 proceeds to the next step, SP8.

[0065] In step SP8, the control unit 11 executes the expansion process for the intermediate data 82 of each band for which the expansion process has not yet been performed using the determined number of parallel cores 25 (i.e., threads), thereby sequentially generating raster data 83 for each of the parallel bands, and when this is completed, proceeds to the next step SP9.

[0066] On the other hand, if the results of steps SP2 and SP7 are positive, this means that the rendering process has already been completed for all bands that make up one page, and the control unit 11 then proceeds to the next step SP9.

[0067] In step SP9, the control unit 11 performs processing to terminate each thread generated in step SP1. Thereafter, the control unit 11 proceeds to the next step SP10, where it ends the expansion processing procedure RT1.

[0068] Incidentally, the control unit 11 is configured to repeatedly execute the rendering processing procedure RT1 for each page of print data 81. Therefore, if there are pages included in the print data 81 for which rendering processing has not been completed, the control unit 11 executes the rendering processing procedure RT1 (FIG. 4) for each page, determines the number of parallel processes, performs rendering processing, and generates raster data 83.

[0069] [5. Effects, etc.] In the above configuration, when print data 81 is supplied from the computer device 3 to the image forming device 2 according to this embodiment, as data processing, the image forming device 2 divides one page of print data 81 into multiple bands, performs editing processing on each of them to form intermediate data 82, and further performs expansion processing on each band to generate raster data 83 (FIG. 3).

[0070] Generally, in a configuration such as the control unit 11 (FIG. 1) of the image forming device 2, in which the CPU 21 has multiple cores 25 and accesses the main memory 22 via the cache memory 23, the capacity of the cache memory 23 that can be used by each core 25 varies depending on the number of cores 25 operating in parallel. Also, in the rendering process, the content and amount of calculations of the arithmetic process vary depending on the type and number of objects included in the print data 81. For this reason, in the image forming device 2, when rendering processes are performed in parallel using two cores 25, the number of cache outs increases, and it may actually take longer than when rendering processes are performed using only one core 25.

[0071] Therefore, when performing decompression processing, the image forming device 2 according to this embodiment first performs a one-core verification process in which one core 25 is used to perform decompression processing on one band, and a two-core verification process in which two bands are performed in parallel using two cores 25. The image forming device 2 then determines the number of parallel cores 25 based on the obtained verification results, and performs decompression processing on the remaining bands using the determined number of parallel cores 25 (FIGS. 4 to 7).

[0072] This allows the image forming device 2 to determine an appropriate parallel number according to the content of the print data 81, and by executing the decompression process using the cores 25 with this parallel number, it is possible to further shorten the time until the decompression process for the remaining bands is completed. As a result, the image forming device 2 can complete the print process based on the supplied print data in a short time, thereby reducing the user's waiting time.

[0073] In particular, the image forming device 2 performs the verification process (one-core verification process and two-core verification process) using a partial band of the print data 81 itself supplied from the computer device 3. This allows the image forming device 2 to determine an appropriate parallel number according to the content of the print data 81.

[0074] From another perspective, in each verification process, the image forming device 2 performs the expansion process using intermediate data 82 of the band that constitutes part of the print data 81, rather than using data prepared separately for verification. Therefore, the image forming device 2 can use the raster data 83 generated as a result of the expansion process in the verification process as is in the print process, and the time required for the expansion process in each verification process is not wasted.

[0075] Furthermore, in step SP3 of the extraction processing procedure RT1 (FIG. 4), the control unit 11 performs extraction processing for one band before the one-core verification processing that is executed first. This allows the image forming device 2 to align the data in the area that is highly relevant to the immediately preceding extraction processing stored in the cache memory 23 at the start of each of the one-core verification processing and the two-core verification processing, thereby improving the accuracy of the verification processing.

[0076] Furthermore, in step SP25 of the one-core verification processing procedure RT2 (FIG. 5), if the intermediate data 82 of the band that has been decompressed does not contain valid data, the control unit 11 discards the verification result of that band and obtains a new verification result for the next band. This allows the image forming device 2 to obtain a new verification result for another band and compare it with the other verification result, for example, if the band located at the beginning of a page is mostly blank and is not appropriate as a verification result. The same applies to the two-core verification processing procedure RT3 (FIG. 7).

[0077] With the above configuration, when performing the latter-stage decompression process of the data processing for the print data 81, the image forming device 2 performs one-core verification processing using one core 25, and two-core verification processing using two cores 25 in parallel processing, and determines the parallel number of the cores 25 based on the obtained verification results, and performs the decompression process for the remaining bands. This allows the image forming device 2 to determine an appropriate parallel number according to the content of the print data 81, and by performing the decompression process using this parallel number of cores 25, the time until the decompression process for the remaining bands is shortened. As a result, the image forming device 2 can shorten the time required for the print process based on the supplied print data, i.e., the user's waiting time.

[0078] 6. Other Embodiments In the above-described embodiment, the parallel number is determined based on the number of cache-outs in each of the one-core verification process and the two-core verification process in step SP8 of the unpacking procedure RT1 (FIG. 4). However, the present invention is not limited to this. The parallel number may be determined based on various information (i.e., the verification results) obtained in each verification process. Specifically, for example, the number of cache-outs per unit time in each verification process may be used. If the value in the two-core verification process is less than twice the value in the one-core verification process, the parallel number may be set to 2; if the value is more than twice the value in the one-core verification process, the parallel number may be set to 1. Alternatively, even if the number of cache-outs in the two-core verification process is more than twice the number in the one-core verification process, the parallel number may be set to 2 if the two-core verification process takes less time to unpack. This is based on the idea that the length of time required for the actual unpacking process is more important than the efficiency of use of the cache memory 23.

[0079] In the above-described embodiment, in step SP3 of the extraction processing procedure RT1 (FIG. 4), the extraction processing for one band is performed before the first one-core verification processing. However, the present invention is not limited to this. For example, the processing of step SP3 may be omitted, and the one-core verification processing may be started from a state in which data in an area highly relevant to the extraction processing is not stored in the cache memory 23. In this case, by caching out the cache memory 23 before ending the one-core verification processing and starting the two-core verification processing, the start conditions for the one-core verification processing and the two-core verification processing can be aligned.

[0080] Furthermore, in the above-described embodiment, in step SP25 of the one-core verification processing procedure RT2 (FIG. 5), whether valid data is included is determined based on three requirements: the amount of object information in the intermediate data 82, the time required for the expansion process, and the number of data requests to the cache memory 23. However, the present invention is not limited to this. For example, one or two of these three requirements may be used, or four or more requirements may be used, including requirements related to various other values ​​obtained in the expansion process. Furthermore, regarding the determination, valid data may be determined to be included when, for example, two or more requirements are satisfied, other than when all three requirements are satisfied: the amount of data is equal to or greater than the reference data amount, the required time is equal to or greater than the reference time, and the number of data requests is equal to or greater than the reference number of requests.

[0081] Furthermore, in the above-described embodiment, if the intermediate data 82 of the extracted band does not contain valid data in step SP25 of the one-core verification processing procedure RT2 (FIG. 5), the verification result is discarded and the extraction process is performed again for the next band. However, the present invention is not limited to this, and for example, the obtained verification result may be used as is, regardless of whether the intermediate data 82 of the extracted band contains valid data.

[0082] Furthermore, in the above-described embodiment, the expansion processing procedure RT1 (FIG. 4) is performed for each page of the print data 81, i.e., each verification process is performed for each page and the parallel number is determined for each page. However, the present invention is not limited to this. For example, if one print data 81 consists of multiple pages, verification process may not be performed for the second and subsequent pages, and the parallel number determined for the first page may be applied to the second and subsequent pages. Alternatively, for example, the number and type of drawing objects constituting each page may be compared, and verification process may be performed only if the number and type of drawing objects differ significantly from those of the previous page. Otherwise, the same parallel number as the previous page may be used. In these cases, for example, a printer driver that generates and transmits print data in the computer device 3 may analyze information regarding the number and type of drawing objects contained in each page in advance and provide the information to the image forming device 2 along with the print data 81.

[0083] Furthermore, in the above-described embodiment, the print data 81 is divided into predetermined widths in the sub-scanning direction to generate each band (i.e., divided data) (FIG. 3). However, the present invention is not limited to this, and the divided data may be generated by dividing the print data 81 using various methods, such as dividing the print data 81 into portions containing only text or portions containing only graphics, for example, by object type.

[0084] Furthermore, in the above-described embodiment, the description has been given of a form in which the expansion process, which is one of the data processes performed by the image forming apparatus 2, is executed according to the number of parallel processes determined based on the results of each verification process. However, the present invention is not limited to this, and for example, the number of parallel processes may also be determined for the edit process by performing each verification process, and then the edit process may be executed according to the determined number of parallel processes.

[0085] Furthermore, in the above-described embodiment, the CPU 21 of the control unit 11 is provided with three cores 25 ( FIG. 1 ), and a maximum of two cores 25 are used in the decompression process, i.e., the maximum number of parallel processes is two. However, the present invention is not limited to this. The CPU 21 may be provided with any number of cores 25, four or more, and any number of cores 25, three or more, may be used in the decompression process. Specifically, for example, the CPU 21 may be provided with five cores 25, and a maximum of four cores 25 may be used in the decompression process. In this case, in addition to the one-core verification process and the two-core verification process, a three-core verification process using three cores 25 and a four-core verification process using four cores 25 may be performed in the decompression process, and the number of parallel processes may be determined based on the obtained verification results.

[0086] Furthermore, in the above-described embodiment, when the CPU 21 (FIG. 1) of the control unit 11 performs the unpacking process, one thread is executed in one core 25. However, the present invention is not limited to this, and for example, two or more threads may be executed in one core 25. In this case, the unpacking process of each verification process can utilize the verification results when each core 25 executes multiple threads.

[0087] Furthermore, in the above-described embodiment, the control unit 11 stores a portion of the area in the main memory 22 in the cache memory 23, and the CPU 21 accesses the cache memory 23. However, the present invention is not limited to this, and for example, in addition to the main memory 22, a portion of the area in the non-volatile storage medium 12 may also be stored in the cache memory 23.

[0088] Furthermore, in the above-described embodiment, various programs and the like are stored in advance in the nonvolatile storage medium 12 of the image forming apparatus 2. However, the present invention is not limited to this, and various programs and the like may be downloaded and executed from a predetermined server device or the like (not shown) connected via the communication unit 13, for example.

[0089] Furthermore, in the above-described embodiment, the image forming apparatus 2 is configured as a single-function printer. However, the present invention is not limited to this, and the image forming apparatus 2 may be configured as, for example, an MFP (Multi Function Peripheral) having the functions of a copier or facsimile machine.

[0090] Furthermore, the present invention is not limited to the above-described embodiments and other embodiments, and the scope of application of the present invention extends to embodiments in which the above-described embodiments and other embodiments are combined in part or in whole, or in which only a part of the above-described embodiments is extracted.

[0091] Furthermore, in the above-described embodiment, the image forming apparatus 2 is configured as an image forming apparatus by the main memory 22 as the main memory, the cache memory 23 as the cache memory, the core 25 as the processing unit, the parallel number determination unit 36 ​​as the parallel number determination unit, and the printing unit 15 as the printing unit. However, the present invention is not limited to this, and the image forming apparatus may be configured by a main memory, a cache memory, a processing unit, a parallel number determination unit, and a printing unit having various other configurations. [Industrial Applicability]

[0092] The present invention can be used, for example, when performing expansion processing in a configuration in which the CPU of the control unit has multiple cores and a cache memory. [Explanation of symbols]

[0093] 1...Image forming system, 2...Image forming device, 11...Control unit, 12...Non-volatile storage medium, 15...Printing unit, 21...CPU, 22...Main memory, 23...Cache memory, 25...Core, 31...Editing unit, 32...Expansion unit, 33...Core processing determination unit, 35...Operation efficiency calculation unit, 36...Parallel number determination unit, 81...Print data, 82...Intermediate data, 83...Raster data

Claims

1. a main memory for storing print data; a cache memory that stores a portion of the data stored in the main memory; a plurality of processing units capable of parallel processing, which execute a generation process for generating image formation data based on a plurality of divided data generated based on the print data; a parallel number determination unit that determines the parallel number of the processing units when executing the generation process based on the print data or the divided data; a printing unit that prints the image formation data on a medium; An image forming apparatus comprising:

2. an operation efficiency calculation unit that performs a plurality of verification processes with different parallel numbers of the processing units that execute the generation process based on a portion of the divided data, and calculates operation efficiencies for each of the parallel numbers based on results of the verification processes; Further comprising: The parallel number determination unit determines the parallel number of the processing units when executing the generation process on the divided data for which the generation process has not yet been executed, based on the operation efficiency for each parallel number.

2. The image forming apparatus according to claim 1, wherein the image forming apparatus is a recording medium.

3. The operation efficiency calculation unit calculates the operation efficiency for each of the parallel numbers based on the number of cache-outs performed from the cache memory to the main memory in each of the plurality of verification processes.

3. The image forming apparatus according to claim 2, wherein the image forming apparatus is a recording medium.

4. The operation efficiency calculation unit calculates the operation efficiency for each of the parallel numbers based on the number of cache-outs performed per unit time from the cache memory to the main memory in each of the plurality of verification processes.

3. The image forming apparatus according to claim 2, wherein the image forming apparatus is a recording medium.

5. the operation efficiency calculation unit measures the required time for each of the plurality of verification processes; The parallel number determination unit determines the parallel number of the processing units when executing the generation process for the divided data for which the generation process has not yet been executed, based on the required time for each parallel number.

3. The image forming apparatus according to claim 2, wherein the image forming apparatus is a recording medium.

6. When a value related to information obtained by the generation process does not satisfy a predetermined requirement in the verification process performed based on the divided data, the operation efficiency calculation unit performs the verification process based on other divided data.

3. The image forming apparatus according to claim 2, wherein the image forming apparatus is a recording medium.

7. A processing unit that can execute multiple calculation processes in parallel using multiple cores Further comprising: The processing unit assigns the generation process based on one of the divided data to one of the cores and causes the core to execute the process.

3. The image forming apparatus according to claim 2, wherein the image forming apparatus is a recording medium.

8. the generation process includes an editing process for generating intermediate data including a drawing object based on the print data, and an expansion process for expanding the intermediate data to generate the image formation data, The parallel number determination unit determines the parallel number of the processing units when executing the expansion process based on the print data or the divided data.

2. The image forming apparatus according to claim 1, wherein the image forming apparatus is a recording medium.

9. a verification step of performing a verification process for generating data suitable for printing processing based on a plurality of divided data pieces generated based on the print data while utilizing a cache memory that stores a portion of the print data stored in the main memory, for each of a plurality of ways with different parallel numbers when a plurality of processing units are executed in parallel; a parallel number determination step of determining the parallel number of the processing units when executing the generation process for the remaining divided data based on a plurality of results of the verification process; An image processing method comprising:

Images