Storage device

Abstract

To provide a storage device that has an error detection function, and in which a large amount of data per unit area can be stored.SOLUTION: A driving circuit of a storage device is constituted using transistors formed on a semiconductor substrate, and memory cells for the storage device are constituted using thin-film transistors. A plurality of layers of memory cells, constituted using thin-film transistors, can be stacked above the semiconductor substrate, thereby increasing the amount of data that can be stored per unit area. Additionally, since a part of a peripheral circuit included in the storage device can be constituted using the thin-film transistors, an error detection circuit is constructed using thin-film transistors and stacked above the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a memory device. In particular, a memory device that can function by utilizing semiconductor characteristics. Related to storage devices.

[0002] Another embodiment of the present invention relates to a semiconductor device. It is a device that utilizes the characteristics of semiconductors, such as semiconductor elements (transistors, diodes, etc.). This refers to a circuit including a photodiode, a device having the same circuit, etc. In this context, a semiconductor device refers to any device that can function by utilizing semiconductor properties. For example, an integrated circuit, a chip with an integrated circuit, or an electronic device with a chip in a package. Electronic devices equipped with components and integrated circuits are examples of semiconductor devices.

[0003] It should be noted that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to products, methods, or manufacturing methods. is a process, machine, manufacture, or composition of matter. This concerns the [Background technology]

[0004] DRAM (Dynamic Random Access Memory) is a It is widely known as a storage device (also called memory) used in devices. A memory cell consists of one transistor and one capacitance element, and DRAM uses a capacitor to charge the element. It is a memory that stores data by accumulating charges.

[0005] Even if there is no abnormality in the operation of memory devices such as DRAM, the effects of cosmic rays and other factors can cause data to be lost in memory cells. Therefore, ECC (Error Check Code) is used. Error detection and correction functions are called Error Check and Correct (ECC) memory. ECC memory is used in, for example, scientific and technical calculations and financial institutions. It is used in electronic devices such as computers where data errors are not allowed.

[0006] On the other hand, a region where a channel of a transistor is formed (also called a channel forming region) is formed with gold. Transistors having metal oxides (also called oxide semiconductor transistors or OS transistors) For example, In-G is a metal oxide that can be used in transistors. Alpha-Zn oxide (also known as IGZO or Iguzo) is known.

[0007] An OS transistor has a drain current (off current) when the transistor is in the off state. (See, for example, Non-Patent Documents 1 and 2) When used in DRAM memory cells, it is possible to retain the charge stored in the capacitance element for a long period of time. can.

[0008] In addition, since the OS transistor is a thin film transistor, it can be provided as a stacked layer. For example, Patent Document 1 discloses a method for fabricating a peripheral circuit of a DRAM using transistors formed on a semiconductor substrate. A DRAM memory cell constructed using OS transistors is placed above the circuit. The present invention discloses a structure in which a plurality of layers each having a memory cell of a DRAM are stacked. By stacking multiple layers, the DRAM chip area can be reduced.

[0009] In this specification and the like, a DRAM in which an OS transistor is used in a memory cell is referred to as an oxide Semiconductor DRAM, or DOSRAM (registered trademark, Dynamic Oxide Semiconductor) Dosram, which stands for Microconductor Random Access Memory (pronounced "). [Prior art documents] [Patent documents]

[0010] [Patent Document 1] US Patent Application Publication No. 2012 / 0063208 [Non-patent literature]

[0011] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). Summary of the Invention [Problem to be solved by the invention]

[0012] Generally, ECC memory consists of a storage area for storing data and an error detection code or error A memory area for storing correction codes (also called redundant bits or check bits), and the above two The ECC memory has a memory controller that controls the storage area of ​​the data. When storing (or writing) data, calculate the check bit corresponding to the data to be stored. , check bits are stored along with the data to be stored.

[0013] When the stored data is read, the check bits are read together with the data. The memory verifies the read data using check bits to ensure that the stored data is correct. You can also find out if there is an error in the stored data. If this occurs, the ECC memory can correct it using the check bits.

[0014] That is, at least the ECC memory has a storage area for storing check bits and a storage area for storing the check bits. A memory controller is required to control the memory area in addition to non-ECC memory. be.

[0015] One aspect of the present invention is an error detection function (having a storage area for storing check bits, a memory device with a function to check whether an error has occurred in the data stored using bits Another object of the present invention is to provide a method for detecting an error. One of the objectives is to provide a storage device that can store a large amount of data per unit area. do.

[0016] It should be noted that one embodiment of the present invention does not necessarily have to solve all of the above problems, but at least It is enough if it can solve one problem. Also, the description of the problem above may not be sufficient if other problems exist. Other issues than these are not covered by the description, claims, drawings, etc. This becomes clear from the description, claims, drawings, etc. It is possible to extract issues other than these. [Means for solving the problem]

[0017] One aspect of the present invention is a memory cell array including a first element layer having memory cells and a second element layer having error detection circuitry. The second element layer is a semiconductor substrate having a driving circuit. It is disposed between the plate and the first device layer.

[0018] Also, one aspect of the present invention provides a memory device including: a plurality of first element layers; a second element layer having an error detection circuit; The second element layer is a memory device having a semiconductor substrate and a drive circuit. a plurality of first element layers each having a memory cell; The first element layer is provided by laminating layers.

[0019] In the above embodiment, a transistor constituting a memory cell and an error detection circuit Each of the transistors constituting the semiconductor device has a metal oxide in a channel formation region.

[0020] In the above embodiment, a transistor constituting a memory cell and an error detection circuit Each of the transistors has a front gate and a back gate.

[0021] In the above embodiment, a transistor constituting a memory cell and an error detection circuit Each of the transistors constituting the memory cell has a metal oxide in a channel forming region. The transistors that make up the filter and the transistors that make up the error detection circuit are It has a front gate and a back gate.

[0022] In addition, one aspect of the present invention is a semiconductor device including first to N-th first element layers (N is a natural number of 2 or more) and second element layers. The memory device has a Kth (K is an integer between 1 and N) layer and a semiconductor substrate. In the element layer, a memory cell is configured using a transistor formed in the Kth first element layer. The second element layer includes an error detection circuit using transistors formed in the second element layer. The semiconductor substrate is configured such that a driving circuit is formed using transistors formed on the semiconductor substrate. The second element layer is stacked above the semiconductor substrate, and the first element layer is , an Lth (L is an integer of 2 or more and N or less) first element layer provided above the second element layer; is provided stacked above the (L-1)th first element layer.

[0023] In the above embodiment, the transistor formed in the Kth first element layer and the second element The transistors formed in the sub-layer each have a metal oxide in a channel forming region.

[0024] In the above embodiment, the transistor formed in the Kth first element layer and the second element The transistors formed in the sub-layers each have a front gate and a back gate. .

[0025] In the above embodiment, the transistor formed in the Kth first element layer and the second element The transistors formed in the second layer each have a metal oxide in a channel forming region. A transistor formed in the first element layer of K and a transistor formed in the second element layer Each of the turbines has a front gate and a back gate. [Effects of the Invention]

[0026] According to one embodiment of the present invention, a memory device having an error detection function can be provided. According to one aspect of the present invention, the data that can be stored per unit area has an error detection function. A large amount of storage can be provided.

[0027] The description of these effects does not preclude the existence of other effects. A form does not necessarily have to have all of these effects. Effects other than these may be included in the specification. It is obvious from the description, claims, drawings, etc. Other effects can be extracted from the claims, drawings, etc. [Brief explanation of the drawings]

[0028] [Figure 1] 1A and 1B are block diagrams illustrating an example of the configuration of a storage device. [Figure 2] FIG. 2 is a schematic diagram showing an example of the configuration of a storage device. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of a storage device. [Figure 4] FIG. 4 is a schematic diagram showing an example of the configuration of a storage device. [Figure 5] 5A and 5B are schematic diagrams showing configuration examples of a storage device. [Figure 6] Fig. 6A is a circuit diagram showing an example of the configuration of a check bit generation circuit, Fig. 6B is a timing chart, and Fig. 6C is a truth table. [Figure 7] Fig. 7A is a circuit diagram showing an example of the configuration of an error detection circuit, and Fig. 7B is a timing chart. [Figure 8] Figure 8 is a truth table. [Figure 9] Fig. 9A is a symbol representing an XOR circuit, Fig. 9B is a circuit diagram showing an example of the configuration of an XOR circuit, Fig. 9C is a timing chart, and Fig. 9D is a truth table. [Figure 10] Fig. 10A is a symbol representing a NAND circuit, Fig. 10B is a circuit diagram showing an example of the configuration of a NAND circuit, Fig. 10C is a timing chart, and Fig. 10D is a truth table. [Figure 11] Fig. 11A is a symbol representing a delay circuit, Fig. 11B is a circuit diagram showing an example of the configuration of a delay circuit, Fig. 11C is a timing chart, and Fig. 11D is a truth table. [Figure 12] FIG. 12 is a schematic diagram showing an example of the configuration of a storage device. [Figure 13] FIG. 13 is a cross-sectional view showing a configuration example of a storage device. [Figure 14] 14A and 14B are cross-sectional views showing examples of the structure of a transistor. [Figure 15] 15A to 15C are cross-sectional views showing examples of the configuration of a memory device. [Figure 16] FIG. 16 is a cross-sectional view showing a configuration example of a storage device. [Figure 17] FIG. 17 is a cross-sectional view showing a configuration example of a storage device. [Figure 18] Fig. 18A is a top view showing an example of the configuration of a memory device, and Figs. 18B and 18C are schematic cross-sectional views showing an example of the configuration of a memory device. [Figure 19] Fig. 19A is a diagram explaining the classification of IGZO crystal structures, Fig. 19B is a diagram explaining the XRD spectrum of silica glass, and Fig. 19C is a diagram explaining the XRD spectrum of crystalline IGZO. [Figure 20] 20A and 20B are schematic diagrams illustrating an example of an electronic component. [Figure 21] FIG. 21 is a diagram illustrating an example of an electronic device. [Figure 22] FIG. 22 is a diagram showing various storage devices by hierarchical level. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in any form without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0030] In addition, the following embodiments can be combined as appropriate. When a plurality of configuration examples are shown in one embodiment, the configuration examples may be combined with each other as appropriate. It is possible to do this.

[0031] In the drawings attached to this specification, the components are classified by function and are shown as independent blocks. Although the block diagram is shown as a block, the actual components are not completely separated by function. It is difficult to achieve this, and one component may be involved in multiple functions.

[0032] In addition, in the drawings, etc., the size, thickness of layers, areas, etc. may be exaggerated for clarity. Therefore, the scale is not necessarily limited to the above. The drawings are only a schematic representation of ideal examples. The present invention is not limited to the shapes or values ​​shown in the drawings.

[0033] In addition, in drawings, etc., the same elements or elements having similar functions, elements made of the same material, Alternatively, elements formed at the same time may be given the same reference numerals, and the repeated explanations thereof may be omitted. may be omitted.

[0034] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to

[0035] In addition, in this specification, terms indicating placement such as "above" and "below" refer to the positional relationship of components. The relationship is not limited to being "directly above" or "directly below." For example, In the case of the expression "gate electrode on an insulating layer," it is understood that there is no other component between the gate insulating layer and the gate electrode. Do not exclude anything that includes.

[0036] In addition, in this specification, ordinal numbers such as "first," "second," and "third" indicate the order of constituent elements. This is added to avoid confusion and is not intended to limit the number.

[0037] In addition, in this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to particularly distinguish between them. If necessary, use identifiers such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL is called wiring GL[2]. Write it down.

[0038] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitor elements, and various other functions. Also, even if it is expressed as "electrically connected", it does not necessarily mean that the actual circuit In some cases, there are no physical connections and only wiring is extended.

[0039] In addition, in this specification and the like, the terms "electrode" and "wiring" are used to refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa.

[0040] In this specification, a "terminal" in an electric circuit refers to a terminal that is used to input (or It refers to the part where the signal is received (or transmitted) or output. Alternatively, a part of the electrode may function as a terminal.

[0041] Generally, a "capacitance" has a structure in which two electrodes face each other through an insulator (dielectric). In this specification and the like, the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, a "capacitance element" refers to a capacitor having two electrodes facing each other with an insulator interposed therebetween. a structure in which two wires face each other through an insulator; This includes cases where two wires are arranged with an insulator between them.

[0042] In this specification, the term "voltage" refers to the difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage and potential difference can be interchanged. can.

[0043] In this specification, a transistor includes a gate, a drain, and a source. , an element having at least three terminals. drain region, or drain electrode) and source (source terminal, source region, or source electrode) A channel forming region is formed between the source and drain. In this specification and the like, a channel formation region is a region where a current can flow. The region refers to the region through which the current mainly flows.

[0044] The source and drain functions may differ depending on the type of transistor used, or the circuit operation. This may be reversed if the direction of the current changes during operation. In the text, the terms source and drain may be used interchangeably.

[0045] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is in an off-state. The drain current when the device is in the off state (also called the non-conducting state or cut-off state). Unless otherwise specified, for n-channel transistors, the gate to source voltage V When gs is lower than the threshold voltage Vth, in a p-channel transistor, This refers to the state in which the gate voltage Vgs is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage Vgs of the gate relative to the source that is equal to the threshold voltage. This may be referred to as the drain current when the voltage is lower than Vth.

[0046] In the above description of the off-state current, the drain may be read as the source. The off-state current is the source current when the transistor is in the off state. In this specification and the like, the off-state current is refers to the current that flows between the source and drain when the transistor is in the off state. There is a match.

[0047] In this specification, the on-state current is the current that flows when a transistor is in an on-state (also called a conductive state). It can also refer to the current that flows between the source and drain when the device is in a non-uniform state.

[0048] In this specification, the term "metal oxide" is used in a broad sense. Metal oxides are oxide insulators and oxide conductors (transparent oxide conductors). semiconductors), oxide semiconductors, etc.

[0049] For example, when a metal oxide is used for a channel formation region of a transistor, the metal oxide is In other words, metal oxides have amplifying, rectifying, and When the metal oxide has at least one switching function, the metal oxide is called a metal oxide semiconductor. (metal oxide semiconductor). Specifically, a transistor having a metal oxide in a channel formation region is called an "oxide semiconductor transistor." These can be called "OS transistors" or "OS transistors."

[0050] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are sometimes called metal oxynitrides (met Metal oxides may also be called metal oxynitrides. Details of metal oxides will be explained later. .

[0051] (Embodiment 1) A configuration example of a storage device according to one embodiment of the present invention will be described with reference to FIGS. One type of memory device is a memory device that can function by utilizing the characteristics of semiconductors, and It is also called.

[0052] Further, a memory device according to one embodiment of the present invention includes a layer including a transistor formed over a semiconductor substrate. The upper layer has a structure in which a plurality of layers each having an OS transistor are stacked. A transistor has the property of having a very small off-state current.

[0053] <Block diagram of storage device> FIG. 1A is a block diagram showing an example of the configuration of a storage device 10A according to an embodiment of the present invention. In the drawings described in this specification, the flow of main signals is indicated by arrows or lines. , power lines, etc. may be omitted.

[0054] The memory device 10A includes a peripheral circuit 20 and a memory cell array 30. The peripheral circuit 20 includes In addition to the row driver 21 and the column driver 22, a precharge circuit 24, a sense amplifier 25, a check bit generation circuit 54, an error detection circuit 55, and a switch circuit 23 are provided. It has a device layer 26 (see FIG. 3).

[0055] The row driver 21 outputs a signal to the word line WL to drive the memory cell array 30. Specifically, the row driver 21 has a function of outputting a signal to the word line WL (WL_1 in FIG. 1A). and WL_N (N is a natural number greater than or equal to 2) The row driver 21 may be called a word line driving circuit. a decoder circuit for selecting a word line WL according to a specified address, and a buffer It includes circuits, etc. The word line WL may be simply called a wiring.

[0056] The column driver 22 transmits a signal to the bit line BL to drive the memory cell array 30. Specifically, the column driver 22 has a function of outputting a signal to the bit line BL (BL in FIG. 1A). The column driver 22 has a function of outputting data signals to the BL_1 and BL_2 (shown in the figure). The column driver 22 may be called a bit line driver circuit. The bit line BL is simply a In the drawings, the bit lines BL are shown as thick lines to improve visibility. Alternatively, it may be illustrated by a thick dotted line.

[0057] The data signal applied to the bit line BL is a signal to be written to the memory cell, or The data signal corresponds to the signal read from the register. High level, corresponding to Data Low, Data H or Data L The high-level potential is a binary signal with a high or low level potential. VDD, the low level potential is the potential VSS or ground potential (GND). The data signal may be multi-valued, having three or more values.

[0058] Other signals given to the bit line BL include a precharge signal for reading data. The precharge potential can be, for example, VDD / 2.

[0059] The memory cell array 30 includes, for example, N layers (N is a natural number of 2 or more) of element layers 34_1 to 34_3. The element layer 34_1 has one or more memory cells 31_1. The element layer 31_1 includes a transistor 32_1 and a capacitor 33_1. N has one or more memory cells 31_N. The memory cells 31_N are transistors 3 2_N and capacitor 33_N.

[0060] The capacitor may be called a capacitance or a capacitance element. A layer on which elements such as transistors are provided, and is made of conductors, semiconductors, insulators, etc. It is a layer having the following structure.

[0061] The transistors 32_1 to 32_N are connected to the word lines WL_1 to WL_N. Depending on the input signal, the transistor can be in a conducting state (also called an ON or ON state), a non-conducting state (also called an OFF or The transistor 32 functions as a switch that is controlled to be in an on-state (also called an off-state). 1 to 32_N are each a bit line BL whose source or drain is connected to one of the bit lines BL. are connected together.

[0062] The transistors 32_1 to 32_N are transistors having a metal oxide in a channel formation region. In one embodiment of the present invention, the semiconductor device is preferably an OS transistor. By using an OS transistor in a memory cell, The leakage current (hereinafter referred to as "off current") that flows between the source and drain is extremely small. Utilizing this, a charge according to a desired potential is supplied to the sources or The voltage is held in the capacitors 33_1 to 33_N electrically connected to the other drain. This can be done.

[0063] That is, once written, data is retained for a long time in the memory cells 31_1 to 31_N. Therefore, the storage device 10A can reduce the frequency of data refresh and Power consumption can be reduced.

[0064] In addition, the memory cells 31_1 to 31_N using OS transistors can be charged or By discharging, data can be rewritten and read. Data can be written and read an unlimited number of times.

[0065] The memory cells 31_1 to 31_N using OS transistors are magnetic memories or resistive memories. Unlike variable memory, it does not involve structural changes at the atomic level, so it has excellent rewrite durability. The memory cells 31_1 to 31_N using OS transistors are flash memory cells. This is due to the increase in electron trap centers caused by repeated rewrite operations, as seen in flash memories. Instability is not recognized.

[0066] In addition, the memory cells 31_1 to 31_N using OS transistors have a channel forming region A silicon transistor (hereinafter referred to as a Si transistor) is formed on the silicon substrate. It can be mounted on a circuit board, etc., and therefore can be easily integrated. In addition, OS transistors can be manufactured using the same manufacturing equipment as Si transistors. Therefore, it can be produced at low cost.

[0067] An OS transistor has a back gate in addition to a gate electrode, a source electrode, and a drain electrode. The semiconductor device can have four terminals, including a gate electrode or a back gate. The input and output of signals flowing between the source and drain are independently controlled according to the potential applied to the electrodes. It can be constructed with a wide range of electrical circuits. Circuit design can be done with the same thinking as in the NI PXIe-4210 (Integration).

[0068] In addition, OS transistors have better electrical properties than Si transistors in high-temperature environments. Specifically, it has the following characteristics: it maintains on-state current even at high temperatures of 125°C or higher and 150°C or lower. The ratio of ON current to OFF current is large, and good switching operation can be performed.

[0069] The memory device 10A shown in FIG. 1A is a DOSR memory cell using OS transistors. AM(Dynamic Oxide Semiconductor Random Ac A memory cell can be called a "transition memory." Since it can be configured with one capacitor, it can store a large amount of data and is highly dense. In addition, by using OS transistors, data retention time can be extended. It is possible.

[0070] The capacitors 33_1 to 33_N are configured such that an insulator is sandwiched between conductors serving as electrodes. In addition to metals, semiconductors that have been given conductivity can also be used as conductors that make up the electrodes. The arrangement of the capacitors 33_1 to 33_N will be described in detail later. However, the structure is such that the transistors 32_1 to 32_N are arranged in an overlapping position above or below the transistors 32_1 to 32_N. In addition to the above, a part of the semiconductor layer or electrode constituting the transistors 32_1 to 32_N is , can be used as one electrode of the capacitors 33_1 to 33_N.

[0071] Precharge circuit 24, sense amplifier 25, check bit generation circuit 54, error detection circuit 5 5. The element layer 26 in which the switch circuit 23 is provided is a detection layer when writing data to the memory cell. The function of generating a scan bit and the function of setting the bit line BL when reading data from a memory cell. The memory has a precharge function, a function to amplify the potential of the bit line BL, and a function to check the memory It has the function of detecting whether there are any errors in the data read from the cell.

[0072] The elements of the element layer 26 include the precharge circuit 24, the sense amplifier 25, the test bit generation circuit 26, and the The circuit 54, the error detection circuit 55, and the switch circuit 23 are configured using OS transistors. It is preferable that each circuit included in the element layer 26 is configured using an OS transistor. By this, the element layer 26 can be provided on a silicon substrate on which a Si transistor is formed. Therefore, integration can be easily achieved. It can be manufactured using the same manufacturing equipment as Si transistors, so it can be manufactured at low cost. It is possible.

[0073] <Schematic diagram of storage device> In each of the configurations described in FIG. 1A, the element layers 34_1 to 34_N and the element layer 26 To explain this, a schematic diagram showing an example of the configuration of the storage device 10A is shown in FIG. 1B. In the schematic diagram, the x-axis, y-axis, and z-axis directions are defined in order to explain the arrangement of each component described in FIG. 1A. FIG.

[0074] As shown in FIG. 1B, the memory device 10A includes an element layer 26 and element layers 34_1 to 34_2. 34_N, a total of (1+N) layers of OS transistors are stacked on the semiconductor substrate 11. The element layer 26 and the element layers 34_1 to 34_N are provided as layers. The memory cells 31_1 to 31_N are each formed by a columnar memory cell provided on a semiconductor substrate 11. The element layer 26 has an area overlapping the driver 22. The element layer 26 is formed by the semiconductor substrate 11 and the element layer 26. It is located between 34_1.

[0075] The semiconductor substrate 11 may be formed with any suitable material, as long as it is capable of forming a channel region of a transistor. For example, single crystal silicon substrates, single crystal germanium substrates, and compound semiconductor substrates (SiC substrate, GaN substrate, etc.), SOI (Silicon on Insulator ) substrates, etc. can be used.

[0076] The transistor of the memory cell 31_1 included in the element layer 34_1 and the transistor of the element layer 34_N The transistor of the memory cell 31_N has a bit line BL provided in the vertical direction. The bit line BL is electrically connected to the element layer 26. The layer 26 is electrically connected to a column driver 22 provided on the semiconductor substrate 11 .

[0077] For example, the bit line BL_1 is connected to the semiconductor layer of the transistor included in the memory cell 31_1. Alternatively, the bit line BL_1 is provided as a transistor included in the memory cell 31_1. The source and drain regions of the semiconductor layer of the transistor are provided in contact with the source and drain regions. The bit line BL_1 is connected to the source of the semiconductor layer of the transistor of the memory cell 31_1. Alternatively, it is provided in contact with a conductor provided in contact with a region that functions as a drain.

[0078] That is, the bit line BL is connected to the source or drain of the transistor of the memory cell 31_1. One of the drains of the transistor in the memory cell 31_N is connected to one of the source and drain of the transistor in the memory cell 31_N. It can be said that the wiring electrically connects the element layer 26 to the other layer.

[0079] The bit lines BL are arranged in a direction perpendicular to the surface of the semiconductor substrate 11 on which the column drivers 22 are provided. It can be said that the conductors extend in the vertical direction or in the substantially vertical direction. In this way, the bit line BL is connected to the transistor of the memory cell 31_1 and the memory The cell 31_N is connected to the transistor, and the surface (xy plane) of the semiconductor substrate The direction of the light source is perpendicular (z direction) or approximately perpendicular to the light source. , refers to a state in which the electrodes are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0080] In a memory device 10A according to one embodiment of the present invention, the following transistors are provided in each element layer: An OS transistor with extremely low off-state current is used. This reduces the frequency of refreshing data, resulting in a memory device with low power consumption. It is possible.

[0081] OS transistors can be stacked and can be fabricated repeatedly in the vertical direction using the same manufacturing process. Since the memory device can be manufactured using the same method, the manufacturing cost can be reduced. The 10A arranges the transistors that make up the memory cells vertically instead of horizontally. This allows for an improvement in memory density, which in turn allows for a reduction in the size of the storage device 10A. can.

[0082] In addition, OS transistors have better electrical characteristics than Si transistors even in high-temperature environments. Because the fluctuation is small, the fluctuation in the electrical characteristics of the transistors when stacked and integrated is small, and the reliability is high. It can function as a highly reliable storage device.

[0083] The memory device 10A can have memory cells arranged above the column drivers, etc. Therefore, the storage device 10A is a small, high-density storage device that can store a large amount of data. Furthermore, the memory cell can operate even if the capacitance of the capacitor is reduced. It is possible.

[0084] Furthermore, the memory device 10A has bit lines extending from the memory cell array. By providing the substrate 11 in a direction substantially perpendicular to the surface of the substrate 11, the bit spacing between the memory cell array and the element layer 26 is Therefore, the parasitic capacitance of the bit line can be reduced, and the memory cell Even if the data signal held in the memory cell is multi-valued, the potential can be read out.

[0085] <Cross-section of storage device> 2, the vertical direction (z-axis direction) of the storage device 10A described with reference to FIGS. 1A and 1B is ) is shown in a schematic diagram of a cross section parallel to the line.

[0086] As shown in FIG. 2, the memory device 10A includes memory cells 31_1 to 31_2 provided in each element layer. 31_N, the element layer 26, and the column driver 22 provided on the semiconductor substrate 11 are vertically connected. The bit lines BL can be connected in the vertical direction. By providing the bit line BL in the negative direction, the length of the bit line BL can be shortened. The load can be reduced.

[0087] In FIG. 3, the memory cell array 30 includes element layers 34_1 to 34_N, a precharge circuit 24, sense amplifier 25, check bit generation circuit 54, error detection circuit 55, switch circuit 23, and the write / read circuit 2 9 is shown.

[0088] 3, the bit line BL_A or BL_B, the precharge circuit 24, and the sensor Transistors 28_a and 28_b for controlling conduction between the amplifier 25 and the switch The switches 23_A to 23_C included in the bit line switch circuit 23 are shown. BL_A is connected to either the source or the drain of the transistor 28_a, and is connected to the bit line BL_B is connected to either the source or the drain of the transistor 28_b.

[0089] Above the element layer 26 shown in FIG. 3, element layers 34_1 to 34_N are provided. The line BL_A and the bit line BL_B are provided in the vertical direction. The element layer 26 constituting the element layer 26 can be provided by stacking the same as the element layers 34_1 to 34_N. The bit lines BL_A and BL_B are connected to the transistors 28_a and 28_b. The precharge circuit 24 and the sense amplifier 25 are connected via the transistor 28_b. The input is connected to a transistor.

[0090] The precharge circuit 24 is composed of n-channel transistors 24_1 to 24_3. The precharge circuit 24 responds to a precharge signal applied to a precharge line PCL. Therefore, the bit lines BL_A and BL_B are set to, for example, the potentials VDD and VSS. This is a circuit for precharging to the intermediate potential VPC, which corresponds to the potential VDD / 2 between the two terminals.

[0091] The sense amplifier 25 has n-channel transistors 25_1 to 25_4. The transistor 25_1 and the transistor 25_2 are connected to the wiring VHH. The transistor 25_3 and the transistor 25_4 are connected to the wiring VLL. The wiring VLL has a function of supplying a potential VSS. 5_1 to 25_4 are transistors that form inverter loops.

[0092] When data is read from a memory cell, the precharge circuit 24 precharges the bit line. The row driver 21 sets the word line of the selected memory cell to a high level, The potential of the recharged bit line changes. In response to this change, the sense amplifier 25 The potential of a pair of wires connected to the sense amplifier 25 is set to the potential VDD or the potential VSS. The potential is output to the write / read circuit 29 via the switch circuit 23 .

[0093] When writing data to a memory cell, the check bit generation circuit 54 It has a function to generate check bits based on the data signal output from 9, and When reading data from a memory cell, the circuit 55 reads the data from the memory cell using the check bits. The output data is checked for errors and the results are output to the write / read circuit 29. The check bit generation circuit 54 and the error detection circuit 55 will be described in detail later. .

[0094] In addition, the element layers 34_1 to 34_N and the element When the layer 26 is referred to as a unit 39, the units 39 may be stacked vertically. 4 shows the units 39 described in FIG. 2 in M ​​stages (units 39_1 to 39_2). M, where M is a natural number of 2 or more). 1 is a schematic diagram of a cross section parallel to the vertical direction (z-axis direction) of B.

[0095] As shown in FIG. 4, the storage device 10B includes units 39_1 to 39_M. , respectively, have element layers 34_1 to 34_N and element layer 26. One of the units 39_1 to 39_M is selected from the performs signal input or signal output via the wiring BL_U and the element layer 26. U is selected by a switch circuit 41 that can be switched by a selection signal SEL, and is connected to a line GBL. The switch circuit 41 is connected to the column driver 22. It may also be configured using OS transistors.

[0096] By configuring the storage device 10B, each of the units 39_1 to 39_M In this case, the number of stacked element layers 34_1 to 34_N can be reduced. By reducing the number of stacked layers 1 to 34_N, the length of the bit line BL can be shortened. The load on the bit line BL can be reduced. To improve clarity, the wiring may be shown in bold or bold dotted lines. It is sometimes called a bit line.

[0097] The wiring GBL shown in FIG. 4 is provided after the element layer having the OS transistor is formed. For example, as shown in the cross-sectional view of FIG. 5A, An opening is provided on the outer periphery of the sealing layer 40A surrounding each element layer, and the opening Alternatively, as shown in the cross-sectional view of FIG. 5B, a wiring GBL can be provided on the OS The device layers having transistors are fabricated, and the outer periphery of the sealing layer 40B that collectively surrounds each device layer is 5A and 5B, an opening can be provided in the wiring GBL. In B, the switch circuit 41 and the like are omitted, and the details of each element layer provided with the wiring GBL are not shown. This will be described in detail in the third embodiment.

[0098] <Check bit generation circuit, error detection circuit> 6A is a circuit diagram showing an example of the configuration of the check bit generation circuit 54. 4 includes XOR circuits 53_1 to 53_3. Examples will be given later.

[0099] For ease of explanation, in the memory device 10A, the memory cell array 30 The element layers 34_1 to 34_N will be described assuming that N is 5. Of the _1 to 34_5 layers, one is used to store check bits, and the remaining four layers store data. That is, the check bit generation circuit 54 described in this embodiment holds the following data. This is a circuit that handles 4-bit data and 1-bit check bit.

[0100] The check bit generation circuit 54 has input terminals T_A0 to T_A3, 4-bit data represented by bits A0 to A3 is input, and a check bit is generated. The generating circuit 54 has input terminals T_CK1 to T_CK4, each of which receives a control signal The clock signals CK1 to CK4 are input. The generating circuit 54 outputs the check bit from the output terminal OUT.

[0101] FIG. 6B shows the clock signals CK1 to C input to the check bit generation circuit 54. The relationship between K4, the 4-bit data input period PDI, and the check bit output period PDO 1 is a timing chart showing the relationship between clock signals CK1 to CK4 and The high level of 4-bit data is expressed using the potential VDD, and the low level is expressed using the potential VSS. In FIG. 6B, these voltages are represented as Vdd(H) and Vss(L), respectively.

[0102] 6C shows the output for 4-bit data input to the check bit generation circuit 54. This is a truth table showing high level (H) or low level (L). The table shows that if the number of high levels (H) among bits A0 to A3 is odd, the check bit The output generating circuit 54 outputs a high level (H), and when the number of high levels (H) is even or 0, In this case, the check bit generation circuit 54 outputs a low level (L).

[0103] 7A is a circuit diagram showing an example of the configuration of the error detection circuit 55. XOR circuits 53_4 to 53_7 and delay circuits 52_1 to 52_8 A configuration example of the delay circuit 52 will be described later.

[0104] In addition, like the check bit generation circuit 54, the error detection circuit described in this embodiment 55 is a circuit that handles 4-bit data and 1-bit check bit.

[0105] The error detection circuit 55 has input terminals T_A0 to T_A3, each of which is 4-bit data represented by bits A0 to A3 is input, and the error detection circuit 55 The input terminals T_CK1 to T_CK4 are clock signals that are control signals. The error detection circuit 55 receives the signals CK1 to CK4 at its input terminals. The error detection circuit 55 has the check bit T_B0 and the check bit B0 is input. If no error is found in the relationship between bit B0 and bits A0 to A3, the output terminal O A low level (L) is output from the UT, and if an error is found, a high level (H) is output.

[0106] FIG. 7B shows the clock signals CK1 to CK4 input to the error detection circuit 55. 4-bit data, check bit input period PDI, and output of error detection circuit 55 10 is a timing chart showing the relationship between the clock signals CK1 to CK2 and the period PDO. The high level of the signal CK4, 4-bit data, and check bit is expressed using the potential VDD. and the low level is represented by the potential VSS, so in FIG. 7B, H), Vss(L).

[0107] 8 shows the error detection circuit 55 for the 4-bit data and check bits. The truth table shown in Figure 8 expresses the output as high level (H) or low level (L). The truth table shows that the check bit B0 is at a low level (L) and the check bits A0 to A3 are If the number of high levels (H) is odd, the error detection circuit 55 outputs a high level (H). This means that the high level ( If the number of check bits (H) is odd, the check bit generation circuit 54 generates a high level (H) as the check bit. Therefore, an error is found in the relationship between the check bit B0 and bits A0 to A3. This indicates that it has been found.

[0108] In addition, the truth table shown in FIG. 8 indicates that the check bit B0 is at a high level (H) and the bits A0 and When the number of high levels (H) among bits A0 to A3 is even or zero, error detection circuit 5 5 indicates that it outputs a high level (H). This means that among bits A0 to A3, when the number of high levels (H) is even or zero, parity bit generation circuit 54 outputs a low level (L) as a parity bit, indicating that an error has been found in the relationship between parity bit B0 and bits A 0 to A3.

[0109] That is, by including parity bit generation circuit 54, parity bit B0, and error detection circuit 55 memory device 10A can perform parity checking both during data writing and reading inside the memory device. Also, the output signal of error detection circuit 55 is output to column driver 22 via switch 23_C.

[0110] <XOR circuit, NAND circuit, delay circuit> Figure 9A is a symbol representing XOR circuit 53, and Figure 9B is a circuit diagram showing a configuration example of XOR circuit 53. As shown in Figure 9B, XOR circuit 53 includes NAND circuits 51_1 to NAND circuits 51_4, delay circuit 52_1, and delay circuit 52_2. Also, XOR circuit 53 has input terminal D, input terminal E, and input terminals C5 to C8 to which control signals S_C5 to control signals S_C8 are input, and outputs a signal from output terminal Z .

[0111] Figure 9C is a timing chart showing the relationship between control signals S_C5 to S_C8 input to XOR circuit 53, the input period PDI of the signals input to input terminal D and input terminal E, and the output period PDO of XOR circuit 53. Control signals S_C5 to control signals S_C8 The high level of the signal S_C8 and the input signal is represented by the potential VDD, and the low level Since the voltages are expressed using the potential VSS, in FIG. 9C, It is marked L).

[0112] 9D shows the output for the signal input to the XOR circuit 53, which is set to a high level (H) or The truth table shown in FIG. 9D is a truth table showing the input terminals D, The relationship between the signal input to input terminal E and the signal output from output terminal Z is shown.

[0113] FIG. 10A is a symbol representing the NAND circuit 51, and FIG. 10B is a diagram of the NAND circuit 51. 10B is a circuit diagram showing an example of a configuration of a NAND circuit 51. As shown in FIG. The transistors 61 to 64 and the capacitor C61 are included. The transistor 64 is an n-channel transistor. Input terminal A, input terminal B, and control signals S_C1 and S_C2 are input. The amplifier has input terminals C1 and C2, and outputs a signal from output terminal X.

[0114] FIG. 10C shows the control signals S_C1 and S_C2 input to the NAND circuit 51. , the input period PDI of the signal input to the input terminal A and the input terminal B, and 10 is a timing chart showing the relationship between the control signal S_C1 and the output period PDO of the circuit 51. The high level of the control signal S_C2 and the input signal is represented by the potential VDD. Since the negative level is expressed using the potential VSS, in FIG. 10C, It is indicated as Vss(L).

[0115] 10D shows that the output for the signal input to the NAND circuit 51 is set to a high level (H ) or low level (L). The truth table shown in Figure 10D is The relationship between the signal input to terminal A and input terminal B and the signal output from output terminal X is shown. There are.

[0116] FIG. 11A is a symbol representing the delay circuit 52, and FIG. 11B is a diagram of the delay circuit 52. 11B is a circuit diagram showing an example of a configuration of a delay circuit 52. As shown in FIG. 71, a transistor 72, and a capacitor C71. The transistor 72 is an n-channel transistor. input terminal C, input terminal C3 to which control signal S_C3 and control signal S_C4 are input, and It has an input terminal C4 and outputs a signal from an output terminal Y.

[0117] FIG. 11C shows the control signals S_C3 and S_C4 input to the delay circuit 52. , an input period PDI of a signal input to the input terminal C, and an output period PDI of the delay circuit 52. 10 is a timing chart showing the relationship between the control signal S_C3 and the control signal S_C4 and the PDO. The high level of the input signal is represented by the potential VDD, and the low level is represented by the potential V SS, they are represented as Vdd(H) and Vss(L) in FIG. 11C. It is written.

[0118] FIG. 11D shows that the output for the signal input to the delay circuit 52 is set to a high level (H ) or low level (L). The truth table shown in Figure 11D is The figure shows the relationship between the signal input to terminal C and the signal output from output terminal Y.

[0119] <Storage device> In the memory device according to one embodiment of the present invention, a transistor provided in each element layer has a low off-state current. Always use small OS transistors. OS transistors are, for example, Si transistors. Since the semiconductor device can be stacked on a silicon substrate on which the semiconductor device is provided, the semiconductor device can be repeatedly mounted in the vertical direction. The same manufacturing process can be used to manufacture the semiconductor device, thereby reducing manufacturing costs. In a memory device according to one aspect of the present invention, transistors constituting memory cells are arranged in a direction other than a plane direction. It can be arranged vertically to increase memory density and reduce the size of storage devices. can.

[0120] In addition, the storage device according to one aspect of the present invention includes a check bit generation circuit, a check bit, and an error Therefore, the storage device according to one aspect of the present invention includes a detection circuit. Parity checks can be performed as data is written and read. ,The check bit generation circuit and error detection circuit can be ,configured using OS transistors. The circuitry can be arranged vertically to reduce the size of the storage device.

[0121] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible.

[0122] (Embodiment 2) In this embodiment, a modification of the circuit that can be applied to the memory device 10A described in the first embodiment is An example will be described with reference to FIG.

[0123] In FIG. 2 and other figures, the memory cells 31_1 to 31_N and the transistors constituting the element layer 26 are The transistor has a top gate structure or a bottom gate structure without a back gate electrode. Although a transistor is shown, the structure of the transistor is not limited to this. For example, Like the memory device 10C, a back gate electrode connected to a back gate electrode line BGL is provided. By using the configuration of FIG. 12, the threshold voltage of the transistor can be The voltage can be controlled externally.

[0124] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible.

[0125] (Embodiment 3) An example of a storage device according to one embodiment of the present invention will be described below.

[0126] FIG. 13 shows a semiconductor device in which a memory unit is formed on an element layer 411 having a circuit formed on a semiconductor substrate 311. 470 (memory unit 470_1 to memory unit 470_m: m is 1 or more 13 is a diagram illustrating an example of a memory device in which an element layer 411 and A plurality of memory units 470 are stacked on the element layer 411. 70, one transistor layer 413 (transistor layer 413_1 to transistor layer 413_m) and a plurality of memory device layers 41 on each transistor layer 413. 5 (memory device layers 415_1 to 415_n: n is a natural number equal to or greater than 2) ) is provided in each memory unit 470. 13, a memory device layer 415 is provided on the substrate 13. The transistor layer 413 may be provided on multiple memory device layers 415. Alternatively, memory device layers 415 may be provided above and below transistor layer 413 .

[0127] The element layer 411 includes a transistor 300 provided over a semiconductor substrate 311. It can function as a peripheral circuit. Examples of peripheral circuits include column drivers, row drivers, driver, column decoder, row decoder, amplifier circuit, input / output circuit, control logic Circuits, etc.

[0128] The transistor layer 413 includes a transistor 200T, which controls each memory unit 470. The memory device layer 415 can function as a circuit for storing memory devices 42. The memory device 420 shown in this embodiment has a transistor 200M and a capacitor It has 292.

[0129] The value of m is not particularly limited, but is preferably 1 to 100, more preferably 1 to 5. It is preferably 0 or less, and more preferably 1 or more and 10 or less. There is no limitation, but it is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more The product of m and n is 2 or more and 256 or less, preferably 2 or more and 12 or less. It is preferably 8 or less, and more preferably 2 or more and 64 or less.

[0130] 13 also shows the transistor 200T included in the memory unit 470 and the transistor 1 shows a cross-sectional view of the transistor 200M in the channel length direction.

[0131] As shown in FIG. 13, a transistor 300 is provided on a semiconductor substrate 311. On the memory unit 470 are a transistor layer 413 and a memory device layer 300. 415 is provided, and the transistors of the transistor layer 413 in one memory unit 470 The transistor 200T and the memory device 420 included in the memory device layer 415 are The conductor 424 electrically connects the transistor 300 and each memory unit 470 The transistor 200T included in the transistor layer 413 is electrically connected to the conductor 426. The conductor 426 is electrically connected to the source, drain, and The transistor 200T is connected to the conductor 428 electrically connected to one of the gates. It is preferable to electrically connect the conductors 424 to each layer of the memory device layer 415. The conductor 426 is preferably formed between the transistor layer 413 and the memory It is preferable that each layer of the device layer 415 is provided with the light emitting element.

[0132] As will be described in detail later, the side surfaces of the conductor 424 and the conductor 426 are coated with water or It is preferable to provide an insulator that suppresses the permeation of impurities such as hydrogen and oxygen. Suitable insulators include, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. Which one should I use?

[0133] The memory device 420 includes a transistor 200M and a capacitor 292. 0M may have a structure similar to that of the transistor 200T included in the transistor layer 413. Also, transistor 200T and transistor 200M can be grouped together as transistor It is sometimes called 200.

[0134] Here, the transistor 200 is formed by using an oxide semiconductor in a semiconductor including a region where a channel is formed. It is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor.

[0135] As the oxide semiconductor, for example, In-M-Zn oxide (element M is aluminum, gallium, Aluminum, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, Germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium tantalum, tungsten, magnesium, or the like) In addition, as the oxide semiconductor, indium oxide, In-G Indium-Zn oxide and In-Zn oxide may also be used. By using it as a compound semiconductor, it is possible to increase the on-current or field effect mobility of the transistor. This can be done.

[0136] The transistor 200 using an oxide semiconductor for a channel formation region has an extremely low Since the leakage current is extremely small, a memory device with low power consumption can be provided. Since the film can be formed by sputtering or the like, it is suitable for use in transistors that make up highly integrated memory devices. It can be used for the transistor 200.

[0137] On the other hand, transistors using oxide semiconductors have a tendency to degrade due to impurities and oxygen vacancies in the oxide semiconductor. This causes the electrical characteristics to change, resulting in a normally-on characteristic (even without applying a voltage to the gate electrode). The presence of a channel allows current to flow through the transistor.

[0138] Therefore, it is preferable to use an oxide semiconductor with a reduced impurity concentration and a reduced density of defect states. In this specification and the like, a low impurity concentration and a low defect level density are referred to as a high purity intrinsic or It is essentially high-purity and authentic.

[0139] Therefore, it is preferable that the impurity concentration in the oxide semiconductor be reduced as much as possible. Impurities in the oxide semiconductor include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, and the like. Metals include iron, nickel, silicon, etc.

[0140] In particular, hydrogen as an impurity contained in oxide semiconductors creates oxygen vacancies (V O In addition, oxygen vacancies can form. Defects containing elements (hereinafter referred to as V O H) generates electrons that act as carriers. Furthermore, some of the hydrogen reacts with oxygen that bonds with the metal atoms, forming electron carriers. may be generated.

[0141] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is a normally-on transistor. In addition, hydrogen in oxide semiconductors tends to move due to stresses such as heat and electric fields. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor will decrease. There is also a risk.

[0142] Therefore, the oxide semiconductor used in the transistor 200 does not contain impurities such as hydrogen and oxygen deficiency. It is preferable to use a high-purity intrinsic oxide semiconductor with reduced loss.

[0143] <Sealing structure> Therefore, in order to prevent the intrusion of impurities from the outside, a material that suppresses the diffusion of impurities (hereinafter referred to as The transistor 200 may be sealed using a material having a barrier property against impurities. .

[0144] In this specification, the term "barrier property" refers to the function of suppressing the diffusion of a corresponding substance (permeability). Or, the corresponding substance is captured and fixed (gettering). This function is also called "gaming."

[0145] For example, aluminum oxide is a material that has the function of suppressing the diffusion of hydrogen and oxygen. Nitride, Hafnium oxide, Gallium oxide, Indium gallium zinc oxide, Silicon nitride In particular, silicon nitride or silicon nitride oxide is It is preferable to use it as a sealing material because it has high barrier properties against hydrogen.

[0146] Furthermore, for example, aluminum oxide is a material that has the function of capturing and fixing hydrogen. metal oxides such as hafnium oxide, gallium oxide, indium gallium zinc oxide, be.

[0147] Between the transistor 300 and the transistor 200, an insulator is provided as a layer having a barrier property. Preferably, insulator 211, insulator 212, and insulator 214 are provided. , insulator 212, and insulator 214. By using a material that suppresses It is possible to prevent impurities such as hydrogen and water from diffusing into the transistor 200. 11, at least one of the insulator 212 and the insulator 214 is made of a material that inhibits oxygen permeation. By using the above, the channel of the transistor 200 or the transistor layer 413 For example, the insulator 211 and the insulating layer 412 can be prevented from diffusing oxygen into the element layer 411. The body 212 is made of a material that suppresses the permeation of impurities such as hydrogen and water, and the insulator 214 is made of a material that suppresses the permeation of impurities such as hydrogen and water. It is preferable to use a material that suppresses the permeation of oxygen. It is more preferable to use a material that has the property of absorbing and storing. The insulator 212 is made of a nitride such as silicon nitride or silicon nitride oxide. The insulator 214 may be, for example, aluminum oxide, hafnium oxide, or Metal oxides such as gallium, indium gallium zinc oxide, etc. can be used. In particular, it is preferable to use aluminum oxide as the insulator 214 .

[0148] Also, the side surfaces of the transistor layer 413 and the memory device layer 415, i.e., the memory unit The side of the memory unit 470 is preferably provided with an insulator 287. It is preferable that an insulator 282 is provided on the upper surface of the insulating member 282. 287, and the insulator 287 is preferably in contact with the insulators 211, 212, and It is preferable that the insulator 287 and the insulator 214 are in contact with each other. It is preferable to use a material that can be used for the insulator 214 as the material 82 .

[0149] In addition, the insulators 283 and 287 are disposed so as to cover the insulators 282 and 287. 4 is preferably provided, and the insulator 283 is made of the insulators 211, 212, and It is preferable that the insulator 287 is in contact with at least one of the insulators 214. In FIG. contacting the side of the edge 214, the side of the insulator 212, and the top and side surfaces of the insulator 211; This shows an example in which the insulator 283 contacts the side surface of the insulator 287 and the top surface of the insulator 211. However, the present embodiment is not limited to this. The insulator 283 contacts the top and side surfaces of the insulator 287 and the insulator 21 The insulator 282 and the insulator 287 may be in contact with the upper surface of the insulator 211. It is preferable to use a material that can be used for the insulating body 212.

[0150] In the above structure, the insulators 287 and 282 are made of a material that suppresses oxygen permeation. It is preferable to use the insulator 287 and the insulator 282 as the insulators for capturing hydrogen. It is more preferable to use a material that has good adhesion and good electrical conductivity. By using a material on the adjacent side that has the function of capturing and fixing hydrogen, The hydrogen in the storage unit 200 or the storage unit 470 is insulated by the insulator 214, the insulator 287, and insulator 282, trapping and adhering to the insulator 282, resulting in a hydrogen concentration in transistor 200. In addition, hydrogen, water, etc. can be used as the insulator 283 and the insulator 284. It is preferable to use a material that inhibits the permeation of impurities.

[0151] With the above structure, the memory unit 470 is made up of the insulators 211 and 212. , insulator 214, insulator 287, insulator 282, insulator 283, and insulator 284. More specifically, the memory unit 470 is surrounded by an insulator 214, an insulator 287, and an insulator 282 (sometimes referred to as a first structure), The first structure includes an insulator 211, an insulator 212, an insulator 283, and The insulating body 284 (sometimes referred to as the second structure) is enclosed. When a structure in which the memory unit 470 is surrounded by two or more layers of structures is called a nested structure, Here, the memory unit 470 is surrounded by a plurality of structures. The knit 470 may be described as being encapsulated by multiple insulators.

[0152] The second structure also seals the transistor 200 via the first structure. The hydrogen existing outside the second structure is absorbed by the second structure into the inside (transition) of the second structure. The diffusion of the first structure to the second structure (transistor 200 side) is suppressed. It is possible to efficiently capture and fix hydrogen present in the internal structure of the material.

[0153] Specifically, the first structure is made of a metal oxide such as aluminum oxide. The second structure may be made of a nitride such as silicon nitride. When an aluminum oxide film is disposed between the transistor 200 and the silicon nitride film, good.

[0154] Furthermore, the material used for the structure can be used to control the hydrogen concentration in the film by appropriately setting the film formation conditions. can be reduced.

[0155] Generally, films formed using the CVD method have higher solubility than films formed using the sputtering method. On the other hand, the compound gas used in the CVD method often contains hydrogen, The film formed by the D method has a higher hydrogen content than the film formed by the sputtering method. There are many.

[0156] Therefore, for example, a film with a reduced hydrogen concentration ( Specifically, it is advisable to use a film formed by sputtering. As a film for suppressing diffusion, a film with high film-forming properties but a relatively high hydrogen concentration in the film (specifically, When a film formed by CVD is used, the transistor 200 and the film having a relatively high hydrogen concentration are It has the function of capturing and fixing hydrogen between the film with high film-forming ability and high film-forming ability. A film with reduced concentration may be provided.

[0157] That is, the film disposed in the vicinity of the transistor 200 is a film having a relatively low hydrogen concentration. On the other hand, a film with a relatively high hydrogen concentration in the film is preferably used at a distance from the transistor 200. It is recommended to arrange them as follows.

[0158] Specifically, the transistor 200 is made of a silicon nitride film formed by a CVD method. When sealing with silicon, the transistor 200 and a silicon nitride film formed by CVD are When an aluminum oxide film formed by sputtering is placed between the silicon film, More preferably, a silicon nitride film formed by CVD and a silicon nitride film formed by sputtering are used. The nitride film formed by sputtering was placed between the aluminum oxide film formed by the method. It is preferable to provide a silicon dioxide film.

[0159] When forming a film using the CVD method, the film does not contain hydrogen atoms or the content of hydrogen atoms is By depositing the film using a compound gas with less hydrogen, the hydrogen concentration in the deposited film is reduced. Good too.

[0160] Also, between each transistor layer 413 and the memory device layer 415, or between each memory device Preferably, an insulator 282 and an insulator 214 are also provided between the layers 415. In addition, it is preferable that an insulator 296 is provided between the insulator 282 and the insulator 214. The insulator 296 may be made of the same material as the insulators 283 and 284. Alternatively, silicon oxide or silicon oxynitride can be used. Insulators 282, 296, and 214 may be made of a conductive material. , may be elements that constitute the transistor 200. The insulator 214 also serves as a component of the transistor 200, which contributes to the fabrication of a memory device. This is preferable because it reduces the number of steps required.

[0161] Also, between each transistor layer 413 and the memory device layer 415, or between each memory device The insulators 282, 296, and 214 provided between the layers 415 are The side surface is preferably in contact with the insulator 287. By adopting such a structure, the transistor The memory device layer 415 is formed by the insulator 282, the insulator 296, and the The insulating material 214, the insulating material 287, the insulating material 283, and the insulating material 284 surround and seal the insulating material 214. can be.

[0162] In addition, an insulator 274 may be provided around the insulator 284. A conductor 430 is provided so as to be embedded in the edge 284, the insulator 283, and the insulator 211. The conductor 430 may be connected to the transistor 300, i.e., the circuit included in the element layer 411. Make an electrical connection.

[0163] In addition, in the memory device layer 415, the capacitor 292 is formed in the same layer as the transistor 200M. Therefore, the height of the memory device 420 can be made to be approximately the same as that of the transistor 200M. This makes it possible to prevent the height of each memory device layer 415 from becoming excessively large. This allows the number of memory device layers 415 to be increased relatively easily. For example, a stack of about 100 layers each consisting of a transistor layer 413 and a memory device layer 415 is formed. It may be set to degrees.

[0164] <Transistor 200> 14A, the transistor 200T included in the transistor layer 413 and the memory The transistor 200 can be used for the transistor 200M included in the device 420. This article explains:

[0165] As shown in FIG. 14A, the transistor 200 includes an insulator 216 and a conductor 205 ( 205a, and conductor 205b), insulator 222, insulator 224, and oxide 230 (oxide 230a, oxide 230b, and oxide 230c) and conductor 242 (conductor 242a, and conductor 242b) and oxide 243 (oxide 243a, and oxide 2 43b), an insulator 272, an insulator 273, an insulator 250, and a conductor 260 (conductor 260a, and conductor 260b).

[0166] The insulator 216 and the conductor 205 are provided on the insulator 214, and the insulator 273 An insulator 280 and an insulator 282 are provided on the top. and insulator 282 can be considered to be part of transistor 200. .

[0167] In addition, in the memory device of one embodiment of the present invention, a transistor 200 is electrically connected to the semiconductor device 100 and serves as a plug. The conductor 240 (conductor 240a and conductor 240b) functions as a The insulator 241 (insulator 241a, and In addition, on the insulator 282 and the conductor 240, , a conductor 246 (conductor 246a, and conductor 246b).

[0168] The conductors 240a and 240b are made of tungsten, copper, or aluminum. It is preferable to use a conductive material containing the following as a main component. 240b may have a laminated structure.

[0169] Furthermore, when the conductor 240 has a laminated structure, impurities such as water or hydrogen and oxygen are permeable. It is preferable to use a conductive material that has the function of suppressing overheating. For example, tantalum, nitride Tantalum, titanium, titanium nitride, ruthenium, or ruthenium oxide can be used. It also has the function of inhibiting the permeation of impurities such as water or hydrogen, and oxygen. The conductive material may be used in a single layer or a multilayer structure. Impurities such as water or hydrogen diffused from the conductor 240a and the conductor 24 0b can further reduce the amount of oxide 230 mixed in. Preventing oxygen added to 80 from being absorbed by conductors 240a and 240b. can be done.

[0170] The insulator 241 provided in contact with the side surface of the conductor 240 is, for example, silicon nitride. The insulator 241 may be made of silicon, aluminum oxide, silicon nitride oxide, or the like. , provided in contact with the insulators 272, 273, 280, and 282. Therefore, impurities such as water or hydrogen from the insulator 280 etc. are transferred to the conductor 240a and the conductor 240b, it is possible to prevent the silicon nitride from being mixed into the oxide 230. The insulator 280 is preferably made of silicon because it has a high blocking property against hydrogen. This can prevent oxygen from being absorbed into the conductors 240a and 240b.

[0171] The conductor 246 is made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor may have a laminated structure, for example, titanium or Alternatively, the conductive material may be a laminate of titanium nitride and the conductive material. The insulating film may be formed so as to be embedded in the opening.

[0172] In transistor 200, conductor 260 functions as the first gate of the transistor. The conductor 205 functions as a second gate of the transistor. a and the conductor 242b function as a source electrode or a drain electrode.

[0173] The oxide 230 functions as a semiconductor having a channel formation region.

[0174] Insulator 250 serves as the first gate insulator, and insulators 222 and 224 acts as a second gate insulator.

[0175] Here, the transistor 200 shown in FIG. 14A is made up of an insulator 280, an insulator 273, an insulator 2 72, the conductor 242, etc., in the opening, the conductor 260 is formed between the oxide 230c and the insulating It is formed in a self-aligned manner via the edge 250 .

[0176] That is, the conductor 260 is connected to the insulator 280 via the oxide 230c and the insulator 250. Since the conductive material is formed to fill the openings between the conductors 242a and 242b, In this region, alignment of the conductors 260 is not required.

[0177] Here, it is preferable to provide the oxide 230c in an opening provided in the insulator 280 or the like. Therefore, the insulator 250 and the conductor 260 are connected to the oxide 230 via the oxide 230c. b and the oxide 230a. Since the oxide 230c and the insulator 250 can be formed by successive film formation, the oxide Therefore, the interface between the object 230 and the insulator 250 can be kept clean. The effect on carrier conduction is reduced, allowing transistor 200 to operate at high on-state current and high frequency. Numerical properties can be obtained.

[0178] In addition, in the transistor 200 shown in FIG. 14A, the bottom and side surfaces of the conductor 260 are insulators. 250. The bottom and side surfaces of the insulator 250 are in contact with the oxide 230c.

[0179] Also, the transistor 200 has an insulator 282 and an oxide 230c, as shown in FIG. By adopting this structure, the acid contained in the insulator 280 is Diffusion into the elemental conductor 260 can be suppressed.

[0180] Therefore, the oxygen contained in the insulator 280 is transferred to the oxide 230a and the oxide 230c via the oxide 230c. Since the oxide 230a and the oxide 230b can be efficiently supplied with the oxygen, the oxygen in the oxide 230a and the oxide 230b can be efficiently supplied with the oxygen. 230b, thereby improving the electrical characteristics and reliability of the transistor 200. It is possible.

[0181] The detailed configuration of a memory device including the transistor 200 according to one embodiment of the present invention will be described below. and explain.

[0182] The transistor 200 includes an oxide 230 (oxide 230a, oxide 230b) including a channel formation region. It is preferable to use an oxide semiconductor for the oxide 230b and the oxide 230c.

[0183] For example, metal oxides that function as oxide semiconductors have an energy gap of 2 eV or more. It is preferable to use one with an energy gap of 2.5 eV or more. By using a metal oxide, the leakage current of the transistor 200 in the non-conducting state (off By using such a transistor, low power consumption can be achieved. This makes it possible to provide a low-power storage device.

[0184] Specifically, the oxide 230 is an In-M-Zn oxide (wherein the element M is aluminum, gallium, Sodium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel Ru, Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more selected from the group consisting of ammonium, tantalum, tungsten, and magnesium In particular, the element M may be an oxide of a metal such as aluminum, gallium, or yttrium. The oxide 230 may be an In-M oxide, an In- Zn oxide or M-Zn oxide may also be used.

[0185] As shown in FIG. 14A, the oxide 230 is formed by oxide 230a on the insulator 224 and oxide 230b on the insulator 224. 30a, and an oxide 230b disposed on the oxide 230b and at least partially covered with oxide 230b. and an oxide 230c in contact with the upper surface of 30b. The side of Oc is made up of oxide 243a, oxide 243b, conductor 242a, conductor 242b, and insulator. It is preferable that the insulating member 272, the insulating member 273, and the insulating member 280 are provided in contact with each other. .

[0186] That is, the oxide 230 is composed of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide The oxide 230c is on the oxide 230b. The oxide 230a is under the oxide 230b. By doing so, the structure formed below the oxide 230a can prevent the oxide 230b from being damaged. The diffusion of impurities can be suppressed. As a result, impurities from the structure formed above the oxide 230c are transferred to the oxide 230b. The diffusion of can be suppressed.

[0187] In the transistor 200, the oxide 230 is formed in the channel formation region and its vicinity. The figure shows a structure in which three layers of oxide 230a, oxide 230b, and oxide 230c are stacked. However, the present invention is not limited to this. For example, a single layer of oxide 230b, oxide 230 a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or For example, the oxide 230c may have a two-layer structure. Alternatively, a four-layer laminate structure may be provided.

[0188] The oxide 230 has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the constituent elements are preferably The atomic ratio of element M in the oxide 230b is It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. Oxide 230c is a metal oxide that can be used for oxide 230a or oxide 230b. Things can be used.

[0189] Specifically, the oxide 230a is composed of In:Ga:Zn=1:3:4 [atomic ratio], is a metal with a composition close to that, or 1:1:0.5 [atomic ratio] or a composition close to that The oxide 230b may be In:Ga:Zn=4:2:3[ or a composition of 1:1:1 [atomic ratio] ... In addition, a metal oxide having the following composition may be used as the oxide 230c: In:Ga:Zn= 1:3:4 [atomic ratio] or a composition close to that, In:Ga:Zn=4:2:3 [atomic ratio] In:Ga:Zn=5:1:3 [atomic ratio] or a composition close to that, In:Ga:Zn=10:1:3 [atomic ratio] or a composition in the vicinity thereof, Ga:Zn=2:1 [atomic ratio] or a composition close to that, or Ga:Zn=2:5 [atomic ratio] or a metal oxide having a composition close to that ratio may be used. A specific example of a laminated structure of c is In:Ga:Zn=4:2:3 [atomic ratio] or a composition in the vicinity thereof, and In:Ga:Zn=1:3:4 [atomic ratio] or a composition in the vicinity thereof Layer structure with a nearby composition, In:Ga:Zn=4:2:3 [atomic ratio] or nearby Composition: In:Ga:Zn=5:1:3 [atomic ratio] or a stacked structure with a composition close to that The structure is Ga:Zn=2:1 [atomic ratio] or a composition close to that, and In:Ga:Zn=4 :2:3 [atomic ratio] or a layered structure with a composition close to that, Ga:Zn=2:5 [atomic ratio] In:Ga:Zn=4:2:3 [atomic ratio] or a composition close to that, or Layered structure with a composition close to that, or gallium oxide and In:Ga:Zn=4:2:3 [Atomic ratio] or a laminated structure with a composition in the vicinity thereof. This includes a range of ±30% of the desired atomic ratio.

[0190] The oxide 230b may have crystallinity. For example, the oxide 230b may have crystallinity. (c-axis aligned crystalline oxide semico It is preferable to use a crystalline oxide such as CAAC-OS. has few impurities and defects (such as oxygen vacancies), and has a highly crystalline, dense structure. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode Furthermore, even if a heat treatment is performed, oxygen is not extracted from the oxide 230b. Since the transistor 200 can be easily exposed to high temperatures during the manufacturing process (so-called It is stable against the thermal budget.

[0191] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216 .

[0192] When the conductor 205 functions as a gate electrode, the potential applied to the conductor 205 is The potential applied to the transistor 200 is changed independently of the potential applied to the transistor 260. In particular, when a negative potential is applied to the conductor 205, the threshold voltage (Vth) of the By adding a second gate, the Vth of the transistor 200 can be increased and the off-current can be reduced. Therefore, it is better to apply a negative potential to the conductor 205 than to not apply a negative potential. In this case, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than that when the potential applied to the conductor 260 is 0 V. can.

[0193] As shown in FIG. 14A, the conductor 205 is formed by the conductor 242a of the oxide 230 and the conductor It is preferable that the area be larger than the area that does not overlap with the conductive material 242b. However, the conductor 205 is formed between the oxide 230a and the oxide 230b in the channel width direction of the oxide 230. It is preferable that the oxide 230b extends to the outer region. The conductor 205 and the conductor 260 are insulated from each other on the outer side of the side in the channel width direction. It is preferable that the conductor 205 overlaps with the other conductor 201 via an edge. In the plasma processing in the manufacturing process after the formation of the conductor 205, local charging However, in one embodiment of the present invention, this The conductor 205 is not limited to the above. The conductor 205 is formed between at least the conductor 242a and the conductor 242b. It is sufficient to overlap with the oxide 230 located at the top.

[0194] In addition, with the bottom surface of the insulator 224 as a reference, the oxide 230a and the oxide 230b and the conductive The height of the bottom surface of the conductor 260 in the region where the conductor 260 does not overlap with the oxide 230b is It is preferable that the electrode be disposed at a position lower than the height of the bottom surface.

[0195] Although not shown, the conductor 260 functioning as a gate in the channel width direction is The side and top surfaces of the oxide 230b in the hole formation region are covered with the oxide 230c and the insulator 250. By using a structure in which the conductor 260 is covered, the electric field generated from the conductor 260 is generated in the oxide 230b. Therefore, the on-current of the transistor 200 In this specification, the conductor 260, and a transistor in which the channel forming region is electrically surrounded by the electric field of the conductor 205. This structure is called the surrounded channel (S-channel) structure.

[0196] The conductor 205a is a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride is preferably used. The conductor 205b is made of a material containing tungsten, copper, or aluminum as a main component. It is preferable to use a conductive material that has a high conductivity. Although the conductor 205 is shown as having two layers, it may be a three-layer structure. The above multi-layer structure may also be used.

[0197] Here, the oxide semiconductor, the insulator or conductor located under the oxide semiconductor, and the oxide The insulator or conductor located on the upper layer of the semiconductor is formed by a different film type without exposing it to the atmosphere. By continuously forming the above films, the concentration of impurities (especially hydrogen and water) is reduced, resulting in a substantially high-purity This is preferable because an intrinsic oxide semiconductor film can be formed.

[0198] At least one of the insulator 222, the insulator 272, and the insulator 273 is water or The present invention prevents impurities such as silicon from entering the transistor 200 from the substrate side or from above. Therefore, the insulator 222 and the insulator At least one of the insulators 272 and 273 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, Diffusion of impurities such as atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms It is preferable to use an insulating material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) can be suppressed. It is preferable to use an insulating material that has the function of preventing oxygen from permeating through the insulating material.

[0199] For example, silicon nitride or silicon nitride oxide is used as the insulator 273. 222 and insulator 272 are made of aluminum oxide or hafnium oxide. It is preferable.

[0200] As a result, impurities such as water or hydrogen pass through the insulator 222 and enter the transistor 200 side. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing into the insulator. Diffusion to the substrate side via the edge 222 can be suppressed.

[0201] In addition, impurities such as water or hydrogen are arranged via the insulators 272 and 273. This can prevent diffusion from the insulator 280 or the like that is provided to the transistor 200 side. In this way, the transistor 200 is protected from impurities such as water or hydrogen, and from the diffusion of oxygen. It is preferable to have a structure in which the insulating material 272 and the insulating material 273 have a function of suppressing the heat generation. I wish.

[0202] Here, it is preferable that the insulator 224 in contact with the oxide 230 desorbs oxygen by heating. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulator 224 may be made of silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. This can improve the reliability of the transistor 200.

[0203] Specifically, the insulator 224 is made of an oxide material from which part of the oxygen is released by heating. It is preferable that the oxides that desorb oxygen by heating are those that are determined by thermal desorption spectroscopy (TDS). Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen content The amount of detached child is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 x 1 0 19 molecules / cm 3 More preferably, 2.0 × 10 19 molec ules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 That's all The surface temperature of the film during the TDS analysis was 100°C or higher. The temperature is preferably in the range of 00°C or lower, or 100°C or higher and 400°C or lower.

[0204] The insulator 222 prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 preferably functions as a barrier insulating film that suppresses the It is preferable that the insulator 222 has a lower hydrogen permeability than the insulator 224. By surrounding the insulator 224 and the oxide 230, etc., water or water This can prevent impurities such as silicon from entering the transistor 200.

[0205] Furthermore, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). Preferably, the body 222 has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of impurities and oxygen contained in the insulator 2. 22, it is preferable because it can reduce the diffusion below. This can prevent the oxide 224 from reacting with the oxygen contained in the oxide 230.

[0206] The insulator 222 is made of an oxide of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing an oxide of aluminum and / or hafnium. Examples of oxide-containing insulators include aluminum oxide, hafnium oxide, aluminum and hafnium oxide. It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using a material other than the oxide 230, the insulator 222 is formed by absorbing oxygen from the oxide 230. and the incorporation of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200. It functions as a controlling layer.

[0207] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators, or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0208] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or oxide. Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTi These include so-called high-k materials such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST). The insulator may be a single layer or a multilayer. However, thinning the gate insulator may cause problems such as leakage current. By using a high-k material as an insulator that functions as an insulating layer, This makes it possible to reduce the gate potential during transistor operation.

[0209] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminate structure is not limited to the same material, but may be a laminate structure made of different materials. stomach.

[0210] Also, the oxide 230b and the conductor 242 ( Conductor 242a and conductor 242b) and oxide 243 (oxide 243a and The conductor 242 and the oxide 230b may be arranged in such a manner that they are not in contact with each other. Therefore, the conductor 242 can be prevented from absorbing oxygen from the oxide 230b. This prevents oxidation of the conductor 242, thereby suppressing a decrease in the conductivity of the conductor 242. Therefore, the oxide 243 has a function of suppressing oxidation of the conductor 242. preferable.

[0211] The oxide 230b is formed between the conductor 242, which functions as a source electrode or a drain electrode, and the oxide 230b. By disposing the oxide 243 having the function of suppressing permeation, the conductor 242 and the oxide 2 This is preferable because the electrical resistance between the transistor 30b and the transistor 30a is reduced. The electrical characteristics and reliability of the transistor 200 can be improved. .

[0212] As oxide 243, aluminum, gallium, yttrium, tin, copper, vanadium, Lithium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, Lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium Metal oxides containing one or more elements M selected from the group consisting of ammonium, ammonium, etc. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. It is preferable that the oxide 243 has a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 243. In addition, In- Metal oxides such as M-Zn oxide may also be used. In the oxide, the atomic ratio of element M to In is In the oxide 24, the atomic ratio of element M to In is preferably larger than that of element M. The thickness of the film 3 is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. The oxide 243 is preferably crystalline. When the oxide 230 has the above structure, the release of oxygen from the oxide 230 can be suitably suppressed. The oxide 243 has a crystalline structure such as a hexagonal crystal, which suppresses the release of oxygen from the oxide 230. It may be possible to control it.

[0213] The oxide 243 does not necessarily have to be provided. In that case, the conductor 242 (conductor 24 2a and the conductor 242b) contacts with the oxide 230, the oxygen in the oxide 230 may diffuse into the conductor 242, causing the conductor 242 to oxidize. As a result, there is a high possibility that the conductivity of the conductor 242 will decrease. The diffusion into the conductor 242 is referred to as the absorption of oxygen in the oxide 230 by the conductor 242. It can be replaced.

[0214] In addition, oxygen in the oxide 230 is converted into conductor 242 (conductor 242a and conductor 242b). The diffusion of the oxide 230b between the conductor 242a and the oxide 230b causes the oxide 230b to diffuse into the conductor 242a. A foreign layer may be formed between the oxide 230b and the conductor 242. Since the hetero layer contains a large amount of oxygen, it is presumed that the hetero layer has insulating properties. The three-layer structure of the oxide 230b and the different layer is a three-layer structure consisting of a metal, an insulator, and a semiconductor. It can be considered as MIS (Metal-Insulator-Semiconductor) structure. It is sometimes called a diode junction structure, or a MIS structure. do.

[0215] The different layer is not limited to being formed between the conductor 242 and the oxide 230b. For example, a different layer may be formed between the conductor 242 and the oxide 230c, or between the conductor 24 The field formed between conductor 242 and oxide 230b, and between conductor 242 and oxide 230c. There is a match.

[0216] On the oxide 243, a conductor 242 (conductor) which functions as a source electrode and a drain electrode is formed. The conductive material 242 has a thickness of, for example, The thickness may be 1 nm or more and 50 nm or less, and preferably 2 nm or more and 25 nm or less.

[0217] The conductor 242 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, or nickel. , titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from the group consisting of tungsten and lanthanum, or an alloy containing the above-mentioned metal elements. It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel, or an oxide containing lanthanum and nickel. Tantalum, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. This is preferable because it is a material that maintains conductivity even after being heated.

[0218] The insulator 272 is provided in contact with the upper surface of the conductor 242 and functions as a barrier layer. By adopting this configuration, the excess of the insulator 280 due to the conductor 242 can be reduced. The absorption of oxygen can be suppressed. In addition, by suppressing oxidation of the conductor 242, Therefore, the increase in the contact resistance between the transistor 200 and the wiring can be suppressed. This can provide the transistor 200 with good electrical characteristics and reliability.

[0219] Therefore, it is preferable that the insulator 272 has a function of suppressing the diffusion of oxygen. The insulator 272 preferably has a function of suppressing oxygen diffusion more than the insulator 280. The insulator 272 may be, for example, an oxide of one or both of aluminum and hafnium. The insulator 272 may be, for example, aluminum nitride. An insulator containing ammonium may be used.

[0220] As shown in FIG. 14A, the insulator 272 is formed on a portion of the upper surface of the conductor 242b and the conductor 2 The insulator 272 contacts a part of the upper surface of the conductor 242a and the side surface of the conductor 242b. The insulator 272 is in contact with the side surface of the insulator 242a. In this way, for example, oxygen added to the insulator 280 is absorbed by the conductor 242. This can prevent this from happening.

[0221] The insulator 250 functions as a gate insulator. The insulator 250 is preferably made of silicon oxide, silicon oxynitride, Silicon oxynitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon Silicon, carbon and nitrogen doped silicon oxide, and silicon oxide with vacancies are used In particular, silicon oxide and silicon oxynitride are stable to heat. preferable.

[0222] Similar to the insulator 224, the insulator 250 is formed using an insulator that releases oxygen when heated. It is preferable to use an insulator that releases oxygen when heated as the insulator 250. By providing the oxide 230b in contact with the upper surface of the oxide 230c, the channel forming region of the oxide 230b is effectively As with the insulator 224, the water in the insulator 250 can effectively supply oxygen. Alternatively, it is preferable that the concentration of impurities such as hydrogen is reduced. It is preferable to set the thickness to 1 nm or more and 20 nm or less.

[0223] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable to suppress the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen from the insulator 250 to the conductor 260, In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0224] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant. By making the insulator have a laminated structure of the insulator 250 and the metal oxide, it is possible to make the insulator stable against heat. Therefore, the physical film of the gate insulator can be formed as a laminated structure having a high dielectric constant. It is possible to reduce the gate potential applied during transistor operation while maintaining the thickness. This makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0225] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, and titanium Titanium, tantalum, nickel, germanium, or magnesium A metal oxide containing one or more selected metals can be used. Aluminum oxide, an insulator containing oxides of either or both aluminum and hafnium Hafnium, hafnium oxide, aluminum and oxides containing hafnium (hafnium aluminum) It is preferable to use a laminate.

[0226] Alternatively, the metal oxide may function as a part of the gate. Preferably, the conductive material containing oxygen is provided on the channel formation region side. By providing the conductive material on the channel formation region side, oxygen released from the conductive material is transferred to the channel formation region. This will make it easier for the supply to the region.

[0227] In particular, the metal oxide in which the channel is formed acts as a conductor that functions as a gate. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing indium tin oxide and tungsten oxide may also be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may also be used. By using such a material, the channel is formed. In some cases, hydrogen contained in the metal oxides surrounding the outer insulating layer can be captured. It may be possible to capture hydrogen that is mixed in from the surroundings.

[0228] Although the conductor 260 is shown as a two-layer structure in FIG. 14A, it may be a single-layer structure or a three-layer structure. The above laminated structure may also be used.

[0229] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule ( Conductive material with the function of suppressing the diffusion of impurities such as N2O, NO, NO2, etc., copper atoms, etc. It is preferable to use a material containing at least oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of the metal oxide (metal oxide) or the metal oxides (metal oxides).

[0230] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, and thus the conductor 260a is included in the insulator 250. The oxygen contained in the conductive material 260b can prevent the conductive material 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitride. It is preferable to use tantalum, ruthenium, or ruthenium oxide.

[0231] The conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as wiring, it is preferable to use a conductive material. It is preferable to use a conductor with a high resistance for the conductor 260b. For example, tungsten, copper, Alternatively, a conductive material containing aluminum as a main component can be used. 0b may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. The structure may also be used.

[0232] <Metal oxides> The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0233] The metal oxide preferably contains at least indium or zinc. In addition to these, gallium, yttrium, It is preferable that the material contains tin, etc. Also, boron, titanium, iron, nickel, germanium, etc. Smoke, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum Even if it contains one or more of the following: iron, tungsten, magnesium, etc. good.

[0234] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. (Element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium , boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum , cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. In particular, the element M is aluminum. , gallium, yttrium, or tin may be used.

[0235] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met). It may also be called hydroxybenzoxanthate (hydroxybenzoxanthate).

[0236] <Transistor 300> The transistor 300 will be described with reference to FIG. 14B. The transistor 300 is formed on a semiconductor substrate 3 11, a conductor 316 that functions as a gate, an insulator that functions as a gate insulator, and The semiconductor region 313 is made up of a portion of the semiconductor substrate 311, and the source region or The semiconductor device has a low resistance region 314a that functions as a drain region, and a low resistance region 314b. The transistor 300 can be either a p-channel or an n-channel type.

[0237] Here, the transistor 300 shown in FIG. 14B has a semiconductor region 313 where a channel is formed. The semiconductor region 313 (part of the semiconductor substrate 311) has a convex shape. The surface is covered with a conductor 316 via an insulator 315 (not shown). The conductor 316 may be made of a material that adjusts the work function. The transistor 300 is also called a FIN type transistor because it utilizes the protruding portion of the semiconductor substrate 311. In addition, an insulating material that is in contact with the top of the convex portion and functions as a mask for forming the convex portion is In this case, a part of the semiconductor substrate 311 is processed to form a convex portion. However, the SOI substrate may be processed to form a semiconductor film having a convex shape.

[0238] The transistor 300 shown in FIG. 14B is an example, and the structure is not limited to this. Appropriate transistors may be used depending on the structure and driving method.

[0239] <Memory device 420> Next, the memory device 420 shown in FIG. 13 will be described with reference to FIG. 15A. Regarding the transistor 200M included in the memory device 420, A repeated explanation will be omitted.

[0240] In memory device 420, conductor 242a of transistor 200M has capacitance 292 The insulator 271 functions as one of the electrodes, and the insulator 272 and the insulator 273 function as a dielectric. The conductor 242a is overlapped with the conductor 242a with the insulator 272 and the insulator 273 sandwiched therebetween. A conductive material 290 is provided and functions as the other electrode of the capacitor 292. Alternatively, the electrode 292 may be used as the other electrode of the capacitor 292 of the memory device 420. The conductor 290 is electrically connected to the conductor 290 of the adjacent memory device 420. You may do so.

[0241] The conductor 290 is disposed on the upper surface of the conductor 242a with the insulators 272 and 273 sandwiched therebetween. In this case, the capacitor 292 is disposed on the side of the conductor 242a. Since a capacitance larger than the capacitance obtained by the overlapping area of ​​a and the conductor 290 can be obtained, I wish.

[0242] The conductor 424 is electrically connected to the conductor 242b and is located in the lower layer via the conductor 205. The conductor 424 is electrically connected to the conductor 424.

[0243] The dielectric of the capacitor 292 may be silicon nitride, silicon oxide nitride, aluminum oxide, or Also, these materials can be used in layers. When the dielectric of the capacitor 292 is made into a laminated structure, aluminum oxide and silicon nitride are used. A stack of hafnium oxide and silicon oxide can be used. For example, silicon nitride may be laminated on aluminum oxide. Alternatively, aluminum oxide may be laminated on top of silicon nitride.

[0244] In addition, zirconium oxide, which has a higher dielectric constant than the above materials, is used as the dielectric of the capacitor 292. As the dielectric of the capacitor 292, zirconium oxide may be used in a single layer. For example, a stack of zirconium oxide and aluminum oxide may be used. Alternatively, the dielectric of the capacitor 292 may be a three-layer laminate, with the first layer being and a third layer made of zirconium oxide, and a second layer between the first and third layers made of Aluminum oxide may also be used.

[0245] By using zirconium oxide, which has a high dielectric constant, as the dielectric of the capacitance 292, the capacitance 92 can reduce the area occupied by the memory device 420. This is preferable because it reduces the area required for 0 and improves the bit cost.

[0246] The conductor 290 includes the conductor 205, the conductor 242, the conductor 260, and the conductor 424. Materials that can be used for the above can be used.

[0247] In this embodiment, the transistor 200M and the capacitor 292 are connected with the conductor 424 interposed therebetween. In this example, a pair of transistors 200M and a capacitor 2 By arranging 92, the number of conductors 424 electrically connected to the transistor 200M is This reduces the area required for the memory device 420 and reduces the number of bits. This is preferable because it can improve the cost.

[0248] When the insulator 241 is provided on the side of the conductor 424, the conductor 424 is 2b and at least a portion of the upper surface of the second electrode 2c.

[0249] The conductors 424 and 205 are used to form transistors in the memory unit 470. The controller 200T and the memory device 420 can be electrically connected.

[0250] <Modification 1 of Memory Device 420> Next, referring to FIG. 15B, as a modification of the memory device 420, the memory device 420 The memory device 420A includes a transistor 200M and a transistor 20 The capacitor 292A is electrically connected to the transistor 200M. It is provided below.

[0251] In memory device 420A, conductor 242a is formed by oxide 243a, oxide 230b, and oxide The insulating layer 230a, the insulating layer 224, and the insulating layer 222 are disposed in openings formed in the insulating layer 230a, the insulating layer 224, and the insulating layer 222. The bottom of the opening is electrically connected to the conductor 205. The conductor 205 is electrically connected to the capacitor 292A. To be continued.

[0252] The capacitor 292A has a conductor 294 that functions as one of the electrodes and an insulator that functions as a dielectric. The conductor 295 functions as the other electrode, and the conductor 297 functions as the other electrode. The conductor 297 overlaps with the conductor 294, sandwiching the conductor 295 therebetween. Connect emotionally.

[0253] The conductor 294 is located at the bottom of an opening formed in an insulator 298 provided on an insulator 296. and the side surface of the insulator 295, and the insulator 298 and the conductor 294 are provided so as to cover the insulator 298 and the conductor 294. The conductor 297 is provided so as to be embedded in a recess of the insulator 295. can be done.

[0254] In addition, a conductor 299 is provided so as to be embedded in the insulator 296. The conductor 299 is electrically connected to the adjacent memory device 420. It may be electrically connected to the conductor 294 of A.

[0255] The conductor 297 is sandwiched between the insulator 295 and is connected not only to the upper surface of the conductor 294 but also to the conductor 29 4. At this time, the capacitor 292A is formed by overlapping the conductor 294 and the conductor 297. This is preferable because it provides a larger capacity than that obtainable with a smaller area.

[0256] The insulator 295, which functions as a dielectric for the capacitance 292A, is made of silicon nitride, silicon oxide nitride, or the like. The following can be used: aluminum oxide, hafnium oxide, etc. When the insulator 295 has a laminated structure, aluminum oxide can be used. The stack of hafnium and silicon nitride, and the stack of hafnium oxide and silicon oxide can be used. Here, the top and bottom of the stack is not limited. For example, silicon nitride can be stacked on aluminum oxide. Alternatively, aluminum oxide may be laminated on silicon nitride.

[0257] In addition, zirconium oxide, which has a higher dielectric constant than the above materials, is used as the insulator 295. The insulator 295 may be made of zirconium oxide in a single layer or as a part of a laminate. For example, a stack of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 295 may be a three-layer laminate, with the first and third layers being Zirconium oxide is used, and aluminum oxide is used as the second layer between the first and third layers. It may be used.

[0258] By using zirconium oxide with a high dielectric constant as the insulator 295, the capacitance is 292A. Therefore, the area occupied by the memory device 420A can be reduced. This is preferable because it can reduce the area required for A and improve the bit cost.

[0259] In addition, the conductor 297, the conductor 294, and the conductor 299 include the conductor 205, the conductor 242, the conductor 260, the conductor 424, etc. do.

[0260] The insulator 298 includes the insulator 214, the insulator 216, the insulator 224, and the insulator Materials that can be used for 280 etc. can be used.

[0261] <Modification 2 of Memory Device 420> Next, as a modification of the memory device 420, the memory device 420 will be described with reference to FIG. 15C. The memory device 420B includes a transistor 200M and a transistor 20 The capacitor 292B is electrically connected to the transistor 200M. It is provided above.

[0262] The capacitor 292B has a conductor 276 that functions as one of the electrodes and an insulator that functions as a dielectric. The conductor 277 functions as the other electrode, and the conductor 278 functions as the other electrode. 277 is sandwiched between the conductor 276 and overlapped therewith.

[0263] An insulator 275 is provided on the insulator 282, and the conductor 276 is connected to the insulator 275, the insulator 28 2, the bottom and sides of the openings formed in the insulators 280, 273, and 272; The insulator 277 is provided to cover the insulator 282 and the conductor 276. The conductor 278 is arranged so as to overlap the conductor 276 in the recess of the insulator 277. At least a part of the insulating material 275 is provided on the insulating material 277. The conductor 278 is an electrode of the capacitor 292B of the adjacent memory device 420B. Alternatively, the conductor 278 may be used as a The conductor 278 may be electrically connected to the conductor 278.

[0264] The conductor 278 is sandwiched between the insulator 277 and is connected not only to the upper surface of the conductor 276 but also to the conductor 277. At this time, the capacitor 292B is formed by overlapping the conductor 276 and the conductor 278. This is preferable because it provides a larger capacity than that obtainable with a smaller area.

[0265] In addition, an insulator 279 may be provided so as to fill the recessed portion of the conductor 278 .

[0266] The insulator 277 that functions as the dielectric of the capacitor 292B is silicon nitride, silicon oxide nitride, or the like. The following can be used: aluminum oxide, hafnium oxide, etc. When the insulator 277 has a laminated structure, aluminum oxide can be used. The stack of hafnium and silicon nitride, and the stack of hafnium oxide and silicon oxide can be used. Here, the top and bottom of the stack is not limited. For example, silicon nitride can be stacked on aluminum oxide. Alternatively, aluminum oxide may be laminated on silicon nitride.

[0267] In addition, zirconium oxide, which has a higher dielectric constant than the above materials, is used as the insulator 277. The insulator 277 may be made of zirconium oxide in a single layer or as a part of a laminate. For example, a stack of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 277 may be a three-layer laminate, with the first and third layers being Zirconium oxide is used, and aluminum oxide is used as the second layer between the first and third layers. It may be used.

[0268] By using zirconium oxide with a high dielectric constant as the insulator 277, the capacitance is 292B. Therefore, the area occupied by the memory device 420B can be reduced. This is preferable because it can reduce the area required for B and improve the bit cost.

[0269] The conductor 276 and the conductor 278 are the conductors 205, 242, and Materials that can be used for the conductive material 260, the conductive material 424, etc. can be used.

[0270] In addition, the insulators 275 and 279 may include the insulators 214, 216, and 224, and the material that can be used for the insulator 280, etc. can be used.

[0271] <Connection between memory device 420 and transistor 200T> In the region 422 surrounded by the dashed line in FIG. 13, the memory device 420 includes the conductors 42 4 and is electrically connected to the gate of transistor 200T via conductor 205. However, the present embodiment is not limited to this.

[0272] FIG. 16 shows memory device 420 including conductor 424, conductor 205, conductor 246b, and and as one of the source and drain of transistor 200T via conductor 240b. An example of electrical connection with functional conductor 242b is shown.

[0273] In this way, the memory device 420 and the transistor layer 413 are connected in accordance with the circuit function of the transistor layer 413. It is possible to determine how the transistor 200T is connected.

[0274] FIG. 17 shows a memory unit 470 in a transistor layer 413 having a transistor 200T. and four memory device layers 415 (memory device layer 415_1 to memory device layer 415_4) is shown below.

[0275] The memory device layers 415_1 to 415_4 each include a plurality of memory It has a device 420.

[0276] The memory device 420 is connected to a different memory device via electrical conductor 424 and electrical conductor 205. The device layer 415 includes a memory device 420, and the transistor layer 413 includes a transistor Electrically connect to Transistor 200T.

[0277] The memory unit 470 includes an insulator 211, an insulator 212, an insulator 214, an insulator 287, The insulator 282, the insulator 283, and the insulator 284 seal the insulator. The insulator 274 is provided around the enclosure. A conductor 430 is provided in the insulator 211 and is electrically connected to the element layer 411 .

[0278] An insulator 280 is provided inside the sealing structure. The insulator 280 is made of a material that can be heated to remove oxygen. Alternatively, the insulator 280 has an excess oxygen region.

[0279] The insulators 211, 283, and 284 have a blocking property against hydrogen. In addition, the insulators 214, 282, and The insulator 287 is preferably a material that has the function of capturing or fixing hydrogen. do.

[0280] For example, the material having a high blocking property against hydrogen is silicon nitride or Silicon nitride oxide or silicon oxynitride can be used. Functional materials include aluminum oxide, hafnium oxide, and aluminum and hafnium oxide. Examples include oxides containing hafnium (hafnium aluminate).

[0281] In this specification, the term "barrier property" refers to the function of suppressing the diffusion of a corresponding substance (permeability). Or, the corresponding substance is captured and fixed (gettering). This function is also called "gaming."

[0282] In addition, the insulators 211, 212, 214, 287, 282, and The crystal structure of the material used for the body 283 and the insulator 284 is not particularly limited, but It may have an amorphous or crystalline structure. For example, it may have the ability to capture hydrogen or fix hydrogen. As a material having the function of providing the above-mentioned protection, an amorphous aluminum oxide film is preferably used. High-quality aluminum oxide is more effective at trapping and solidifying hydrogen than highly crystalline aluminum oxide. There may be a lot of clothing to wear.

[0283] Here, the excess oxygen in the insulator 280 is generated by the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280. The following model can be considered for dispersion:

[0284] Hydrogen present in the oxide semiconductor is transferred to other structures via the insulator 280 in contact with the oxide semiconductor. The hydrogen diffusion occurs when excess oxygen in the insulator 280 is absorbed by water in the oxide semiconductor. The hydrogen atom reacts with the hydrogen atom to form an OH bond, which then diffuses through the insulator 280. A material (typically an insulator 282) that has the function of capturing or fixing hydrogen is reached. When it reaches the insulator 282, it reacts with oxygen atoms bonded to atoms (e.g., metal atoms) in the insulator 282. The excess oxygen atoms that had OH bonds are trapped or fixed in the insulator 282. The oxygen atoms are assumed to remain in the insulator 280 as excess oxygen. In the diffusion, excess oxygen in the insulator 280 likely plays a bridging role.

[0285] In order to satisfy the above model, the manufacturing process of the memory device is one of the important factors.

[0286] For example, an insulator 280 having excess oxygen is formed above an oxide semiconductor. The insulator 282 is formed. After that, heat treatment is preferably performed. Specifically, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixture of oxygen and nitrogen The heat treatment is carried out at a temperature of 350°C or higher, preferably 400°C or higher. The heat treatment time is 1 hour or longer. The time is preferably 4 hours or more, and more preferably 8 hours or more.

[0287] By the heat treatment, hydrogen in the oxide semiconductor is oxidized into the insulators 280, 282, and The oxide semiconductor and the insulator 287 can diffuse outward. The absolute amount of hydrogen present in the vicinity of the oxide semiconductor can be reduced.

[0288] After the heat treatment, the insulators 283 and 284 are formed. The insulator 284 is made of a material having a high blocking property against hydrogen. The hydrogen diffused in the semiconductor or the hydrogen present outside is transferred to the inside, specifically, the oxide semiconductor or Alternatively, it is possible to prevent the air from entering the insulator 280 side.

[0289] The above-mentioned heat treatment is performed after the insulator 282 is formed. For example, after forming the transistor layer 413 or after forming the memory After the device layer 415_1 to the memory device layer 415_4 are formed, the above-mentioned heat treatment is performed. In addition, when hydrogen is diffused outward by the heat treatment, a transistor may be used. Similarly, hydrogen is diffused upward or laterally into the memory device layer 413. When heat treatment is performed after forming the memory device layers 15_1 to 415_4, hydrogen is diffused upward or laterally.

[0290] By using the above manufacturing process, the insulator 211 and the insulator 283 are bonded to each other. As a result, the above-mentioned sealing structure is formed.

[0291] As described above, the hydrogen concentration is reduced by using the above structure and manufacturing process. Therefore, a memory device using an oxide semiconductor can be provided. Furthermore, according to one embodiment of the present invention, a recording device having good electrical characteristics can be provided. A storage device can be provided.

[0292] 18A to 18C are diagrams showing different examples of the arrangement of the conductors 424. 18A shows a layout diagram of the memory device 420 as viewed from above. 18A is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 18A, and FIG. 18C is a cross-sectional view of the portion indicated by the dashed line B1-B2 in FIG. 18A is a cross-sectional view of the portion indicated by the dashed line in FIG. In the case where the conductor 205 is provided, the conductor 205 is 424.

[0293] As shown in FIG. 18A, the conductor 424 overlaps with the oxide 230a and the oxide 230b. The oxide 230a and the oxide 230b are also formed outside the oxide 230a. In FIG. 18A, the conductor 424 is located on the B2 side of the oxide 230a and the oxide 230b. However, the present embodiment is not limited to this. 24 may be provided so as to protrude onto the B1 side of the oxide 230a and the oxide 230b. Alternatively, it may be provided so as to protrude onto both the B1 side and the B2 side.

[0294] 18B and 18C show a memory device layer 415_p-1 on top of the memory device layer 415_p-2. 415_p is stacked (p is a natural number between 2 and n). The memory device 420 of the 15_p-1 is connected to the conductor 424 and the conductor 205. This electrically connects to the memory device 420 included in the memory device layer 415_p.

[0295] In FIG. 18B, in the memory device layer 415_p-1, the conductor 424 is The conductor 242 of the memory device layer 415_p-1 and the conductor 20 of the memory device layer 415_p 5. Here, the conductor 424 is connected to the conductor 242 and the oxide 243. , oxide 230b, and memory device layer 415_p on the outer side of oxide 230a on the B2 side. It is also connected to the conductor 205 of -1.

[0296] In FIG. 18C, conductor 424 is made up of conductor 242, oxide 243, oxide 230b, and oxide. The insulating layer 280, the insulating layer 273, and the insulating layer 230a are formed along the B2 side of the insulating layer 230a. 72, the insulator 224, and the opening formed in the insulator 222, and the conductor 205 and the electrical Here, the conductor 424 is electrically connected to the conductor 242 and the oxide 243. 1, the oxide 230b and the oxide 230a are provided along the B2 side of the oxide 230a. 8B, the conductor 242, the oxide 243, the oxide 230b, and the oxide Between the object 230a, the insulator 224, and the B2 side of the insulator 222 and the conductor 424, , an insulator 241 may be formed.

[0297] By providing the conductor 424 in an area that does not overlap with the conductor 242, etc., the memory device 4 20 electrically connects to memory devices 420 provided in different memory device layers 415. The memory device 420 can be connected to the transistor layer 413. It can also be electrically connected to the transistor 200T.

[0298] When the conductor 424 is used as a bit line, the conductor 424 must not overlap with the conductor 242 or the like. By providing the same in a small area, the bit lines of the memory devices 420 adjacent in the B1-B2 direction can be As shown in FIG. 18, the distance between the conductor 424 and the conductor 242 can be increased. The distance between the oxide 230a and the insulator 224 is d1. The distance between the conductors 424 located in the openings formed in the insulator 222 is d2. The distance between adjacent conductors 424 in the B1-B2 direction is d1. By setting a part of the distance to d2, the parasitic capacitance of the conductor 424 can be reduced compared to the case where the distance is set to d2. By reducing the parasitic capacitance of the conductor 424, the capacitance required for the capacitor 292 can be reduced. This is preferable because it can be done easily.

[0299] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible.

[0300] (Fourth embodiment) In this embodiment, a metal oxide film that can be used for the OS transistor described in the above embodiment will be described. CAC-OS (Cloud-Aligned Composite Oxide) xide semiconductor), and CAAC-OS (c-axis al The structure of the ionized crystalline oxide semiconductor This section explains the composition of the system.

[0301] <Metal oxide composition> CAC-OS or CAC-metal oxide is a material that has the function of conductivity in some parts. The material has an insulating function in part and a semiconductor function in the whole. In addition, CAC-OS or CAC-metal oxide is used as the channel of a transistor. When used in the hole formation region, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is the function of preventing the flow of electrons, which act as carriers. The function of switching is achieved by making the insulating function and the switching function ( On / Off function) is given to CAC-OS or CAC-metal oxide In CAC-OS or CAC-metal oxide, By separating the functions, the functionality of both can be maximized.

[0302] Also, CAC-OS or CAC-metal oxide is used in conductive and insulating areas. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a bell. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0303] In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be dispersed in the material:

[0304] In addition, CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxidized de is a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In this configuration, when carriers flow, In the narrow gap component, carriers mainly flow. The component having a wide gap acts complementary to the component having a narrow gap. Carriers also flow into the wide-gap component in conjunction with the component with a wide gap. AC-OS or CAC-metal oxide is placed in the channel formation region of the transistor. When used, the transistor has a high current driving force in the on state, i.e., a large on-current. Furthermore, high field-effect mobility can be obtained.

[0305] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called a matrix composite.

[0306] <Metal oxide structure> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c-axis alignable oxide semiconductor) gned crystalline oxide semiconductor), polycrystalline nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS) amorphous oxide semiconductors) and amorphous oxide semiconductors etc.

[0307] Furthermore, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of crystal structures in oxide semiconductors will be explained with reference to FIG. 19A. FIG. 19A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). FIG. 1 is a diagram illustrating the classification of crystal structures of metal oxides.

[0308] As shown in Figure 19A, IGZO can be broadly divided into Amorphous and Crystal They are classified into Illine and Crystal. Also, among Amorphous, Completely amorphous. Also includes Crystalline. Among them are CAAC (c-axis aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned C Crystal also includes single crystals. Includes stal, and poly crystal.

[0309] The structure within the bold frame in Figure 19A is in the new crystalline phase. This structure is in the boundary area between Amorphous and Crystal. In other words, the energetically unstable Amorphous and Crystal This can be rephrased as a structure that is completely different from ine.

[0310] The crystal structure of the film or substrate was determined by X-ray diffraction (XRD). Here, quartz glass and Crystal XRD spectrum of IGZO (also called crystalline IGZO) with a crystal structure classified as ine The spectra are shown in Figures 19B and 19C. Figure 19B shows quartz glass, and Figure 19C shows crystalline The XRD spectrum of IGZO. Note that the crystalline IGZO shown in Figure 19C is I The composition is n:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the GZO film is 500 nm.

[0311] As shown by the arrows in Figure 19B, the peaks in the XRD spectrum of silica glass are almost symmetrical. On the other hand, as shown by the arrow in Figure 19C, crystalline IGZO has a peak in the XRD spectrum. The asymmetric peaks in the XRD spectrum clearly indicate the presence of crystals. In other words, if the peaks in the XRD spectrum are not symmetrical, it is called Amorphous. It cannot be said that it is us.

[0312] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is the area where multiple nanocrystals are connected. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. Indicates the point where the direction is changing.

[0313] Nanocrystals are basically hexagonal, but they are not limited to regular hexagonal shapes and may be non-regular hexagonal. The distortion may also have lattice arrangements such as pentagons and heptagons. In CAAC-OS, clear grain boundaries (grain boundaries) are observed even near the strain. It is not possible to confirm the grain boundary (also called grain boundary distortion) due to the distortion of the lattice arrangement. This is because the CAAC-OS has a high SiO2 content in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by making the The crystal structure in which grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, trapping carriers and causing transistors. This is likely to cause a decrease in the on-state current of the transistor or a decrease in the field effect mobility. Therefore, CAAC-OS, which does not have clear grain boundaries, is suitable for the semiconductor layer of transistors. It is one of the crystalline oxides with a crystal structure. For example, In-Zn oxide and In-Ga-Zn oxide are preferable. The material is preferable because it can suppress the generation of grain boundaries more effectively than In oxide.

[0314] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. It is noted that indium and element M tend to have a layered structure. It is possible, and when the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn) Also, when indium in the In layer is replaced with element M, (In,M ) layer.

[0315] CAAC-OS is an oxide semiconductor with high crystallinity. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility due to the grain boundaries is unlikely to occur. In addition, the crystallinity of oxide semiconductors can be degraded by the inclusion of impurities and the generation of defects. Therefore, CAAC-OS is an oxide with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors having CAAC-OS are heat-resistant and highly reliable. CAAC-OS can withstand the high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for an OS transistor, the manufacturing process can be automated. This allows for greater flexibility.

[0316] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range (nm or less). There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. It may be difficult to distinguish between the two.

[0317] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. Conductive. A-like OS has voids or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS.

[0318] Oxide semiconductors have a variety of structures, each of which has different properties. Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and nc The compound may have two or more of -OS and CAAC-OS.

[0319] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0320] By using the oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0321] The transistor is preferably formed using an oxide semiconductor with low carrier density. When the carrier density of the conductive film is to be reduced, the impurity concentration in the oxide semiconductor film is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. The low density is referred to as high purity intrinsic or substantially high purity intrinsic.

[0322] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may also be low.

[0323] In addition, it takes a long time for the charges trapped in the trap levels of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. There are cases where this happens.

[0324] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0325] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0326] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, oxide Defect levels are formed in semiconductors. This causes defects in silicon and carbon in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0327] In addition, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor can be reduced. Specifically, it is preferable to use an alkali metal or alkali metal in an oxide semiconductor obtained by SIMS. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 1 6 atoms / cm 3 Do the following:

[0328] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor used in the formation region tends to have normally-on characteristics. It is preferable that the nitrogen content in the conductor is reduced as much as possible. For example, in an oxide semiconductor, The nitrogen concentration in the sample was 5×10 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0329] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, hydrogen in the oxide semiconductor It is preferable that the SIM is reduced as much as possible. The hydrogen concentration obtained by S is 1×10 20 atoms / cm 3 Less than 1x1 0 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than, More preferably, 1 × 10 18 atoms / cm 3 Less than.

[0330] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0331] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible.

[0332] (Embodiment 5) This embodiment mode will be described with reference to an electronic component and an electronic device incorporating the memory device or the like shown in the above embodiment mode. An example of the device is shown below.

[0333] <Electronic components> First, an example of an electronic component incorporating the storage device 10A will be described with reference to FIGS. 20A and 20B. The explanation will be given below.

[0334] FIG. 20A shows an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. 20A shows an electronic component 700 mounted on a semiconductor substrate 11 in a mold 711. The memory device 10A has an element layer 34 stacked on the semiconductor layer 32. In order to show the inside, a part of the electronic component 700 is omitted. The land 712 is electrically connected to the electrode pad 713. The electrode pad 713 is electrically connected to the storage device 10A by a wire 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of components are combined and electrically connected on the printed circuit board 702. This completes the mounting board 704.

[0335] 20B shows a perspective view of the electronic component 730. The electronic component 730 is a SiP (System in Package) in Package) or MCM (Multi Chip Module) The electronic component 730 is mounted on a package substrate 732 (printed circuit board) via an interposer 734. 31 is provided, and a semiconductor device 735 and a plurality of memory devices 1 are mounted on the interposer 731. 0A is provided.

[0336] In the electronic component 730, the memory device 10A is a high bandwidth memory (HBM). The semiconductor device 735 is used as a CP Integrated circuits (semiconductor devices) such as U, GPU, and FPGA can be used.

[0337] The package substrate 732 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be a silicon interposer, a resin interposer, or the like. An interposer or the like can be used.

[0338] The interposer 731 has a plurality of wirings and electrically connects a plurality of integrated circuits with different terminal pitches. The wiring can be provided in a single layer or multiple layers. The interposer 731 supports the integrated circuit provided on the interposer 731 to the package substrate 73. 2. The interposer 731 is sometimes called a "rewiring substrate" or "intermediate substrate." and a through electrode is provided in the package substrate 732, and the through electrode is used to electrically connect the integrated circuit and the package substrate 732. In addition, in silicon interposers, TSV (Transmission Through-Vessel) is used as a through electrode. Through Silicon Via can also be used.

[0339] It is preferable to use a silicon interposer as the interposer 731. Silicon Since an interposer does not require active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring of the silicon interposer is formed by the semiconductor process. This makes it easy to form fine wiring, which is difficult to do with resin interposers.

[0340] In HBM, many wires must be connected to achieve a wide memory bandwidth. Therefore, the interposer that mounts HBM requires fine and high-density wiring. Therefore, a silicon interposer should be used for implementing HBM. is preferred.

[0341] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to be affected by differences in the expansion coefficient between the silicon interposer and the silicon interposer. The silicon interposer has a high level of surface flatness, making it easy to mount the integrated circuit on the silicon interposer and the silicon interposer. In particular, it is possible to mount multiple integrated circuits horizontally on an interposer. In a 2.5D package (2.5-dimensional mounting), silicon interposers are used to arrange the It is preferable to use

[0342] A heat sink (heat sink) may be provided on top of the electronic component 730. If provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, the memory device 10A and the semiconductor device 735 It is preferable to make the heights of the respective electrodes uniform.

[0343] In order to mount the electronic component 730 on another substrate, electrodes 733 are attached to the bottom of the package substrate 732. FIG. 20B shows an example in which the electrode 733 is formed by a solder ball. By providing solder balls in a matrix on the bottom of the cage substrate 732, a BGA (Ball Grid Array mounting can be realized. In addition, the electrodes 733 are formed by conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) implementation can be achieved.

[0344] The electronic component 730 is not limited to BGA and PGA, and may be mounted on other substrates using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ay), LGA (Land Grid Array), QFP (Quad Flat P ackage), QFJ(Quad Flat J-leaded package), Or QFN (Quad Flat Non-leaded package) A packaging method can be used.

[0345] <Electronic equipment> Next, an example of an electronic device equipped with the above electronic component will be described with reference to FIG.

[0346] The robot 7100 is equipped with a light sensor, microphone, camera, speaker, display, Various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezo sensors, optical sensors, The electronic component 730 includes a processor, etc. For example, the electronic component 700 may acquire information by a sensor. It has the function of storing the data.

[0347] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker also has the function of emitting audio signals such as voice and warning sounds. The 7100 analyzes the audio signal input through the microphone and outputs the necessary audio. The robot 7100 can emit audio signals from a speaker. It is possible to communicate with the user using a microphone and speaker. do.

[0348] The camera has a function of capturing images of the surroundings of the robot 7100. The robot 7100 has the function of moving using a moving mechanism. It can capture images, analyze them, and detect whether or not there are any obstacles when moving.

[0349] The flying object 7120 has a propeller, a camera, a battery, etc., and is an autonomous flying object. The electronic component 730 has the function of controlling these peripheral devices.

[0350] For example, image data captured by a camera is stored in the electronic component 700. It can analyze image data and detect the presence or absence of obstacles when moving. The remaining battery capacity is estimated from the change in the battery storage capacity by the electronic component 730. can be done.

[0351] The cleaning robot 7140 has a display on the top surface and multiple cameras on the sides. The cleaning robot has a brush, an operation button, various sensors, etc. The cleaning robot 7140 is equipped with tires, a suction nozzle, etc. The cleaning robot 7140 is self-propelled. It can detect dust and suck it up through a suction port on the bottom.

[0352] For example, the electronic component 730 analyzes the image captured by the camera and detects obstacles such as walls, furniture, or steps. It can determine whether there are any obstacles. In addition, image analysis can be used to detect wires and other objects that are tangled in the brushes. If such an object is detected, the brush can stop rotating.

[0353] The car 7160 has an engine, tires, brakes, a steering system, a camera, etc. For example, the electronics 730 may include navigation information, speed, engine status, gear selection status, To optimize the driving condition of the car 7160 based on data such as the frequency of brake use. For example, image data captured by a camera is stored in the electronic component 700.

[0354] The electronic component 700 and / or the electronic component 730 may be a TV device 7200 (television receiver). device), smartphone 7210, PC (personal computer) 7220, 7230 , can be incorporated into game console 7240, game console 7260, etc.

[0355] For example, the electronic component 730 built into the TV device 7200 functions as an image engine. For example, the electronic component 730 can perform functions such as noise reduction and resolution up-conversion. Which image processing is performed?

[0356] The smartphone 7210 is an example of a mobile information terminal. Electronic components 730 include a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by

[0357] The PC7220 and PC7230 are examples of notebook PCs and desktop PCs, respectively. The keyboard 7232 and the monitor device 7233 are connected to the computer 7230 by wireless or wired means. The game console 7240 is an example of a portable game console. The game console 7260 is a stationary game console. The game machine 7260 is an example of a stationary game machine. 262 is connected to the controller 7262. The controller 7262 is connected to the electronic component 700 and / or the electronic Component 730 may also be incorporated.

[0358] <Various storage devices> Generally, in semiconductor devices such as computers, various memory devices are used depending on the application. Figure 22 shows various storage devices by layer. Fast access speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density. In Figure 22, from the top layer, the registers and The memory embedded in the chip is SRAM (Static Random Access Memory) ory), DRAM, and 3D NAND memory.

[0359] The memory embedded as a register in a CPU or other processing unit is used for temporary storage of calculation results. Therefore, the frequency of access from the processor is high. A high operating speed is required. Also, registers are used to store setting information for the arithmetic processing unit. It also has Noh.

[0360] SRAM is used for caches, for example. Caches are held in main memory. It has the function of duplicating and storing some of the information that is being used. By replicating the data, you can increase the speed at which you can access the data.

[0361] DRAM is used for main memory, for example. Main memory is used for reading data from storage. DRAM has the function of storing programs and data. The recording density of DRAM is approximately 0 .1~0.3Gbit / mm 2 is.

[0362] 3D NAND memory is used for storage, for example. It has the function of storing important data and various programs used by the processing unit. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of the memory device used for storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0363] A memory device according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. In a storage device according to one aspect of the present invention, a hierarchy where a cache is located and a hierarchy where a main memory is located are separated. The storage device can be suitably used as a storage device located in a boundary area 901 including both the hierarchical layers. In addition, the storage device according to one aspect of the present invention has a hierarchy where the main memory is located and a storage. It is suitable for use as a storage device located in a boundary area 902 that includes both the layer where the image data is located and the layer where the image data is located. This can be done.

[0364] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible. [Explanation of symbols]

[0365] A0: bit, A3: bit, B0: check bit, BL_1: bit line, C1: input terminal , C2: Input terminal, C3: Input terminal, C4: Input terminal, C5: Input terminal, C8: Input terminal , C61: capacitor, C71: capacitor, CK1: clock signal, CK4: clock signal, S_C1: control signal, S_C2: control signal, S_C3: control signal, S_C4: control signal, S_C5: control signal, S_C8: control signal, T_A0: input terminal, T_A3: input Terminal, T_B0: Input terminal, T_CK1: Input terminal, T_CK4: Input terminal, WL_N: Word line, WL_1: word line, 10A: memory device, 10B: memory device, 10C: memory device 11: semiconductor substrate; 20: peripheral circuit; 21: row driver; 22: column driver; 23: Switch circuit, 23_A: Switch, 23_C: Switch, 24: Precharge circuit Path, 24_1: transistor, 24_3: transistor, 25: sense amplifier, 25_1 :Transistor, 25_2:Transistor, 25_3:Transistor, 25_4:Transistor 26: element layer, 28_a: transistor, 28_b: transistor, 29: circuit , 30: memory cell array, 31_N: memory cell, 31_1: memory cell, 32_N: Transistor, 32_1: transistor, 33_N: capacitor, 33_1: capacitor , 34: element layer, 34_N: element layer, 34_1: element layer, 34_5: element layer, 39: unit 39_M: unit, 39_1: unit, 40A: sealing layer, 40B: sealing layer, 4 1: Switch circuit, 51: NAND circuit, 51_1: NAND circuit, 51_4: NAND circuit, 52: delay circuit, 52_1: delay circuit, 52_2: delay circuit, 52_ 4: Delay circuit, 53: XOR circuit, 53_1: XOR circuit, 53_3: XOR circuit, 53_4: XOR circuit, 53_7: XOR circuit, 54: Check bit generation circuit, 55: Error - detection circuit, 61: transistor, 64: transistor, 71: transistor, 72: transistor Transistor, 200: Transistor, 200M: Transistor, 200T: Transistor , 205: conductor, 205a: conductor, 205b: conductor, 211: insulator, 212: insulator Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Acid oxides, 230a: oxides, 230b: oxides, 230c: oxides, 240: conductors, 24 0a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator body, 242: conductor, 242a: conductor, 242b: conductor, 243: oxide, 243a : oxide, 243b: oxide, 246: conductor, 246a: conductor, 246b: conductor, 250: insulator, 260: conductor, 260a: conductor, 260b: conductor, 272: insulator body, 273: insulator, 274: insulator, 275: insulator, 276: conductor, 277: insulation body, 278: conductor, 279: insulator, 280: insulator, 282: insulator, 283: insulation body, 284: insulator, 287: insulator, 290: conductor, 292: capacitance, 292A: capacitance , 292B: Capacitor, 294: Conductor, 295: Insulator, 296: Insulator, 297: Conductor , 298: insulator, 299: conductor, 300: transistor, 311: semiconductor substrate, 31 3: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 31 6: conductor, 411: element layer, 413: transistor layer, 413_m: transistor layer, 413_1: transistor layer, 415: memory device layer, 415_n: memory device Layer, 415_p: memory device layer, 415_p-1: memory device layer, 415_1: Memory device layer, 415_4: Memory device layer, 420: Memory device, 420A : memory device, 420B: memory device, 422: area, 424: conductor, 426 : conductor, 428: conductor, 430: conductor, 470: memory unit, 470_m: memory Memory unit, 470_1: Memory unit, 700: Electronic components, 702: Printed circuit board , 704: mounting substrate, 711: mold, 712: land, 713: electrode pad, 714 : Wire, 730: Electronic component, 731: Interposer, 732: Package substrate, 73 3: electrode, 735: semiconductor device, 901: boundary region, 902: boundary region, 7100: robot 7120: Aircraft, 7140: Cleaning robot, 7160: Car, 7200: TV Device, 7210: Smartphone, 7220: PC, 7230: PC, 7232: Keyboard 7233: Monitor device, 7240: Game console, 7260: Game console, 7262: Controller

Claims

1. a semiconductor substrate; first to N-th first element layers (N is a natural number of 2 or more) provided above the semiconductor substrate; and a second element layer provided between the semiconductor substrate and the first to N-th first element layers; each of the first to Nth first element layers includes a plurality of memory cells; The K (K is an integer between 1 and N) first element layers hold check bits; Data is held in the first element layers other than the K first element layer, the second layer of elements includes an error detection circuit; the error detection circuit includes an XOR circuit; the semiconductor substrate has a driving circuit; a channel formation region of a first transistor included in each of the plurality of memory cells and a channel formation region of a second transistor included in the XOR circuit each include a metal oxide; The memory device, wherein the metal oxide is indium oxide.

2. a semiconductor substrate; first to N-th first element layers (N is a natural number of 2 or more) provided above the semiconductor substrate; and a second element layer provided between the semiconductor substrate and the first to N-th first element layers; each of the first to Nth first element layers includes a plurality of memory cells; The K (K is an integer between 1 and N) first element layers hold check bits; Data is held in the first element layers other than the K first element layer, the second element layer includes an error detection circuit and a check bit generation circuit; the error detection circuit includes a first XOR circuit; the check bit generation circuit has a second XOR circuit; the semiconductor substrate has a driving circuit; a channel formation region of a first transistor included in each of the plurality of memory cells, a channel formation region of a second transistor included in the first XOR circuit, and a channel formation region of a third transistor included in the second XOR circuit each contain a metal oxide; The memory device, wherein the metal oxide is indium oxide.

3. In claim 2, The check bit generation circuit has a function of generating the check bits when writing the data to the memory cells.

4. In any one of claims 1 to 3, The error detection circuit has a function of detecting an error in the data by using the check bits when reading the data from the memory cells.

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