Semiconductor device and manufacture method thereof

Abstract

To provide a semiconductor device in which a clip and a metal plating layer serving as an electrode are joined in parallel.SOLUTION: A semiconductor device includes a first electrode, an N-type semiconductor layer on a first electrode, a P-type semiconductor layer on the N-type semiconductor layer, a first insulating layer on the P-type semiconductor layer that surrounds and separates a first region in a planar view, a second electrode on the P-type semiconductor layer, a second insulating layer on the first insulating layer that surrounds and separates the first region in a planar view on the second electrode, a metal plating layer on the second electrode, a solder layer on the metal plating layer, and a clip on the solder layer. The first region is a region where the clip is joined to the metal plating layer.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 describes a Schottky barrier diode that does not cause aluminum cracks. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-100811 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the clip and the metal plated layer serving as the electrode are joined using solder, there is a problem in that the solder is unevenly distributed, causing the clip to be joined at an angle. Therefore, an object of the present disclosure is to provide a semiconductor device in which the clip and the metal plated layer serving as the electrode are joined in parallel.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, in the semiconductor device, the clip and the metal plating layer are bonded to each other at the divided bonding areas. [Effects of the Invention]

[0007] According to the embodiment, the clip and the metal plating layer serving as the electrode can be joined in parallel. [Brief explanation of the drawings]

[0008] [Figure 1]1A and 1B are a top view and an electrical circuit diagram of a related semiconductor device; [Figure 2] FIG. 1 is a cross-sectional view of a related semiconductor device. [Figure 3] FIG. 10 is a cross-sectional view illustrating a problem with a related semiconductor device. [Figure 4] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to a first embodiment; [Figure 5] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view showing a current path of the semiconductor device according to the first embodiment. [Figure 7] 10A and 10B are a top view and a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a current path of a semiconductor device according to a second embodiment. [Figure 9] 11A and 11B are a top view and a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a current path of a semiconductor device according to a third embodiment. [Figure 11] 10 is a graph showing the tendency of loss and VF characteristics according to the first, second and third embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiment Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the invention according to the claims is not limited to the following embodiments. Furthermore, not all of the configurations described in the embodiments are necessarily essential means for solving the problems. For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] (Explanation of related semiconductor device configuration and issues) FIG. 1 is a top view and an electrical circuit diagram of a related semiconductor device. FIG. 2 is a cross-sectional view of the related semiconductor device. FIG. 3 is a cross-sectional view showing the problems of the related semiconductor device. The configuration and problems of the related semiconductor device will be described with reference to FIGS. 1 to 3. The related semiconductor device disclosed herein is, for example, a power diode such as a Schottky barrier diode.

[0011] As shown in Figure 1, the semiconductor device has a rectangular planar shape. An anode, which is a second electrode, is formed on the top surface of the semiconductor device, and a cathode, which is a first electrode, is formed on the back surface. A metal plating layer 101 on the second electrode is surrounded by a second insulating layer 103, which forms a first region in plan view.

[0012] FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1. As shown in FIG. 2, an N-type semiconductor layer 201 is disposed on a first electrode on the back surface. The N-type semiconductor layer 201 is an N-type semiconductor layer formed, for example, of a semiconductor substrate, particularly a silicon substrate. A P-type well layer 203 and a P-type semiconductor layer 205 are disposed on the N-type semiconductor layer 201. The P-type well layer 203 is a region that determines the region of each transistor in an element isolation or CMOS structure. The P-type semiconductor layer 205 is a region that forms a channel. The P-type well layer 203 is doped with a higher concentration of P-type impurities than the P-type semiconductor layer 205. Since transistors are formed in regions other than the diode, the P-type semiconductor layer 205 forms a channel region. In the diode region, which is the semiconductor device of the present disclosure, the P-type semiconductor layer 205 forms a PN junction with the N-type semiconductor layer 201 to form a Schottky barrier diode.

[0013] A second electrode 207 is disposed on the P-type semiconductor layer 205. The second electrode 207 is made of, for example, a metal containing aluminum. A metal plating layer 101, which is OPM (Over Pad Metallization), is disposed on the second electrode 207. The metal plating layer 101 is formed on the second electrode by, for example, electrolytic plating or electroless plating.

[0014] A first insulating layer 209 is disposed on the P-type well layer 203. The first insulating layer 209 is formed of, for example, PSG (Phosphorous Silicate Glass). The first insulating layer 209 is formed around the element to prevent cracks from occurring in the aluminum second electrode 207. In addition, a third insulating layer 211, which is a well formation mask, is disposed on the P-type well layer 203.

[0015] Second electrode 207 is disposed on first insulating layer 209. Second insulating layer 103 is disposed on second electrode 207 and on first insulating layer 209 in plan view. Second insulating layer 103 is formed of, for example, polyimide.

[0016] 3, clip 303 is bonded to this semiconductor device using solder layer 301. At this time, if the first region, which is the region where clip 303 is bonded to metal plating layer 101, is large, solder layer 301 may become biased, and clip 303 may not be positioned parallel to second electrode 207. The semiconductor device of the present disclosure solves this problem.

[0017] (Description of Semiconductor Device According to First Embodiment) Fig. 4 is a top view and a cross-sectional view of the semiconductor device according to the first embodiment. Fig. 5 is a cross-sectional view of the semiconductor device according to the first embodiment. Fig. 6 is a cross-sectional view showing a current path of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment will be described with reference to Figs. 4 to 6.

[0018] FIG. 4A is a top view of the semiconductor device according to the first embodiment, and FIG. 4B is a cross-sectional view of FIG. 4A taken along the line IVB-IVB of FIG. 4A. As shown in FIGS. 4A and 4B, the semiconductor device according to the first embodiment differs from related semiconductor devices in that the metal plating layer 101 is divided by the second insulating layer 103. As shown in FIG. 4A, the second insulating layer 103 divides the first region into a cross shape in a plan view. The division is not limited to a cross, and may have any shape, such as a grid including a cross in a plan view, a circle, or a triangle. By dividing the first region in this manner, the first region to which the clip 303 is bonded is divided into smaller regions, thereby reducing the unevenness of the solder layer 301. Therefore, the clip 303 is arranged parallel to the second electrode 207.

[0019] As shown in FIG. 5, the semiconductor device includes a first electrode 501, which is a cathode. An N-type semiconductor layer 201 is disposed on the first electrode 501. A P-type semiconductor layer 205 is disposed on the N-type semiconductor layer 201. A first insulating layer 209, which surrounds and separates a first region in a planar view, is disposed on the P-type semiconductor layer 205. A second electrode is disposed on the P-type semiconductor layer 205. A second insulating layer 103, which is disposed on the first insulating layer 209, which surrounds and separates the first region in a planar view, is disposed on the second electrode 207. A metal plating layer 101 is disposed on the metal plating layer 101. A clip 303 is disposed on the solder layer 301. Here, the first region is a region where the clip is bonded to the metal plating layer.

[0020] Furthermore, in a plan view, the first insulating layer 209 is disposed below the second insulating layer 103. The second insulating layer 103 may have the same shape as the first insulating layer 209 in a plan view, or may have a larger area than the first insulating layer 209, as shown in FIG. 5. The second insulating layer 103 has a similar shape to the first insulating layer 209 in a plan view. As shown in FIG. 6, even if a crack 601 occurs in the aluminum of the second electrode 207, the first insulating layer 209 acts as a stopper, preventing the crack 601 from spreading. Therefore, overheating does not occur in the current path, and the semiconductor device operates normally.

[0021] In a method for fabricating a semiconductor device, first, a semiconductor substrate is prepared, and a first electrode 501 is formed on the back surface of the semiconductor substrate. Next, an N-type semiconductor layer 201 is formed in the semiconductor substrate. Next, a P-type well layer 203 is formed. The P-type well layer 203 is formed by selectively introducing a high concentration of P-type impurities using a third insulating layer 211 and then diffusing them. Next, a P-type semiconductor layer 205 is formed on the N-type semiconductor layer 201. A first insulating layer 209 is formed on the P-type semiconductor layer 205 on the front surface of the semiconductor substrate, surrounding and separating a first region in a planar view. A second electrode 207 is formed on the first region of the P-type semiconductor layer 205 and on the first insulating layer 209. A second insulating layer 103 is formed on the second electrode 207, surrounding and separating the first region in a planar view, on the first insulating layer 209. A metal plating layer 101 is formed on the second electrode 207. A solder layer 301 is formed on the metal plating layer 101. Finally, a clip 303 is placed on the solder layer 301. Here, the first region is the region where the clip is bonded to the metal plating layer.

[0022] The method for fabricating a semiconductor device according to the present disclosure uses the same materials and steps as related methods for fabricating a semiconductor device, and therefore can provide a semiconductor device in which the clip is arranged parallel to the second electrode without increasing costs.

[0023] (Description of Semiconductor Device According to Second Embodiment) Fig. 7 is a top view and a cross-sectional view of a semiconductor device according to embodiment 2. Fig. 8 is a cross-sectional view showing a current path of the semiconductor device according to embodiment 2. The semiconductor device according to embodiment 2 will be described with reference to Figs. 7 and 8.

[0024] Fig. 7A is a top view of the semiconductor device according to the second embodiment, and Fig. 7B is a cross-sectional view taken along line VIIB-VIIB of Fig. 7A. As shown in Fig. 7A, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that it includes a P-type well layer 203 having a higher concentration of P-type impurities than the P-type semiconductor layer below a first insulating layer 209 that separates it in a plan view.

[0025] The P-type well layer 203 may have the same shape as the first insulating layer 209 in a planar view, or the area of ​​the first insulating layer 209 may be enlarged as shown in Fig. 7. The P-type well layer 203 has a shape similar to that of the first insulating layer 209 in a planar view.

[0026] 8, the above configuration allows the current path to avoid the P-type well layer 203. Therefore, even if a crack 601 occurs, overheating does not occur. In addition, carriers are replenished from the P-type well layer 203, and the VF characteristics (forward voltage characteristics) are reduced and improved.

[0027] (Description of Semiconductor Device According to Third Embodiment) Fig. 9 is a top view and a cross-sectional view of a semiconductor device according to embodiment 3. Fig. 10 is a cross-sectional view showing a current path of the semiconductor device according to embodiment 3. The semiconductor device according to embodiment 3 will be described with reference to Figs. 9 and 10.

[0028] Fig. 9A is a top view of the semiconductor device according to the third embodiment, and Fig. 9B is a cross-sectional view taken along line IXB-IXB of A. As shown in Fig. 9, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that a P-type well layer 203 having a higher concentration of P-type impurities than the P-type semiconductor layer is provided at the end of a first insulating layer 209 that separates them in a plan view.

[0029] The P-type well layer 203 has a shape that follows the outer periphery of the separating first insulating layer 209. Therefore, the P-type well layer 203 has a shape that slightly protrudes from the first insulating layer 209. The P-type well layer 203 has a region that overlaps with the separating first insulating layer 209 in a plan view, but does not exist directly below the center of the separating first insulating layer 209.

[0030] 10, the above configuration allows the current path to avoid the P-type well layer 203. Therefore, even if a crack 601 occurs, overheating does not occur. In addition, carriers are replenished from the P-type well layer, and the VF characteristics are reduced and improved.

[0031] (Comparison of characteristics of semiconductor devices according to first, second and third embodiments) 11 is a graph showing the tendency of loss and VF characteristics according to the first, second, and third embodiments. The characteristics of the semiconductor devices according to the first, second, and third embodiments will be compared with each other with reference to FIG.

[0032] 11, the VF characteristics of the semiconductor devices according to the second and third embodiments are smaller and improved than that of the semiconductor device according to the first embodiment. This is because the P-type well layer is enlarged, making it easier for carriers to be replenished. The VF characteristics of the semiconductor device according to the third embodiment are larger than those of the semiconductor device according to the second embodiment because the P-type well layer is smaller.

[0033] On the other hand, the semiconductor devices according to the second and third embodiments have larger losses than the first embodiment. This is also because the P-type well layer is enlarged, making it easier for carriers to be replenished. The reason why the semiconductor device according to the third embodiment has smaller losses than the semiconductor device according to the second embodiment is because the P-type well layer is smaller. There is a trade-off between the VF characteristics and losses, and the structure of the semiconductor device is determined depending on the required characteristics of the semiconductor device.

[0034] For example, the semiconductor device according to the above embodiments may be configured such that the conductivity types (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. are reversed. Therefore, when one of the n-type and p-type conductivity types is a first conductivity type and the other conductivity type is a second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0035] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0036] 101 metal plating layer, 103 second insulating layer, 201 N-type semiconductor layer, 203 P-type well layer, 205 P-type semiconductor layer, 207 second electrode, 209 first insulating layer, 301 solder layer, 303 clip, 501 first electrode, 601 crack

Claims

1. A first electrode; an N-type semiconductor layer on the first electrode; a P-type semiconductor layer on the N-type semiconductor layer; a first insulating layer on the P-type semiconductor layer that surrounds and divides a first region in a plan view; a second electrode on the P-type semiconductor layer; a second insulating layer on the first insulating layer that surrounds and divides the first region in a plan view on the second electrode; a metal plating layer on the second electrode; a solder layer on the metal plating layer; a clip on the solder layer; The first region is a region where the clip is bonded to the metal plating layer.

2. The semiconductor device according to claim 1 , wherein the sections are in a lattice pattern in a plan view.

3. 2. The semiconductor device according to claim 1, further comprising a P-type well layer having a higher concentration of P-type impurities than said P-type semiconductor layer, below said first insulating layer that divides said semiconductor layer in plan view.

4. 2. The semiconductor device according to claim 1, further comprising a P-type well layer having a higher concentration of P-type impurities than said P-type semiconductor layer at an end of said first insulating layer that divides said semiconductor layer in a plan view.

5. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a power diode.

6. 2. The semiconductor device according to claim 1, wherein said first insulating layer is made of PSG (Phosphorus Silicate Glass).

7. 2. The semiconductor device according to claim 1, wherein said second insulating layer is made of polyimide.

8. The semiconductor device according to claim 1 , wherein said second electrode includes aluminum.

9. The semiconductor device according to claim 1 , wherein the N-type semiconductor layer and the P-type semiconductor layer contain silicon.

10. forming a first electrode on a rear surface of a semiconductor substrate; forming an N-type semiconductor layer in the semiconductor substrate; forming a P-type semiconductor layer on the N-type semiconductor layer; forming a first insulating layer on the P-type semiconductor layer on the surface of the semiconductor substrate so as to surround and separate a first region in a plan view; forming a second electrode on the first region of the P-type semiconductor layer and on the first insulating layer; forming a second insulating layer on the first insulating layer that surrounds and divides the first region on the second electrode in a plan view; forming a metal plating layer on the second electrode; forming a solder layer on the metal plating layer; A method for manufacturing a semiconductor device, comprising: placing a clip on the solder layer; The method for manufacturing a semiconductor device, wherein the first region is a region where the clip is bonded to the metal plating layer.

11. The method for manufacturing a semiconductor device according to claim 10 , wherein the sections are in a lattice pattern.

12. 11. The method for manufacturing a semiconductor device according to claim 10, further comprising providing a P-type well layer having a higher concentration of P-type impurities than said P-type semiconductor layer below said first insulating layer that divides said semiconductor layer in plan view.

13. 11. The method for manufacturing a semiconductor device according to claim 10, further comprising providing a P-type well layer having a higher concentration of P-type impurities than said P-type semiconductor layer at an end of said first insulating layer that divides said semiconductor layer in a plan view.

14. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is a power diode.

15. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the first insulating layer is made of PSG (Phosphorus Silicate Glass).

Images