Memory network processor

Abstract

To provide a multiprocessor system having processing elements, interspersed memories, and primary and secondary interconnection networks optimized for high performance and low power consumption.SOLUTION: In a secondary interconnection network, a plurality of message routing nodes are arranged in an interspersed manner with a plurality of processors. A given message routing node may receive a message from other message nodes and relay the received message to a destination message routing node using a relative offset included in the message. The relative offset may specify the number of message nodes from the message node initiating the message to the destination message node.SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) Inventors are Michael B. Doerr, Carl S. Dobbs, and Mich ael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Ary a, John Mark Beardslee, and David A. Gibson "Memory-Network Processor with Progr Memory with programmable optimizations U.S. Patent No. 9,430,369, entitled "Network Processor" No. 6,399,423, filed Dec. 1, 2002, which is incorporated herein by reference in its entirety as if fully set forth herein. can be.

[0002] Inventors are Michael B. Doerr, Carl S. Dobbs, and Mich ael B. Solka, Michael R. Trocino, and David A. Gibson, "Multiprocessor fabric hav ing configurable communication that is s selectively disabled for secure processing U.S. Patent No. 6,399,444 entitled "Selectively Disabled Multiprocessor Configuration for Secure Processing" The specification of U.S. Pat. No. 9,424,441 is incorporated herein by reference in its entirety as set forth herein. The entirety of which is incorporated herein by reference.

[0003] The present invention relates to a multi-processor system, and more particularly to the operation and and improved implementation. [Background technology]

[0004] The primary goal of a generic hardware system is to The goal is to achieve application-specific (non-programmable) hardware performance. Historically, these two concepts have been polar opposites. It is a fixed hardware solution that performs specific functions in an efficient manner. is typically the energy per function or per one or more operations Regarding the cost of the product, as well as the functionality per area (circuitry) that may be related to the cost of the product. The cost of a chip product is determined by many factors, including die area and final package. Costs should also consider the entire ecosystem for developing a product. This ecosystem cost is incurred by tying a specific application to a specific hardware solution. The time to convert, the specific hardware solutions required to configure the entire system Unique hardware solutions with a number of customizable communication and memory structures The time it takes to integrate all of the The solution supports a wide range of unique hardware solutions with custom interconnects. porting, resulting in very large area requirements on a single chip die Historically, this process has been inefficient in terms of area, energy, and time to market. It has provided an efficient solution.

[0005] When you think about the world of programmability and the concept of target hardware, Market or situation in terms of hardware architecture and software development style is a general-purpose processor offered by Intel, AMD, and ARM. Purpose Processor (GPP), available from NVIDIA and AMD Graphical Processing Unit (G PU), from Texas Instruments and Analog Devices The resulting digital signal processor ssor, DSP), FPGA (Field Programmable Gate Array (FPGA) from Xilinx, Altera, etc. d Programmable Gate Array), Cavium and Tile Multi-core architectures / many-core processors derived from RA, as well as Application Specific Integrated Circuits ASIC (Advanced Semiconductor Device) or System On Chip (System On Chip) Chip, SoC).

[0006] GPP is for general purpose processing, i.e., old but validated, over 40 years old. Based on a hardware architecture that is conceived as a jack-of-all-trades, The general purpose of GPP is to support operating systems (e.g., Windows ws and Linux (registered trademark) to provide a user interface interface, UI), and high-performance applications such as MS Word, Excel, email, etc. The main challenge is running applications that are highly interactive and UI intensive. The hardware characteristics that affect it are multi-level caches, complex hardware memory, The GPP consists of a memory management unit, a large bus, and a large clock control structure. dissipates a lot of power to accomplish these tasks. Therefore, the goal is to create the simplest software programming model. This model assumes that the user is developing a single thread of execution that runs sequentially or serially. Parallel processing, or multiple hardware threads (more than about four) When you introduce threads (many threads), the ability to program efficiently becomes much more difficult. This is basically the architecture to support parallel thread operation. The fact that it was not developed and as a result the hardware architecture is This is due to the fact that it requires a tremendous amount of overhead and complexity to The software programming model supports the provision of multiple software threads. To support this, API or language extensions must be introduced. These extensions are complex and Unfortunately, current GPP hardware architectures do not support such This requires a certain level of complexity.

[0007] At a high level, C, C++, Fortran have been used for many years on all the supercomputers in the world. The API, which has been widely used along with ran, has been in the industry since the early 1990s. MPI (Message Passing Interface), a world standard MPI is a very simple and well-understood API. The MPI API is an API that does not restrict the hardware implementation. This allows for the specification of software threads and communication in an MPI AP independent manner. I am using OpenMP, Coarray Fortran, OpenCL, etc., as well as Imagine Unlike other languages / APIs that inherently specify the underlying hardware model that is being defined, This therefore limits the flexibility of interpretation and causes forward compatibility problems. When using these other languages / APIs, the programmer must be aware of every new hardware You will need to rewrite the program for the hardware platform.

[0008] GPUs were historically developed to process and target data displays. The architecture is determined by the out-of-core (external) memory model requirements and the in-core memory model requirements of the PU. The off-core memory is a GPU memory for GPP. The GPU then gets the data and runs it through the pipeline. It operates on the data in a linear fashion and then places the data back into the GPU's external memory space. From here, the data can be sent to a display device or the GPP can be used for general processing. Move data out of the GPU memory space for further use / storage in subsequent operations The hardware is inefficient due to (1) the need to support out-of-core hardware constraints; (2) the support needed to move data around to Deeply pipelined SIM that is constrained to process data in a closed pipeline This is due to the limited internal core memory structure similar to that of a D machine. High power usage due to inefficient hardware used for · The programming model is extremely hardware-centric, using OpenCL, CUDA, etc. Therefore, it is complex to achieve efficiency, not very portable, and requires new When migrating to a hardware target platform, the code needs to be rewritten and restructured. It must be accomplished.

[0009] DSPs use instruction sets that are reduced and targeted for general signal processing. DSP can be thought of as a GPP, which is a big brother / sister of GPP. It has the drawbacks of having a large memory footprint, MMU, and bus overhead. Practically any high throughput processing function, such as bo decoding or motion estimation, is typically ASICs with limited capabilities, supporting only a limited set of specific standards on the market The programming model is a single hardware thread. Similar to GPP when targeting signal processing instructions, but in execution unit hardware. Because of this approach, hand assembly of the function is required to achieve any high efficiency. requires the use of required or proprietary software libraries. When creating a multi-parallel DSP architecture similar to the parallel GPP, the problem becomes even more serious. It gets worse.

[0010] FPGAs allow functions to be defined at the bit level, and are programmable wired structures. This is a completely different hardware approach where communication between logic functions is achieved by This hardware approach introduces tremendous overhead and complexity. This has led to the development of hardware programming languages ​​such as Verilog or VHDL. Programmable wiring and programmable logic allow efficient programming. ,Timing similar to what is required in ASIC / SOC but with structured wired configuration The compilation process is much more complex due to the introduction of a programming convergence bottleneck. The power dissipation and performance throughput for a specific function are calculated by the FPGA. Performing exactly one function at a time, and nothing else. When compared, it is clear that it is much better than GPP or GPU. However, if you try to implement all of the capabilities of GPP in an FPGA, the FPGA will It is clear that it is far inferior to PP. The difficulties of FPGA programming are obvious (e.g. timing closure). It's not really "programming", but rather, logical / hardware design, and VHD L / Verilog is a logic / hardware design language, not a programming language. stomach.

[0011] Almost all multi-core / many-core architectures From a hardware perspective, the core processor, cache, MMU, bus, and all It employs related logic and duplicates these on the die along with their surrounding communication buses / fabrication. Examples of multi-core architectures are IBM's Cell, Intel and and AMD quad-core and N multi-core, Cavium and Tilera products, Some custom SoCs, etc. Additionally, multi-core architectures are used to achieve The power savings achieved are largely insignificant. This result is indicative of the multi-core approach. This is derived from the fact that it is simply a replacement for the GPU approach. The only real power savings in the ChipCore architecture is the slowing down of some IO drivers. These drivers are now on the chip, whereas the core was previously on a separate chip. This is no longer necessary as the processors are connected by a communication bus on the same processor. The assembly method does not save much energy. Second, software programming The model is not an improvement over the GPP discussed above.

[0012] The list of problems identified by other approaches is provided by system developers in specific markets. but depends on custom chips with unique GPP, DSP, and ASIC accelerators This is why we combine these to form a system on a chip (SoC). To balance cost and expense, programmability is provided where necessary, and specific However, nowadays, software programming is required to provide ASIC performance. The programming model is more sophisticated than that discussed under the programmable hardware solution above. Additionally, SoCs lack the flexibility associated with fully programmable solutions. This can result in a loss of flexibility.

[0013] The common thread between all of these programmable solutions is that they represent the leading solutions on the market today. The software programming model often dictates the execution model and underlying hardware. Instead of becoming hardware independent, the hardware architecture is The focus is on extrapolating to support applications more efficiently. .

[0014] OpenCL is an ANSI C programming language with some limitations and additions. OpenCL supports writing kernels using a programming language. Recursion, bit fields, variable length arrays, and the use of standard header fields are not permitted. The language supports parallelism, synchronization, and work items / operations with vector types and vector operations. It has been extended to support functions for working with groups. Application Programming Interface ing interface, API) to define the platform, and then Controlling the platform. OpenCL is a core-level, task-based parallel processing and supporting parallel computing using data-driven parallelism.

[0015] Software applications for parallel execution on multi-processor systems Prior art approaches to developing parallel programs generally compromise between ease of development and efficiency of parallel execution. In other words, the development process is generally easier for programmers. The more the resulting executable program runs on the hardware, the better it will perform. It generally requires a lot more effort from the programmer to make it run more efficiently. Efforts must be made to improve the program to avoid inefficient processing. It is necessary to design it in a way that makes use of the efficiency-enhancing features of the target hardware. That was the truth. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] U.S. Patent No. 9,430,369 [Patent Document 2] U.S. Patent No. 9,424,441 Summary of the Invention [Problem to be solved by the invention]

[0017] Therefore, it facilitates software description from an application and system level perspective. It is easy to understand and targets the execution model and the underlying hardware architecture. Hardware programming model and later software programming model Improved systems and methods for promoting use are desirable. Improvements also provide mechanisms for efficient and programmable implementation of applications. MPI (Message Passing Interface) is a standard A standardized, language-independent, extensible, and portable message-passing communication protocol API The MPI API uses language-specific syntax (binding) in a language-independent way (no between a pair of processes (mapped to a node / server / computer instance) It is intended to provide virtual topology, synchronization, and communication functionality. MPI API standard Point-to-point and collective / broadcast communication with various prescribable behaviors Support for sending / receiving operations and synchronizing processes It specifies the core syntax and semantics of library routines that are not limited to MPI. Today, it is the dominant model used in high performance computing. An even greater advance in achieving higher performance per watt of dissipation is in dense communication. Many processing elements, distributed high-speed memory, and a more efficient way of dividing the system into a hierarchy of modules. This is possible with more sophisticated software development tools. Tasks assigned to the management elements, their supporting memory, and dynamically configurable interconnects There are flexible communication paths across the network. [Means for solving the problem]

[0018] Various embodiments for a multiprocessor integrated circuit including multiple message nodes Roughly speaking, multiple message nodes are included in a multiprocessor. The message nodes are connected in a scattered array across multiple processors. A message node receives a first message that includes a payload and routing information. Based on the routing information and multiprocessor operation information, multiple messages are The message node is configured to select a different message node from the message node. The node also calculates routing information for the first message based on the different message nodes. Modify it to generate a second message and send the second message to a different message node. It is configured to send [Brief explanation of the drawings]

[0019] [Figure 1] 1 depicts an embodiment of a multi-processor array. [Figure 2] 1 illustrates one embodiment of a data path for a PE. [Figure 3] FIG. 2 is a block diagram of an embodiment of an instruction decoder. [Figure 4] FIG. 2 is a block diagram illustrating an embodiment of an address generator. [Figure 5] FIG. 1 is a configuration diagram comparing programming models. [Figure 6] 1 illustrates a table depicting the testing of predicate flags. [Figure 7] Three tables illustrating different conditional commands are shown. [Figure 8] Illustrates a conditional block instruction. [Figure 9] Describes data path logic circuits. [Figure 10] FIG. 2 is a block diagram illustrating the active logic for turbo instructions. [Figure 11] FIG. 1 is a block diagram illustrating the active logic for half-turbo instructions. [Figure 12] FIG. 1 is a block diagram illustrating the active logic for the box plus instruction. [Figure 13] FIG. 10 is a block diagram illustrating the active logic for the Max* instruction. [Figure 14] FIG. 10 is a block diagram illustrating the active logic for another Max* instruction. [Figure 15] Draw a logical overview of a message bus in a multiprocessor array. [Figure 16] 1 is a table depicting information to be programmed as part of sending a message on a message bus. [Figure 17] This is a block diagram depicting the general interface of a message bus node. [Figure 18] FIG. 1 is a block diagram illustrating the internal components of a message bus node. [Figure 19] FIG. 1 is a block diagram illustrating one embodiment of a message bus network. [Figure 20] FIG. 1 is a block diagram depicting the HyperOp data path. [Figure 21] FIG. 1 is a block diagram illustrating a programming model. [Figure 22] 1 depicts a flow diagram illustrating an embodiment of a method for operating a message node. DETAILED DESCRIPTION OF THE INVENTION

[0020] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof The embodiments are shown by way of example in the drawings and will be described in detail herein. The drawings and detailed description of the embodiments are not intended to limit the disclosure to the particular forms illustrated. Rather, the present invention is defined by the appended claims. All modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure are intended to be included herein. It should be understood that the headings used herein are for organizational purposes only. These terms are for illustrative purposes only and are not intended to limit the scope of the present application. When used, the word "may" has an obligatory meaning (i.e. It does not mean "must" but "allow" (i.e., Similarly, the word "include" is used to mean "to have the possibility of "," "including," and "includes" mean, but are not limited to, This means that it is not.

[0021] The flow charts are provided to illustrate exemplary embodiments and are not intended to be limiting unless the specific steps illustrated are within the scope of the present disclosure. The illustration is not intended to be limiting. In various embodiments, the method elements shown may be Some of the elements may be performed simultaneously, may be performed in a different order than shown, or Additional method elements may also be performed as desired.

[0022] Perform one or more tasks for various units, circuits, or other components. In such a context, the term "configured to" is sometimes used. "Constructed to" means "having circuitry" that performs one or more tasks during operation. It is a comprehensive description of the structure in general terms. Therefore, the unit / circuit / composition An element can be configured to perform a task even when it is not currently active. Generally, the circuit forming the structure corresponding to "configured to" is a hardware circuit. Similarly, various units / circuits / components may be referred to as , may be described as performing one or more tasks. Such descriptions may be used in conjunction with " The phrase "configured to perform one or more tasks" should be interpreted as including the phrase "configured to perform one or more tasks." Describing a unit / circuit / component configured to perform a function is a It is clear that the interpretation of Section 112, paragraph 6 of the U.S. Patent Act is cited with respect to units / circuits / components. More generally, the description of any element may be preceded by the term "means for." "Means for" or "Steps for" are specifically stated. Unless otherwise stated, the interpretation of 35 U.S.C. 112, paragraph 6, regarding that element may be relied upon. It is not explicitly intended.

[0023] Detailed Description of the Embodiments Referring to FIG. 1, one embodiment of a multi-processor system (MPS) is illustrated. In the illustrated embodiment, the MPS 10 comprises multiple processor elements ( processor element (PE) and a processor element (PE) to communicate data and instructions with each other. These interconnected components are called dynamically configurable communicators or dynamically configurable communication elements. Multiple data memory routers that may be exposed r, DMR). As used herein, a PE may also be referred to as a PE node. A DMR is also sometimes called a DMR node.

[0024] Dual / quad processing elements (PEs) and their local auxiliary memory for data (sup A datapath diagram for one embodiment of a porting memory (SM) is shown in FIG. The top left corner of Figure 2 shows the address generator for the data SM (data RAM), and the right Above are the register file and some control for the Data Memory Router (DMR). DMR indicates the primary interconnection network between PEs. A node in a large-scale MU (multi-connection network, PIN) X (multiplexing) is used to connect different data sources to the main input operand registers A and B. , and switch in C. Another large MUX transfers operand data to the arithmetic pipeline. The third large MUX switches the X and Y inputs of the arithmetic processors DP1 and DP0. Pipeline outputs Z1 and Z0 can be switched to datapath D to allow for the register file or device The data RAM is shared with neighboring PEs, and access conflicts are handled by hardware. Control of the pipeline comes from the instruction decode block in Figure 3.

[0025] Referring to the address generator in Figure 4, the programmable arithmetic unit generates the address as To support sophisticated address calculations that may initiate some operations before using The address generator shown in Figure 4 consists of three integer adder units (AGU0, AGU1 and AGU2), general-purpose integer ALU (GALU), and "iterative H / W (hardware)" Hardware and Auto Incrementer box The register contains up to eight indexes with independent base and stride values. Supports nested loops using the GALU and iteration registers. The output multiplexer routes any calculated address to the data R Supports routing to A, B, or D address ports on AM.

[0026] The execution register and predicate flags shown in the center of Figure 2 support conditional execution of instructions. The execution of an instruction depends on the execution state, and the predicate is prior art. If the execution completes after a certain number of clock cycles, conditional execution is unlikely to be beneficial. However, in many cases, critical instructions can be completed in fewer clock cycles. and provide the results needed by the next instruction or multiple instructions. The next instruction in the above example would be faster if it were conditioned to wait for the status bit. The predicate is not just for waiting, but also for selecting and branching. These are some bits that may be used more commonly by conditional instructions. Use the following instructions to set / clear the predicate value:

[0027] In various embodiments, the PEs support two types of instructions: 64-bit and It may support programs that mix 128-bit and shorter instructions, as shown in Figure 5 below. It supports the assembly language programming model shown on the left. It is useful to support older code and easier compilers. The SET instruction supports the "HyperOp" programming model shown on the right side of Figure 5. Longer instructions allow for more precise control of the dual datapath hardware, This is necessary to make the hardware more efficient for signal processing, so that a given It improves performance in terms of power dissipation (Pdiss), however programming is more It needs to be further refined.

[0028] In Figure 2 of the PE architecture, the hardware-assisted scheduling in other architectures is The detailed scheduling of operations within each pipeline (as opposed to parallel processing) is programmed. However, PE instructions are designed for conditional execution. The condition for execution depends on the execution state and the registered value of the predicate. Six predicates appear in pairs, two pairs in the datapath and one pair in the address generator. A single conditional instruction can access a single pair of predicates, but more instructions In some embodiments, the conditional Use execution to optimize PE performance in dual-pipeline or multi-processor IC situations Conditional execution may, in various embodiments, be performed by the algorithm of each application. Based on the flow structure details, the average speed / power ratio (also called "speed / Pdiss ratio") is calculated as There may be improvements.

[0029] In various embodiments, the PEs included in the embodiment of FIG. 1 may include the following features: : ●Two data paths, each capable (per cycle): ○One or two 16x16 multiplications or one 32x16 multiplication One or two 16-bit additions / subtractions, or one 32-bit addition / subtraction 40-bit barrel shift ○32-bit logical operations 40-bit accumulation, two 40-bit accumulators ○ Datapaths can be performed together (per cycle): ○One 32x32 multiplication or multiplication and accumulation operation One 32-bit floating-point add / subtract / multiply Three Address Generation Units , AGU) Three loads: srcA (source A), srcB (source B), srcC (source C) Two loads and one store: srcA, srcB, dstD (destination D) ○8 base registers and 8 index registers ●GP register file ○3 registers accessible as 16 x 32-bit registers or 8 x 64-bit registers 2 x 16-bit registers ●Instruction decoding: 64-bit conventional assembly instructions ○128-bit HyperOp instructions ○IM provides 128 bits / cycle in any 64-bit alignment Iteration Loop Hardware Zero overhead looping Three primary index registers are used to support three levels of nesting. R ○ Auto-increment of four secondary base / index registers Loop buffer Reduce instruction fetch power during one or more inner loops

[0030] Iteration loops built into the design to accommodate repetition of small sections of code This hardware includes an index counter, an increment / decrement logic by processing, testing for completion, and executing software instructions that perform these "overhead" functions. If done properly, this hardware can Eliminates instruction cycles for overhead functions. Directly program the hardware state machine that performs the looping without software instructions. Use the REPEAT command to perform zero-over-zero nesting up to three levels deep. It may provide overhead looping. It manages indexing automatically so that no additional instructions are typically required within the group. This allows multiple arrays to be accessed within a loop without additional instruction overhead. This allows the system to manage and conserve power and provide better performance. In various embodiments, the iterative loop hardware may include: ●8 base registers B0~B7 ○B0 yields the value zero in addressing mode ○B0 is used as the stack pointer (SP relative addressing mode) ●8 index registers I0~I7 ○I0 gives the value zero in addressing mode ○I0 can be used as a temporary register for other AGU arithmetic (this register (The data is called GR0 instead of I0 in the register map.) ● 7 stride registers S1 to S7 ○Sn is used with In or Bn Hardware support for three-level iterative loops ○The primary loop indexes are I1, I2, and I3 4 additional increments for secondary indexes or base registers ○Index registers I4 to I7 ○Base registers B4~B7 ○Increment by stride registers S4 to S7 ○Start address / temporary registers T4~T7

[0031] The repeat loop is controlled by the REPEAT instruction: REPEAT is similar to the previous HyperX generation with the following improvements: ● Primary loop index I1, I2, I3 Up to four base / index registers that are incremented at the end of the loop Option to select the desired format, i.e. I4 / B4, I5 / B5, I6 / B6, I7 / B7. Repeat loop information is loaded into the loop register before the label that specifies the loop instruction. will be done.

[0032] The repeat buffer is an instruction FIFO for holding instructions that comprise a repeat loop. The goal is to reduce instruction fetch power consumption during the most time-consuming sections of code. The allocation of instructions to the buffers is determined at compile time by the HyperX tools. This document is intended only to provide a basic understanding to users. Key features of a repeat buffer may include: • The REPEAT instruction and its label determine the group of instructions. The repeat buffer usage is determined at compile time and is set by a flag. Shown inside. The first instruction of any repeat loop is stored in the repeat buffer for performance and power reasons. Always loaded. • The buffer can hold 64-bit or 128-bit instructions. ●Up to 12 64-bit entries are available. Two 64-bit entries are available for 128-bit instructions. Use the entry. Use the buffer for anything other than buffering the first instruction of a loop To do this, the entire loop must fit into the buffer.

[0033] The iteration hardware stores the primary index (I1-I3) and other associated control registers. In addition to the primary hardware, the AGU provides additional access For the dress calculation, another set of iterations can be automatically managed by the iterative hardware. There are registers. These special registers are: ●B4~B7 - Four additional base registers. ●I4~I7 - Four additional index registers. ●S4~S7 - Four additional stride registers. T4 to T7 - ​​Used to initialize the base or index registers Four additional registers.

[0034] There are four additional adders available to perform additions on these registers. These adders are activated by instructions (INIT and INCR) or by the REPEAT and This can be controlled by the auto-increment feature of the hardware. You can also tie each primary REPEAT operation together using the AUTOINC register, which will be described later. It also performs address addition on one or more index or base registers. It can be carried out.

[0035] Using each adder, each of the loops for any primary index (I1 to I3) is calculated. For each iteration, a given stride (S4~D7) is assigned to the same base number (B4~B7) or can be added to the index of the same number (I4~I7). Whenever the primary index is loaded with a starting value at the beginning of the Load the T register (T4 to T7) with the same number into the INC BASE or INDEX. This allows multiple arrays to be accessed within a loop without additional instruction overhead. This allows the network to be accessed and managed, saving power and providing better performance.

[0036] In various embodiments, the conditional execution may be based on a predicate flag. The tag may include: ●P0~P3: ○ Set by DP test command ○ Set according to DP timing GP0 and GP1 ○Set by AGU test command (example shown in Figure 6) ○ Set according to AGU timing

[0037] Predicate flags are set using instructions from the TEST class that do the following: ● Execute TEST operation Check the resulting conditions ● Set selected predicate flags

[0038] [Table 1]

[0039] A conditional directive specifies a test against a pair of predicate flags, for example: GP0, GP1 - Used by AGU instructions P0, P1 - Used by DP instructions, typically DP0 P2, P3 - Used by DP instructions, typically DP1

[0040] An example of testing the predicate flag is illustrated in Figure 6. In addition, the conditional instructions of the DP, Conditional instructions and program flow instructions are illustrated in FIG.

[0041] An example of a conditional block command is shown in Figure 8. The explanation of the command shown in Figure 8 is a simple explanation of the actual operation. The STARTIF, ELSE, and ENDIF commands can be nested, so There is a condition stack that holds the condition state stored in the STARTIF. pushes a new condition onto the stack, and ELSE pushes the current condition state (top of the stack) Toggle and ENDIF pop the condition stack. The current condition state is STARTI. You may inhibit the actions of F, ELSE, and ENDIF.

[0042] You may execute a Hyper-Op in a variety of ways. Here is an example of a Hyper-Op execution: Examples are shown in Table 3.

[0043] [Table 2] TIFF2025131765000004.tif121170

[0044] The GPn will be ready in the next cycle, so you can use the GTEST instruction to start the GP If the n bit is set, no branch prediction is required. However, if the GPn bit is If a general register is written by MOV, the branch prediction is delayed and the correct Branch prediction is performed. Pn is ready after 5 cycles and therefore does not require branch prediction. If n is the number of instruction cycles between the test instruction and the branch, then the misprediction The cost is 5-n cycles. If the test instruction can be moved forward in the code, In this case, n can be increased and the cost of a misprediction is likely to be zero (0) cycles. can be reduced to

[0045] The predicate is computed using explicit instructions to set the predicate and is modified by other instructions. This often results in the code being scheduled and the associated branch misprediction. Any cost incurred can be significantly reduced. Branch prediction is done statically and branch probabilities are This may be determined at compile time based on industry standard heuristics regarding

[0046] The Hyper-Op mode may allow instructions to be encoded, in which case the data packets Each separate part of the process is controlled by a portion of the instruction encoding. This allows for more direct control of parallel processing. The mat enables parallel processing as depicted in Table 4.

[0047] [Table 3]

[0048] There are restrictions on which HyperOp instructions can run in parallel on DP0 and DP1. Two HyperOp instructions can execute in parallel if they have the same latency. By definition, the DP0 and DP1 slots always execute the same instruction in parallel. (SIMD equivalent). There are a few exceptions: only a single FP instruction can When both DP slots use hardware from both datapaths in their calculations, It can run in either DP slot. Supports SIMD implementations that execute the same instructions. On the other hand, the usage model is such that any two instructions with the same latency can be executed in parallel. Note that this allows for much more flexibility in terms of how the

[0049] The address instruction occurs during the FD pipeline stage, takes one cycle, and results in In this cycle, all load / store instructions are available for use. In an embodiment, the automatic increment and iteration includes reloading to reduce overhead.

[0050] Each DMR supports multi-point sources and multi-point destinations simultaneously. Direct memory access (DMA) Additionally, the complete state of each DMA engine can be captured and stored in memory. This state information may be saved in the DMA buffer and later retrieved to restart the DMA operation if it is interrupted. The ability to save the state of the DMA configuration allows the PE to obtain the entire state of the DMA. It requests that up to 11 DM registers be read in order to These are often internal DMA registers that are exposed to external access for the purpose of capturing state. Ta.

[0051] To save register space, the DMA stores its state in compact structures called descriptors. The PE specifies the start location of this descriptor and and the modified push engine will register the memory starting from the specified memory address. The push engine can write register data to the The DMA engine uses the data transfer mechanism to extend a message from one destination DMR to a second destination DMR. It is part of the

[0052] The push engine steps through each register in the DMA to program it. We already have a state machine that advances the register. We can use this same machine again to advance the register. The read data can then be read out to the adjacent intra-port module. The important part is to push any DMA write stalls to the engine. This is done by tying the DMA function to the Push Engine's busy input signal. This may be done by gating the shutdown.

[0053] A DMA wakeup can be used to signal the PE that it has saved the descriptor. At that point, the PE is free to swap tasks. When the new task is completed, the PE can point to the saved descriptor and DMA operations will resume. Note that routers outside the port must be configured appropriately during task swaps. .

[0054] The accumulator storage is performed by a predetermined shift amount, with an optional post-shift to the right (po In various embodiments, there are the following shift amounts: ●1:To take the average ●8: ●16:ACCH=To store ACC[31:16] ●15:

[0055] These values ​​are stored in the three shift fields used as indirect shift amounts. The three fields are represented in the HyperOp syntax as SHR1, SHR2, and SHR3. The shift value fields SHIFT_CTL1-3 in the PE_CONFIG register are indicated. Refers to...

[0056] Two types of accumulator pairs: one accumulator (AC) from each DP. C2_ACC0, ACC2_ACC1, ACC3_ACC0, ACC3_ACC1), and and SIMD 16-bit data. H_ACC0L, ACC1H_ACC1L, ACC2H_ACC2L, ACC3H_AC C3L). The storage with post-shift of the accumulator pair is done by the bit position number. is the same, but performs an independent shift on each part of the accumulator pair. In the description, the "tmp" designation is used to attempt to clarify the semantics. , not an actual hardware register.

[0057] [Table 4] TIFF2025131765000007.tif85170

[0058] Shifts may also be performed with split stores and split loads. More shift operations are possible with Generally increases hardware power dissipation (Pdiss). The soft hardware design is based on the most desired shift options for a given Pdiss budget. The application code and PE architecture may be selected. By analyzing the structure, the most needed shift options may be determined. In some embodiments, for example, memory is word-addressed instead of byte-addressed. When addressing, the most important thing is to align the bytes to / from a word boundary. It may be necessary to shift

[0059] In some embodiments, additional auxiliary computing units are employed to increase performance. A list of possible auxiliary computing units is depicted in Table 6.

[0060] [Table 5]

[0061] HyperOp instructions—Use static scheduling during the program compilation process Allows independent control of dual data paths. Threads of execution are passed to the compiler. By comparison, modern GPP architectures A compiler for a program places related instructions together in the machine code, but does not schedule them. The fine details of scheduling are handled by the (power-hungry) hardware. Juuling saves a lot of Pdiss at runtime.

[0062] During data transmission, imperfections in the system can result in distortion or degradation of the transmitted signal. Such distortion or degradation of the transmitted signal can result in the data bits having incorrect values ​​at the receiving circuitry. To eliminate such effects, some embodiments is a Forward Error Correction (FEC) code It contains instructions to support encoding and decoding. FEC is It has applications in other areas such as digital communications, and digital recording and playback from storage media. The basic idea is to take any block of input data and send it to the receiver or playback electronics. Blocks with additional parity bits in a way that allows for bit error correction in the circuit. The purpose of this is to encode the encoded block of data and parity bits. The FEC frame is further processed by a modulator and then transmitted to the medium (wired , wirelessly, or in a storage medium).

[0063] At the receiving end, the signal is picked up by an antenna or transducer, amplified, and demodulated. The signal is sampled by an AD converter (A to D converter, ADC). Signals in the medium may be subject to interference, fading, and echoes, and may be transmitted by the receiver. Noise has been added. The output of the ADC is a sequence of digital samples. It takes a sequence of samples, synchronizes them and formats them into an FEC frame. There are various methods for doing this, but these methods are largely irrelevant to the FEC calculation. These methods are not described here. Each bit position has a digital value, sometimes called a soft bit, and is used in digital systems. It is represented by the actual bits of an integer in the system.

[0064] FEC decoding extracts the soft bits in the formatted FEC frame and and outputting the corrected FEC frame. The goal of the FEC decoding algorithm is to decode the parity bits without prior knowledge of how they were generated. The goal is to output the most likely correct data frame. To work properly, a specific FEC decoding scheme (using parity bits for error correction) must be used. It must be coordinated with the FEC coding scheme (parity bit generation).

[0065] Hamming, BCH, and Reed-Solomon codes were used to develop early FECs. The success was achieved by using convolutional codes and serial concatenations of convolutional codes and other codes. On the decoding side, the objective is to decode the received soft bits with noise-induced errors. The goal is to find the block of data that is most likely to be correct, given the is a single-pass algorithm (such as Viterbi) or an iterative algorithm (such as Turbo etc.) can be achieved.

[0066] The FEC calculation is performed by a binary filter according to the sequence of observed values ​​obtained from the sampler. It involves calculating the predicted correctness of two choices for the value of the rebit. The sequence of values ​​that change can be treated as a random variable, so that the mathematics of probability can be applied. The main concern is to determine the specific The transmitted data bit was either 1 or -1. Before making a hard decision, a number of soft decisions can be calculated. These soft decisions have the probability A method for comparing probabilities, including parity bits, may be calculated by comparing , calculate the ratio of conditional probabilities called the likelihood ratio (LR) The logarithm of LR (LLR) is the sum of It is of particular interest because it converts operations and divisions into additions and subtractions, which are then is calculated more quickly and is less likely to overflow or underflow. As a result, the FEC decoding cannot be calculated using the LLR values ​​stored as integers. This can be done.

[0067] The sum of products of log-probabilities is also called the MAX* operator. Add-compare-select (ACS) using the The MAX* operator may be performed in a similar manner. The MAX* operator is used to calculate the logarithmic domain on exponential probabilities. It provides multiply-and-accumulate type operations for mathematical operations in the domain. Write it as (x0+y0,x1+y1).

[0068] In various embodiments, the PE implements functions such as: Z[15:0]=MAX((X[15:0]+Y[15:0]),(X[31:16] +Y[31:16]))+TLU offset

[0069] A slight modification to the operand usage provides a higher throughput regime useful for turbo operation. By providing this, we can achieve a double logarithmic probability multiply-accumulate instruction. This one is Max*(x1 +y0, x0+y1): Max*(x0+y0, x1+y1) This has two consequences.

[0070] In various embodiments, the PE implements functions such as: Z[31:16]=MAX((X[31:16]+Y[15:0]),(X[15:0 ]+Y[31:16]))+TLU offset Z[15:0]=MAX((X[15:0]+Y[15:0]),(X[31:16] +Y[31:16]))+TLU offset

[0071] Another form of MAX* operation produces 32 bits per datapath in the following form: Max*(0,x1+y1)-Max*(x1,y1):Max*(0,x0+y0) -Max*(x0,y0)

[0072] In various embodiments, the PE implements functions such as: Z[31:16]=MAX(0,(X[31:16]+Y[31:16]))+TLU offset-(MAX(X[31:16],Y[31:16]))+TLU offset) Z[15:0]=MAX(0,(X[15:0]+Y[15:0]))+TLU offset Bit-(MAX(X[15:0],Y[15:0])+TLU offset)

[0073] Another instruction is a dual MAX* operation on two operands, with two in each data path. Another instruction may provide the value in the accumulator of the By using an accumulator, you can use MAX* for large groups of numbers. Provides a fast way to obtain the result. The two 16-bit results are the sum of the two accumulators. When both data paths are used, when all input data is available, The accumulators run a MAX* operation on their input data to produce a final result. Symbolically, the equation looks like this: ACC n+1 =Max*(ACC n+1 ,Max*(x1,y1)):ACC n =Max*( ACC n,Max*(x0,y0))

[0074] The following formula may be used to achieve the double accumulation form for the log-probability sum-of-products: ACC n+1 =Max*(ACC n+1 ,x0+y0):ACC n =Max*(ACC n ,x1 +y)

[0075] A corollary of the special hardware for LP instructions is that the "0" index data is stored in the upper A The CC is reminded to swap the "1" index data to the lower ACC. It is preferable if this data can be easily swapped within the data path. In this form, the PE implements the following functions: ACC n+1 =MAX(ACC n+1 ,(X[15:0]+Y[15:+1]))+TLUo Fusset ACC n =MAX(ACC n ,(X[31:16]+Y[31:+16]))+TLUo Fusset

[0076] It is also possible to generate the double sum of quotients in the logarithmic domain. A method that uses subtraction instead of addition to provide: ACC n+1 =Max*(ACC n+1 ,x0-y0):ACC n =Max*(ACC n ,x1 -y1)

[0077] In various embodiments, the PE implements functions such as: ACC n+1 =MAX(ACC n+1 ,(X[15:0]-Y[15:0]))+TLU off set ACC n =MAX(ACC n ,(X[31:16]-Y[31:16]))+TLU off set

[0078] To implement the instructions referenced above, we use dedicated logic circuits as shown in Figures 9 to 14. In some cases, logic may be selectively enabled based on the type of instruction. This allows multiple instructions to be performed using a minimal amount of logic circuitry.

[0079] Within an application running on a PE, or communicating with chip I / O ports The primary phase of MPS is for high-bandwidth, low-latency data transfer between applications. Primary interconnection network k, PIN) and design the interconnection network (interconnection n An IN (Infrastructure Network) is a set of nodes with links connecting them. Most PINs require much more wiring, so it is best to use a single It is not entirely point-to-point capable. PIN is a multi-stage system that uses routers at each node of the network, and the nodes Messages can be routed through PINs, and PIs N is the number of nodes to start, pause, and deliver a message from a source node to a destination node. Enforces the rule: if a message remains open, it is used indefinitely as a data pipe. However, because it is multi-stage, existing messages may be deleted before new messages are sent. The setup of a new message by occupying the link or destination specified by the message. This may block the message delivery, resulting in message delivery not being guaranteed. Some of them use dynamic cut-through and long-distance routing to "jump over" congestion. However, the approach of the present inventors has The idea is to add layers of interconnection, each with a different set of links. PIN node routers can be extended to allow messages to traverse from one layer to another. To do so.

[0080] In a large-scale MPS, it is necessary to manage the system without affecting the efficiency of PIN operation. This may have a lower bandwidth than the PIN in some embodiments. , a secondary interconnection network that may guarantee message delivery This led to the development of the SIN (Society Interconnection Network). Such an interconnection network is shown in Figure 15. As illustrated, a message bus 1500 It contains multiple message bus nodes connected to each other by a fixed connectivity scheme. The bus connects to every accessible register inside the chip, including both PE and DMR locations. Moderate bandwidth, variable latency, and guaranteed delivery to data and memory locations In addition to the method, an I / O controller such as I / O controller 1502 is also provided.

[0081] Not only can you boot, debug, and load data outside of the core array structure, , making virtually every addressable location accessible through MPS equipment For example, a message bus can be used to communicate between all PEs / D MR data and instruction memory locations, internal PE registers, DMR registers (registers access the I / O buses, including their locations, as well as the I / O peripherals attached to the I / O buses. That's fine.

[0082] The message bus may, in some embodiments, be a PE, a development access port (DAP), or a power access port (DAP) 1503, boot control 1504, and It may provide support for multiple simultaneous masters, such as multiple I / O processors. Messages are routed using automatic routing based on the relative positioning of the source and destination. The response is routed over the message bus. The response is similar to the request, using relative location. The error return route is automatically routed using a method that maintains the Use successive locations leading to the source.

[0083] In some embodiments, the message bus comprises two or more independent message structures. If messages from independent constituents try to access the same destination, automatic reconciliation is useful. The outcome of arbitration may be determined by a simple scheme such as a priority structure. The message bus priority structure is based on the two established priorities for accessing the DMR address. It may consider a specific priority, i.e., lowest or highest, and it allows access to all PE addresses. Seth has the lowest priority in PE.

[0084] The message bus supports multiple endpoint message groups to Allows a subset of rays to respond to a single message. Multiple group memberships It may be configured on a single node. In various embodiments, broadcast capabilities are used. It may reach all nodes and many independent groups are available for distribution. It may be Noh.

[0085] In various embodiments, the message bus may enable multiple chip operations. When implementing a multi-die architecture, the relative addresses of destinations may be bridged between chips. In some cases, the message format allows up to 256 characters in the X and Y directions. In other embodiments, the message may be modified to support additional nodes. You can extend the message by adding a table (for example, table 1807) to the By employing a relay technique, any suitable number of message nodes may be supported.

[0086] The message bus allows a processor inside the device to reach any addressable location within the device. This capability allows messages to be passed between processors. and updating the table of values ​​as the algorithm progresses, Manage the behavior of the cell, collect operational statistics, and manage cell security. and general communication of non-time critical information between processors, It allows for a variety of possibilities.

[0087] The message bus is preferably used as an extra layer for PIN routing configuration. It should be noted that the bandwidth may be much less than the For example, in some implementations, the message bus is 10 times slower than the PIN. In some implementations, it may be as much as twice as slow as PIN, while in other implementations it may be only twice as slow. Second, the data delivery latency is the same for messages between the same source and destination pair. There is no concept of programmed route setup and teardown, In this case, the configuration involves setting up a route of known length for the message and Each time you use a device, you cross the same wire to connect two endpoints, resulting in a device This provides predictable latency for data delivery. Relatively short messages are sent from source to destination using routes determined by the generation hardware. If the message is blocked at some point along its path, Wait for other messages in progress to complete, then continue. If only messages are used (no priority delay at the destination), the data by message Delivery may exhibit predictable latency. However, additional message traffic may be required. Traffic can disrupt data delivery and affect the route each subsequent message takes. As a result, arrival times are not guaranteed, so the message bus is It may not be suitable for distributing messages.

[0088] The message bus sends short, low-bandwidth messages to and from any destination within the MPS. These messages are useful for ensuring power-efficient delivery of PIN configuration data. It consumes significant internal resources, potentially ties up the link for an extended period of time, and the data is mostly To prevent the link from interrupting the system, The message bus also requires fast setup and teardown of chip I / O. This simplifies inter-processor management, and in MPS, these Only the processor in the good.

[0089] Although not suitable for timing-critical applications, message buses still offer considerable performance benefits. The bus itself moves one word per clock, and the clock This clock may be the same as the functional core clock, which may have a target frequency of 500 MHz. The message buffer effectively moves 1500 MHz words per second between nodes. The process transfers data and addresses across the bus for each word delivered to the register. It is designed to push and then release the bus for other messages as quickly as possible. So you define the root, identify where to read or write the word, and Required to identify how to return data or state to the requesting node. These non-data words are used in a single transaction. This reduces bus throughput in some applications, limiting the impact of message construction overhead. To achieve this, any number of words can be transmitted in one message, the only restriction being , the words must be contiguous from a single starting address.

[0090] Under normal conditions, access to any normally accessible location inside the MPS equipment is prohibited. This means that any register, memory location, or normal mode address is available. Write a peripheral with a unique address in the parameters accessing that address. Some PE internal registers can be written to or read from the P The contents of PE can be read while E is running, however the value contained It represents a snapshot at the time the read is made and is updated only when the value is requested. Additionally, when a request is generated and a value is sent from the PE or DMR via the message bus, There is a time interval between when the data is read and when the results are delivered back to the requester. The time interval may vary depending on the system and message bus load, as you may have to wait a significant amount of time for results. At almost every clock, some PE internal registers required for operation are may wait too long to access the This effectively stalls the request. Gaps appear in the code that cause these registers to be This may be possible by reading the data, but the PE operates some registers. The message bus messages must be configured to reset these registers to their default low Attempting to read at priority generally results in prolonged message stalls. In the DMR, the access priority is programmable, so the address Making the request wait until there are no other requests pending for the region or access that address immediately and request access to the same area. It can block all other requests that attempt to access the

[0091] Normal mode address locations may include: Read / write access to any DMR data memory location Read / write access to any DMR memory-mapped register Read / write access to any PE instruction memory location Read / write access to PE state and control registers Read / write access to clock control registers ●Breakpoint control except for hardware break insertion PE wake-up control Parity control PE message delivery PE programmer register access Memory and peripherals on the IO bus

[0092] While a program is running, great care must be taken when operating on instruction memory. A block of instructions can be written to memory and As the program runs, new code fragments are added to blocks of code. may be executed without first fully substituting, resulting in unpredictable behavior. The MPS contains a parity bit for each write to memory and The read operation may be configurable to check parity and if an error is detected, However, parity checking is more efficient than not having it. Parity checking in MPS is done by dividing memory with and without parity into separate parts. This means that this is an operating mode that should be used in extreme environments. You can switch between these modes while running the applications that use that memory. It is not wise to do so.

[0093] Access to the clock control is possible under all conditions; however, Changing the state of the lock register is not always wise. While it is operating, especially on a data set that is shared among multiple processors, When the clock control is changed, it is local and not shared with other nodes. may also be accessed to update the clock control at those locations. If you try to change the clock configuration while the algorithm is running, you may need to access the data. There is a high possibility that the timing will be lost.

[0094] When the PE is stopped at a breakpoint, additional access to the message bus is available When the PE is suspended, the program counter stops and a hardware breakpoint is reached. All of the capabilities of normal mode are available and the hardware bootstrap is Rake point insertion capability is additionally available.

[0095] The implementation of breakpoints prevents values ​​from changing while the system is running. , which may lead to unpredictable results, including missed interruptions and unintended interruptions. Therefore, changing a breakpoint most reliably occurs when program execution Becomes effective while stopped.

[0096] When the PE stops at a breakpoint, the internal register access time is improved and the The return value for the processor is still correct. Arbitration for the debug request remains unchanged while there are no higher priority requesters active. This allows the PE's internal state registers to be accessed by the DM system more quickly. On R, after the DMA operation is complete, there are no other accesses competing for the address and the Even low priority requests are fulfilled immediately.

[0097] During boot, a message bus is used to initially load the processor and set the clock and The boot process can then be started by configuring the boot process and security, releasing the PE from reset and starting operation. In operation, the majority of transactions on the message bus have device-wide destinations. It is expected that the load will be generated from the boot processor. This is expected to reduce the overhead of program loading caused by the address.

[0098] One use for the boot controller then is to implement dynamic cells, in this case In this case, it is possible to load a new cell into an already running system. As used and defined herein, a cell is a cell that includes one or more PEs and one or more Part of the application allocated to the DMR. At least one DMR is included in the cell to serve as instruction memory for E. Note that in this case, there is likely to be more activity on the message bus. Again, since the device is already around, arbitration can be simplified and new cells can be added to the array. Load dynamic cells by utilizing larger block transfers. This minimizes the time required to load replacement cells, unlike the initial load. There is a high probability that there will be contention at some point. Dynamic cell loading is a potentially long-running process. Implement dynamic cell loading because it consumes When doing so, the total length of the burst should be taken into consideration.

[0099] One common problem with in-system debuggers is the lack of consistency between the debugging facilities and the functional operation of the system. In some cases, the possibility of interaction is due to the debug When engaging in a task, changes in the behavior of the functional system or even problems can be detected. This may result in error correction or modification when debugging is running. Any access that must be performed must be performed to ensure proper interaction between the functioning system and the parallel debugging facility. Although it can never be completely removed, it is advisable to route debug operations to a separate message bus interface. If mapping into a single instance, this mapping is This will remove all interactions. By selecting deep, the debug only interacts with the system while not being used in any other way. Interact with and do not disrupt the functional access that arises from the functional system. In some embodiments, the priority may be varied between high and low.

[0100] When the processor is at a breakpoint, it generates a request that is delivered to the DMR. This means that the PEs are not processing DMA requests continuously while they are stopped. This means that there is no request in the DMR at all, since the This is because there are no other requests for data, so the PE Split state where requests are immediately satisfied and DMA transactions are debug requests This results in a DMR state that continues to exist before the breakpoint. We support the idea that debugging should not interfere with operation in a processor.

[0101] Before we delve into the details of the bus itself, let's take a look at what a message means in relation to a message bus. In the most general sense, a message is a message sent to its intended recipient. a means to deliver the message to the In particular, a message bus needs a means of passing unique messages through its network. There are several different messages, which we will cover next.

[0102] Message bus nodes can be configured by programming configuration registers inside the node. These registers are used for two channels (A and B) of the message bus. There are two sets of registers. Programming these registers is discussed below. There are several possible message formats. These are categorized as follows: You can: Point-to-point messages - read information from any other single node , or be able to write. Multi-point messages - A single message is used to send a message to an end point node. Allows a user to read or write to a group of Response messages - not generated directly by the user, but used to provide acknowledgment of other messages It is used by the message bus for this purpose. Secure Configuration Message - A message used to configure security for the chip. The form of Ji.

[0103] To send a message, a program stores the basic components of the message in a configuration register. In the processor, the signal must then be programmed for the message to be sent. The gramming components are listed in FIG.

[0104] Use the STATUS register to observe the status of the sent message. In addition to these registers, which directly control the messages being sent, there are also registers that control the message bus. There are several other configuration registers, described later, that are used to control other aspects of the system. The only registers that need to be modified to specify a new message are: Note that the message must be updated before sending it. For example, To send a message to five locations, use the route information in DELTA_OFFSET. Simply update and resend the message using GEN_MSG. Message Format is described more fully below.

[0105] The most common DMA controller that can be used by any master to reach any location within the chip. The basic message is a point-to-point message. As such, this message is targeted to and issued from a single location. Every place in the world has a way to snoop on the data passing through it. Therefore, the information passed between two nodes is sent via a message bus. Only seen from the outside, at this point all point-to-point messages are secure. It is safe to balance the capacity and overhead associated with this message type. A variety of options are available for constructing the message.

[0106] A slave can only receive and process one message at a time, so There is no need to know which node is requesting data access, only the route back to the master is necessary so that a response can be delivered. The return path for responses required to complete a point-to-point message round trip Includes:

[0107] A point-to-point message can be a read request or a write request. A read request can generate a response message containing the requested read data. A write request generates a response indicating the success or failure of the write. Similar to the way that a message in a st or write request balances capacity and performance. Therefore, the response message also reduces overhead at the expense of some loss of flexibility at the master. Minimize the noise.

[0108] One response for each point-to-point read or write request If a message is present and contains multiple data words, it contains multiple response words; As a result, every address sent out will either contain a status to write or data to read. The data in the message body is the same as when the request was sent. The data is returned in order, so that it is quickly removed from the bus when it arrives back to the requesting node. To ensure that the response is removed immediately, the address to be remembered is separated from the MBN. Only one response location can be stored at a time, so two locations can be stored in the return. If more than one MBN is expected and an automatic memory loading mechanism is used, each MBN There can be one outstanding transaction at a time. If you extract all the data, there will be as many outstanding requests as the processor wants. There is a possibility.

[0109] Use the same response message format for all multiple endpoint responses However, these multiple endpoint responses use a single response word in the payload. For example, in a read message, the response is to insert the value of the requested address into or a security error control if a non-valid read is attempted to a secure area. Alternatively, in a write message, the response may include a write command. The value may include a success or failure value indicating whether the task was completed or not.

[0110] Two or more active nodes receive multiple endpoint write messages. These messages are useful for communication within a cell, where the cell uses a message bus structure. It can be instructed which messages it should respond to through a write address. Security may prevent a write from occurring, potentially changing the individual word state. A single write is used for the entire message, rather than for individual word states, as this would cause interference. The status is returned. Multicast messages are distributed throughout the array so that the responses The answer address is recorded as a calculated delta offset from the requesting node. This results in many paths being used to return the response message to the master, or does not follow the same path as the request, as expected. Multiple endpoint messages An example of this is a broadcast message that addresses all nodes at once.

[0111] It also ensures that the same address can be read from a collection of message bus nodes. In these cases, multiple endpoint readouts are useful. The operation is such that only nodes that match the multi-node address respond. As with other multi-endpoint messages, the reply path is The response is determined by the delta offset calculated on the way to the node. Follow the route back to the requesting node, and many of the routes are taken from source to destination. It is different from a path, and all nodes may respond and return a single word.

[0112] Each node maintains a security configuration that describes the operations that are allowed on the node. Setting this configuration must be a secure operation and is selected as part of the boot operation. Implemented through the processor. This message is used to update the security configuration. and a security configuration can be generated by selected processors in the system. The format of this message is unique and can be constructed by writing data. flaw, therefore only identified security processors can generate this message. Since the only consideration is message delivery, the security configuration message The underlying security decisions that lead to the generation of messages are outside the scope of the message bus. Disable the master to implement forced isolation of debug from functional network. Similar to how a node can be enabled, a node that is not selected as the security master can be enabled. In this case, the security message will not be sent. As such, only certain types of messages are restricted, not all messages.

[0113] The message bus should be implemented as a 2D mesh network as shown in Figure 15. In addition, two identical networks are running in parallel, with recombination points located inside each node. Each link shown is an input port and an output port that are replicated for both networks. Both networks have both ports, allowing up to a total of four active ports on either side of the node. Allows simultaneous transmission and reception on the same side of a node for up to two messages. In one maximum use case for the network, all four input and four output ports are It can be used to forward messages across nodes. When using a route map, the only constraint on routing is that no U-turns are allowed. However, any other combination of routes to the other three outputs is acceptable. There are two networks at the node, but the two networks are completely independent of each other. Routing between the two networks is not possible, and A blockage may occur while the other network is idle.

[0114] There are several advantages to implementing a mesh network compared to other topologies, most notably The main advantage of a message bus is its ability to route around obstacles. Since it is a network that dynamically routes between From the nodes in the middle to the nodes that are powered down to reduce the overall chip power consumption, There is always the possibility of encountering an obstacle on the direct path between two nodes. It provides options for reaching a destination, and in most cases, the closer the endpoint is, the better. There are two logical directions in which messages can move, one of which is closer to the edge. This means that even if a route is blocked, another direction generally exists. It is still possible to have a message that is not The end-user located in the powered-off area is not necessarily a failure to The path between the requested endpoints does not exist at all, such as a .

[0115] Another advantage of mesh networks is that messages travel less distance. For a number of nodes, serial chains, multiple loops, row or column oriented buses, and meshes are possible. There are several possible connections, such as serial chains. The long distances a sage may have to travel between two locations. Typically, there is only one path available through the chip, so the network The number of messages that can coexist is generally reduced. Timing can be variable, making it difficult to design for adequate timing margins. This may be the case.

[0116] Another problem with large serial chains is power, and the fact that any one of the nodes may You can power down any region if it is part of a path that requires access to the node. An improvement over a single serial bus is several smaller loops. However, this is a centralization issue where the data needs to be moved between loops, and the connections between the loops. Multiple loops also have the potential for significant delays if a collision occurs at any point. The entire group requires power cycling, which results in fairly large power steps. The number of concurrent accesses increases, but the number of independent loops remains a problem with power optimization. You are still limited by the points where data must travel.

[0117] Multiple bus oriented arrangements have similar problems to multiple loop configurations, i.e., the various buses The points at which traffic must travel between service segments ultimately become bottlenecks throughout the interconnected network. Bus arrays actually provide an easier means to send multiple messages at once. However, the ease of getting messages on one bus segment may differ. This reduces the complexity of having to arbitrate between different bus segments. ,Data can be moved between bus segments depending on the location of the bus-to-bus interconnect. Certain areas of the equipment may need to remain on simply because With IO scattered around the device, data can potentially be affined to either side of the device. Therefore, there is no ideal location for placing the bus-to-bus connectors. This is because some layouts This results in relatively power efficient, but at the expense of interconnectivity with other bus segments. This requires a large number of otherwise unused nodes to be on and available for connection. Leave the other layout as the poorer performing layout.

[0118] The mesh also supports many messages operating in parallel. There are no bottlenecks, so many messages can travel through the network simultaneously. Routes merge through significant obstacles and are not constrained to pass through a single node. Unless otherwise specified, each message is often associated with another message regardless of when the message was sent. Each processor can proceed one at a time without ever encountering a message. If the system supports multiple messages, the limit on concurrent long-lived messages is However, parallel message delivery is possible, and the number of processors in the system is equal to the number of Depending on the route required to return a response to a message, congestion may reduce the actual upper bound. There is a saying.

[0119] Every node within a message bus structure can be a master, a slave, or a root intermediate point. These basic functions of each node are generally detailed in this section. The exact interface details may vary across embodiments, and this description is Provides a functional overview of the message bus node components. The general interface of a bus node is illustrated in Figure 17. Since no PE link is required, There are changes in how the nodes are attached to the IO bus, but the underlying behavior is similar is doing.

[0120] As illustrated, the message bus node 1701 is a payload and a routing receiving a first message including routing information and a multiprocessor Selecting a different message node from multiple message nodes based on the operation information of the array As used herein, operational information refers to a multi-processor Information relating to the past or current performance of the array. For example, operational information is It includes network usability, network performance heuristics, and congestion information on the message bus. In some cases, the operational information may include information about the performance of a multi-processor array. In other cases, the performance of a multi-processor array may be In some embodiments, a message bus node may include historical information about It is noted that during operation, operational information may be received from the multi-processor array.

[0121] The message bus node 1701 receives the first message based on the different message nodes. Modify the routing information of the message to generate a second message and route it to a different message node. The routing information is further configured to send a second message to the node. As used in this document, this is information that specifies the absolute or relative destination of a message. When specifying a destination, the number of nodes from the starting node and and the corresponding direction. Alternatively, when specifying an absolute destination, you can specify a particular node as Each message node then sends the specified absolute To propagate a message to its destination, the best possible node to send the message to is selected. As described in more detail below, routing information may be determined in some messages. Contains the offset specifying the message node and the direction in which the message should be sent. It is possible.

[0122] As used and described herein, a message is a message that contains a payload along with routing information. A message is a collection of data that contains a message (i.e., the contents of the message). , operational information, or any suitable portion of operational information.

[0123] Message Bus Nodes (or simply "Message Nodes") can be used in various design styles. A specific embodiment is depicted in Figure 18. As illustrated, The bus node 1800 includes a router 1801, a router 1802, a network processor 1803, a network processor 1804, an arbiter 1805, a configuration circuit 1806, and table 1807.

[0124] The message bus node 1800 transmits the message to the PE and the DMR through the arbiter 1805. In the case of an IO bus, the arbiter 1805 acts as a hub between the IO bus and the message bus. The bridge is a bridge that connects the local processor to the message bus node 1800. There are three targets for the access: the configuration registers (located in the configuration circuit 1806) ) and network processors 1803 and 1804. Additionally, The network processors 1803 and 1804 may be generating accesses to the local node. There is a possibility that one action will be sent from the message bus node 1800 back to the DMR or PE. Only access paths are possible. The node configuration, the type of access, and the remote request processing Based on the processing, local requests being generated, or responses being remembered, the arbiter 1805 connects the network processor 1803 and Connect one side of 1804.

[0125] Only request generation is susceptible to outages from the network side, so DMR or All writes to the PE can be generated immediately. When requested to fill out a form or to read in response to a remote access being processed In this case, the arbiter 1805 waits for one request before switching to the other network processor. The DMR or PE must wait for the request to complete. If the access is configured to be of higher priority, the current request It is possible to remove the host and switch to the other network processor. Or the DMR has already stalled the access and is not allowing the other processor to access it. There is no data in transition that is affected by the switch.

[0126] The arbiter 1805 also allocates register bus traffic based on the requested address. to the appropriate network processor or configuration register. The controller 1805 also reads the configuration register if a remote access is currently using it. is the only contention in the message bus node 1800 between the local node and the remote access. So it generates a stall back on the register bus interface.

[0127] Network processors 1804 and 1805 are connected to the attached PE / DMR or is responsible for the interaction between the IO bus and the rest of the message bus nodes. The network processors 1803 and 1804 have three responsibilities: The second function is to generate a request message into the network. Processes messages received from the network (including modifying the routing information for the messages) and the local address requested in the message for writing or reading. The final function is to respond to a request message and return the received response. The next step is to process the response message.

[0128] A first function of a network processor (e.g., network processor 1803) is to generate a new message in the network. This can be done in two ways: On the other hand, i.e., achieved by the first method, for a single word message, the PE Node deltas leading to remote nodes or multiple endpoint groups to be accessed, The address of the remote node to which the write should be sent, and in the case of a write, the write data to be written. The network processor then generates the message structure and Send a message to the router. Longer messages mean a word length of two or more words. In this case, the PE receives the node delta to the remote node, the start address of the remote node, and the remote The end address of the node and the local address in the DMR where the write data can be found. Write the address, or in the case of a read, the location to store the returned data. Once configured, the network processor generates a message structure for the router and sends it to the DM Generate a read request to R to fetch the required write data.

[0129] The second function of the network processor is to process messages received from the network. In this case, the incoming message structure is decomposed and The first and last addresses to be accessed are stored separately. Generates a read request to the DMR, starting with the first address and continuing until the last address is reached. Perform a check to see if the area you are accessing is protected by security. In this configuration, an error value is returned instead of data for a read word that is inaccessible. For a write, the network processor waits until the first data word arrives, It then generates a write to the DMR for each word received. If the address is a security configuration address, the received message is also a security message. Perform additional checks to verify the type.

[0130] The third function of the network processor is to receive responses to requests and The first step is to store the response back for the server to read. There are two options for this step: The first option is for the processor to receive the response of the message bus node 1800. It is a single word response that allows you to read the response directly from the register. To prevent multi-word messages from stalling in the network, return more than one word. When the network processor receives the message, it stores these words back in the DMR memory. When a read request is made, a response that remembers the address range is also sent in the message. The network processor was configured in the 1800 Gigabit bus node. It uses a programmed address range to send back and store responses, and as a safety measure, Discard any additional data that may have been returned in the message.

[0131] Since there are three functions competing for a single resource, the network processor also In practice, the response or Only the service of the request can be active on the router side of the network processor. Since the request generation can be active on the PE / DMR side, three Only two of them can exist at the same time. The main problem with arbitration is deadlock. The goal of deadlock avoidance is to ensure that a condition cannot form. The potential for lockout behavior is more important than system performance. Arbitration methods allow you to plan how messages flow through the system. , one of three options is selected. In the first method, the first one entered is In this mode, the node processes the message before considering any other messages. It processes the first request that arrives from the network or processor side and then This is the easiest way to maintain full network performance. However, this method is prone to deadlocks. This is a round-robin process that alternates between the two requests. Due to the pipeline depth of the DMR interface, the second method reduces the access speed. There is a chance that it will drop to 2 / 5. What actually happens is that the return is written or A read or write occupies one cycle, and the next cycle is used to load the write data. The interface then handles the local write and message read operations. You have to wait for the execution to complete, which can result in significantly slower performance. Network outages interacting with the DMR pipeline are avoided at the expense of Between victimization and outage avoidance, there is a time lag between messages entering and leaving the MBN. There is a way to determine that both messages are not between the same nodes. There is a possibility of node deadlock, but the system is not hardware protected. We must proactively create scenarios. We must identify where the data comes from and By comparing where the data is going, you can distinguish between two competing messages. It is possible to determine whether a given In such scenarios, round-robin operation can be selected; otherwise, full speed You can make FIFS running under that mode the default for message delivery across your system. ,messages complete more quickly than in a round-robin implementation.

[0132] Each of the routers 1801 and 1802 is connected to a corresponding network. Receives messages from the network and sends them to the network processors 1803 and 1804. to the next destination corresponding to the message. The routers 1801 and 1802 are configured as multiple switches or network processors. 1803 and 1804 to their corresponding networks. The circuit may include appropriate circuitry.

[0133] Routers 1801 and 1802 are identical and each handles the data passing through the node. The first operation is to send a message to the node that is intended to The purpose of this is to identify the message. This is the two bytes of the node delta address that was delivered. When it finds a set of zeros, it starts extracting the next part of the message and This involves delivering the content to a subprocessor.

[0134] When no match is found, the second main action is to send the message to the next node. and progress towards the destination. Progress towards the destination can potentially take two directions: If there is a possibility that a path along the two options that leads closer to the destination is unavailable, With the option to detour in direction 3. There is no turning back, so data arrives Direction is not optional, and the underlying requirements for system design are subject to routing rules. When a route is established, a path is allowed between two nodes that need to communicate so that the route does not need to make a U-turn. This is what we should do.

[0135] Routers are also responsible for inserting new messages into the network. To insert a message into a queue, the destination delta offset must be known and the destination Messages are accepted unless one of the two logical output directions is used. , placed in the message bus. Immediately before the first address and data pair, The response data is included in the message so that the destination node can reply with the results of the action taken. The response delta is the path the message takes through the network. It is automatically updated based on the route and in case of an error response, any node along the route or the destination The destination node has the correct destination to send a response to in response to the request message. To make it possible.

[0136] When we talk about addresses inside a message bus, we refer to the addresses of message bus nodes. distinguish between the address and the value placed in the message to route it to that node It is important to note that the address of a node effectively encompasses the IO node, the PE, and the DMR. The location of the core array containing only the DMR, as occurs in the upper right corner of the array. The X,Y coordinate location of the node within the entire array containing the node. ) is found in the lower left corner of the device, connected to the boot processor, and outside the main core array. The core array is arranged at these four corners (1,1) as shown above the entire array in Figure 19. ), (1,17), (17,17), and (17,1), and the Note that the format is (top number, bottom number).

[0137] The location address of the Message Bus node is used as the route for use in the message header. This is used to generate the routing delta information required for the message. To calculate the data, we take the signed difference of the two locations and move from the source node to the destination node. Identify the number of nodes that must be traversed in each direction of the mesh to transition to For example, to move from (2,2) to (4,7), use the delta address (+2,+5). The return route is (-2,-5), which means the destination is two nodes east of the current location. , and 5 nodes north. This means that the routing information is relative. This allows for flexible cell placement, so that if a cell moves, the endpoints remain at the same distance. It moves and the delta between the two locations remains the same.

[0138] In some cases, the information stored in table 1807 is used to For example, the destination information contained in the message may be input to table 1807. Such data may be used as an index to retrieve data. The table 1807 may specify the next message bus node to which the message should be sent. Static Random Access Memory s memory (SRAM), a register file, or other suitable storage circuitry. In various embodiments, the information stored in table 1807 may be stored in a boot sequence. The data may be loaded between sequences and updated during operation of the multi-processor array.

[0139] Assuming 8-bit row and column address values, the message bus is 256× It may be possible to extend to a 256 node array. The message bus remains constant and scales as the technology nodes shrink. It allows the device to be scaled or to support multiple die array configurations. This means that the address file does not need to be revised between generations, but may be revised in later generations. You may choose the format.

[0140] When the message arrives at the destination node, it places the value in the destination node that needs to be accessed. A second address is needed for the row and column addresses with enough room to expand. Unlike the PE / DMR address, the destination node local address component of the PE / DMR is actually However, there is not enough space. As currently specified, the DMR data memory is 16k words. 8k words of PE instruction memory, DMR register bus space, PE internal registers, and There is a message bus internal configuration register. The local address is a 16-bit word. Since we don't need all of it, and the read / write command only needs one bit, Use bit 15 as a control bit. This can also be written or read. The address is repeated for each burst, which is convenient and allows for reads and writes to be performed for each burst. Allowing users to select only those access controls provides a flexible and efficient means for applying access controls. A tier is provided.

[0141] In an IO bus interface node, the bus operates with 32-bit addresses. Based on the message format, only 15 bits are transferred per burst, resulting in The message leaves 17 bits unaccounted for. A double register is used, with an implicit high bit of 0, so that the IO bus Potentially 31-bit addresses, more than enough to map the necessary memory and peripheral space As part of the message to access the IO bus, the message is written You should start by writing to the page register, as the page holds the last value written to it. and another master has set the page register to a different value than the current master was expecting. If set, this could potentially lead to unintended access locations.

[0142] To further illustrate the operation of a Message Bus Node, A flow chart illustrating one embodiment of a method for operating the message is illustrated in FIG. May be applied to bus node 1800 or any other suitable message bus node The method begins at block 2201 .

[0143] The method includes: identifying one of a plurality of message nodes included in a multiprocessor array; The message node of As mentioned above, the method includes receiving a particular message node (block 2202). The first message may be received via one of a plurality of message buses coupled to the node.

[0144] The method also provides routing information and multi-processing information by a particular message node. Based on the operational information of the sensor array, different message nodes among multiple message nodes are selected. As noted above, different media types may be used. The message node is determined by the relative offset contained in the routing information and the The routing may be based on congestion or other heuristics.

[0145] Additionally, the method may include, by a particular message node, determining whether a second message is based on a different message node. 2 message (block 2204). In other words, a network processor (e.g., network processor 1803) can The message node may generate a second message based on which message node is selected. In the example, the second message is sent to the next message node. contains modified routing information that can be used by different message nodes. good.

[0146] The method includes the step of: sending a second message to a different message node by a particular message node; In some embodiments, the router further includes sending the The router (for example, router 1801) receives the corresponding route information included in the first message. The router may route the second message based on the pair offset. Such a relative offset can be used when determining which direction to send. The method ends at block 2206.

[0147] HyperOp Data Path Referring to Figure 20, one embodiment of a HyperOp datapath is shown. As shown, the HyperOp data path consists of two data paths identified as DP0 and DP1. Each of DP0 and DP1 may be identical and may include an accumulator circuit, an adder circuit, and The shifter circuitry is not just a circuit for moving operands through the datapath. A given PE in a multi-processor array may also include a Hype It is noted that the rOp data path may be included.

[0148] Using the multi-processor architecture described above, different programming An example of such a programming model is depicted in Figure 21. As such, Figure 21 includes the programming models for ASM and HyperOp. Additional details about the programming model and coding examples are provided below. Each example includes: • C - Standard code that describes functional operations / algorithms. ASM - How to implement operations / algorithms using 64-bit instructions ASM also uses vector intrinsics (v Includes examples using vector intrinsic (pseudo ASM instructions). Embedded functions are ASM-like instructions that map to HyperOp instructions. HyperOp - How operations / algorithms are implemented using 128-bit instructions One or more examples of how to do this.

[0149] memory operand

[0150] ASM Code add16s M1.H,M2.H,M3.H add16s M1.L, M2.L, M3.L

[0151] HyperOp Code |A| ld32 M1,%A; / / Load SIMD data from 32-bit M1 do |B| ld32 M2,%B; / / Load SIMD data from 32-bit M2 do |DP1| add16s %AH,%BH,%ACC2; / / ACC2=M1[0 ]+M2[0] |DP0| add16s %AL,%BL,%ACC0; / / ACC0=M1[1 ]+M2[1] |D| dst16 %ACC2_ACC0,M3; / / SIM to 32-bit M3 Remember the result of D

[0152] Immediate Operand

[0153] ASM Code sub16 %r2,$10,%r8

[0154] HyperOp Code { |A| ld16 %r2,%AL; / / Load 16-bit R2 |C| ld16 $10,%CLH; / / Loads the 16-bit immediate value 10 |DP1| sub16s %AL,%CLH,%D1; / / D1=R2-10 |D| st16 %D1,%r8; / / Store the result in 16-bit R8 } load immed uses slot C to read the 16-bit segment of the %C register. loads the 16-bit segment of the %B register, but uses slot B to load the 16-bit segment of the %B register. Note that you can

[0155] Conditional execution on scalars

[0156] C Code int16 a,b,c,d,e; if(a>b) e=c+d;

[0157] ASM Code / / Assumptions: / / a is in %R2 / / b is in %R3 / / c is in %R4 / / / / d is in %R5 / / e is in %R6 / / Use %R7 as tmp tcmp16s GT %R2,%R3,%P0 add16s %R4,%R5,%R7 cmov16 (%P0) %R7,%R6

[0158] HyperOp Code (Conditional Storage Slots) - Version 1 { |A| ld16s %R2,%AL; / / Load 16-bit R2 |B| ld16s %R3,%BL; / / Load 16-bit R3 |DP0| tcmp16s GT %AL,%BL,%P0; / / Try R2>R3 Experiment and set predicate P0 } { |A| ld16s %R4,%AH; / / Load 16-bit R4 |B| ld16s %R5,%BH; / / Load 16-bit R5 |DP0| add16s %AH,%BH,%D0; / / D0=R4+R5 |D| st16 (%P0) %D0,%R6; / / If P0 is true, 16-bit Store the result in R6 of the }

[0159] HyperOp Code (Conditional Storage Slots) - Version 2 { |A| ld32 %R2.d,%A; / / Load 32-bit R2:R3 |B| ld32 %R4.d,%B; / / Load 32-bit R4:R5 |DP1| tcmp16s GT %AH,%AL,%P0; / / Try R2>R3 Experiment and set predicate P0 |DP0| add16s GT %BH,%BL,%D0; / / D0=R4+R5 } { |D| st16 (%P0) %D0,%R6; / / If P0 is true, 16-bit Store the result in R6 of the }

[0160] Note: Conditional execution in ASM models is only available when using CMOV. Requires calculating the result into a temp register, then conditionally moving it to the destination to make Conditional execution in HyperOp models allows conditions to be applied independently to slots. to Predicated execution uses the predicate flag Pn set by the previous instruction, not the same instruction. ● The conditional store is performed in slot D of a separate instruction. ●It may be possible to hide conditional memories in subsequent HyperOps

[0161] Conditional execution on vectors

[0162] C Code int16 a[2],b[2],c[2],d[2],e[2]; if(a[0]>b[0]) e[0]=c[0]+d[0]; if(a[1]>b[1]) e[1]=c[1]+d[1];

[0163] ASM Code / / Assumptions: / / a[0], a[1] are in %R2, %R3 / / b[0], b[1] are in %R4, %R5 / / c[0], c[1] are in %R6, %R7 / / d[0], d[1] are in %R8, %R9 / / e[0], e[1] are in %R10, %R11 / / Use %R12 and %R13 as temp tcmp16s GT %R2,%R4,%P1 tcmp16s GT %R3,%R5,%P0 add16s %R6,%R8,%R12 add16s %R7,%R9,%R13 cmov16 (%P1) %R12,%R10 cmov16 (%P0) %R13,%R11

[0164] HyperOp code (double conditional storage) { |A| ld32 %R2.D,%A; / / Load 32-bit R2:R3 ||B| ld32 %R4.D,%B; / / Load 32-bit R4:R5 |DP1| tcmp16s GT %AH,%BH,%P1; / / Try R2>R4 To test this, set the predicate P1. |DP0| tcmp16s GT %AL,%BL,%P0; / / Try R3>R5 Experiment and set predicate P0 } { |A| ld32 %R6.D,%A; / / Load 32-bit R6:R7 |B| ld32 %R8.D,%B; / / Load 32-bit R8:R9 |DP1| add16s %AH,%BH,%D1; / / D1=R6+R8 |DP0| add16s %AL,%BL,%D0; / / D0=R7+R9 |D| dst16 (%P1 %P0) %D1_D0,%R10.D; / / P1 If is true, store D1 in 16-bit R10, and if P0 is true, / / Store D0 in 16-bit R11 }

[0165] Note: ●Conditional execution applies to slot D instructions. Use SIMD predicate execution mode if(%P1 %P0) {…} ●%P1 controls the upper word ●%P0 controls the lower word

[0166] Find non-zero elements in an array and save the values

[0167] C Code int16 a[N],b[N]; int16 i,j; j=0; for(i=0,i <N;i++) { if(a[i]<>0) b[j++]=a[i]; }

[0168] ASM code using GPn / / Assumptions: / / Use %I1 as i / / Use %I2 as j / / %B1 points to a[] / / %B2 points to b[] / / Use %I0 as temporary GR gmovi $0,%I2 / / I2=0 repeat $0,$N-1,$1,%I1,L_loop_start,L_lo op_end L_loop_start: mov16 0[%B1+%I1],%I0 / / I0=a[i] / / Load %I0 in EX and stall +4 cycles when used in FD gtcmps NE %I0,$0,%GP0 / / Test a[i]<>0 and check predicate G Set P0 cmov16 (%GP0) 0[%B1+%I1],0[%B2+%I2] / / G If P0 is true, move a[i] to the 16-bit b[j] gadd (%GP0) %I2,$1,%I2 / / If GP0 is true, then j++ R L_loop_end: Cycle: 2+N(1+4+3)=2+8N

[0169] ASM code using Pn gmovi $0,%I2 / / I2=0 repeat $0,$N-1,$1,%I1,L_loop_start,L_lo op_end L_loop_start: tcmp16s NE 0[%B1+%I1],$0,%P0 / / a[i]<>0 Test and set predicate P0 cmov16 (%P0) 0[%B1+%I1],0[%B2+%I2] / / P0 If true, move a[i] to the 16-bit b[j] / / Set %P0 in EX to disable +3 cycles when used in FD gadd (%P0) %I2,$1,%I2 / / If P0 is true, do j++ L_loop_end: Cycle: 2+N(2+3+1)=2+6N

[0170] Simple HyperOp code using Pn (conditional G slot execution) / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gmovi $0,%I2 / / I2=0 repeat $0,$N-1,$1,%I1,L_loop_start,L_lo op_end L_loop_start: { |A| ld16 0[%B1+%I1],%AL; / / 16-bit a[i] is loaded Load |DP0| mov16s %AL,%D0; |DP1| tcmp16 NE %AL,$0,%P0; / / try a[i]<>0 Experiment and set predicate P0 } { |D| st16 (%P0) %D0,0[%B2+%I2]; / / P0 is true If so, move a[i] to 16-bit b[j] } / / Set %P0 in EX to disable +3 cycles when used in FD { |G| gadd (%P0) %I2,$1,%I2 If P0 is true, then j ++ } L_loop_end: Cycle: 2+N(1+1+3+1)=2+6N

[0171] Pipelined HyperOp code using Pn (conditional store) / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gdmovi $0,$1,%I2,%S2 / / I2=0,S2=1 repeat $0,$N-1,$4 %I1,L_loop_start,L_lo op_end L_loop_start: {|A| ld16 0[%B1+%I1],%AL;|DP1| mov16 %A L,%ACC0;|DP0| tcmp16 NE %AL,$0,%P0;} {|A| ld16 1[%B1+%I1],%AL;|DP1| mov16 %A L,%ACC1;|DP0| tcmp16 NE %AL,$0,%P1;} {|A| ld16 2[%B1+%I1],%AL;|DP1| mov16 %A L,%ACC2;|DP0| tcmp16 NE %AL,$0,%P2;} {|A| ld16 3[%B1+%I1],%AL;|DP1| mov16 %A L,%ACC3;|DP0| tcmp16 NE %AL,$0,%P3;} / / Set %P0 in EX to disable +1 cycle when used in FD {|A| incr (%P0) $(__i2Mask);|D| st16 (% P0) %ACC0,0[%B2+%I2];} {|A| incr (%P1) $(__i2Mask);|D| st16 (% P1) %ACC1,0[%B2+%I2];} {|A| incr (%P2) $(__i2Mask);|D| st16 (% P2) %ACC2,0[%B2+%I2];} {|A| incr (%P3) $(__i2Mask);|D| st16 (% P3) %ACC3,0[%B2+%I2];} L_loop_end: Cycle: 1+N / 4(4+1+4)=1+2.25N

[0172] HyperOp code using two PEs / / Use PE0 to perform a test on the input array a[]: for(i=0;i <N;i++) { if(a[i]<>0) sendToPE1(a[i]); } / / Use PE1 to store the sparse output array b[]: idx=0; while(1) { tmp=recvFromPE0(); b[idx++]=tmp; }

[0173] PE0 / / Assumptions: / / %B1 points to a[] and i is in %I1 repeat $0,$N-1,$1 %I1,L_loop_start,L_lo op_end L_loop_start: tcmp16 NE 0[%B1+%I1],$0,%P0; cmov16 (%P0) 0[%B1+%I1],PE0_PE1_QPORT; L_loop_end: PE0 cycle: 1+2N

[0174] PE1 / / Assumptions: / / %B2 points to b[] and j is in %I2 gdmovi $0,$1,%I2,%S2 / / I2=0,S2=1 L_loop: jmp L_loop; / / Loop infinitely on the Q port { |A| incr $(__i2Mask); / / I2+=S2; for the next command Helpful Updates |B| ld16 PE0_PE1_QPORT,%BL; |DP0| mov16 %BL,%D0; |D| st16 %D0,0[%B2+%I2]; / / Store the current value of I2 ( (not updated) }

[0175] Note: ●By using two PEs, when you set %GP0 in EX and use it in FD Avoid outages

[0176] Find non-zero elements in an array and save their indices

[0177] C Code int16 a[N],b[N]; int16 i,j; j=0; for(i=0;i <N;i++) { if(a[i]<>0) { b[j++]=i;} }

[0178] ASM code using GPn / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gmov $0,%I2 repeat $0,$N-1,$1 %I1,L_loop_start,L_lo op_end L_loop_start: mov16 0[%B1+%I1],%I0 / / Load a[i] into temporary I0 do / / Load %I0 in EX and stall +4 cycles when used in FD gtcmps NE %I0,$0,%GP0 / / Test a[i]<>0 and check predicate G Set P0 cmov16 (%GP0) %I1,0[%B2+%I2] / / GP0 is true If so, move i to 16-bit b[j] gadd (%GP0) %I2,$1,%I2 / / If GP0 is true, increment j ++ L_loop_end: Cycle: 2+N(1+4+3)=2+8N

[0179] ASM code using Pn / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gmov16 $0,%I2 repeat $0,$N-1,$1 %I1,L_loop_start,L_lo op_end L_loop_start: tcmp16s NE 0[%B1+%I1],$0,%P0 / / a[i]<>0 Test and set predicate P0 cmov16 (%P0) %I1,0[%B2+%I2] / / If P0 is true , move i to 16-bit b[j] / / Set %P0 in EX to disable +3 cycles when used in FD gadd (%P0) %I2,$1,%I2 / / If P0 is true, increment j++ do L_loop_end: Cycle: 2+N(2+3+1)=2+6N

[0180] ASM code using pipelined Pn / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gmov16 $0,%I2 repeat $0,$N-1,$4 %I1,L_loop_start,L_lo op_end L_loop_start: tcmp16s NE 0[%B1+%I1],$0,%P0 / / a[i+0]<> Test for 0 and set predicate P0 tcmp16s NE 1[%B1+%I1],$0,%P1 / / a[i+1]<> Test for 0 and set predicate P1 tcmp16s NE 2[%B1+%I1],$0,%P2 / / a[i+2]<> Test for 0 and set predicate P2 tcmp16s NE 3[%B1+%I1],$0,%P3 / / a[i+3]<> Test for 0 and set predicate P3 add16s (%P0)%I1,$0,0[%B2+%I2] / / P0 is true If so, move i+0 to 16-bit b[j] gadd (%P0) %I2,$1,%I2 / / If P0 is true, increment j++ do add16s (%P1) %I1,$1,0[%B2+%I2] / / If P1 is true, If so, move i+1 to 16-bit b[j] gadd (%P1) %I2,$1,%I2 / / If P1 is true, increment j++ do add16s(%P2) %I1,$2,0 [%B2+%I2] / / P2 is true If so, move 16 bits of b[j] gadd (%P2) %I2,$1,%I2 / / If P2 is true, increment j++ do add16s (%P3) %I1,$3,0[%B2+%I2] / / If P3 is true, If so, move i+3 to 16-bit b[j] gadd (%P3) %I2,$1,%I2 / / If P3 is true, increment j++ do L_loop_end: Cycle: 2+N / 4(4+8)=2+3N

[0181] Simple HyperOp code using GPn (conditional G slot and memory) / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gdmov $0,$1,%I2,%S2 repeat $0,$N-1,$1 %I1,L_loop_start,L_lo op_end L_loop_start: { |A| ld16 0[%B1+%I1],%AL; / / Load a[i] into AL Do ||DP0| mov16 %AL,%D0; / / Move a[i] to D0 |D| st16 %D0,%I0; / / Store D0=a[i] in temporary I0 R } / / Write %I0 in EX and stall +4 cycles when used in FD { |B| ld16 %I1,%BH; / / Load i into BH |DP0| mov16s %BH,%D0; / / Move i to D0 |G| gtcmps NE %I0,$0,&GP0; / / Test a[i]<>0 and set predicate P0 } { |A| incr (%GP0) $(__i2Mask); / / GP0 is true If so, increment j++ |D| st16 (%GP0) %D0,0[%B2+%I2]; / / GP0 is true If so, move i to 16-bit b[j] } L_loop_end: Cycle: 2+N(1+4+2)=2+7N

[0182] Simple HyperOp code using Pn / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gdmovi $0,$1,%I2,%S2 repeat $0,$N-1,$1 %I1,L_loop_start,L_lo op_end L_loop_start: { |A| ld16 0[%B1+%I1],%AL; / / Load a[i] into AL Do |B| ld16 %I1,%BL; / / Load i into BL |DP1| tcmp16s NE %AL,$0,%P0; / / a[i]<>0 Test and set predicate P0 |DP0| mov %BL,%D0; / / Move i to D0, prepare for storing Preparation } / / Write %P0 in EX and stall +4 cycles when used in FD { |A| incr (%P0) $(__i2Mask); / / If P0 is true , increment j++ |D| st16 (%P0) %D0,0[%B2+%I2]; / / P0 is true If so, move i to 16-bit b[j] } L_loop_end: Cycle: 2+N(1+4+1)=2+6N

[0183] HyperOp Code Pipeline with GPn / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gdmovi $0,$1,%I2,%S2 repeat $0,$N-1,$5 %I1,L_loop_start,L_lo op_end L_loop_start: / / Load the next 5 values ​​from a[] into the temporary GR {|A| ld16 0[%B1+%I1],%AL;|DP0| mov16s % AL,%D0;|D| st16 %D0,%T4;} {|A| ld16 1[%B1+%I1],%AL;|DP0| mov16 %A L,%D0;|D| st16 %D0,%T5;} {|A| ld16 2[%B1+%I1],%AL;|DP0| mov16 %A L,%D0;|D| st16 %D0,%T6;} {|A| ld16 3[%B1+%I1],%AL;|DP0| mov16 %A L,%D0;|D| st16 %D0,%T7;} {|A| ld16 4[%B1+%I1],%AL;|DP0| mov16 %A L,%D0;|D| st16 %D0,%I0;} / / if(a[i]<>0) { b[j++]=i;} / / Test a[i+0] R {|A| ld16 %I1,%AH;|G| gtcmpi16 NE %T4,$ 0,%GP0;|DP0| add16s %AH,$0,%D0;} {|A| incr (%GP0) $(__i2Mask);|D| st16 ( %GP0) %D0,0[%B2+%I2];} / / if(a[i+1]<>0) { b[j++]=i+1;} / / a[i+1] Test the {|G| gtcmpi16 NE %T5,$0,%GP0;|DP0| add1 6s %AH,$1,%D0;} {|A| incr (%GP0) $(__i2Mask);|D| st16 ( %GP0) %D0,0[%B2+%I2];} / / if(a[i+2]<>0) { b[j++]=i+2;} / / a[i+2] Test the {|G| gtcmpi16 %T6,$0,%GP0;|DP0| add16s %AH,$2,%D0;} {|A| incr (%GP0) $(__i2Mask);|D| st16 ( %GP0) %D0,0[%B2+%I2];} / / if(a[i+3]<>0) { b[j++]=i+3;} / / a[i+3] Test the {|G| gtcmpi16 NE %T7,$0,%GP0;|DP0| add1 6s %AH,$3,%D0;} {|A| incr (%GP0) $(__i2Mask);|D| st16 ( %GP0) %D0,0[%B2+%I2];} / / if(a[i+4]<>0) { b[j++]=i+4;} / / a[i+4] Test the {|G| gtcmpi16 NE %I0,$0,%GP0;|DP0| add1 6s %AH,$4,%D0;} {|A| incr (%GP0) $(__i2Mask);|D| st16 ( %GP0) %D0,0[%B2+%I2];} L_loop_end: Cycle: 2+N / 5(5+5(2))=2+3N Note: ● By loading into 5 GRs, all outages can be hidden.

[0184] Pipelined HyperOp code using Pn / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gdmovi $0,$1,%I2,%S2 repeat $0,$N-1,$4 %I1,L_loop_start,L_lo op_end L_loop_start: / / Test the next 5 values ​​of a[] and put them into P0~P3 {|A| ld32 0[%B1+%I1],%A; |C| ld16 %I1,%CLL; / / CLL=I1 |DP1| tcmp16s NE %AH,$0,%P0; |DP0| tcmp16s NE %AL,$0,%P1; } {|B| ld32 2[%B1+%I1],%B; |DP1| tcmp16s NE %BH,$0,%P2; |DP0| tcmp16s NE %BL,$0,%P3; } / / Set %P0 in EX to disable +3 cycles when used in FD / / if(a[i]<>0) { b[j++]=i;} / / Use P0 {|A| incr (%P0) $(__i2Mask); |DP0| add16s %CLL,$0,%D0; |D| st16 (%P0) %D0,0[%B2+%I2]; } / / if(a[i+1]<>0) { b[j++]=i+1;} / / Use P1 R {|A| incr (%P1) $(__i2Mask); |DP0| add16s %CLL,$1,%D0; |D| st16 (%P1) %D0,0[%B2+%I2]; } / / if(a[i+2]<>0) { b[j++]=i+2;} / / Use P2 R {|A| incr (%P2) $(__i2Mask); |DP0| add16s %CLL,$2,%D0; |D| st16 (%P2) %D0,0[%B2+%I2]; } / / if(a[i+3]<>0) { b[j++]=i+3;} / / Use P3 R {|A| incr (%P3) $(__i2Mask); |DP0| add16s %CLL,$3,%D0; |D| st16 (%P3) %D0,0[%B2+%I2]; } L_loop_end: Cycle: 2+N / 4(2+3+4)=2+2.25N Note: ●Not all outages can be hidden using four Pn

[0185] HyperOp code using tagged data / / Assumptions: / / %B1 points to a[] and i is in %I1 / / %B2 points to b[] and j is in %I2 gdmovi $0,$1,%I2,%S2 repeat $0,$N-1,$4 %I1,L_loop_start,L_lo op_end L_loop_start: / / Test the next four values ​​of a[] and put them into P0~P3 { |A| ld32 0[%B1+%I1],%A; / / Load, AH=a[i+ 0], AL=a[i+1] |C| ld16 $a,%CLL; / / CLL=&a[0] |DP1| tcmp16s NE %AH,$0,%P0; / / a[i+0]<> Test for 0 and set predicate P0 |DP0| tcmp16s NE %AL,$0,%P1; / / a[i+1]<> Test for 0 and set predicate P1 } { |B| ld32 2[%B1+%I1],%B; / / Load, BH=a[i+ 2], BL=a[i+3] |DP1| tcmp16s NE %BH,$0,%P2; / / a[i+2]<> Test for 0 and set predicate P2 |DP0| tcmp16s NE %BL,$0,%P3; / / a[i+3]<> Test for 0 and set predicate P3 } / / Set %P0 in EX to disable +3 cycles when used in FD ( INCR instruction) / / if(a[i]<>0) { b[j++]=i;} { |A| incr (%P0) $(__i2Mask); / / If P0 is true , increment j++ |B| ld16t 0[%B1+%I1],%B; / / Load tagged data B={&a[i]:a[i]} |DP0| sub16s %BH,%CLL,%D0; / / D0=&a[i]-& a[0]=i |D| st16 (%P0) %D0,0[%B2+%I2]; / / P0 is true If so, store i in 16-bit b[j]. } / / if(a[i+1]<>0) { b[j++]=i+1;} { |A| incr (%P1) $(__i2Mask); / / if P1 is true , increment j++ |B| ld16t 1[&B1+%I1],%B; / / Load tagged data B={&a[i+1]:a[i+1]} |DP0| sub16s %BH,%CLL,%D0; / / D0=&a[i+1] -&a[0]=i+1 |D| st16 (%P1) %D0,0[%B2+%I2]; / / If P1 is true, If so, store i+1 in 16-bit b[j]. } / / if(a[i+2]<>0) { b[j++]=i+2;} { |A| incr (%P2) $(__i2Mask); / / if P2 is true , increment j++ |B| ld16t 2[&B1+%I1],%B; / / Load tagged data B={&a[i+2]:a[i+2]} |DP0| sub16s %BH,%CLL,%D0; / / D0=&a[i+2] -&a[0]=i+2 |D| st16 (%P2) %D0,0[%B2+%I2]; / / P2 is true If so, store i+2 in 16-bit b[j]. } / / if(a[i+3]<>0) { b[j++]=i+3;} { |A| incr (%P3) $(__i2Mask); / / if P3 is true , increment j++ |B| ld16t 3[&B1+%I1],%B; / / Load tagged data B={&a[i+3]:a[i+3]} |DP0| sub16s %BH,%CLL,%D0; / / D0=&a[i+3] -&a[0]=i+3 |D| st16 (%P3) %D0,0[%B2+%I2]; / / P3 is true If so, store i+3 in 16-bit b[j] } L_loop_end: Cycle: 2+N / 4(2+3+4)=2+2.25N

[0186] Note: The tagged load LD16T stores 16-bit data (in the lower 16 bits) and its address. Loads addresses as packed data (in the upper 16 bits) The data index is the data address (or tag), i.e., the address of the array. It's the start

[0187] Accessing an array using indirection

[0188] C Code int16 a[N],b[N],c[N]; int16 i,j; for(i=0;i <N;i++) { j=b[i]; a[i]=c[j]; }

[0189] ASM Code / / Assume %B1 points to a[] and i is in %I1 / / Assume %B2 points to b[] and i is in %I1 / / Assume %B4 points to c[] and j is in %I2 repeat $0,$N-1,$1 %I1,L_loop_start,L_lo op_end L_loop_start: mov16 0[%B2+%I1],%I2 / / Set %I2 in EX to disable +4 cycles when used with FD mov16 0[%B4+%I2],0[%B1+%I1] L_loop_end: Cycle: 1+N(1+4+1)=1+6N

[0190] Simple HyperOp Code / / Assume %B1 points to a[] and i is in %I1 / / Assume %B2 points to b[] and i is in %I1 / / Assume %B4 points to c[] and j is in %I2 repeat $0,$N-1,$1 %I1,L_loop_start,L_lo op_end L_loop_start: {|A| ld16 0[%B2+%I1],%AL;|DP0| mov %AL, %D0;|D| st16 %D0,%I2} / / Set %I2 in EX to disable +4 cycles when used with FD {|B| ld16 0[%B4+%I2],%BL;|DP0| mov %BL, %D0;|D| st16 %D0,0[%B1+%I1]}; L_loop_end: Cycle: 1+N(1+4+1)=1+6N

[0191] Pipelined HyperOp Code / / Assume %B1 points to a[] and i is in %I1 / / Assume %B2 points to b[] and i is in %I1 / / Assume that %B4 points to c[] and j is in %I2~%I7 / / j0=b[0];j1=b[1]; {|A| ld32 0[%B2],%A;|DP0| mov32 %A,%D0; |D| st32 %D0,%I2I3;} / / j2=b[2]; j3=b[3]; {|A| ld32 2[%B2],%A;|DP0| mov32 %A,%D0; |D| st32 %D0,%I4I5;} / / j4=b[4]; j5=b[5]; {|A| ld32 4[%B2],%A;|DP0| mov32 %A,%D0; |D| st32 %D0,%I6I7;} / / Set %I2 and %I3 in EX and use it in FD to stop functioning for +1 cycle. Stop repeat $0,$N-1,$6 %I1,L_loop_start,L_lo op_end L_loop_start: / / a[i+0]=c[j0];a[i+1]=c[j1];j0=b[i+6];j 1=b[i+7]; {|A| ld16 0[%B4+%I2],%AL;|B| ld16 0[%B4 +%I3],%BL; |DP1| mov16 %AL,%D1;|DP0| mov16 %BL,%D0 ;|D| dst16 %D1_D0,0[%B1+%I1];} {|A| ld32 6[%B2+%I1],%A;|DP0| mov32 %A, %D0;|D| st32 %D0,%I2I3;} / / a[i+2]=c[j2];a[i+3]=c[j3];j2=b[i+8];j 3=b[i+9]; {|A| ld16 0[%B4+%I4],%AL;|B| ld16 0[%B4 +%I5],%BL; |DP1| mov16 %AL,%D1;|DP0| mov16 %BL,%D0 ;|D| dst16 %D1_D0,2[%B1+%I1];} {|A| ld32 8[%B2+%I1],%A;|DP0| mov32 %A, %D0;|D| st32 %D0,%I4I5;} / / a[i+4]=c[j4];a[i+5]=c[j5];j4=b[i+10]; j5=b[i+11]; {|A| ld16 0[%B4+%I6],%AL;|B| ld16 0[%B4 +%I7],%BL; |DP1| mov16 %AL,%D1;|DP0| mov16 %BL,%D0 ;|D| dst16 %D1_D0,4[%B1+%I1];} {|A| ld32 10[%B2+%I1],%A;|DP0| mov32 %A ,%D0;|D| st32 %ACC0,%I6I7;} / / Ignore the last values ​​loaded into I1~I7 L_loop_end: Cycle: 3+1+1+N / 6(6)=5+N

[0192] Note: Index j is loaded pairwise from b[i] in one cycle. Two c[j] are loaded as a pair in one cycle and stored in a[i]. ●By using six index registers, you can set indexes in EX and Avoiding pipeline bubbles with indexes on FDs and

[0193] Conditional Accumulation using Double DP

[0194] Below are examples of where a conditional HyperOp with two predicates can be used: This is an example.

[0195] C Code int16 a[N],b[N],c[N]; int16 i; int32 sum=0; for(int i=0;i <N;i++) { if(a[i]>b[i]) sum+=a[i]*c[i]; }

[0196] ASM Code

[0197] This example uses vector eigenfunctions (pseudo-ASM instructions) to access double DPs. . repeat $0,$N-1,$2,IDX_i,L_loop_start,L_ loop_end movx16s $0,%ACC2 movx16s $0,%ACC0 L_loop_start: vtcmp16s GT 0[BP_a+IDX_i],0[BP_b+IDX_i] ,%P1P0; cmov16 (%P1) 0[BP_a+IDX_i],$0,%R0 cmov16 (%P0) 1[BP_1+IDX_i],$0,%R1 vmulaa16s %R0.D,0[BP_c+IDX_i],%ACC2_ACC 0 L_loop_end: accadd %ACC0,$0,%ACC2 Cycle: 3+N / 2(4)+1=4+2N

[0198] HyperOp code (conditional DP slot execution - both slots) #define BP_a %B1 #define BP_b %B2 #define BP_c %B3 #define IDX_i %I1 repeat $0,$N-1,$2,IDX_i,L_loop_start,L_ loop_end {|DP1| movx16s $0,%ACC2;|DP0| movx16s $ 0,%ACC0;} L_loop_start: {|A| ld32 0[BP_a+IDX_i],%A;|B| ld32 0[B P_b+IDX_i],%B; |DP1| tcmp16s GT %AH,%BH,%P1;|DP0| tcmp 16s GT %AL,%BL,%P0;} {|C| ld32 0[BP_c+IDX_i],%B; |DP1| mulaa16s (%P1) %AH,%BH,%ACC2;|DP0 | mulaa16s (%P0) %AL,%BL,%ACC0;} L_loop_end: accadd %ACC0,$0,%ACC2 Cycle: 1+N / 2(2)+1=2+N

[0199] Note: Use DP1 and DP0 to process iterations i and i+1 in parallel Split the total into %ACC0 and %ACC2, then combine at the end Use the predicate flags %P1 and %P0 to calculate the accumulation in %ACC2 and %ACC0. Independently controlled by

[0200] Conditional accumulation using double DP with double MUL respectively

[0201] Below are examples of where a conditional HyperOp with four predicates can be used: This is an example. C Code int16 a[N],b[N],c[N]; int16 i; int32 sum=0; for(int i=0;i <N;i++) { if(a[i]>b[i]) sum+=a[i]*c[i]; }

[0202] HyperOp code (using both DPs with a 4-fold condition) #define BP_a %B1 #define BP_b %B2 #define BP_c %B3 repeat $0,$N-1,$4,IDX_i,L_loop_start,L_ loop_end {|DP1| movx16s $0,%ACC2;|DP0| movx16s $ 0,%ACC0;} L_loop_start: {|A| ld64 0[BP_a+IDX_i],%AB;|C| ld64 0[ BP_b+IDX_i],%C; |DP1| dtcmp16s GT %A,%CH,%P3P2; |DP0| dtcmp16s GT %B,%CL,%P1P0;} {|C| ld64 0[BP_c+IDX_i],%C; |DP1| dmulaa16s (%P3P2) %A,%CH,%ACC2; |DP0| dmulaa16s (%P1P0) %B,%CL,%ACC0;} L_loop_end: accadd %ACC0,$0,%ACC2 Cycle: 2+N / 4(2)+1=3+0.5N

[0203] Note: ●Process iterations i to i+3 in parallel: ● i and i+1 in DP1 ●i+2 and i+3 at DP0 DP0 performs dual operation, and DP1 performs dual operation. Split the total into %ACC0 and %ACC2, then combine at the end Use predicate flags %P0~P3 to separate product accumulations in %ACC0 and %ACC2. Controlled b[] and c[] have a different DM than a[] in order for 64-bit access to work. Must be R

[0204] Conditional memory using double DP

[0205] The following C code uses a conditional HyperOp to perform a conditional store where: This is an example of what can be done.

[0206] C Code int16 a[N],b[N],c[N],d[N]; int16 i; for(int i=0;i <N;i++) { if(a[i]>b[i]) d[i]=a[i]*c[i]; }

[0207] ASM Code

[0208] This example uses vector eigenfunctions (pseudo AM instructions) to access the double DP. #define BP_a %B1 #define BP_b %B2 #define BP_c %B3 #define BP_d %B4 #define IDX_i %I1 repeat $0,$N - 1,$2,IDX_i,L_loop_start,L_ loop_end L_loop_start: vtcmp16s GT [BP_a + IDX_i],[BP_b + IDX_i],% P1P0 vmul16s (%P1P0) [BP_a + IDX_i],[BP_c + IDX_ i],[BP_d + IDX_i] L_loop_end:

[0209] HyperOp code (dual conditional memory) #define BP_a %B1 #define BP_b %B2 #define BP_c %B3 #define BP_d %B4 #define IDX_i %I1 repeat $0,$N - 1,$2,IDX_i,L_loop_start,L_ loop_end L_loop_start: {|A| ld32 0[BP_a + IDX_i],%A;|B| ld32 0[B P_b + IDX_i],%B; |DP1| tcmp16s GT %AH,%BH,%P1;|DP0| tcmp 16s GT %AL,%BL,%P0;} {|C| ld32 0[BP_c + IDX_i],%C; |DP1| mul16s %AH,%CLH,%D1;|DP0| mul16s %AL,%CLL,%D0; |D| dst16 (%P1P0) %D1_D0,0[BP_d + IDX_i]; } L_loop_end:

[0210] Note: Use DP1 and DP0 to process iterations i and i+1 in parallel Use the predicate flags %P1 and %P0 to store 16-bit:16-bit data independently. Control (SIMD mode)

[0211] Conditional if-else-if example using conditional jumps

[0212] C Code absq=abs(q); if(absq <qmin) { qmin2=qmin; qmin=absq; imin=i; } else if(absq <qmin2) { qmin2=absq; }

[0213] ASM Code / / imin and qmin are stored as packed data imin_qmin (even address) abs16s q,absq / / absq=abs(q) tcmp16 LT absq,qmin,%P1 / / P1=(absq <qmin ) jmp (!%P1) L_else PNT / / If !P1 is true, qmin Skip Update tcmp16 LT absq,qmin2,%P0 / / P0=(absq <qmi n2) - Delay slot L_if: / / Update qmin and qmin2: mov16 qmin,qmin2 / / qmin2=qmin jmp L_end dmov16 i,absq,imin_qmin / / qmin=absq,imi Delay n=i-slots L_else: jmp (!%P0) L_end PNT DLY nop / / Delay slot mov16 absq,qmin2 / / Update only qmin2 L_end:

[0214] ASM code using DLY optimization abs16s q,absq tcmp16 LT absq,qmin,%P1 jmp (!%P1) L_else PNT tcmp16 LT absq,qmin2,%P0 / / Executes in the delay slot L_if: mov16 qmin,qmin2 jmp L_end dmov16 i,absq,imin_qmin / / Executed in delay slot L_else: jmp (!%P0) L_end PNT DLY mov16 absq,qmin2 / / Executes after JMP and in the delay slot Not performed L_end:

[0215] Conditional if-else-if example using conditional move

[0216] C Code absq=abs(q); if(absq <qmin) { qmin2=qmin; qmin=absq; imin=i; } else if(absq <qmin2) { qmin2=absq; }

[0217] ASM Code / / imin and qmin are stored as packed data imin_qmin (even address) abs16s q,absq / / absq=abs(q) tcmp16s LT absq,qmin,%P1 / / P1=(absq <qmi n) tcmp16s LT absq,qmin2,%P0 / / P0=(absq <qm in2) cmov16 (%P1) qmin,qmin2 / / If P1 is true, qmin n2=qmin cmov16 (%P1) absq,qmin / / qmin if P1 is true =absq cmov16 (%P1) i,imin / / if P1 is true, imin=i cmov16 (!%P1&%P0) absq,qmin2 / / else P0 is true If qmin2=absq Cycle: 7

[0218] HyperOp Code {|A| ld16 q, AL; |B| ld16 i,%BL; |DP1| mov16 %BL,%ACC3; / / ACC3=i |DP1| abs16s %AL,%ACC1; / / ACC1L=absq |D| dst16 %ACC3_ACC1,%ACC3;} / / ACC3H=i, ACC3L=absq {|A| ld32 imin_qmin,%A; / / AH=imin,AL=qm in |B| ld16 qmin2,%BL; / / BL=qmin2 |DP1| tcmp16 LT %ACC3L,%AL,%P1; / / P1=(a bsq <qmin) |DP0| tcmp16 LT %ACC1L,%BL,%P0;} / / P0=( absq <qmin2) {|DP1| if(%P1) cmov32 %ACC3,%A,%ACC2; / If / P1 is true, {ACC2H=i,ACC2L=absq} / / Otherwise, {ACC2H=imin,ACC2L=qmin} |DP0| if(%P1) cmov16 %AL,%BL,%ACC0; / / A CC0=(P1) ? qmin2:qmin |D| st32 %ACC2,imin_qmin;} / / imin:qmin= Update to ACC2H:ACC2L {|DP0| if(!%P1&%P0) cmov16 %ACC3L,%ACC0 L,%ACC0; / / Otherwise, ACC0L=(P0) ? absq:qm in |D| st16 %ACC0,qmin2;} / / Update to qmin2=ACC0L do Cycle: 4

[0219] Note: Use P1 and %P0 to determine the Boolean results of the IF and ELSE IF tests. Retaining the fruit imin and qmin are stored in memory as packed 16:16 Assume that Use %P1 and %P0 with CSEL to set pairwise state variables when possible. Conditionally Update

[0220] Combining tests using predicate flags

[0221] C Code int16 a,b,c,d,e; void test() { a=(b <c)&&(d<e); }

[0222] ASM Code tcmp16s LT b,c %P0 / / P0=(b <c) tcmp16s LT d,e,%P1 / / P1=(d <e) cmov16 (%P0&%P1) $1,$0,a / / a=(P0&P1)1:0

[0223] Note: The compiler replaces the && operator with the & operator: ●a=(b <c)&(d<e)

[0224] Combining tests using register files

[0225] C Code int16 a,b,c,d,e; void test() { a=(b <c)&&(d<e); }

[0226] ASM Code tcmp16s LT b,c,%R0 / / R0=(b <c) tcmp16s LT d,e,%R1 / / R1=(d <e) and16 %R0,%R1,a / / a=R0&R1

[0227] Note: The compiler replaces the && operator with the & operator: ●a=(b <c)&(d<e)

[0228] Conditional jump to subroutine

[0229] C Code int16 a,b,c,d,e,f; if((a <b)&(c<e)|(d> f)) foo();

[0230] ASM Code tcmp16s LT a,b,%R1 / / R1=(a <b) tcmp16s LT c,e,%R2 / / R2=(c <e) tand16 NZ %R1,%R2,%P0 / / P0=(a <b)&(c<e) tcmp16s GT d,f,%P1 / / P1=(d>f) jsr (%P0|%P1) foo / / If P0|P1 is true, execute foo() to go

[0231] Note: Use TAND16 instead of AND16 Note that Pn cannot be dstD in any ALU operation other than TEST. I want to

[0232] Allocation of logical / test operation results

[0233] C Code int16 a,b,c,d,e,f,result; result=((a <b)&(c<e)|(d> f));

[0234] ASM Code tcmp16s LT a,b,%R1 / / R1=(a <b) tcmp16s LT c,e,%R2 / / R2=(c <e) and16 %R1,%R2,%R3 / / P3=(a <b)&(c<e) tcmp16s GT d,f,%R4 / / R4=(d>f) or16 %R3,%R4,result / / result=(R3|R4)

[0235] Any of the various aspects described herein may be implemented, for example, as computer-implemented methods. and in various forms, such as computer-readable storage media and computer systems. The system may be implemented in any form. Application Specific Integrated Circuit (ASIC) One or more custom-designed hardware devices provide FPGA (Field Programmable Gate Array) One or more programmable gate arrays The hardware element provides one or more processors that execute stored-program instructions. or any combination of the above.

[0236] In some embodiments, the non-transitory computer readable storage medium includes program instructions and The program instructions may be configured to store program information and / or data. When executed by a computer system, the method may be implemented as, for example, a method described herein. any of the embodiments of the method described herein, or any combination of the embodiments of the method described herein; any subset of any of the method embodiments described herein, or Any combination of such subsets may be performed by the computer system.

[0237] In some embodiments, the computer system comprises a processor (or a set of processors). The program may be configured to include a program processor and a storage medium, in which case the storage medium may include a program The instructions are stored in the storage medium, where the processor reads and executes the program instructions from the storage medium. wherein the program instructions are configured to perform the various methods described herein. any of the embodiments of (or any combination of the method embodiments described herein, any subset of any of the method embodiments described herein, or A computer system may be implemented to implement the method described above (any combination of such subsets). The system may be implemented in any of a variety of forms, for example, a computer system refers to a personal computer (any of the various implementations of a personal computer) (commonly in the form of a workstation, a computer on a card, or a special-purpose computer in a box) computers, server computers, client computers, handheld devices , mobile devices, wearable computers, detection devices, televisions, video capture devices, biometrics The computer system may be one or Any of the various computational results disclosed herein may be displayed on a display. may be displayed via a device or otherwise output via a user interface device It may be presented as.

[0238] The device comprises a plurality of processors and a plurality of data processors coupled to the plurality of processors in a sparse arrangement. A specific data memory router may have multiple data memory - Send the received message to at least one other data memory of the router a particular processor among the plurality of processors configured to relay a plurality of predicate functions; An instruction with multiple predicate flags must have at least one predicate flag set. is configured to run conditionally.

[0239] In the above-described apparatus, multiple predicate flags are associated with data paths included in a particular processor. and at least a first set of predicate flags for the particular processor. Contains a second set of predicate flags associated with the unit.

[0240] In the above-mentioned device, a method for setting at least one predicate flag among a plurality of predicate flags is provided. To do so, the particular processor compares the first value with the second value in response to execution of a test instruction; The method is further configured to generate a result and set at least one predicate flag based on the result. can be.

[0241] In the above-mentioned device, in order to compare the first value with the second value, the specific processor and performing a logical operation using the first value and the second value to generate a result. do.

[0242] In the above-mentioned device, a method for setting at least one predicate flag among a plurality of predicate flags is provided. Therefore, a particular processor may require timing behavior of the datapaths contained within that particular processor. and further configuring at least one predicate flag based at least in part on the information indicated. It is composed of:

[0243] In the above-mentioned device, a method for setting at least one predicate flag among a plurality of predicate flags is provided. Therefore, a particular processor may have different address generator units depending on the type of address generator unit contained in the particular processor. setting at least one predicate flag based at least in part on the information indicative of the filtering behavior. The method is further configured to:

[0244] In the aforementioned apparatus, in order to conditionally execute instructions, a particular processor may include a plurality of predicates. Flags are used to specify one or more of the The datapath slot is further configured to be conditionally executed.

[0245] The method further comprises: selecting, by a particular processor of the plurality of processors, one of the plurality of predicate flags; setting at least one predicate flag of the plurality of processors in a sparse manner; and connecting the plurality of processors to a plurality of data memory routers in a My particular processor allows conditional execution of instructions using multiple predicate flags. Steps are provided.

[0246] In the above method, multiple predicate flags are associated with the datapaths contained in a particular processor. and at least a first set of predicate flags for the particular processor. Contains a second set of predicate flags associated with the unit.

[0247] In the above method, a step for setting at least one predicate flag among a plurality of predicate flags is The step is to generate a first value and a second value in response to executing a test instruction by a particular processor. comparing the values ​​of the predicates to generate a result; and based on the result, generating at least one predicate flag. and setting a tag.

[0248] In the above method, the step of comparing the first value and the second value includes: The method includes performing logical operations using the input and output to produce a result.

[0249] In the above method, a step for setting at least one predicate flag among a plurality of predicate flags is A step is a timing step that is performed by a particular processor to determine the timing of the datapaths contained in that particular processor. a scheduling step for setting at least one predicate flag based at least in part on the information indicating the scheduling behavior; Includes step.

[0250] In the above method, a step for setting at least one predicate flag among a plurality of predicate flags is The step is performed by a particular processor using the address generator unit contained in the particular processor. at least one predicate flag based at least in part on information indicative of the timing behavior of the The step of setting

[0251] The method of claim 22 further comprises conditionally executing instructions by a particular processor. The step of performing the predicate flags is to use the predicate flags to determine the data path included in the particular processor. conditionally executing one or more datapath slots included in

[0252] The device comprises a plurality of processors and a plurality of data processors coupled to the plurality of processors in a sparse arrangement. A specific data memory router may have multiple data memory - Send the received message to at least one other data memory of the router a particular processor among the plurality of processors configured to relay the received instruction; Based on this, the data included in a specific data path among multiple data paths included in a specific processor a plurality of arithmetic logic circuits, each of which is connected to a logic circuit, for selectively activating a subset of the plurality of arithmetic logic circuits; The set is configured to execute the received instructions.

[0253] In the above-mentioned apparatus, a specific logic circuit is provided for selectively activating a subset of the plurality of arithmetic logic units. The processor decodes the instruction to generate a decoded instruction and uses the decoded instruction to , further configured to selectively activate a subset of the plurality of arithmetic logic units.

[0254] In the above-mentioned device, a specific processor among the plurality of processors executes a plurality of Routing data between individual arithmetic logic units in a subset of the arithmetic logic units of The method is further configured to:

[0255] In the above-mentioned device, between individual arithmetic logic circuits included in a subset of a plurality of arithmetic logic circuits To route data in a particular processor, a particular data path must be included. selectively changing the state of at least one multiplexing circuit of the plurality of multiplexing circuits; Further composed.

[0256] In the above-mentioned device, a specific arithmetic logic circuit among the plurality of logic circuits includes at least an adder circuit. Includes roads.

[0257] In the above-mentioned device, a specific arithmetic logic circuit among the plurality of logic circuits executes an instruction. It includes a look-up table configured to store the offsets to use.

[0258] In the aforementioned device, the instructions specify a log-probability operation.

[0259] The method includes: selectively activating a subset of a plurality of arithmetic logic units included in a particular data path of the a plurality of processors configured to communicate with a plurality of data memory routers in a sparse array; and a step of performing a plurality of calculations by a particular processor of the plurality of processors. and executing the instruction using a subset of the technical logic.

[0260] In the above method, the step of selectively activating a subset of the plurality of arithmetic logic units comprises: decoding the instructions to generate decoded instructions; and generating a plurality of instructions using the decoded instructions. and selectively activating a subset of the arithmetic logic units.

[0261] The method includes: generating individual arithmetic logic circuits included in a subset of the plurality of arithmetic logic circuits based on the instruction; The method further comprises routing data between the logic circuits.

[0262] In the above-mentioned method, the arithmetic logic circuits included in the subset of the plurality of arithmetic logic circuits are The step of routing data in the Selectively changing the state of at least one multiplexing circuit among the multiplexing circuits included The method includes the step of:

[0263] In the above-mentioned method, a specific arithmetic logic circuit among the plurality of logic circuits includes at least an adder circuit. Includes roads.

[0264] In the above-mentioned method, a specific arithmetic logic circuit among the plurality of logic circuits is A sequence that stores in a lookup table the offsets to be used when executing instructions. It also has a step.

[0265] In the above method, the instructions specify a log-probability operation.

[0266] The above embodiments have been described in connection with preferred embodiments, and the It is not intended to be limiting to any particular form, but rather to include such alternative forms, Modifications, and equivalents, are intended to cover embodiments of the invention as defined by the appended claims. It is intended to include as much as can reasonably be included within the spirit and scope of the present invention.

Claims

1. 1. An apparatus comprising: a multiprocessor including a plurality of processors; a plurality of message nodes coupled to said plurality of processors in a sparse arrangement, A specific message node among the plurality of message nodes is receiving a first message including a payload and routing information; Based on the routing information and the operation information of the multiprocessor, Select a different message node among the message nodes, the routing information for the first message based on the different message nodes; to generate a second message; Sending the second message to the different message node. With multiple message nodes configured as An apparatus comprising:

2. the routing information includes information indicating an absolute destination for the first message; 10. The apparatus of claim 1.

3. The routing information is a message from the particular message node to the first message. When the message reaches another message node among the plurality of message nodes specified as a destination, 2. The apparatus of claim 1, further comprising information indicating a relative offset between the first and second inputs.

4. The specific message node is Responding to determining that the first message is a broadcast message. generating a plurality of third messages based on Sending each of the plurality of third messages to a corresponding one of the plurality of message nodes. Attach The apparatus of claim 1 further configured to:

5. The method of claim 1 , wherein the first message includes at least a portion of the operational information. Device.

6. To select the different message node, the particular message node using information contained in the first message specifying the particular message node 2. The method of claim 1, further configured to retrieve the next destination from a table included in the node. Equipment.

7. 1. A method comprising: A specific message node among multiple message nodes in a multi-processor array A first message including a payload and routing information is received by the message node. and The particular message node transmits the routing information and the multi-processor information. and selecting different message nodes from the plurality of message nodes based on the operational information of the message node array. selecting a geonode; The particular message node sends a second message based on the different message node. generating a message; The particular message node sends the second message to the different message node. Steps for sending the message A method for providing the above.

8. The step of generating the second message may include: modifying the routing information to generate modified routing information included in said second message. The method of claim 7, comprising the step of:

9. the routing information includes information indicating an absolute destination for the first message; The method of claim 7.

10. The routing information is a message from the particular message node to the first message. When the message reaches another message node among the plurality of message nodes specified as a destination, 8. The method of claim 7, further comprising: information indicating a relative offset between the first and second inputs.

11. The specific message node sends a message to a process included in the multi-processor array. Receives a request from an element and executes a message based on the request by the particular message node.

8. The method of claim 7, further comprising generating a third message based on the first message.

12. Responding to determining that the first message is a broadcast message. generating a plurality of third messages based on Each of the plurality of third messages is sent to a corresponding one of the plurality of message nodes. Steps for sending the The method of claim 7 further comprising:

13. From the table, the particular message node retrieves at least one of the routing information. using a portion of the message to retrieve information indicating a next destination for the first message. The method of claim 7 further comprising:

14. 1. An apparatus comprising: configured to receive a first message including a payload and routing information; Also, a router circuit coupled to the message bus; 1. A network processor circuit, comprising: Based on the routing information and operational information regarding the multi-processor array, , identifying a plurality of message nodes connected together via the message bus; Select the message node in the routing information for the first message based on the particular message node; to generate the second message A network processor circuit configured as follows: Equipped with The router circuit routes the second message to the particular message node. The apparatus further comprising:

15. the routing information includes information indicating an absolute destination for the first message; 15. The apparatus of claim 14.

16. The routing information includes information about a plurality of messages designated as destinations of the first message. a message node including information indicating a relative offset to a given message node among the message nodes; 15. The apparatus of claim 14.

17. 15. The method of claim 14, further comprising: configuring circuitry configured to store the operational information. Equipment.

18. 15. The method of claim 14, wherein the first message includes at least a portion of the operational information. Equipment.

19. The network processor circuit is a processor included in the multi-processor array. receiving a request from an element and generating a third message based on said request; and the router circuitry is configured to select the plurality of routers based on information contained in the third message. and sending the third message to a different message node among the plurality of message nodes. The apparatus of claim 14 , further configured to:

20. a table configured to store a plurality of entries; The processor circuit uses information contained in the first message to select the next address from the table. The apparatus of claim 14 , further configured to retrieve a destination of the

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