Improvements in or relating to quantum computing

Abstract

To provide improved surface ion traps which can better realize requirements of each function carried out in a quantum computer, while minimizing power consumption and use of valuable space on a silicon chip.SOLUTION: A surface ion trap comprises a plurality of electrodes and DACs 26, 28, each electrode being controlled by a DAC, where a first DAC controls electrodes configured to trap an ion in a first area and a second DAC controls electrodes configured to trap an ion in a second area. The first DAC operates with low noise and low bandwidth, and the second DAC operates with a high bandwidth and high noise.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to improvements in or relating to quantum computing, and in particular to an improved digital-to-analog converter (DAC) for optimized surface ion traps. [Background technology]

[0002] Generally, unlike so-called "classical computing," quantum computing relies on the quantum mechanical properties of particles or matter to generate or modify data. Data may be represented by quantum bits or "qubits," which are two-state quantum mechanical systems. Unlike classical computing, qubits may be in a superposition of quantum states. Another feature of quantum computing is entanglement between qubits, where the state of one particle or atom is influenced by the state of another particle or atom.

[0003] Quantum mechanical qubits can simultaneously encode information as combinations of zeros and ones. This property enables many complex numerical applications that have traditionally been difficult with classical computers. Examples include artificial intelligence, image processing and recognition, cryptography, or secure communications.

[0004] Within the ionic hyperfine electron states (Zeeman split states) this can be revealed by the use of magnetic fields and different electronic levels used as different qubit states, and electrons moving between levels using microwave radiation or lasers.

[0005] In ion trap quantum computers, surface ion traps are used to control ions used in quantum computing, and surface electrodes are used to generate electric fields to manipulate and trap ions suspended in free space. The surface electrode potential of the ion trap is in turn controlled by a DAC. State-of-the-art quantum computers use many DACs of the same type, for example, 16-bit DACs with update rates exceeding 1 MHz.

[0006] The performance of a surface ion trap can be considered in terms of meeting requirements for noise, bandwidth, power, and resolution, and a DAC is selected for use that best meets these requirements throughout the surface ion trap. Summary of the Invention

[0007] However, different functions performed by quantum computers have different requirements: for example, gating operations require DACs with low noise and low bandwidth, while shuttling operations require faster DACs that can tolerate more noise.

[0008] Ion traps currently use the same DACs throughout the ion trap, with properties that are sufficient throughout the entire ion trap: they have sufficient bandwidth in the shuttling region and low enough noise to allow gating operations to be performed.

[0009] Meeting the various requirements for performing different functions with a single type of DAC is difficult and requires a large amount of space as well as a large portion of the power budget.

[0010] Therefore, there is a requirement for improved surface ion traps that can better realize the requirements of each function performed in a quantum computer while minimizing power consumption and use of valuable space on a silicon chip.

[0011] It is against this background that the present invention was born.

[0012] According to the present invention, there is provided an ion trap comprising a plurality of electrodes and DACs, each controlled by a DAC, wherein a first set of DACs controls electrodes configured to trap ions in a first region and a second set of DACs controls electrodes configured to trap ions in a second region, the first set of DACs being configured to operate with low noise and the second set of DACs being configured to operate with high bandwidth. By having different types of DACs for different regions, the DACs can be selected to have characteristics suitable for the purpose of the region in which they are located. The first set of DACs may be a different type of DAC than the second set of DACs.

[0013] A first set of DACs may be configured to operate at low noise and low bandwidth, and a second set of DACs may be configured to operate at high bandwidth, but as a result have a larger noise profile.

[0014] A low noise DAC may have a noise level of less than 10 nV / rtHz, or more specifically, less than 5 nV / rtHz. A high bandwidth DAC may have a bandwidth of 1 million updates per second (1 MSPS).

[0015] By selecting a DAC for a particular area, a DAC with the most suitable characteristics can be selected. This also helps minimize space, as smaller DACs can be used in areas where minimizing noise is less important. DACs with larger footprints can be used in areas where minimizing noise is more important.

[0016] There may also be a set of additional electrodes configured to trap ions in the first region, a third set of DACs, and each additional electrode controlled by one of the third set of DACs, where the third set of DACs is configured to operate at high bandwidth and high noise. The additional electrodes may be interleaved with the multiple electrodes. Thus, the additional electrodes may be used for high speed applications, and the original first electrodes may be used for low noise and low bandwidth applications.

[0017] The first set of DACs may be of the same type as the second set of DACs, and each DAC has two operating modes: a first mode with low noise and low bandwidth, and a second mode with high noise and high bandwidth. Thus, different operating modes can be used for different applications.

[0018] Each DAC has an output and may include a first sub-DAC and a second sub-DAC, and the output of the DAC is selected by one or more of an output switch connected to one or more of the sub-DACs, a power switch connected to one or more of the sub-DACs, and / or an analog summation of the sub-DACs.

[0019] The first sub-DAC may include a capacitive architecture, and the second sub-DAC may include a resistive architecture. In particular, the first sub-DAC may have no or minimal resistive elements to operate with very low noise. The second sub-DAC may have no or minimal capacitive elements. Thus, the second sub-DAC may operate at high speed and occupy only a small area, but as a result, generate more noise.

[0020] The first and second sub-DACs may be of different formats. The DAC may comprise a precision code portion for operating in a first mode with low noise and low bandwidth and a second high-speed code portion for operating in a second mode with high noise and high bandwidth, and the surface ion trap further comprises a switch for switching between the precision code portion and the high-speed code portion.

[0021] The first mode may include a feedback loop to avoid drift in low-noise, low-bandwidth applications. The feedback loop may comprise a proportional-integral-derivative controller configured to control the output to a reference output. The DAC may use selectable compensation and / or a variable gain stage.

[0022] The ion trap may be a surface ion trap.

[0023] According to the present invention, there is provided an ion trap quantum computer comprising the above-described ion trap.

[0024] According to the present invention, DACs can be selected according to the purpose and design requirements of the area (such as footprint size, noise, and speed). There is a balance between noise, bandwidth, power, and footprint size. For example, in the gate area where noise reduction is important, low-noise DACs can be used. Low-noise DACs often have a larger footprint. Conversely, in the shuttling area, only a small area may be available and high-bandwidth DACs can be used. There may be higher noise associated with such DACs, but in the shuttling area, this may be acceptable.

[0025] The invention will now be more particularly described, by way of example only, with reference to the accompanying drawings in which: [Brief explanation of the drawings]

[0026] [Figure 1]FIG. 1 shows a schematic diagram of an x-junction device in a trapped ion quantum computer with a DAC tailored for a specific use for a given region. [Figure 2] 1 shows a schematic diagram of two DACs used independently in the same area. [Figure 3] Figure 3A shows the potential energy plots of two DACs operating independently in the same region, and Figure 3B shows the potential energy plots of two DACs operating independently in the same region. [Figure 4] 1 shows a dual electrode scheme with a shuttling control DAC with a series of fast switches for reference. [Figure 5] 1 shows a surface view of a surface ion trap with several pairs of axial electrodes. [Figure 6] FIG. 1 shows a surface view of a surface ion trap with interleaved electrode pairs. [Figure 7] A single hybrid DAC architecture is shown to achieve either accuracy or high speed. [Figure 8] A single hybrid DAC architecture is presented to achieve high speed and low drift. [Figure 9] 1 shows a selectable compensation scheme in the output stage. [Figure 10] 1 illustrates a scheme for using a variable gain stage in a feedback loop. DETAILED DESCRIPTION OF THE INVENTION

[0027] The invention will now be more particularly described, by way of example only, with reference to the accompanying drawings in which:

[0028] The present invention allows for tailoring DAC performance to the specific requirements for use of surface ion traps in a given region of a quantum computer. Referring to FIG. 1, there is an example showing different DACs used in different regions of a quantum computer in accordance with the present invention. FIG. 1 shows an x-junction device 12 in a trapped ion quantum computer 10. The x-junction device 12 is divided into regions. Depending on the function performed in each region, the regions of the x-junction device 12 can be divided into crystal operations 14, junction shuttling 16, logic region / gate zone 18, and linear shuttling 20. Each region of the x-junction device 12 has different requirements for noise, bandwidth, drift, linearity, resolution, and power consumption.

[0029] The x-junction 12 comprises a plurality of electrodes 22 configured to trap ions in a region of the x-junction device 12. Each electrode 22 is driven by a DAC to perform the function of a region of the x-junction device 12.

[0030] Dividing the x-junction device 12 into regions according to the requirements of that region of the device facilitates the selection of DACs that can achieve the best performance in each region of the device. Although an x-shaped junction is shown here, the junction need not be x-shaped, but may be divided into regions simply by the function of the electrodes.

[0031] For example, the logic region 18 of the x-junction device 12 requires a 16-bit DAC with low noise and high resolution, and a low noise level, e.g., less than 100 nV / rtHz, preferably less than 10 nV / rtHz, or especially less than 5 nV / rtHz. The level can be selected to meet the requirements of this region of the x-junction device 12. An exemplary DAC is the AD5791, which has 20-bit resolution with a 7.5 nV / rtHz noise spectral density that is 7.5 μV RMS over a 1 MHz bandwidth. The AD5791 settles to within 1 μs of 0.02% and has a 1 MSPS update rate.

[0032] For the low noise region, there can be less than 10 μV total RMS noise with a 10 V full-scale deflection over 1 hour.

[0033] On the other hand, the linear shuttling 20 and junction shuttling 16 regions of the x-junction device 12 require high bandwidth and low resolution. These regions may preferably have an update rate exceeding 1 million updates per second. One example is an 8-bit DAC with 100 MHz bandwidth, which may be best selected to meet the requirements for electrode control in these regions of the device. An example DAC for the linear shuttling region or junction shuttling may be an LTC1668 with a 50 MSPS update rate, 16-bit resolution, and 10 ns settling with 50 pA / rtHz noise.

[0034] Dividing the x-junction device 12 into regions with sets of DACs configured to operate with specific performance characteristics can reduce the power consumption of the quantum computer while optimizing the use of space on the silicon chip. However, shuttling still occurs in the logic regions, and therefore optimizing performance is desirable.

[0035] Referring to Figure 2, there is a scheme for combining the effects of two different DACs in the same region. Using the scheme shown in Figure 2, further increases in performance of surface ion traps requiring dual functions such as shuttling speed and low-noise quantum operation can be achieved. The scheme shown in Figure 2 can be implemented, for example, in the gate zone / logic region 18 of a device requiring shuttling in the gate zone region and therefore requiring high bandwidth for shuttling in addition to low noise and high resolution.

[0036] 2 shows two DACs 26 and 28 with independent DAC outputs. A selection mechanism 24 allows for the selection of the DAC that can meet the requirements of the task to be performed and achieve the best control over the position of the ions.

[0037] The first DAC 26 may have a capacitive architecture and may therefore be used in applications where low noise is required. In particular, the first DAC has no resistive components and is therefore very quiet. The second DAC may have a resistive architecture and may therefore be used in applications where high bandwidth is required.

[0038] A selection mechanism 24 allows the electric field at the ion location to be generated from either or both of two independent DAC outputs.

[0039] The selection mechanism 24 can be, but is not limited to, an output that connects or disconnects the DAC as needed, a power switch that enables or disables the DAC output as needed, an analog summing circuit with appropriately weighted DAC outputs, e-field summing that splits the electrode area into two separate interleaved areas, or part of the DAC design itself, such as a hybrid DAC.

[0040] Alternatively or additionally, the selection mechanism 24 may combine one or more of these mechanisms.

[0041] Figure 3 shows a potential energy plot for the scheme with two independently operable DACs shown in Figure 2. Figure 3A shows an example where the first DAC "DAC" 1 is a high speed DAC and is set to 0V everywhere. The second DAC "DAC2", a low noise DAC, provides a potential well of the total potential in the gate zone / logic region 18.

[0042] Figure 3B shows the potential energy plot for shuttling in and out of the gating zone / logic region 18 by adjusting the DAC1 output. The total potential shifts to the right. The potential well created by DAC2 does not change, so there is no bandwidth requirement imposed on DAC2.

[0043] In the embodiment shown in FIG. 2, it is important that the performance of the DACs does not interfere with each other. If the selection mechanism 24 is an output switch, unused DACs can be temporarily switched off or disconnected from the ion to avoid noise contribution. Alternatively, a power switch can be used to power down unused DACs. Alternatively, the DAC selection mechanism 24 can be included in the DAC design itself, which may prevent the need to separately and independently quiet inactive DACs. The DACs can have internal switches that modify the DAC architecture and prevent unused DAC contributions.

[0044] In some embodiments, switches are undesirable due to switching noise or charge injection. The DAC can be configured so that the noise output is code dependent, with the idle state during quantum operation being at the lowest noise level. This is typical of DACs where the output noise is dominated by the input reference noise and is therefore reduced with codes that produce a smaller percentage of the reference as the output.

[0045] Figure 4 shows a scheme in which the shuttling control DAC is implemented as a series of high-speed switches to a reference, and the gated zone DAC is implemented as a static filtered reference voltage. The electrodes are positioned so that the qubit sees the electric field sum of the two outputs. The shuttling DAC shorts the electrodes to GND for an output of 0V, minimizing noise on the potential well during quantum operation.

[0046] FIG. 5 shows a surface view of a surface ion trap with several pairs of axial electrodes.

[0047] Figure 6 shows a surface view of a surface ion trap with a single axially positioned electrode replaced by an interleaved electrode pair. Alternatively, any other electrode shape may be used that achieves the desired effect of e-field summation on the ions.

[0048] Figure 7 shows a scheme of a hybrid DAC with a custom architecture, where the selection mechanism is included in the DAC design itself. Figure 7 shows an example where locations require precision or high-speed DACs at different times. A single hybrid DAC architecture is created by combining precision and high-speed codes.

[0049] 8 shows another scheme of hybrid DAC architecture for locations requiring high speed or low drift at various times. This scheme includes a proportional-integral-derivative (PID) controller and a slow feedback loop. The slow feedback loop checks the level back to the reference input and facilitates adjustment.

[0050] If low noise bandwidth / high speed devices are required at different times, the bandwidth can be dynamically adjusted within the DAC output buffer.

[0051] Figure 9 shows an additional scheme for a hybrid DAC architecture using selectable compensation in the output stage. Figure 10 shows how to use a variable gain stage in the feedback loop (using the open-loop gain of the amplifier). This is also possible using a switchable filter.

[0052] Various further aspects and embodiments of the present invention will be apparent to those skilled in the art in view of the present disclosure.

[0053] As used herein, "and / or" should be taken as a specific disclosure of each of the two specified features or components with or without the other. For example, "A and / or B" should be taken as a specific disclosure of each of (i) A, (ii) B, and (iii) A and B, as if each were individually set forth herein.

[0054] Unless the context dictates otherwise, the above feature descriptions and definitions are not limited to any particular aspect or embodiment of the invention, but apply equally to all aspects and embodiments described.

[0055] Those skilled in the art will further appreciate that although the present invention has been described by way of example with reference to certain embodiments, it is not limited to the disclosed embodiments and alternative embodiments may be constructed without departing from the scope of the invention as defined in the appended claims.

Claims

1. An ion trap comprising: An electrode; a digital-to-analog converter (DAC) connected to the electrode; a selection mechanism; The ion trap, wherein the selection mechanism is configured to alter at least one parameter of a signal delivered from the DAC to the electrode, the at least one parameter including noise or bandwidth.

2. The ion trap of claim 1, wherein the DAC is configured to operate in a low noise mode.

3. The ion trap of claim 2, wherein the low noise mode includes a low bandwidth.

4. The ion trap of claim 1, wherein the DAC is configured to operate in a high bandwidth mode.

5. The ion trap of claim 4, wherein the high bandwidth mode includes high noise.

6. The ion trap of claim 1, wherein the DAC further comprises a first sub-DAC and a second sub-DAC.

7. The ion trap of claim 6, wherein the first sub-DAC comprises a capacitive architecture and the second sub-DAC comprises a resistive architecture.

8. An ion trap as described in claim 6, wherein the signal delivered from the DAC to the electrode is selectable from a first mode or a second mode, and the first mode or the second mode includes at least a portion of the output of the first sub-DAC, the output of the second sub-DAC, or both.

9. An ion trap as described in claim 8, wherein the first mode and the second mode are selectable by (i) an output switch connected to the first sub-DAC and the second sub-DAC, (ii) a power switch connected to the first sub-DAC and the second sub-DAC, (iii) an e-field sum of the outputs of the first sub-DAC and the second sub-DAC, (iv) an analog sum of the outputs of the first sub-DAC and the second sub-DAC, or (v) any combination thereof.

10. The ion trap of claim 2, wherein the low noise mode includes a feedback loop.

11. The ion trap of claim 10, wherein the feedback loop includes a proportional-integral-derivative (PID) controller.

12. The ion trap of claim 10, wherein the feedback loop includes a variable gain stage.

13. The ion trap of claim 1 further comprising a selectable compensation stage.

14. The ion trap of claim 8, wherein the noise or bandwidth of the signal delivered from the DAC to the electrodes is modified by the signal control mechanism before performing an action on the ions.

15. The ion trap of claim 1, wherein the DAC comprises a hybrid DAC.

16. The ion trap of claim 15, wherein the selection mechanism includes at least a precision code or a high speed code.

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