Semiconductor element

Abstract

To provide a semiconductor element in which the leak current and the turn-on time are reduced.SOLUTION: In a semiconductor element including Group-III nitride semiconductor, a polarization super-junction region PSJ where a fourth semiconductor layer 14 does not exist is provided in a region between a gate electrode 20 and a drain electrode 22 on a third semiconductor layer 13. A thickness D2 of the third semiconductor layer 13 in the polarization super-junction region PSJ is 30 nm or more. A difference D3 between a thickness D1 of the third semiconductor layer 13 below the fourth semiconductor layer 14 and the thickness D2 of the third semiconductor layer 13 in the polarization super-junction region PSJ is 15 nm or more. The leak current is 1 μA or less and the turn-on time is 20 ns or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices. [Background technology]

[0002] A field effect transistor (FET) having a polarization super junction region is known as a semiconductor element using a group III nitride semiconductor (for example, Patent Document 1).

[0003] Patent Document 1 discloses a structure in which a first semiconductor layer made of undoped GaN, a second semiconductor layer made of undoped AlGaN, a third semiconductor layer made of undoped GaN, and a fourth semiconductor layer made of p-GaN are stacked in this order, a gate electrode is provided on the fourth semiconductor layer, and a source electrode and a drain electrode are provided on the second semiconductor layer so as to sandwich the gate electrode, and the fourth semiconductor layer is not present in the region on the third semiconductor layer between the gate electrode and the drain electrode. This region without the fourth semiconductor layer is called a polarization super junction region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-146369 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the inventors' investigations revealed that depending on the thickness of the third semiconductor layer below the fourth semiconductor layer and the thickness of the third semiconductor layer in the polarization super junction region, the leakage current and turn-on time may increase.

[0006] The present invention has been made in view of the above background, and aims to provide a semiconductor device with reduced leakage current and reduced turn-on time. [Means for solving the problem]

[0007] One aspect of the present invention is In a semiconductor device using a Group III nitride semiconductor, an undoped first semiconductor layer; an undoped second semiconductor layer provided on the first semiconductor layer and having a band gap energy larger than that of the first semiconductor layer; an undoped third semiconductor layer provided on the second semiconductor layer and having a band gap energy smaller than that of the second semiconductor layer; a p-type fourth semiconductor layer provided on the third semiconductor layer; a gate electrode provided on the fourth semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer at a position facing the source electrode with the gate electrode interposed therebetween, a polarization super junction region in which the fourth semiconductor layer is not present is provided in a region between the gate electrode and the drain electrode on the third semiconductor layer; The thickness of the third semiconductor layer in the polarization super junction region is 30 nm or more; a difference between a thickness of the third semiconductor layer under the fourth semiconductor layer and a thickness of the third semiconductor layer in the polarization super junction region is 15 nm or more; The semiconductor element has a leakage current of 1 μA or less and a turn-on time of 20 ns or less. [Effects of the Invention]

[0008] In the above embodiment, the thickness of the third semiconductor layer in the polarization super junction region is 30 nm or more, the difference between the thickness of the third semiconductor layer below the fourth semiconductor layer and the thickness of the third semiconductor layer in the polarization super junction region is 15 nm or more, and the leakage current can be set to 1 μA or less and the turn-on time to 20 ns or less.

[0009] As described above, according to the above aspect, it is possible to provide a semiconductor device with reduced leakage current and reduced turn-on time. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing the configuration of a semiconductor element according to Embodiment 1, taken along a plane perpendicular to the main surface of a substrate. [Figure 2] Graph showing the relationship between thickness D2 and turn-on time. [Figure 3] Graph showing Mg concentration distribution in the depth direction. [Figure 4] Graph showing the relationship between Mg concentration and turn-on time. [Figure 5] 10 is a graph showing the in-plane variation in the total film thickness of the third semiconductor layer and the fourth semiconductor layer. [Figure 6] Graph showing the in-plane variation of thickness D2. [Figure 7] 1 is a graph showing current-voltage characteristics. [Figure 8] Graph showing the relationship between thickness D2 and leakage current. [Figure 9] Graph showing the relationship between thickness D2 and carrier concentration in the 2DEG and 2DHG. DETAILED DESCRIPTION OF THE INVENTION

[0011] a gate electrode provided on the fourth semiconductor layer; a source electrode provided on the second semiconductor layer; and a drain electrode provided on the second semiconductor layer at a position facing the source electrode with the gate electrode interposed therebetween; a polarization super junction region in which the fourth semiconductor layer is absent is provided in a region on the third semiconductor layer between the gate electrode and the drain electrode; a thickness of the third semiconductor layer in the polarization super junction region is 30 nm or more; a difference in thickness between the third semiconductor layer below the fourth semiconductor layer and the third semiconductor layer in the polarization super junction region is 15 nm or more; a leakage current of 1 μA or less; and a turn-on time of 20 ns or less.

[0012] In the semiconductor element, the difference between the thickness of the third semiconductor layer below the fourth semiconductor layer and the thickness of the third semiconductor layer in the polarization super junction region may be 20 nm or more.

[0013] In the semiconductor element, the third semiconductor layer below the fourth semiconductor layer may have a thickness of 90 nm or more.

[0014] In the semiconductor device, the p-type impurity concentration of the third semiconductor layer in the polarization super junction region is 5×10 18 / cm 3 It may be the following:

[0015] In the semiconductor element, the p-type impurity concentration of the third semiconductor layer in the polarization super junction region is 1×10 18 / cm 3 It may be the following:

[0016] In the semiconductor element, the concentration of two-dimensional electron gas formed in the first semiconductor layer near the interface between the first semiconductor layer and the second semiconductor layer is 1.2 × 10 13 / cm 2The concentration of the two-dimensional hole gas formed in the third semiconductor layer near the interface between the second semiconductor layer and the third semiconductor layer is 0.8 × 10 13 / cm 2 The difference between the two-dimensional electron gas concentration and the two-dimensional hole gas concentration is 0.8 × 10 13 / cm 2 It may be the following:

[0017] In the semiconductor element, the in-plane variation in thickness of the third semiconductor layer in the polarization super junction region may be 10 to 30 nm.

[0018] (Embodiment 1) 1. Overview of semiconductor elements Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to embodiment 1, taken perpendicular to the main surface of a substrate. As shown in Fig. 1, the semiconductor device according to embodiment 1 includes a substrate 10, a first semiconductor layer 11, a second semiconductor layer 12, a third semiconductor layer 13, a fourth semiconductor layer 14, a p-type contact layer 15, a gate electrode 20, a source electrode 21, and a drain electrode 22. The semiconductor device according to embodiment 1 is a field-effect transistor (FET) having a polarization super junction region PSJ between the gate electrode 20 and the drain electrode 22.

[0019] 2. Components of semiconductor elements Next, each component of the semiconductor device in the first embodiment will be described.

[0020] The substrate 10 is made of sapphire. Its thickness is, for example, 50 to 600 μm. In addition to sapphire, any material on which a group III nitride semiconductor can be grown can be used. For example, Si, GaN, SiC, ScAlMgO4 (SAM), etc. can be used.

[0021] The first semiconductor layer 11 is a semiconductor layer made of a group III nitride semiconductor and provided on the first semiconductor layer via a buffer layer (not shown). The first semiconductor layer 11 is made of, for example, undoped GaN. The thickness of the first semiconductor layer 11 is, for example, 300 to 6000 nm.

[0022] The second semiconductor layer 12 is a semiconductor layer made of a Group III nitride semiconductor provided on the first semiconductor layer 11. The band gap energy of the second semiconductor layer 12 is larger than the band gap energies of the first semiconductor layer 11 and the third semiconductor layer 13. The second semiconductor layer 12 is, for example, undoped AlGaN, and has an Al composition of, for example, 0.2 to 0.3. The thickness of the second semiconductor layer is, for example, 20 to 150 nm.

[0023] The third semiconductor layer 13 is a semiconductor layer made of a Group III nitride semiconductor provided on the second semiconductor layer 12. The band gap energy of the third semiconductor layer 13 is smaller than the band gap energy of the second semiconductor layer 12. The third semiconductor layer 13 is, for example, undoped GaN. Due to the stacked structure of the first semiconductor layer 11 to the third semiconductor layer 13, a two-dimensional electron gas (2DEG) is formed in the first semiconductor layer 11 in a region near the interface between the first semiconductor layer 11 and the second semiconductor layer 12, and a two-dimensional hole gas (2DHG) is formed in the third semiconductor layer 13 in a region near the interface between the second semiconductor layer 12 and the third semiconductor layer 13.

[0024] The third semiconductor layer 13 is undoped, but Mg from the fourth semiconductor layer 14 and the p-type contact layer 15 above it diffuses into the third semiconductor layer 13. The Mg concentration in the third semiconductor layer 13 decreases from the fourth semiconductor layer 14 side toward the second semiconductor layer 12 side. The Mg concentration in the third semiconductor layer 13 near the interface with the fourth semiconductor layer 14 is approximately the same as that of the fourth semiconductor layer 14, and is, for example, 1×10 18 ~1×10 20 / cm 3 The Mg concentration in the third semiconductor layer 13 is 5×10 at a depth of 15 nm from the interface between the fourth semiconductor layer 14 and the third semiconductor layer 13 toward the second semiconductor layer 12. 18 / cm 3 At a depth of 20 nm, the 18 / cm 3 The details are as follows.

[0025] The thickness of the third semiconductor layer 13 differs between the region below the fourth semiconductor layer 14 and the region of the polarization super junction region PSJ. This is because a recess 40 is formed in the polarization super junction region PSJ, the upper portion of the third semiconductor layer 13 is etched and removed, and the third semiconductor layer 13 is also etched to a predetermined thickness. Hereinafter, the thickness (total thickness) of the third semiconductor layer 13 below the fourth semiconductor layer 14 is defined as D1, the thickness (remaining thickness) of the third semiconductor layer 13 in the polarization super junction region PSJ is defined as D2, and the difference between D1 and D2 (removed thickness) is defined as D3.

[0026] The thickness D2 is 30 nm or more, and the thickness difference D3 is 15 nm or more. By setting the thicknesses D2 and D3 in these ranges, the leakage current and turn-on time of the semiconductor element in the first embodiment can be reduced.

[0027] The turn-on time can be reduced by setting the thickness difference D3 to 15 nm or more, and by setting the Mg concentration in the third semiconductor layer 13 to 5×10 18 / cm 3 The Mg concentration of the third semiconductor layer 13 in the polarization super junction region PSJ is 5×10 18 / cm 3 Furthermore, by setting the thickness D2 to 30 nm or more, even if there is in-plane variation in the etching amount, the Mg concentration is 5×10 18 / cm 3 For example, the thickness D2 may vary by about 10 to 30 nm in the plane due to variations in the amount of etching.

[0028] In addition, the leakage current can be reduced because, by making the thickness D2 30 nm or more, the difference in carrier concentration between the 2DEG formed in the first semiconductor layer 11 in the region near the interface between the first semiconductor layer 11 and the second semiconductor layer 12 and the 2DHG formed in the third semiconductor layer 13 in the region near the interface between the second semiconductor layer 12 and the third semiconductor layer 13 is reduced, making it easier to deplete the polarization super junction region PSJ.

[0029] The difference D3 in thickness is preferably 20 nm or more. 18 / cm 3 If the thickness difference D3 is too large, the etching time becomes long and the etching amount varies greatly within the surface, so the thickness difference D3 is preferably 30 nm or less.

[0030] The thickness D2 is preferably 50 nm or more, which can further reduce leakage current. It is more preferably 80 nm or more. If the thickness D2 is too thick, it takes time to form the third semiconductor layer 13, so it is preferably 200 nm or less, and more preferably 80 to 100 nm.

[0031] The thickness D2 is set so that the difference in carrier concentration between the 2DEG and 2DHG is 0.8 × 10 13 / cm 2 It is preferable that the value is set to 0.5×10 or less, which can further reduce the leakage current. 13 / cm 2 The concentration of the 2DEG is, for example, 1.2 × 10 13 / cm 2 The concentration of 2DHG is, for example, 0.8 × 10 13 / cm 2 That's all.

[0032] The thickness D1 is preferably 90 nm or more. By setting the thickness within this range, the crystallinity and flatness of the third semiconductor layer 13 can be improved, and Mg diffusion from the fourth semiconductor layer 14 to the third semiconductor layer 13 can be suppressed. The thickness is more preferably 100 to 200 nm, and even more preferably 100 to 150 nm.

[0033] The fourth semiconductor layer 14 is a semiconductor layer made of a p-type Group III nitride semiconductor provided on the third semiconductor layer 13. However, the fourth semiconductor layer 14 does not exist on the third semiconductor layer 13 in the polarization super junction region PSJ. The fourth semiconductor layer 14 is, for example, Mg-doped GaN. A p-type impurity other than Mg may also be used. The Mg concentration of the fourth semiconductor layer 14 is, for example, 1×10 18 ~1×10 20 / cm 3 The thickness of the fourth semiconductor layer 14 is, for example, 20 to 150 nm. The in-plane variation in the total film thickness of the third semiconductor layer 13 and the fourth semiconductor layer 14 is 2 to 7 nm. It is believed that by making the third semiconductor layer 13 thicker, the flatness of the crystal is improved, and as a result, Mg diffusion from the fourth semiconductor layer 14 to the third semiconductor layer 13 is made more difficult.

[0034] The p-type contact layer 15 is a semiconductor layer made of a p-type Group III nitride semiconductor provided on the fourth semiconductor layer 14. The p-type contact layer 15 is made of, for example, Mg-doped GaN. The Mg concentration of the p-type contact layer 15 is, for example, 1×10 19 ~1×10 21 / cm 3 The thickness of the p-type contact layer 15 is, for example, 1 to 50 nm.

[0035] Recesses 41 and 42 are formed in predetermined regions on the p-type contact layer 15. The recesses 41 and 42 have the same depth, which is the depth that exposes the second semiconductor layer 12. These recesses 41 and 42 are for providing a source electrode 21 and a drain electrode 22.

[0036] Furthermore, a recess 40 is formed on the p-type contact layer 15 in a region between the gate electrode 20 and the drain electrode 22. This region is a polarization super junction region PSJ. The depth of the recess 40 is such that the thickness of the third semiconductor layer 13 becomes D2 when the third semiconductor layer 13 is etched by D3.

[0037] The gate electrode 20 is an electrode provided on the p-type contact layer 15. The gate electrode 20 is a laminated body in which, for example, Ni and Au are laminated in this order from the p-type contact layer 15 side.

[0038] The source electrode 21 is an electrode provided on the bottom surface of the recess 41, and is in contact with the second semiconductor layer 12. The source electrode 21 is a laminate in which, for example, V, Al, Ti, and Au are laminated in this order from the second semiconductor layer 12 side.

[0039] The drain electrode 22 is an electrode provided on the bottom surface of the recess 42 and is in contact with the second semiconductor layer 12. In a plan view, the source electrode 21 and the drain electrode 22 are arranged to face each other with the gate electrode 20 interposed therebetween. The drain electrode 22 is, for example, a laminate similar to the source electrode 21, and is a laminate in which V, Al, Ti, and Au are laminated in this order from the second semiconductor layer 12 side.

[0040] As described above, in the semiconductor element of the first embodiment, the thickness D2 of the third semiconductor layer 13 is set to 30 nm or more and D3 is set to 15 nm or more, so that the leakage current and turn-on time can be reduced.

[0041] 3. Operation of semiconductor elements The semiconductor device in embodiment 1 is turned on by applying a gate voltage equal to or greater than the threshold voltage to gate electrode 20, and turned off by applying a gate voltage less than the threshold voltage. Due to the piezoelectric polarization and spontaneous polarization of second semiconductor layer 12, a 2DEG is formed in first semiconductor layer 11 near the interface between first semiconductor layer 11 and second semiconductor layer 12, and a 2DHG is formed in third semiconductor layer 13 near the interface between second semiconductor layer 12 and third semiconductor layer 13. Of these, the 2DEG acts as a channel. In other words, during on-state operation, a current flows from drain electrode 22 through the 2DEG to source electrode 21.

[0042] When the gate voltage is less than the threshold voltage, holes in the 2DHG in the third semiconductor layer 13 are extracted by the gate electrode 20, and electrons in the 2DEG in the first semiconductor layer 11 are annihilated. As a result, the polarization super junction region PSJ is entirely depleted, and the electric field strength between the gate and drain becomes constant. Therefore, the semiconductor device in embodiment 1 can achieve a high breakdown voltage.

[0043] Ideally, the drain current is zero in the off state, but in reality, a weak current (leakage current) flows. However, in the semiconductor device of embodiment 1, the thickness D2 of the third semiconductor layer 13 in the polarization super junction region PSJ is set to 30 nm or more, so the leakage current can be reduced. For example, the leakage current can be reduced to 1 μA or less.

[0044] Furthermore, in the semiconductor device of embodiment 1, the thickness D2 is 30 nm or more and the thickness difference D3 is 15 nm or more, so the turn-on time can be reduced, for example, to 20 ns or less.

[0045] 4. Manufacturing method of semiconductor element Next, a method for manufacturing the semiconductor device according to embodiment 1 will be described. First, a first semiconductor layer 11, a second semiconductor layer 12, a third semiconductor layer 13, a fourth semiconductor layer 14, and a p-type contact layer 15 are formed in this order on a substrate 10 via a buffer layer. The formation method is, for example, MOCVD.

[0046] Next, predetermined regions of the p-type contact layer 15 are dry-etched until the third semiconductor layer 13 is exposed, and the third semiconductor layer 13 is further removed down to a predetermined thickness difference D3, thereby forming recesses 40. Then, predetermined regions of the third semiconductor layer 13 are dry-etched until the second semiconductor layer 12 is exposed, thereby forming recesses 41 and 42.

[0047] Next, the gate electrode 20 is formed on the p-type contact layer 15, and the source electrode 21 and the drain electrode 22 are formed on the bottom surfaces of the recesses 41 and 42, respectively. The electrodes are formed by evaporation, sputtering, or the like. The gate electrode 20 may be formed after the source electrode 21 and the drain electrode 22 are formed first. In this manner, the semiconductor element of embodiment 1 shown in FIG. 1 is manufactured.

[0048] 5. Experimental Results Next, various experimental results relating to the first embodiment will be described.

[0049] Experiment 1 In the semiconductor device of embodiment 1, semiconductor devices (semiconductor devices of examples) were fabricated in which the thickness D1 of the third semiconductor layer 13 below the fourth semiconductor layer 14 was 100 nm, the thickness of the fourth semiconductor layer 14 was 65 nm, and the thickness D2 of the third semiconductor layer 13 in the polarization super junction region PSJ was various values, and the turn-on time was measured. For comparison, semiconductor devices (semiconductor devices of comparative examples) were fabricated in which the thickness D1 was 65 nm, the thickness D2 was various values, and the other configurations were the same as in example 1, and the turn-on time was measured in the same manner.

[0050] Figure 2 is a graph showing the relationship between thickness D2 and turn-on time. As shown in Figure 2, in the example, the turn-on time was approximately constant when the thickness D2 was in the range of 45 to 90 nm. On the other hand, in the comparative example, the turn-on time was longer than in example 1.

[0051] Experiment 2 The Mg concentration in the depth direction was measured for the semiconductor elements of the example and comparative example. Figure 3 is a graph showing the relationship between depth and Mg concentration. The depth is measured from the surface of the fourth semiconductor layer 14 toward the substrate 10. The position at a depth of 65 nm in Figure 3 is the interface between the third semiconductor layer 13 and the fourth semiconductor layer 14.

[0052] 3, Mg is diffused into the third semiconductor layer 13 from the fourth semiconductor layer 14 and the p-type contact layer 15, and it was found that the Mg concentration decreases as the depth from the interface between the third semiconductor layer 13 and the fourth semiconductor layer 14 increases. It was also found that the diffusion of Mg is smaller in the example than in the comparative example. In the example, the Mg concentration was 5×10 at approximately 15 nm from the interface between the third semiconductor layer 13 and the fourth semiconductor layer 14. 18 / cm 3 However, in the comparative example, the Mg concentration was 5×10 18 / cm 3 It was.

[0053] 4 is a graph showing the relationship between the Mg concentration and the turn-on time obtained from the results of FIGS. 2 and 3. The Mg concentration in FIG. 4 is the Mg concentration at the surface of the third semiconductor layer 13 in the polarization super junction region PSJ. From FIG. 4, it can be seen that the Mg concentration is 5×10 18 / cm 3 It was found that the turn-on time can be reduced to 25 ns or less if the Mg concentration is 1×10 18 / cm 3 It was found that the turn-on time can be further reduced to 20 ns or less if the Mg concentration is 1×10 18 / cm 3 Below this, it was found that the turn-on time was constant and did not depend on the Mg concentration.

[0054] Experiment 3 For Example 1 and the Comparative Example, the in-plane variation in the total film thickness of the third semiconductor layer 13 and the fourth semiconductor layer 14 and the in-plane variation in the thickness D2 of the third semiconductor layer 13 in the polarization super junction region PSJ were measured. In the Comparative Example, the thickness difference D3 was set to 20 nm, and the target thickness D2 was 45 nm. In the Example, the thickness difference D3 was set to 15 nm, and the target thickness D2 was 85 nm. That is, from FIGS. 2 to 4, it can be seen that when the Mg concentration of the third semiconductor layer 13 in the polarization super junction region PSJ is 1×10 18 / cm 3 The target thickness was D2.

[0055] Fig. 5 is a graph showing the in-plane variation in the total film thickness of the third semiconductor layer 13 and the fourth semiconductor layer 14. Fig. 6 is a graph showing the in-plane variation in D2.

[0056] 5, in the comparative example, the in-plane variation in the total film thickness of the third semiconductor layer 13 and the fourth semiconductor layer 14 was about 10 nm, whereas in the example, it was about 5 nm, meaning that the comparative example had a larger in-plane variation than the example. It is thought that by making the third semiconductor layer 13 thicker, the flatness of the crystal is improved, and as a result, Mg diffusion from the fourth semiconductor layer 14 to the third semiconductor layer 13 is made more difficult.

[0057] 6, the thickness D2 in the comparative example and the example had a similar in-plane variation of about 15 nm. This variation is due to the in-plane variation in the amount of dry etching. The thickness D2 in the comparative example varied between 50 and 65 nm, while in the example it varied between 62 and 78 nm.

[0058] 2 to 4, in order to sufficiently reduce the turn-on time, the Mg concentration in the polarization super junction region PSJ must be 5×10 18 / cm 3 Less than 1 × 10 18 / cm 3 In the comparative example, the Mg concentration is 5×10 18 / cm 3 The thickness D2 is 30 to 55 nm and the Mg concentration is 1×10 18 / cm 3 As shown in FIG. 6, in the comparative example, the Mg concentration is 1×10 18 / cm 3 Most of the thickness is outside the range of 40 to 50 nm, and the Mg concentration is 5×10 18 / cm 3 Many of them are outside the range below (thickness D2 is in the range of 30 to 55 nm).

[0059] As described above, in the comparative example, the range of thickness D2 in which the turn-on time can be reduced is narrow, and it is difficult to keep thickness D2 within the range in which the turn-on time can be reduced due to in-plane variations in the etching amount.

[0060] On the other hand, in the example, the Mg concentration was 5×10 18 / cm 3 The thickness D2 is 30 to 85 nm and the Mg concentration is 1×10 18 / cm 3 As shown in FIG. 6, in the example, even if there is in-plane variation in the thickness D2, the Mg concentration is 1×10 18 / cm 3 The thickness falls within the following range (thickness D2 is in the range of 40 to 85 nm).

[0061] In this way, in the embodiment, the range of thickness D2 within which the turn-on time can be reduced can be set wide, so even if there is in-plane variation in thickness D2 due to in-plane variation in the etching amount, the turn-on time can be kept within the range within which it can be reduced.

[0062] Experiment 4 In the semiconductor element of embodiment 1, semiconductor elements were fabricated in which the thickness D1 of the third semiconductor layer 13 below the fourth semiconductor layer 14 was 100 μm and the thickness D2 of the third semiconductor layer 13 in the polarization super junction region PSJ was 55 nm, 70 nm, and 85 nm, and the current-voltage characteristics were measured.

[0063] Figure 7 is a graph showing the relationship between drain voltage and drain current, and Figure 8 is a graph showing the relationship between thickness D2 and leakage current. Here, leakage current is the drain current at a drain voltage of 1.2 kV in the off state. As shown in Figures 7 and 8, the larger the thickness D2, the smaller the leakage current.

[0064] Experiment 5 For the semiconductor device fabricated in Experiment 4, the carrier concentrations of the 2DEG generated in first semiconductor layer 11 near the interface between first semiconductor layer 11 and second semiconductor layer 12 and the 2DHG generated in third semiconductor layer 13 near the interface between second semiconductor layer 12 and third semiconductor layer 13 were measured. Fig. 9 is a graph showing the relationship between thickness D2 and carrier concentration.

[0065] As shown in Figure 9, the carrier concentration (electron concentration) of the 2DEG is approximately constant (1.7 × 10 13 / cm 2 On the other hand, the carrier concentration (hole concentration) of 2DHG increased as the thickness D2 increased, reaching 0.8 × 10 when the thickness D2 was 55 nm. 13 / cm 2 When the thickness D2 is 85 nm, it is 1.1 × 10 13 / cm 2 As shown above, it was found that the larger the thickness D2, the closer the carrier concentration becomes to that of the 2DEG. From this, it is speculated that the reason why the leakage current decreases when the thickness D2 is increased is because the difference in carrier concentrations between the 2DEG and 2DHG becomes smaller, making it easier to deplete the polarization super junction region PSJ.

[0066] (Modification of the first embodiment) The first semiconductor layer 11 and the second semiconductor layer 12, and the second semiconductor layer 12 and the third semiconductor layer 13 may be in contact with each other, or an intermediate layer may be provided. The intermediate layer is a group III nitride semiconductor having a larger band gap energy than the second semiconductor layer 12, such as AlN. The thickness of the intermediate layer is, for example, 0.2 to 10 nm. By providing such an intermediate layer, the carrier concentration of the 2DEG and the 2DHG can be increased. [Explanation of symbols]

[0067] 10: Circuit board 11: First semiconductor layer 12: Second semiconductor layer 13: Third semiconductor layer 14: Fourth semiconductor layer 15: p-type contact layer 20 gate electrodes 21: Source electrode 22: Drain electrode PSJ: Polarization superjunction region 40~42: Recess

Claims

1. In a semiconductor device using a Group III nitride semiconductor, an undoped first semiconductor layer; an undoped second semiconductor layer provided on the first semiconductor layer and having a band gap energy larger than that of the first semiconductor layer; an undoped third semiconductor layer provided on the second semiconductor layer and having a band gap energy smaller than that of the second semiconductor layer; a p-type fourth semiconductor layer provided on the third semiconductor layer; a gate electrode provided on the fourth semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer at a position facing the source electrode with the gate electrode interposed therebetween, a polarization super junction region in which the fourth semiconductor layer is not present is provided in a region between the gate electrode and the drain electrode on the third semiconductor layer; the thickness of the third semiconductor layer in the polarization super junction region is 30 nm or more; a difference between a thickness of the third semiconductor layer under the fourth semiconductor layer and a thickness of the third semiconductor layer in the polarization super junction region is 15 nm or more; A semiconductor device having a leakage current of 1 μA or less and a turn-on time of 20 ns or less.

2. The semiconductor device according to claim 1 , wherein a difference between a thickness of the third semiconductor layer below the fourth semiconductor layer and a thickness of the third semiconductor layer in the polarization super junction region is 20 nm or more.

3. The semiconductor device according to claim 1 , wherein the thickness of the third semiconductor layer below the fourth semiconductor layer is 90 nm or more.

4. The p-type impurity concentration of the third semiconductor layer in the polarization super junction region is 5×10 １８ / cm ３ 2. The semiconductor device of claim 1, wherein:

5. The p-type impurity concentration of the third semiconductor layer in the polarization super junction region is 1×10 １８ / cm ３ 2. The semiconductor device of claim 1, wherein:

6. The concentration of two-dimensional electron gas formed in the first semiconductor layer near the interface between the first semiconductor layer and the second semiconductor layer is 1.2×10 １３ / cm ２ That's all, The concentration of the two-dimensional hole gas formed in the third semiconductor layer near the interface between the second semiconductor layer and the third semiconductor layer is 0.8×10 １３ / cm ２ That's all, The difference between the concentration of the two-dimensional electron gas and the concentration of the two-dimensional hole gas is 0.8×10 １３ / cm ２ 2. The semiconductor device of claim 1, wherein:

7. 2. The semiconductor device according to claim 1, wherein the in-plane variation in thickness of said third semiconductor layer in said polarization super junction region is 10 to 30 nm.

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