Display device and control method for display device

Abstract

To provide a display device capable of reducing crosstalk.SOLUTION: A display device comprises a display panel 10 and a controller 50. The display panel includes a plurality of pixels arranged two-dimensionally in a first direction and a second direction. Each pixel includes a common electrode connected to adjacent pixels. The controller 50 receives an image signal and includes a killer pattern detection circuit 52 which detects a killer pattern composed of periodic repetition of dark portions and bright portions contained in an image displayed by the image signal, and generates information regarding a ratio of the killer pattern in the image, and performs feedback control of a common voltage applied to the common electrode at an amplification factor based on the information regarding the ratio of the killer pattern.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a display device and a method for controlling the display device. [Background technology]

[0002] As described in Patent Document 1, it has been known that liquid crystal display devices sometimes have problems with crosstalk, which can prevent images from being displayed correctly. In recent years, as liquid crystal display devices have become higher in resolution and the picture frames of display panels have become narrower, such crosstalk can become more pronounced. This type of crosstalk is not limited to liquid crystal display devices, but is also a problem in organic EL display devices, LED display devices, and the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-159223 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a display device and a method for controlling the display device that can reduce crosstalk. [Means for solving the problem]

[0005] A display device according to an embodiment of the present disclosure is a display device comprising a display panel and a control device, wherein the display panel includes a plurality of scanning lines extending in a first direction and arranged in a second direction intersecting the first direction, a plurality of data lines extending in the second direction and arranged in the first direction, and a plurality of pixels arranged two-dimensionally in the first direction and the second direction, each of the plurality of pixels having a switching element connected to one of the plurality of scanning lines and one of the plurality of data lines, and a common electrode connected to each other between adjacent pixels, and the control device includes a killer pattern detection circuit that receives an image signal, detects a killer pattern consisting of a periodic repetition of dark and light areas contained in an image displayed by the image signal, and generates information regarding the proportion of the killer pattern in the image, and feedback controls a common voltage applied to the common electrode with an amplification factor based on the information regarding the proportion of the killer pattern. [Effects of the Invention]

[0006] According to an embodiment of the present disclosure, a display device and a control method for the display device that can reduce crosstalk can be provided. In particular, since the amplification factor of feedback control is determined based on the proportion of killer patterns contained in an image, crosstalk can be more appropriately suppressed. Furthermore, since the amplification factor is variable, power consumption can be reduced compared to when control is performed with a constant amplification factor. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1A is a schematic diagram showing crosstalk that occurs when a killer pattern is displayed. [Figure 1B] FIG. 1B is a schematic diagram showing crosstalk that occurs when a killer pattern is displayed. [Figure 1C] FIG. 1C is a schematic diagram showing crosstalk that occurs when a killer pattern is displayed. [Figure 2] FIG. 2 is a schematic cross-sectional view showing an example of the configuration of the display device according to the first embodiment. [Figure 3] FIG. 3 is a schematic diagram showing the configuration of the active matrix substrate in the display device shown in FIG. [Figure 4] FIG. 4 is a circuit diagram showing a pixel of the TFT substrate. [Figure 5] FIG. 5 is a block diagram showing an example of the configuration of the control device. [Figure 6] FIG. 6 is a schematic circuit diagram showing connections between source drivers and source bus lines according to the SSD method. [Figure 7] FIG. 7 is a circuit diagram showing an example of a feedback circuit. [Figure 8] FIG. 8 is a timing chart for explaining the operation of the liquid crystal display device. [Figure 9] FIG. 9 is a schematic diagram showing a change in voltage of the common electrode. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of a control device in a display device according to the second embodiment. [Figure 11] FIG. 11 is a block diagram showing an example of the configuration of a control device in a display device according to the third embodiment. [Figure 12] FIG. 12 is a block diagram showing an example of the configuration of a feedback circuit of a control device in the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Crosstalk in LCDs can occur for a variety of reasons. In recent years, LCDs with wide viewing angles and narrow frame frames have become popular. When such LCDs display black and white or a checkerboard pattern with large brightness differences, crosstalk is likely to occur. For example, as shown in FIG. 1A, when a checkerboard pattern P1 is displayed in an image G1, an area S1 adjacent to the checkerboard pattern P1 in the horizontal direction may be displayed with a different brightness than the remaining area SB. Generally, an image pattern that causes display abnormalities such as crosstalk or flicker is called a killer pattern. Hereinafter, a checkerboard pattern will be referred to as a killer pattern.

[0009] According to the inventors' research, the brightness of horizontally adjacent regions of a killer pattern depends on the size of the killer pattern. As shown in FIGS. 1B and 1C, when killer patterns P2 and P3, which are horizontally larger than killer pattern P1, are displayed, the brightness of adjacent regions S2 and S3 is higher than that of region S1. In FIGS. 1A to 1C, the dot densities of the illustrated regions S1, S2, and S3 indicate differences in brightness, with lower dot density indicating higher brightness. In other words, the impact of crosstalk depends on the size of the killer pattern. Therefore, it is preferable to suppress crosstalk according to the size of the killer pattern. In light of these issues, the inventors have devised a novel display device and a method for controlling a display device.

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments, and appropriate design modifications may be made within the scope of the configuration of the present disclosure. In the following description, the same reference numerals are used in different drawings for identical parts or parts having similar functions, and repeated description thereof may be omitted. Furthermore, the configurations described in the embodiments and other aspects may be appropriately combined or modified without departing from the spirit of the present disclosure. For ease of understanding, the drawings referred to below may show simplified or schematic configurations, or may omit some components. Furthermore, the dimensional ratios between components shown in each drawing do not necessarily represent actual dimensional ratios.

[0011] (First embodiment) 2 is a schematic cross-sectional view showing an example of the configuration of a liquid crystal display device 101, which is a display device of this embodiment. The liquid crystal display device 101 includes a liquid crystal panel 10, which is a display panel, and a control device 50. The liquid crystal panel 10 includes a TFT substrate 20, a counter substrate 30, and a liquid crystal layer 40. As will be described later, the liquid crystal panel 10 includes a plurality of pixels arranged in row and column directions. The liquid crystal layer 40 is located between the TFT substrate 20 and the counter substrate 30, and is sealed between the TFT substrate 20 and the counter substrate 30 by a seal 41.

[0012] The liquid crystal display device 101 may further include a pair of polarizing plates 42 and a backlight 80. The pair of polarizing plates 42 are arranged in a crossed Nicol state with the liquid crystal panel 10 sandwiched between them.

[0013] The backlight 80 is disposed on the rear surface 10b of the liquid crystal panel 10. The backlight 80 may be an edge-type backlight or a direct-type backlight. The backlight 80 may also be capable of being partially driven.

[0014] 3 is a schematic diagram showing the configuration of the TFT substrate 20. The TFT substrate 20 includes a substrate 21, a plurality of source bus lines (data signal lines) SL, a plurality of gate bus lines (scanning signal lines) GL, and a plurality of pixels PX.

[0015] The substrate 21 has a main surface 21a including a display region 21h and a non-display region 21g other than the display region 21h. A plurality of gate bus lines GL, a plurality of source bus lines SL, and a plurality of pixels PX are arranged in the display region 21h. Specifically, the plurality of gate bus lines GL extend in a first direction (row direction, x direction) and are arranged at predetermined intervals in a second direction (column direction, y direction) intersecting the first direction. The plurality of source bus lines SL extend in the second direction and are arranged at predetermined intervals in the first direction. A pixel PX is arranged in a region surrounded by a pair of adjacent gate bus lines GL and a pair of adjacent source bus lines SL. The plurality of pixels PX are arranged two-dimensionally in the first and second directions. The source bus lines SL and gate bus lines GL extend into the non-display region 21g.

[0016] 4 is a circuit diagram showing pixels PX on the TFT substrate 20. Each pixel PX includes a pixel electrode PE, a switching element SW, and a common electrode CE. The switching element SW is, for example, a three-terminal element, with three terminals connected to a gate bus line GL, a source bus line SL, and a pixel electrode PE. For example, the switching element is a TFT having a gate electrode G, a source electrode S, and a drain electrode D. The gate electrode G is connected to the gate bus line GL, the source electrode S is connected to the source bus line SL, and the drain electrode D is connected to the pixel electrode PE and the storage capacitor CS. Each gate bus line GL is connected to the gate electrode G of the TFT of pixels PX arranged in the row direction among the multiple pixels PX. Furthermore, each source bus line SL is connected to the source electrode S of the TFT of pixels PX arranged in the column direction among the multiple pixels PX.

[0017] The pixel electrodes PE are disposed to face the liquid crystal layer 40. The common electrode CE is, for example, a plate- or sheet-like single element that connects adjacent pixels PX and extends across the entire display area 21h, and is located between the pixel electrodes and the substrate 21. An insulating layer is disposed between the common electrode CE and the pixel electrodes PE. The common electrode CE is provided across the entire display area 21h, and applying a voltage between the pixel electrodes PE and the common electrode CE generates an electric field in the liquid crystal layer 40, driving the liquid crystal panel 10 in a transverse electric field mode such as in-plane switching (IPS) or fringe field switching (FFS). This allows the liquid crystal panel 10 to have a wide viewing angle.

[0018] 5 is a block diagram showing the configuration of the control device 50. The control device 50 includes a timing controller 51, a killer pattern detection circuit 52, a gain control circuit 53, a feedback circuit 54, a gate driver 55, and a source driver 56.

[0019] The control device 50 is configured by an electronic circuit using active components such as ICs, LSIs, and FETs, and passive components such as resistors and capacitors.

[0020] The timing controller 51 receives a video signal from an external device. The video signal includes a video data signal and a video synchronization signal. The timing controller 51 generates an image signal and a start signal based on the received video signal.

[0021] 3, the gate driver 55 and the source driver 56 are arranged in the non-display area 21g of the substrate 21. The gate driver 55 is connected to one end of a gate bus line (scanning signal line) GL. The source driver 56 is connected to one end of a source bus line SL. Other components of the control device 50, such as the timing controller 51, are connected to the gate driver 55 and the source driver 56 by, for example, a flexible printed circuit (FPC) 90.

[0022] The gate driver 55 receives a start signal, generates a scanning signal, and outputs it to the gate bus line GL. The source driver 56 receives an image signal, generates a data signal including a voltage value corresponding to the gradation display of each pixel, and outputs it to the source bus line SL. In FIG. 3, the gate driver 55 is shown as a single IC, but each gate driver 55 may be composed of multiple ICs. Furthermore, the source driver 56 is shown as a multiple ICs, but may be composed of a single IC.

[0023] The gate driver 55 and the source driver 56 may be packaged components covered with resin or the like, or may be bare chips, and may be mounted in the non-display area 21g of the substrate 21. Alternatively, the gate driver 55 and the source driver 56 may be monolithic drivers configured with a plurality of TFTs or the like fabricated in the non-display area 21g of the substrate 21.

[0024] The source driver 56 and the source bus lines SL may be connected by an SSD (Source Shared Driving) method. Fig. 6 is a schematic circuit diagram showing the connection between the source driver and the source bus lines by the SSD method.

[0025] If the source bus lines connected to the red (R), green (G), and blue (B) pixels are designated SL(R), SL(G), and SL(B), respectively, the source driver 56A outputs data signals to be applied to the source bus lines SL(R), SL(G), and SL(B) from one terminal in a time-division manner, and distributes the output data signals to the source bus lines SL(R), SL(G), and SL(B) by switching using the SSD switch 56B.

[0026] According to the SSD method, the number of output terminals of the source driver 50A can be reduced to, for example, one-third of the number of source bus lines SL, and the area occupied by the wiring between the source driver 50A and the source bus lines SL can be reduced, thereby reducing the area of ​​the non-display area 21g and enabling a narrower frame of the liquid crystal display panel 10.

[0027] The killer pattern detection circuit 52 detects killer patterns contained in an image displayed by the image signal and outputs a detection signal indicating information about the proportion of killer patterns in the image. To this end, the killer pattern detection circuit includes an image processing circuit. More specifically, the killer pattern detection circuit 52 detects killer patterns, which are periodically repeated between dark and light areas, in each row of a frame of an image displayed by the image signal using multiple pixels on the liquid crystal panel 10, and obtains information about the proportion of killer patterns in each row. For example, the information about the proportion of killer patterns in each row may be a digital value indicating the proportion or a voltage value proportional to the proportion. The killer pattern detection circuit 52 outputs the obtained information about the proportion of killer patterns as a detection signal to the gain control circuit 53.

[0028] The gain control circuit 53 sets the amplification factor of a feedback circuit 54 (described later) based on the detection signal received from the killer pattern detection circuit 52. For example, the gain control circuit 53 outputs a control signal to the feedback circuit 54 that sets the amplification factor to a larger value as the proportion of killer patterns increases.

[0029] The feedback circuit 54 feedback-controls the common voltage applied to the common electrode CE using an amplification factor set by the gain control circuit 53. FIG. 7 is a circuit diagram showing an example of the feedback circuit 54. The feedback circuit 54 includes, for example, an inverting amplifier circuit using an operational amplifier OP. A feedback terminal TVcom_FB connected to the common electrode CE is connected to the inverting input terminal of the operational amplifier OP via a resistor R1 having a resistance value r1, and the voltage Vcom of the common electrode CE is input thereto. A common voltage Vcom_ORG generated by a common voltage generation circuit 60 is connected to the non-inverting input terminal. A regulated common voltage Vcom_APL is output from the output terminal of the operational amplifier OP and input to common voltage supply terminals TVcom_L and TVcom_R connected to the common electrode CE. The inverting input terminal and output terminal are connected via a resistor R2 having a resistance value r2.

[0030] The gain of the feedback circuit 54 is represented by r2 / r1. At least one of the resistors R1 and R2 is preferably a variable resistor. This allows the gain ratio r2 / r1 to be varied. For example, resistor R1 or R2 can be configured using a JFET or the like, and the gain control circuit 53 can vary the value of resistor R1 or R2 by varying the gate voltage of the JFET based on the detection signal. Such a circuit can utilize the gain control used in gain control amplifiers and auto gain control circuits.

[0031] Next, the cause of crosstalk that occurs when an image including a killer pattern is displayed and a method for controlling the liquid crystal display device according to this embodiment will be described.

[0032] 8 is a timing chart for one charging period (1H period) for explaining the operation of the liquid crystal display device of this embodiment. From top to bottom, Fig. 8 shows the scan signal Sg, the control signals SSD_R, SSD_G, and SSD_B of the SSD switch 53B, the potentials Vp_R, Vp_G, and Vp_B of the pixel electrodes of the red, green, and blue pixels, and the potential Vcom of the common electrode.

[0033] When the scanning signal Sg goes high, the switching elements of the pixels connected to the gate bus line GL to which the scanning signal Sg is applied are turned on. As shown in Figure 6, red, green, and blue pixels are arranged adjacent to each other on the gate bus line GL, and data signals for displaying the red, green, and blue pixels are output in a time-division manner from one terminal of the source driver 56A. The SSD switch 56B outputs control signals SSD_R, SSD_G, and SSD_B that are selectively turned on.

[0034] While the control signals SSD_R, SSD_G, and SSD_B are at a high level, the switching elements are turned on, and the voltages applied to the source bus lines are also applied to the pixel electrodes PE. Because the liquid crystal display device uses a column-line inversion drive system for display, the polarity of the potential of the pixel electrodes PE is inverted alternately in the row direction. In other words, the polarity of Vp_G is inverted relative to the polarities of Vp_R and Vp_B. Ideally, if there is no charge leakage, the voltage applied to the pixel electrodes PE is maintained even after the switching elements are turned off.

[0035] At this time, a common voltage Vcom is applied to the common electrode CE. Ideally, the potential Vcom of the common electrode CE is constant, but if the image contains a killer pattern, the potential of the data signal applied to the source bus line SL fluctuates significantly, which in turn affects the potential of the common electrode CE. This effect is particularly pronounced when the pixel electrode and the common electrode are arranged on the same TFT substrate and are therefore close to each other in order to drive the liquid crystal display device in the horizontal electric field mode.

[0036] A voltage (potential difference) defined by the difference between the potential of the pixel electrode PE and the potential of the common electrode CE is applied to the liquid crystal layer 40 of each pixel PX. The voltage applied to the liquid crystal layer of each pixel PX is determined by the timing at which the switching element is turned off.

[0037] FIG. 9 is a schematic diagram showing the change in the voltage Vcom of the common electrode CE. As described above, the potential of the common electrode Vcom fluctuates due to the data signal applied to the source bus line. As indicated by the ripple voltage ΔV, the common potential Vcom increases by ΔV from Vcom_ORG and then returns to the original potential Vcom_ORG over time. Meanwhile, the period during which the switching element of the selected pixel is ON is shortened by the time division using the SSD method. In other words, the switching element is ON only for a portion of the 1H period. Therefore, when the switching element is turned OFF, the potential of the common electrode Vcom has not returned to the potential Vcom_ORG, but is deviated from the common potential Vcom_ORG by the residual ripple ΔVr. As a result, the voltage applied to the liquid crystal layer also deviates from the correct voltage by the residual ripple ΔVr.

[0038] In the liquid crystal display device of this embodiment, the potential of the common electrode Vcom is detected and a voltage of the opposite polarity is applied to the common electrode CE. Specifically, an inverting amplifier circuit is used to quickly converge the residual ripple ΔVr through negative feedback control. Furthermore, since the magnitude of the ripple voltage ΔV varies depending on the proportion of killer patterns in the image, the common voltage applied to the common electrode CE is determined using an amplification factor based on information about the proportion of killer patterns. This allows the fluctuation in the potential of the reference electrode to converge quickly, as shown by the dashed line in Figure 9, and minimizes the residual ripple ΔVr' at the timing when the switching element is turned off.

[0039] More specifically, the killer pattern detection circuit 52 receives an image signal from the timing controller 51, detects killer patterns in each row of the image for each frame, and generates a detection signal indicating information about the proportion of killer patterns in each row. The gain control circuit 53 sets the amplification factor of the feedback circuit 54 based on the detection signal received from the killer pattern detection circuit 52.

[0040] The feedback circuit 54 receives the voltage Vcom of the common electrode CE and the common voltage Vcom_ORG from the common voltage generation circuit 60, and generates an adjusted common voltage Vcom_APL. This common voltage Vcom_ORG is a target value for feedback control. The adjusted common voltage Vcom_APL is generated by amplifying the common voltage Vcom_ORG by an amplification factor set by the gain control circuit 53 and inverting its polarity. Because the adjusted common voltage Vcom_APL has an inverted polarity from the current voltage of the common electrode CE, applying the adjusted common voltage Vcom_APL cancels out the voltage values ​​and reduces the ripple voltage ΔV. This reduces the ripple voltage ΔV early, thereby reducing the residual ripple ΔVr at the time the switching element is turned off. This suppresses crosstalk.

[0041] Furthermore, the gain control circuit 53 sets the amplification factor of the feedback circuit 54 in accordance with the detection signal indicating information about the proportion of killer patterns. As explained with reference to FIGS. 1A to 1C, the greater the proportion of killer patterns P1 to P3 in the row direction, the higher the luminance of adjacent regions S1 to S3 in the row direction; that is, the larger the ripple voltage ΔV superimposed on the common potential Vcom. In such a case, by setting the amplification factor of the feedback control to a larger value as the proportion of killer patterns increases, the ripple voltage ΔV can be converged more quickly. Furthermore, by making the amplification factor variable in this way, the power consumption of the feedback circuit 54 can also be changed, making it possible to reduce the power consumption of the liquid crystal display device.

[0042] As described above, according to the liquid crystal display device and the method for controlling the liquid crystal display device of the present embodiment, by feedback-controlling the common voltage applied to the common electrode with an amplification factor based on information about the proportion of killer patterns, it is possible to appropriately suppress crosstalk even if killer patterns of any size are included in the displayed image, and also to reduce the power consumption of the liquid crystal display device.

[0043] (Second embodiment) 10 is a block diagram showing the configuration of a control device 150 of a liquid crystal display device 102 of this embodiment. The liquid crystal display device 102 of this embodiment differs from the first embodiment in that the control device 150 further includes a switch circuit 57.

[0044] If the proportion of killer patterns is equal to or less than a predetermined value, the switch circuit 57 suspends the feedback circuit 54 and the gain control circuit 53. For example, the switch circuit 57 receives a detection signal from the killer pattern detection circuit 52, and if the proportion of killer patterns is greater than a predetermined value, it outputs an enable signal to the gain control circuit 53 and the feedback circuit 54. The predetermined value may be zero, or may be set to a value greater than zero, such as 0.05 (5%) or 0.1 (10%), at which the effects of crosstalk are barely noticeable even if killer patterns are included.

[0045] The gain control circuit 53 and the feedback circuit 54 operate as described in the first embodiment only while receiving an enable signal from the switch circuit 57, and are inactive while not receiving an enable signal. Furthermore, while the feedback circuit 54 is not operating, it outputs the common voltage Vcom_ORG received from the common voltage generation circuit 60 as Vcom_APL to Vcom_L and Vcom_R without modification.

[0046] According to the liquid crystal display device 102, when a killer pattern is not included in an image, or when a killer pattern is included but the effects of crosstalk are not substantially visible, the feedback circuit 54 and the gain control circuit 53 can be paused. Thus, the current consumption of the liquid crystal display device 102 can be further reduced, while the effects of crosstalk can be reduced when a killer pattern is displayed.

[0047] (Third embodiment) Fig. 11 is a block diagram showing the configuration of a control device 150 of a liquid crystal display device 103 of this embodiment. The liquid crystal display device 102 of this embodiment differs from the second embodiment in that the control circuit 250 does not include a gain control circuit, but further includes a feedback circuit 154 including a programmable operational amplifier. Fig. 12 is a block diagram showing an example configuration of the feedback circuit 154. The feedback circuit 154 includes a programmable operational amplifier 161, a memory 162, a register 163, and a signal processing circuit 164.

[0048] The programmable operational amplifier 161 is an inverting amplifier circuit that can set a plurality of gains by combining resistors. The gain can be switched by a signal input to a terminal 161t. A resistor 163 is connected to the terminal 161t.

[0049] The memory 162 stores a look-up table in which the proportion of killer patterns is associated with the amplification factor of the programmable operational amplifier 161 or a register value corresponding to the amplification factor.

[0050] The signal processing circuit 164 receives the detection signal from the killer pattern detection circuit 52, references a lookup table stored in memory 162, determines a register value based on the killer pattern ratio represented by the detection signal, and writes the determined register value to the register 163. The set register value is set to an amplification factor corresponding to the killer pattern ratio. This allows the programmable operational amplifier 161 to feedback-control the voltage of the common electrode CE with an amplification factor corresponding to the killer pattern ratio.

[0051] As described in the first and second embodiments, the liquid crystal display device 103 of this embodiment also feedback-controls the common voltage applied to the common electrode with an amplification factor based on information about the proportion of killer patterns, thereby making it possible to appropriately suppress crosstalk even if killer patterns of any size are included in the displayed image. Furthermore, if the image does not include a killer pattern, or if the killer pattern is included but the effect of crosstalk is not substantially visible, the feedback circuit is deactivated, thereby further reducing the current consumption of the liquid crystal display device.

[0052] (Other forms) In the above embodiment, the display device of the present disclosure has been described using a liquid crystal display device as an example, but the display device may be an organic EL display device or an LED display device. In these display devices, when an image including a killer pattern is displayed, the data signal applied to the source bus line may affect the common signal line, so the same effect can be obtained.

[0053] Furthermore, the display device of the present disclosure is not limited to the above-described embodiment, and various modifications are possible. For example, the configuration of the control device is not limited to the configuration described in the above-described embodiment, and the control device can be configured using other programmable gain amplifiers, auto gain control circuits, etc.

[0054] The display device of the present disclosure can also be described as follows.

[0055] A display device according to a first configuration of the present disclosure includes a display panel and a control device, the display panel includes a plurality of scanning lines extending in a first direction and arranged in a second direction intersecting the first direction, a plurality of data lines extending in the second direction and arranged in the first direction, and a plurality of pixels arranged two-dimensionally in the first direction and the second direction, each pixel having a switching element connected to one of the plurality of scanning lines and one of the plurality of data lines, and a common electrode connected to each other between adjacent pixels; the control device includes a killer pattern detection circuit that receives an image signal, detects a killer pattern that is composed of periodic repetition of dark and light areas included in an image displayed by the image signal, and generates information regarding the proportion of the killer pattern in the image; The common voltage applied to the common electrode is feedback-controlled with an amplification factor based on information about the proportion of the killer patterns.

[0056] According to the first configuration, the feedback control gain is determined based on the proportion of killer patterns contained in the image, which allows for more appropriate crosstalk suppression. In addition, because the gain is variable, power consumption can be reduced compared to when control is performed with a fixed gain.

[0057] In the display device of the second configuration, in the first configuration, the information regarding the proportion of the killer pattern may be the proportion of the killer pattern in the first direction when the image is displayed using the multiple pixels.

[0058] A display device according to a third configuration may be configured such that, in the second configuration, the control device includes a feedback circuit constituted by an inverting amplifier circuit, the potential of the common electrode is input to an inverting input terminal of the inverting amplifier circuit, the common potential is input to a non-inverting input terminal of the inverting amplifier circuit, and the output terminal of the inverting amplifier circuit is connected to the common electrode.

[0059] A display device according to a fourth configuration may be configured such that, in the third configuration, the control device further includes a gain control circuit, and the gain control circuit determines the amplification factor of the inverting amplifier circuit based on information regarding the proportion of the killer pattern.

[0060] A display device according to a fifth configuration may be the third configuration, wherein the control device further includes a switch circuit, and the switch circuit may suspend the feedback circuit when the proportion of the killer pattern is equal to or less than a predetermined value.

[0061] A display device according to a sixth configuration is the third configuration, wherein the feedback circuit further includes a lookup table in which information regarding the proportion of the killer pattern corresponds to the amplification factor, and a setting register, the inverting amplifier circuit is a programmable gain amplifier capable of selecting from a plurality of amplification factors, and the feedback circuit receives information regarding the proportion of the killer pattern from the killer pattern detection circuit, and selects one of the plurality of amplification factors by referring to the lookup table and setting the amplification factor determined from the information regarding the proportion of the killer pattern in the setting register.

[0062] A display device according to a seventh aspect is the display device of the first aspect, wherein the display panel is a liquid crystal display panel.

[0063] A display device according to an eighth aspect is the display device according to the first aspect, wherein the display panel is an organic EL panel.

[0064] A control method for a display device according to a ninth aspect of the present disclosure is a control method for a liquid crystal display device including a display panel and a control device, the display panel includes a plurality of scanning lines extending in a first direction and arranged in a second direction intersecting the first direction, a plurality of data lines extending in the second direction and arranged in the first direction, and a plurality of pixels arranged two-dimensionally in the first direction and the second direction, each pixel having a switching element connected to one of the plurality of scanning lines and one of the plurality of data lines, and a common electrode connected to each other between adjacent pixels; the control device includes a killer pattern detection circuit that receives an image signal, detects a killer pattern that is composed of periodic repetition of dark and light areas included in an image displayed by the image signal, and generates information regarding the proportion of the killer pattern in the image; The common voltage applied to the common electrode is feedback-controlled with an amplification factor based on information about the proportion of the killer patterns.

[0065] According to the ninth configuration, the gain of the feedback control is determined based on the proportion of killer patterns contained in the image, thereby enabling more appropriate crosstalk suppression. Furthermore, because the gain is variable, power consumption can be reduced compared to when control is performed with a fixed gain.

[0066] A tenth configuration of a control method for a display device is the ninth configuration, wherein the information regarding the proportion of the killer pattern may be the proportion of the killer pattern in the first direction when the image is displayed using the plurality of pixels.

[0067] A control method for a display device according to an eleventh configuration may be the tenth configuration, wherein the control device includes a feedback circuit constituted by an inverting amplifier circuit, the potential of the common electrode is input to an inverting input terminal of the inverting amplifier circuit, the common potential is input to a non-inverting input terminal of the inverting amplifier circuit, and the output terminal of the inverting amplifier circuit is connected to the common electrode.

[0068] A twelfth configuration of the control method for a display device is the eleventh configuration, wherein the control device further includes a gain control circuit, and the gain control circuit may determine the amplification factor of the inverting amplifier circuit based on information regarding the proportion of the killer pattern.

[0069] A thirteenth configuration of the control method for a display device is the eleventh configuration, wherein the control device further includes a switch circuit, and the switch circuit may suspend the feedback circuit when the proportion of the killer pattern is equal to or less than a predetermined value.

[0070] A display device control method according to a fourteenth configuration may be the eleventh configuration, wherein the feedback circuit further includes a lookup table in which information regarding the killer pattern proportion is associated with the amplification factor, and a setting register, the inverting amplifier circuit is a programmable gain amplifier capable of selecting from a plurality of amplification factors, and the feedback circuit receives information regarding the killer pattern proportion from the killer pattern detection circuit, and selects one of the plurality of amplification factors by referring to the lookup table and setting the amplification factor determined from the information regarding the killer pattern proportion in the setting register.

[0071] A fifteenth aspect of the present invention is a method for controlling a display device according to the ninth aspect, wherein the display panel is a liquid crystal display panel.

[0072] A sixteenth aspect of the present invention is directed to a method of controlling a display device according to the ninth aspect, wherein the display panel is an organic EL panel. [Explanation of symbols]

[0073] 10...liquid crystal panel, 10b...rear, 20...TFT substrate, 21...substrate, 21a...main surface, 21g...non-display area, 21h...display area, 30...counter substrate, 40...liquid crystal layer, 41...seal, 42...polarizer, 50...controller, 50A...source driver, 51...timing controller, 52...killer pattern detection circuit, 53...gain control circuit, 53B...scanning signal SSD switch, 54...feedback circuit, 55...gate driver, 56...source driver, 56A...source driver, 56B...SSD switch, 57...switch circuit, 60...common voltage generation circuit, 80...backlight 101 to 103...liquid crystal display device, 150...controller, 154...feedback circuit, 161...programmable operational amplifier, 161t...terminal, 162...memory, 163...register, 164...signal processing circuit, 164...register, 250...control circuit

Claims

1. A display device including a display panel and a control device, The display panel includes: a plurality of scanning lines extending in a first direction and arranged in a second direction intersecting the first direction; a plurality of data lines extending in the second direction and arranged in the first direction; a plurality of pixels arranged two-dimensionally in the first direction and the second direction, each of the pixels having a switching element connected to one of the plurality of scanning lines and one of the plurality of data lines, and a common electrode connected to each other between adjacent pixels; Including, The control device a killer pattern detection circuit that receives an image signal, detects a killer pattern that is composed of periodic repetitions of dark and light areas included in an image displayed by the image signal, and generates information about the proportion of the killer pattern in the image; feedback-controlling a common voltage applied to the common electrode with an amplification factor based on information about the proportion of the killer patterns; Display device.

2. The display device according to claim 1 , wherein the information relating to the proportion of the killer pattern is a proportion of the killer pattern in the first direction when the image is displayed using the plurality of pixels.

3. the control device includes a feedback circuit configured by an inverting amplifier circuit; The potential of the common electrode is input to the inverting input terminal of the inverting amplifier circuit, A common potential is input to the non-inverting input terminal of the inverting amplifier circuit, an output terminal of the inverting amplifier circuit is connected to the common electrode; The display device according to claim 2 .

4. the control device further includes a gain control circuit; The display device according to claim 3 , wherein the gain control circuit determines the amplification factor of the inverting amplifier circuit based on information about the proportion of the killer patterns.

5. the control device further includes a switch circuit; The display device according to claim 3 , wherein the switch circuit suspends the feedback circuit when the proportion of the killer pattern is equal to or less than a predetermined value.

6. the feedback circuit further includes a lookup table in which information about the killer pattern ratio and the amplification factor are associated with each other, and a setting register; the inverting amplifier circuit is a programmable gain amplifier capable of selecting a plurality of gains, the feedback circuit receives information about the killer pattern ratio from the killer pattern detection circuit, and refers to the lookup table to set an amplification factor determined from the information about the killer pattern ratio in the setting register, thereby selecting one of the plurality of amplification factors. The display device according to claim 3 .

7. The display device according to claim 1 , wherein the display panel is a liquid crystal display panel.

8. The display device according to claim 1 , wherein the display panel is an organic electroluminescence (EL) panel.

9. A method for controlling a display device including a display panel and a control device, comprising: The display panel includes: a plurality of scanning lines extending in a first direction and arranged in a second direction intersecting the first direction; a plurality of data lines extending in the second direction and arranged in the first direction; a plurality of pixels arranged two-dimensionally in the first direction and the second direction, each of the pixels having a switching element connected to one of the plurality of scanning lines and one of the plurality of data lines, and a common electrode connected to each other between adjacent pixels; Including, The control device a killer pattern detection circuit that receives an image signal, detects a killer pattern that is composed of periodic repetitions of dark and light areas included in an image displayed by the image signal, and generates information about the proportion of the killer pattern in the image; feedback-controlling a common voltage applied to the common electrode with an amplification factor based on information about the proportion of the killer patterns; A method for controlling a display device.

10. The display device control method according to claim 9 , wherein the information regarding the proportion of the killer pattern is a proportion of the killer pattern in the first direction when the image is displayed using the plurality of pixels.

11. the control device includes a feedback circuit configured by an inverting amplifier circuit; The potential of the common electrode is input to the inverting input terminal of the inverting amplifier circuit, A common potential is input to the non-inverting input terminal of the inverting amplifier circuit, an output terminal of the inverting amplifier circuit is connected to the common electrode; The method for controlling a display device according to claim 10.

12. the control device further includes a gain control circuit; the gain control circuit determines the amplification factor of the inverting amplifier circuit based on information relating to the proportion of the killer pattern. The method for controlling a display device according to claim 11.

13. the control device further includes a switch circuit; The method of claim 11 , wherein the switch circuit suspends the feedback circuit when the rate of the killer pattern is equal to or less than a predetermined value.

14. the feedback circuit further includes a lookup table in which information about the killer pattern ratio and the amplification factor are associated with each other, and a setting register; the inverting amplifier circuit is a programmable gain amplifier capable of selecting a plurality of gains, 12. The display device control method of claim 11, wherein the feedback circuit receives information regarding the proportion of the killer pattern from the killer pattern detection circuit, refers to the lookup table, and selects one of the plurality of amplification factors by setting the amplification factor determined from the information regarding the proportion of the killer pattern in the setting register.

15. The method for controlling a display device according to claim 9 , wherein the display panel is a liquid crystal display panel.

16. The method for controlling a display device according to claim 9 , wherein the display panel is an organic EL panel.

Images