Light detection device and electronic apparatus

Abstract

To allow pixel microfabrication without increasing a chip area.SOLUTION: A light detection device is composed by stacking a first substrate including a pixel array region on which light receiving elements are two-dimensionally arrayed in matrix, and a second substrate including a pixel array lower region corresponding to the pixel array region. The pixel array lower region includes: one or more pixel read-out circuits which are composed by arraying a plurality of unit regions composed of one or more pixels in row direction or column direction and have a circuit layout common for each unit region; and a first logic circuit in which the circuits are disposed across the unit region. The technique according to the disclosure can be for example used for a distance measuring device or the like that measures a distance to a measuring object.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a photodetector and an electronic device, and more particularly to a photodetector and an electronic device that enable miniaturization of pixels without increasing the chip area. [Background technology]

[0002] A direct ToF (Time-of-Flight) light receiving device is known (see, for example, Patent Document 1). A direct ToF light receiving device measures the distance to an object by measuring the time between irradiating the object with light and receiving the light reflected by the object. The light receiving device includes a light receiving element such as a SPAD (Single Photon Avalanche Diode) that detects photons, a TDC that measures the time it takes for the light receiving element to detect the light and react, and a histogram generator that generates a histogram based on the measured time. The TDC and histogram generator may be arranged, for example, at each pixel in a pixel array (see, for example, Patent Document 2), or may be arranged outside the pixel array. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-110697 [Patent Document 2] Special Publication No. 2020-504299 Summary of the Invention [Problem to be solved by the invention]

[0004] Placing the TDC and histogram generator in each pixel within the pixel array increases the mounting area, making it difficult to miniaturize the pixels. On the other hand, placing the TDC and histogram generator outside the pixel array increases the chip area.

[0005] The present disclosure has been made in view of such circumstances, and makes it possible to miniaturize pixels without increasing the chip area. [Means for solving the problem]

[0006] The photodetector according to the first aspect of the present disclosure comprises: The display device is configured by stacking a first substrate having a pixel array region in which light receiving elements are two-dimensionally arranged in a matrix, and a second substrate having a pixel array lower region corresponding to the pixel array region, The region below the pixel array is configured by arranging a plurality of unit regions, each consisting of one or more pixels, in a row or column direction, and includes one or more pixel readout circuits having a common circuit layout in the unit regions, and a first logic circuit whose circuitry is arranged across the unit regions.

[0007] An electronic device according to a second aspect of the present disclosure includes: a light source device that outputs irradiation light; a light detection device that receives reflected light of the irradiated light reflected by an object; Equipped with the photodetector is configured by stacking a first substrate having a pixel array region in which light receiving elements are two-dimensionally arranged in a matrix, and a second substrate having a pixel array lower region corresponding to the pixel array region; The region below the pixel array is configured by arranging a plurality of unit regions, each consisting of one or more pixels, in a row or column direction, and includes one or more pixel readout circuits having a common circuit layout in the unit regions, and a first logic circuit whose circuitry is arranged across the unit regions.

[0008] In the first and second aspects of the present disclosure, the semiconductor device is configured by stacking a first substrate having a pixel array region in which light receiving elements are arranged two-dimensionally in a matrix, and a second substrate having a pixel array lower region corresponding to the pixel array region, wherein the pixel array lower region is configured by arranging a plurality of unit regions, each consisting of one or more pixels, in a row or column direction, and includes one or more pixel readout circuits having a common circuit layout in the unit regions, and a first logic circuit whose circuitry is arranged across the unit regions.

[0009] The photodetector and electronics may be stand-alone devices or may be modules that are incorporated into other devices. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating a configuration example of an electronic device in which a photodetector according to an embodiment of the present disclosure is mounted. [Figure 2] 2 is a perspective view showing an example of the substrate configuration of the photodetector of FIG. 1. FIG. [Figure 3] FIG. 2 is a diagram illustrating an example of the configuration of a pixel sensor unit and a pixel readout circuit. [Figure 4] 4 is a diagram illustrating the operation of the SPAD of FIG. 3. [Figure 5] 1 shows a cross-sectional view of pixel portions of a first substrate and a second substrate. [Figure 6] FIG. 4 is a block diagram showing an example of the configuration of a second substrate. [Figure 7] FIG. 10 is a diagram illustrating a series of processes up to the generation of distance information. [Figure 8] 10A and 10B are diagrams illustrating an example of allocation of logic circuits arranged in a region below the pixel array and logic circuits arranged outside the region below the pixel array. [Figure 9] FIG. 2 is a plan view showing a first arrangement example of a region below a pixel array. [Figure 10] FIG. 10 is a plan view showing a second arrangement example of the region below the pixel array. [Figure 11] FIG. 10 is a plan view showing a third arrangement example of the region below the pixel array. [Figure 12] FIG. 10 is a plan view showing a fourth arrangement example of the region below the pixel array. [Figure 13] FIG. 10 is a plan view showing a fifth arrangement example of the region below the pixel array. [Figure 14] FIG. 10 is a diagram illustrating a first modified example of a pixel readout circuit. [Figure 15] FIG. 10 is a diagram illustrating a second modified example of a pixel readout circuit. [Figure 16] FIG. 10 is a diagram illustrating another example of connection between the pixel sensor unit and the pixel readout circuit. [Figure 17]FIG. 10 is a diagram illustrating another example of connection between the pixel sensor unit and the pixel readout circuit. [Figure 18] FIG. 1 is a perspective view showing an example of a photodetector having a stacked structure of three substrates. [Figure 19] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 20] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, with reference to the accompanying drawings, a description will be given of a mode for carrying out the technology of the present disclosure (hereinafter referred to as an embodiment). Note that in this specification and the drawings, components having substantially the same functional configuration are designated by the same reference numerals, and redundant description will be omitted. The description will be given in the following order. 1. Electronic device configuration examples 2. Example of photodetector board configuration 3. Example of pixel sensor and pixel readout circuit configuration 4. Pixel cross section 5. Block diagram of the second board 6. Example of allocation of logic circuits within the array and logic circuits outside the array 7. Example of circuit layout in the area below the pixel array 8. Other configuration examples of pixel readout circuits 9. Other connection examples between pixel sensor unit and pixel readout circuit 10. Example of a three-layer laminated structure 11. Mobile application examples

[0012] <1. Configuration examples of electronic devices> FIG. 1 is a block diagram showing an example of the configuration of an electronic device in which a photodetector according to the present disclosure is mounted.

[0013] The electronic device 1 includes a distance measuring device 11 and an application unit 12. The distance measuring device 11 measures the distance to a measurement target object (object to be measured) 30 using a direct ToF method, and outputs distance information, which is the measurement result, to the application unit 12. The distance information is configured, for example, as a depth image in which a depth value indicating the distance to the subject is stored as the pixel value of each pixel. The application unit 12 is realized, for example, by a program running on a CPU (Central Processing Unit), and requests the distance measuring device 11 to perform distance measurement and obtains the distance information, which is the distance measurement result, from the distance measuring device 11. The electronic device 1 is assumed to be, for example, a smartphone, a tablet, a wearable device, a camera such as an in-vehicle camera, a digital still camera, or a digital video camera, or an on-board device mounted on a vehicle such as an automobile or a mobile object such as a drone.

[0014] The distance measuring device 11 includes a control unit 21, a light source device 22, and a photodetector device 23. The control unit 21 includes control circuits and processors such as a field programmable gate array (FPGA) and a digital signal processor (DSP), and controls the overall operation of the distance measuring device 11. For example, the control unit 21 generates a reference clock signal that serves as a reference for clock signals used by each unit of the distance measuring device 11, and supplies the reference clock signal to the light source device 22 and the photodetector device 23. In addition, the control unit 21 instructs the photodetector device 23 to perform distance measurement in response to a request to perform distance measurement from the application unit 12, obtains distance information, which is the distance measurement result, from the photodetector device 23, and outputs the information to the application unit 12.

[0015] The light source device 22 includes a light-emitting element that emits light with a wavelength in the infrared region, for example, and a drive circuit that drives the light-emitting element. The light-emitting element that emits light with a wavelength in the infrared region can be, for example, an LED (Light Emitting Diode). The light-emitting element is not limited to this, and can also be, for example, a VCSEL (Vertical Cavity Surface Emitting Laser) in which a plurality of light-emitting elements are formed in an array. The light source device 22 outputs irradiation light 31 based on a light-emission timing signal supplied from the photodetector 23. The light-emission timing signal is, for example, a pulse signal modulated into a rectangular wave with a predetermined duty ratio. Hereinafter, unless otherwise specified, "the light-emitting element of the light source device 22 emits light" will be expressed as "the light source device 22 emits light," etc.

[0016] The photodetector 23 includes a light-receiving element capable of detecting light with a wavelength in the infrared region, for example, and a signal processing circuit that outputs a signal corresponding to the light detected by the light-receiving element. For example, a SPAD (Single Photon Avalanche Diode) can be used as the light-receiving element included in the photodetector 23. Hereinafter, unless otherwise specified, "the light-receiving element of the photodetector 23 detects light" will be expressed as "the photodetector 23 receives light," etc.

[0017] The photodetector 23 executes distance measurement processing in response to a distance measurement instruction from the control unit 21. For example, the photodetector 23 generates a light emission timing signal indicating the timing at which the light source device 22 emits light, and supplies the light source device 22 with the signal. The photodetector 23 also performs a light receiving operation in synchronization with the light emission timing signal and measures a count value that serves as the basis for calculating a depth value. The count value is a count value obtained by counting the time from when the light source device 22 emits irradiation light 31 to when the photodetector 23 receives reflected light 32 from the object 30. The photodetector 23 supplies the count value to the control unit 21 as distance information. Alternatively, the photodetector 23 may calculate and generate a distance D to the object 30 from the count value, and store the calculated depth image as a depth value and supply the depth image to the control unit 21 as distance information. The control unit 21 may perform the process of generating a depth image based on the count value.

[0018] <2. Example of photodetector board configuration> FIG. 2 is a perspective view showing an example of the substrate configuration of the photodetector 23. As shown in FIG.

[0019] 2, the photodetector 23 is configured by a semiconductor chip having a stacked structure in which a first substrate 51 and a second substrate 52 are stacked. The upper surface of the first substrate 51 is the light incident surface, and reflected light 32 is incident on the first substrate 51 from above.

[0020] The first substrate 51 has at least a pixel array region 72 in which pixel sensor units 71 are two-dimensionally arranged in a matrix in the row and column directions. The pixel sensor units 71 have light-receiving elements capable of detecting incident light of a predetermined wavelength (for example, a wavelength in the infrared region) and output detection signals indicating the results of detecting the incident light. In this embodiment, the pixel sensor units 71 have SPADs as light-receiving elements.

[0021] The second substrate 52 has at least a pixel array lower region 82 in which pixel readout circuits 81 are two-dimensionally arranged in a matrix in the row and column directions. The pixel readout circuits 81 are provided in one-to-one correspondence with the pixel sensor units 71 of the first substrate 51 and are electrically connected to the pixel sensor unit 71 above. The pixel readout circuits 81 are arranged in a region overlapping with the pixel sensor unit 71 above in a planar view, and the pixel array lower region 82 is also a region overlapping with the pixel array region 72 of the first substrate 51 in a planar view. The pixel readout circuits 81 are circuits that read out detection signals generated in the pixel sensor units 71.

[0022] 3. Example of the configuration of the pixel sensor unit and pixel readout circuit FIG. 3 is a diagram showing an example of the configuration of pixel sensor units 71 and pixel readout circuits 81 provided in one-to-one correspondence.

[0023] The pixel sensor unit 71 includes a light receiving element, that is, a SPAD 101. The pixel readout circuit 81 includes a transistor 102, an inverter 103 (input amplifier), and a level-down unit 104.

[0024] The cathode of the SPAD 101 is connected to the drain of the transistor 102 and also to the input terminal of the inverter 103. The anode of the SPAD 101 is connected to a power supply voltage VA (hereinafter also referred to as an anode voltage VA). When incident light is incident on the SPAD 101, the SPAD 101 avalanche amplifies the generated electrons and outputs a signal of the cathode voltage VS.

[0025] The SPAD101 has the property that when a large negative voltage that causes avalanche multiplication is applied to the cathode, the electrons generated in response to the incidence of a single photon undergo avalanche multiplication, resulting in a large current flow. By utilizing this property of the SPAD101, the incidence of a single photon can be detected with high sensitivity. The power supply voltage VA supplied to the anode of the SPAD101 is a negative voltage corresponding to the breakdown voltage VBD, and is set to a negative bias of, for example, about -20V.

[0026] The transistor 102 is a constant current source that operates in the saturation region and performs passive quenching by acting as a quenching resistor. The source of the transistor 102 is connected to the power supply voltage VE, and the drain is connected to the cathode of the SPAD 101 and the input terminal of the inverter 103. This allows the power supply voltage VE to be supplied to the cathode of the SPAD 101 as well. A bias voltage BIAS is supplied to the gate of the transistor 102.

[0027] To detect photons with sufficient efficiency, a voltage (hereinafter referred to as excess bias) greater than the breakdown voltage VBD of the SPAD 101 is applied to the SPAD 101. For example, if the breakdown voltage VBD of the SPAD 101 is 20 V and a voltage 3 V greater than that is applied, the power supply voltage VE supplied to the source of the transistor 102 is set to 3 V.

[0028] The breakdown voltage VBD of the SPAD 101 varies significantly depending on the temperature, etc. Therefore, the voltage applied to the SPAD 101 is controlled (adjusted) in accordance with the change in the breakdown voltage VBD. For example, if the power supply voltage VE is a fixed voltage, the anode voltage VA is controlled (adjusted).

[0029] The inverter 103 compares the cathode voltage VS signal from the SPAD 101 with a threshold voltage Vth, and outputs a detection signal PFout that is inverted every time the threshold voltage Vth is exceeded in either a positive or negative direction. The inverter 103 is configured using thick-film MOS transistors.

[0030] FIG. 4 shows the relationship between the signal of the cathode voltage VS input from the SPAD 101 to the inverter 103 and the detection signal PFout output by the inverter 103.

[0031] The inverter 103 inverts the detection signal PFout at time t0 when the cathode voltage VS crosses the threshold voltage Vth in the voltage drop due to avalanche multiplication in response to the incidence of photons on the SPAD 101. Next, the SPAD 101 is charged by a recharge operation, and the cathode voltage VS rises. The inverter 103 again inverts the detection signal PFout at time t1 when this rising cathode voltage VS crosses the threshold voltage Vth. The width in the time direction between time t0 and time t1 becomes the output pulse in response to the incidence of photons on the SPAD 101. The inverter 103 shapes this output pulse and outputs it to the level-down unit 104.

[0032] 3, the level-down unit 104 is a voltage conversion unit that converts the detection signal PFout input from the inverter 103 to a voltage level at which the TDC provided downstream operates. For example, if the power supply voltage VE is 3V, the level-down unit 104 converts the detection signal PFout, which has a voltage amplitude of 0V to 3V, into a signal having a voltage amplitude of 0V to 1V.

[0033] <4. Pixel cross section> Fig. 5 shows a cross-sectional view of the pixel portion of the first substrate 51 and the second substrate 52. Fig. 5 shows a cross-sectional view of a portion where two pixels PX, each consisting of a pair of pixel sensor units 71 and a pixel readout circuit 81, are lined up in the row or column direction.

[0034] 5, the first substrate 51 and the second substrate 52 are bonded together at the bonding surface indicated by the dotted line. The first substrate 51 has a semiconductor substrate 141 formed of a silicon substrate or the like, and a wiring layer 142. Hereinafter, the wiring layer 142 will be referred to as the sensor-side wiring layer 142 to easily distinguish it from the wiring layer 212 on the second substrate 52 side described later. The wiring layer 212 on the second substrate 52 side will be referred to as the logic-side wiring layer 212. With respect to the semiconductor substrate 141, the surface on which the sensor-side wiring layer 142 is formed is the front surface, and the surface on which the upper on-chip lens 143 is formed in the figure is the back surface of the semiconductor substrate 141, which is the light-receiving surface onto which reflected light is incident.

[0035] The pixel region of the semiconductor substrate 141 includes an N-well 151, a P-type diffusion layer 152, an N-type diffusion layer 153, a hole accumulation layer 154, and a high-concentration P-type diffusion layer 155. An avalanche multiplication region 156 is formed by a depletion layer formed in a region where the P-type diffusion layer 152 and the N-type diffusion layer 153 are connected.

[0036] The N well 151 is formed by controlling the impurity concentration of the semiconductor substrate 141 to be n-type, and forms an electric field that transfers electrons generated by photoelectric conversion in the pixel PX to the avalanche multiplication region 156. Note that instead of the N well 151, a P well may be formed by controlling the impurity concentration of the semiconductor substrate 141 to be p-type.

[0037] The P-type diffusion layer 152 is a dense P-type diffusion layer (P+) formed over almost the entire surface of the pixel region in the planar direction. The N-type diffusion layer 153 is a dense N-type diffusion layer (N+) formed over almost the entire surface of the pixel region near the surface of the semiconductor substrate 141, similar to the P-type diffusion layer 152. The N-type diffusion layer 153 is a contact layer that connects to the contact electrode 181 serving as a cathode electrode for supplying a negative voltage to form the avalanche multiplication region 156, and has a convex shape such that a part of it extends to the contact electrode 181 on the surface of the semiconductor substrate 141.

[0038] The hole accumulation layer 154 is a P-type diffusion layer (P) formed to surround the side and bottom surfaces of the N-well 151, and accumulates holes. The hole accumulation layer 154 is also connected to a high-concentration P-type diffusion layer 155 that is electrically connected to a contact electrode 182 serving as an anode electrode of the SPAD 101.

[0039] The high-concentration P-type diffusion layer 155 is a high-concentration P-type diffusion layer (P++) formed near the surface of the semiconductor substrate 141 so as to surround the outer periphery of the N-well 151, and constitutes a contact layer for electrically connecting the hole accumulation layer 154 to the contact electrode 182 of the SPAD 101.

[0040] On the sensor-side wiring layer 142, contact electrodes 181 and 182, metal wires 183 and 184, contact electrodes 185 and 186, and metal wires 187 and 188 are formed.

[0041] The contact electrode 181 connects the N-type diffusion layer 153 to a metal wiring 183 , and the contact electrode 182 connects the high-concentration P-type diffusion layer 155 to a metal wiring 184 .

[0042] The metal wiring 183 is formed in a planar region wider than the avalanche multiplication region 156 so as to cover at least the avalanche multiplication region 156. The metal wiring 183 may have a structure that reflects light that has passed through the pixel region of the semiconductor substrate 141 toward the semiconductor substrate 141.

[0043] The metal wiring 184 is formed so as to surround the outer periphery of the metal wiring 183 in the planar region and overlap with the high concentration P-type diffusion layer 155.

[0044] The contact electrode 185 connects the metal wiring 183 and the metal wiring 187 , and the contact electrode 186 connects the metal wiring 184 and the metal wiring 188 .

[0045] On the other hand, the second substrate 52 has a semiconductor substrate 211 made of a silicon substrate or the like, and a wiring layer 212 (logic-side wiring layer 212).

[0046] In the drawing, a plurality of MOS transistors Tr are formed on the front surface side of the upper semiconductor substrate 211, and a logic-side wiring layer 212 is also formed on the front surface side of the semiconductor substrate 211. The plurality of MOS transistors Tr include an N-type MOS transistor Tr1 and a P-type MOS transistor Tr2.

[0047] The logic-side wiring layer 212 includes metal wirings 231 and 232 , metal wirings 233 and 234 , and contact electrodes 235 and 236 .

[0048] The metal wiring 231 is electrically connected to the metal wiring 187 of the sensor-side wiring layer 142 by metal bonding such as Cu-Cu. The metal wiring 232 is electrically connected to the metal wiring 188 of the sensor-side wiring layer 142 by metal bonding such as Cu-Cu.

[0049] The contact electrode 235 connects the metal wiring 231 and the metal wiring 233 , and the contact electrode 236 connects the metal wiring 232 and the metal wiring 234 .

[0050] The logic-side wiring layer 212 further includes a plurality of layers of metal wiring 241 between the layer of the metal wirings 233 and 234 and the semiconductor substrate 211 .

[0051] On the second substrate 52, a pixel readout circuit 81 and logic circuits 301 and 311 (described later) are formed by a plurality of MOS transistors Tr and a plurality of layers of metal wiring 241 formed on the front surface side of the semiconductor substrate 211.

[0052] In a pixel PX including the pixel sensor unit 71 and pixel readout circuit 81 configured as described above, metal wiring 187 and metal wiring 231, and metal wiring 188 and metal wiring 232, which electrically connect the first substrate 51 and the second substrate 52 by metal junctions such as Cu-Cu, form the connection parts of the pixel region.

[0053] <5. Block diagram of the second board> FIG. 6 is a block diagram showing an example of the configuration of the second substrate 52. As shown in FIG.

[0054] The second substrate 52 has a plurality of pixel readout circuits 81 and a logic circuit 301 in a pixel array lower region 82 formed in a position corresponding to the pixel array region 72 of the first substrate 51. The rectangular regions divided into a grid pattern in the pixel array lower region 82 indicated by dashed lines represent the pixel regions of one pixel, and the pixel readout circuit 81 is provided for each pixel region. The logic circuit 301 is made up of a plurality (R>1) of logic circuits 301-1 to 301-R. The logic circuits 301-1 to 301-R are distributed and arranged in the region below the pixel array 82 excluding the region of the pixel readout circuit 81. Adjacent logic circuits 301-P, 301-Q (P and Q are different integers equal to or less than R) are electrically connected to each other by connection wiring. Therefore, each pixel region includes a pixel readout circuit 81 provided for each pixel, and a portion of the logic circuit 301.

[0055] In addition, the second substrate 52 has, in an area outside the pixel array lower area 82, a logic circuit 311, an array driving unit 312, a distance measurement control unit 313, a clock generation unit 314, an I / F unit 315, a memory 316, a reference current source 317, a thermometer 318, etc.

[0056] The logic circuit 311 is a circuit that performs a different function from the logic circuit 301 arranged in the pixel array lower region 82. Specific circuit examples of the logic circuit 301 arranged in the pixel array lower region 82 and the logic circuit 311 arranged outside the pixel array lower region 82 will be described later with reference to FIGS. 7, 8, etc. In the following, to easily distinguish between the logic circuit 301 and the logic circuit 311, the logic circuit 301 arranged in the pixel array lower region 82 will be referred to as a first logic circuit 301, and the logic circuit 311 arranged outside the pixel array lower region 82 will be referred to as a second logic circuit 311. However, as will be described later with reference to FIG. 13, the logic circuit 311 may also be arranged within the pixel array lower region 82.

[0057] The array driver 312 controls the pixel readout circuits 81 arranged in a matrix in the pixel array lower region 82. The array driver 312 may be able to individually control whether the operation of each pixel readout circuit 81 is enabled or disabled.

[0058] The ranging control unit 313 controls the overall operation of the photodetector 23 in accordance with, for example, a pre-installed program. The ranging control unit 313 controls the operations of the first logic circuit 301, the second logic circuit 311, the array driving unit 312, etc., based on a clock signal supplied from a clock generating unit 314. The ranging control unit 313 also generates a light emission timing signal indicating the timing at which the light source device 22 emits light, and supplies the light source device 22 with the light emission timing signal.

[0059] The clock generating unit 314 generates one or more clock signals used in the photodetector 23 based on a reference clock signal supplied from the outside (for example, the control unit 21 of the distance measuring device 11), and supplies the generated signals to the distance measurement control unit 313 and the like.

[0060] The I / F unit 315 converts the distance information generated by the first logic circuit 301 into a predetermined communication interface format and outputs it to an external device (for example, the control unit 21 of the distance measuring device 11). As the communication interface, for example, MIPI (Mobile Industry Processor Interface) can be applied.

[0061] The memory 316 is a storage unit that stores various setting information such as operation modes and temporarily stores data required during operation.

[0062] The reference current source 317 generates a basic reference current used in each circuit in the photodetector 23 and supplies it to each section.

[0063] The thermometer 318 measures the temperature inside the photodetector 23. The measured temperature is used to control (adjust) the anode voltage VA of the SPAD 101, for example.

[0064] As described above, the second substrate 52 of the photodetector 23 has a configuration in which the logic circuit is divided into a first logic circuit 301 in the pixel array lower region 82 and a second logic circuit 311 outside the pixel array lower region 82.

[0065] <6. Example of allocation of logic circuits within the array and logic circuits outside the array> Next, an example of the division of functions between the first logic circuit 301 and the second logic circuit 311 will be described.

[0066] First, a series of processes up to the generation of distance information based on the detection signal PFout output by the pixel readout circuit 81 will be described with reference to FIG.

[0067] 7, a MUX 331, a plurality of TDCs 332, a TDC result calculation unit 333, a histogram generation unit 334, and a distance calculation unit 335 are arranged in either the first logic circuit 301 or the second logic circuit 311. The TDC result calculation unit 333 and the distance calculation unit 335, which are indicated by dashed lines in FIG. 7, may be omitted. The histogram generation unit 334 is made up of a decoder unit 351, a counter unit 352, and a readout unit 353.

[0068] The MUX (multiplexer) 331 switches the connection between the pixel readout circuit 81 of each pixel PX arranged in a matrix in the pixel array lower region 82 and the multiple TDCs 332. The MUX 331 appropriately switches between the multiple pixel readout circuits 81 arranged in a matrix in a predetermined order, and acquires the detection signal PFout output by the pixel readout circuit 81 of each pixel PX. The MUX 331 also outputs the detection signal PFout acquired from a predetermined pixel readout circuit 81 to one of the multiple TDCs 332.

[0069] Each TDC (Time to Digital Converter) 332 converts the time at which the SPAD 101 of the pixel PX reacts into time information. The TDC 332 generates a count value indicating the time from when the light source device 22 emits light to when the SPAD 101 of the pixel PX receives light and reacts, based on the pixel signal (detection signal PFout) of the predetermined pixel PX supplied from the MUX 73 and the light emission timing signal generated by the distance measurement control unit 313. The TDC 332 supplies the count value generated for each pixel to the TDC result calculation unit 333 as the TDC result. A MUX (multiplexer) that switches the connection between multiple TDCs 332 and the TDC result calculation unit 333 may also be provided downstream of each TDC 332.

[0070] The TDC result calculation unit 333 performs predetermined calculations as necessary on the count values ​​supplied as TDC results from the TDC 332. For example, the TDC result calculation unit 333 subtracts a correction value for correcting distance information from the count values ​​from the TDC 332 in order to correct the distance measurement results. Furthermore, for example, the TDC result calculation unit 333 merges (adds up) count values ​​of multiple pixels in order to improve the count rate per distance measurement point and increase the S / N ratio. The TDC result calculation unit 333 supplies the calculated count values ​​to a decoder unit 351 of the histogram generation unit 334. If calculations by the TDC result calculation unit 333 are not required, the TDC result calculation unit 333 can be omitted.

[0071] The decoder unit 351 generates a signal for counting up the bin of the histogram corresponding to the count value from the TDC 332 or the TDC result calculation unit 333 , and supplies the signal to the counter unit 352 .

[0072] The counter unit 352 counts up the frequency value of a bin with a predetermined count value in the histogram based on the signal supplied from the decoder unit 351. In direct ToF distance measurement, light is emitted by the light source device 22 and reflected light is received by the photodetector device 23 a predetermined number of times (for example, thousands to tens of thousands of times). The frequency value of the bin with a count value corresponding to the time until the reflected light is received is counted up, and a histogram is generated for each pixel.

[0073] The readout unit 353 reads out the histogram data generated for each pixel by the counter unit 352 (histogram data), and outputs it to the distance calculation unit 335. When the distance calculation unit 335 is omitted, the histogram data for each pixel is output to the control unit 21 as distance information.

[0074] The distance calculation unit 335 detects the bin with the highest frequency value for each pixel based on the histogram data of each pixel supplied from the readout unit 353, and outputs the detected bin as distance information to the control unit 21. Alternatively, the distance calculation unit 335 calculates the distance D corresponding to the bin with the highest frequency value, stores the calculated distance D as a depth value, and outputs the calculated distance D to the control unit 21 as distance information. The distance calculation unit 335 may calculate the distance D not only using the bin with the highest frequency value, but also using multiple bins surrounding the bin. For example, the distance calculation unit 335 may calculate the center of gravity of the count values ​​of multiple bins including the peak position, and calculate and output the distance D at a resolution lower than that of the bin. If the distance calculation unit 335 is omitted, the calculation equivalent to that of the distance calculation unit 335 can be performed by the control unit 21.

[0075] FIG. 8 is a diagram showing an example of allocation of the first logic circuit 301 and the second logic circuit 311 of each part shown in FIG.

[0076] 8, for example, the TDC result calculation unit 333, the histogram generation unit 334, and the distance calculation unit 335 are arranged in the first logic circuit 301 in the pixel array lower area 82. More specifically, the TDC result calculation unit 333, the histogram generation unit 334, and the distance calculation unit 335 are appropriately distributed and arranged in the first logic circuits 301-1 to 301-R. How the TDC result calculation unit 333, the histogram generation unit 334, and the distance calculation unit 335 are arranged in the first logic circuits 301-1 to 301-R can be determined using, for example, an automatic circuit placement and routing tool.

[0077] Meanwhile, the MUX 331 and the plurality of TDCs 332 are arranged in a second logic circuit 311 outside the region 82 below the pixel array. Note that circuits other than the MUX 331 and the TDC 332 may also be arranged in the second logic circuit 311. For example, a configuration may be adopted in which a plurality of clock generation circuits that generate clock signals used for the counting operation of the TDC 332 are arranged in the second logic circuit 311, and an individual clock generation circuit is used for each region obtained by dividing the region 82 below the pixel array.

[0078] In the signal (data) flow, the detection signal PFout output from the pixel readout circuit 81 of each pixel region in the pixel array lower region 82 is input to a second logic circuit 311 outside the pixel array lower region 82. In the second logic circuit 311 outside the pixel array lower region 82, the MUX 331 appropriately switches between the connection with the pixel readout circuit 81 and the connection with the plurality of TDCs 332, and each TDC 332 generates a count value corresponding to the time from when the light source device 22 emits light to when the pixel PX receives the light. The count value generated by each TDC 332 is output to a first logic circuit 301 (one of 301-1 to 301-R) in the pixel array lower region 82. Then, a histogram is generated in the first logic circuit 301 in the pixel array lower region 82, and the distance D to the object 30 is calculated based on the generated histogram and output to the outside as distance information. In this way, the signal (data) goes from inside the region 82 below the pixel array to outside the region 82 below the pixel array, and then returns to the region 82 below the pixel array.

[0079] A control unit 336 may be further provided in the first logic circuit 301 in the pixel array lower region 82. The control unit 336 may have the following functions, for example: The control unit 336 controls the enable / disable of each pixel readout circuit 81 and the enable / disable of each TDC 332 based on signals from the control unit 21 outside the photodetector 23 and signals from the memory 316. Furthermore, for example, the control unit 336 generates a control signal that specifies a bias voltage BIAS to be input to the gate of the transistor 102 serving as a current source for each pixel readout circuit 81. For example, if the range of the illumination light 31 output by the light source device 22 is limited and it is not necessary to drive all pixels in the pixel array region 72 in the photodetector 23, it is possible to stop some of the pixel readout circuits 81 and some of the TDCs 332 depending on the pixels not to be driven.

[0080] As described above, the photodetector 23 can distribute the logic circuits that process the detection signals PFout output from each pixel readout circuit 81 between the first logic circuit 301 within the pixel array lower region 82 and the second logic circuit 311 outside the pixel array lower region 82.

[0081] <7. Example of circuit layout in the area below the pixel array> 6, a pixel readout circuit 81 and a part of the first logic circuit 301 are arranged in each pixel region of the region 82 under the pixel array of the second substrate 52. Examples of the arrangement of the pixel readout circuit 81 and the first logic circuit 301 will be described with reference to FIGS.

[0082] (1st placement example) FIG. 9 is a plan view showing a first arrangement example of the pixel array lower region 82 of the second substrate 52. As shown in FIG.

[0083] Fig. 9 shows a plan view of a 4x4 pixel region in the pixel array lower region 82. In Fig. 9, rectangular regions separated by dashed lines represent pixel regions of one pixel. This also applies to Figs. 10 and 11.

[0084] 9, the pixel readout circuit 81 is disposed in the center of the pixel region, and the connection portion 401 is disposed within the region of the pixel readout circuit 81 and in the center of the pixel region. The connection portion 401 is a wiring that is electrically connected to the SPAD 101 of the pixel sensor unit 71 of the first substrate 51. The connection portion 401 corresponds to, for example, the metal wiring 231, 232 that is connected to the sensor-side wiring layer 142 of the first substrate 51 by metal junction, as shown in the cross-sectional view of FIG. 5. The region of the pixel region other than the pixel readout circuit 81 is the region of one of the first logic circuits 301-1 to 301-R.

[0085] If an area of ​​NxM pixel units (N and M are integers equal to or greater than 1) is defined as a unit area 411, the pixel array lower area 82 in the first arrangement example is configured such that 1x1 pixel unit areas 411 indicated by thick solid lines are repeatedly arranged in the row and column directions, with N and M = 1. The 1x1 pixel unit areas 411 are configured with a pixel readout circuit 81 in which the arrangement of transistors and metal wiring is common to the unit areas 411, and (a part of) a first logic circuit 301 in which the arrangement of transistors and metal wiring is different (non-common) in the unit areas 411.

[0086] Looking at the region of each pixel readout circuit 81 in the region 82 under the pixel array, the transistors of a unit region 411 consisting of one pixel readout circuit 81 are regularly arranged in the region under the pixel array 82. Therefore, the region under the pixel array 82 is made up of a region (first transistor region) of a plurality of pixel readout circuits 81 in which the transistors of the unit regions 411 are regularly arranged, and a region (second transistor region) of the first logic circuit 301 in which the transistors are irregularly arranged.

[0087] The connection portion 401 is disposed within the pixel readout circuit 81. For example, if the connection portion 401 is the metal wiring 231 in the cross-sectional view shown in FIG. 5 , the contact electrode 235 connected to the metal wiring 231 and the arrangement of the contact electrode 235 are also the same in the unit area 411. By disposing the connection portion 401 within the pixel readout circuit 81, the coupling capacitance of the wiring leading to connection to the pixel readout circuit 81 can be made uniform within the area 82 under the pixel array.

[0088] Furthermore, in the first arrangement example, the positions of the connection portions 401 are the same for all pixels, so that the optical characteristics of all pixels can be made uniform.

[0089] (Second placement example) FIG. 10 is a plan view showing a second arrangement example of the pixel array lower region 82 of the second substrate 52. As shown in FIG.

[0090] In the first arrangement example shown in Fig. 9, the pixel readout circuits 81 were arranged in the center of the pixel region, but in the second arrangement example shown in Fig. 10, the pixel readout circuits 81 are arranged on one side of the pixel region so that the pixel readout circuits 81 of two adjacent rows are adjacent. Specifically, in one of the odd-numbered rows and the even-numbered rows, the pixel readout circuits 81 are arranged at the bottom of the pixel region in the column direction, and in the other, the pixel readout circuits 81 are arranged at the top of the pixel region in the column direction. As in the first arrangement example, the connection unit 401 is arranged within the pixel readout circuit 81.

[0091] The pixel array lower region 82 of the second arrangement example is configured such that 1x2 pixel unit regions 411 indicated by thick solid lines are repeatedly arranged in the row and column directions in an NxM pixel unit region 411 where N=1 and M=2. The 1x2 pixel unit region 411 is configured with two pixel readout circuits 81 in which the arrangement of transistors and metal wiring is common to the unit region 411, and (part of) a first logic circuit 301 in which the arrangement of transistors and metal wiring is different (non-common) in the unit region 411.

[0092] Looking at the region of each pixel readout circuit 81 in the pixel array lower region 82, transistors of a unit region 411 consisting of two pixel readout circuits 81 are regularly arranged in the pixel array lower region 82. Therefore, the pixel array lower region 82 is made up of a region (first transistor region) of a plurality of pixel readout circuits 81 in which the transistors of the unit regions 411 are regularly arranged, and a region (second transistor region) of the first logic circuit 301 in which transistors are irregularly arranged.

[0093] In the second arrangement example as well, the connection section 401 is arranged inside the pixel readout circuit 81, so that the coupling capacitance of the wiring leading to the pixel readout circuit 81 can be made uniform within the region 82 under the pixel array.

[0094] Furthermore, in the second arrangement example, by arranging the pixel readout circuits 81 so that they are adjacent to each other in two adjacent rows, the area efficiency of the pixel readout circuits 81 can be improved.

[0095] (3rd arrangement example) FIG. 11 is a plan view showing a third arrangement example of the pixel array lower region 82 of the second substrate 52. As shown in FIG.

[0096] In the third arrangement example shown in Fig. 11, pixel readout circuits 81 are arranged on one side of the pixel region so as to contact two adjacent rows, similar to the second arrangement example in Fig. 10. On the other hand, the difference from the second arrangement example shown in Fig. 10 is that, while in the second arrangement example, connection unit 401 is arranged inside pixel readout circuit 81, in the third arrangement example, connection unit 401 is arranged inside the region of first logic circuit 301 and in the center of the pixel region.

[0097] The pixel array lower region 82 of the third arrangement example is configured such that 1x2 pixel unit regions 411 indicated by thick solid lines are repeatedly arranged in the row and column directions in an NxM pixel unit region 411 where N=1 and M=2. The 1x2 pixel unit region 411 is configured with two pixel readout circuits 81 in which the arrangement of transistors and metal wiring is common to the unit region 411, and (part of) a first logic circuit 301 in which the arrangement of transistors and metal wiring is different (non-common) in the unit region 411.

[0098] Looking at the region of each pixel readout circuit 81 in the pixel array lower region 82, transistors of a unit region 411 consisting of two pixel readout circuits 81 are regularly arranged in the pixel array lower region 82. Therefore, the pixel array lower region 82 is made up of a region (first transistor region) of a plurality of pixel readout circuits 81 in which the transistors of the unit regions 411 are regularly arranged, and a region (second transistor region) of the first logic circuit 301 in which transistors are irregularly arranged.

[0099] In the third arrangement example, the pixel readout circuits 81 are arranged so that two adjacent rows are in contact with each other, thereby improving the area efficiency of the pixel readout circuits 81.

[0100] Furthermore, in the third arrangement example, the positions of the connection portions 401 are the same for all pixels, so that the optical characteristics of all pixels can be made uniform.

[0101] (4th placement example) In the above example, the first logic circuit 301 is arranged in the region 82 below the pixel array. However, a part of the first logic circuit 301 may be formed outside the region 82 below the pixel array.

[0102] FIG. 12 is a plan view showing a fourth arrangement example of the pixel array lower region 82 of the second substrate 52, and shows an example in which the first logic circuit 301 is also arranged outside the pixel array lower region 82.

[0103] 12 is similar to the first arrangement example in Fig. 9 except that a part of the first logic circuit 301 (first logic circuit 301-R) is arranged outside the pixel array lower region 82. In the example of Fig. 12, an example is shown in which the first logic circuit 301 extends outside the pixel array lower region 82 only in the direction of one side of the rectangular pixel array lower region 82, but the first logic circuit 301 may extend outward in the directions of two or more sides of the pixel array lower region 82.

[0104] (5th placement example) In the above example, the second logic circuit 311 is arranged outside the region 82 below the pixel array. However, the second logic circuit 311 may be arranged inside the region 82 below the pixel array.

[0105] FIG. 13 is a plan view showing a fifth arrangement example of the region 82 below the pixel array of the second substrate 52, and shows an example in which the second logic circuit 311 is arranged in the region 82 below the pixel array.

[0106] In this way, the second logic circuit 311 can also be arranged within the pixel array lower region 82. The second logic circuit 311 may also be arranged across both the pixel array lower region 82 and outside the pixel array lower region 82.

[0107] (Summary of circuit layout in the area below the pixel array) The region 82 below the pixel array of the second substrate 52 is configured by arranging a plurality of unit regions 411, each consisting of one or more pixels, in the row or column direction, and includes one or more pixel readout circuits 81 in which transistors and metal wiring are commonly arranged in the unit regions 411, and a first logic circuit 301 in which circuits including transistors and metal wiring are arranged across the unit regions 411. In other words, the region 82 below the pixel array of the second substrate 52 includes a first transistor region made up of a plurality of pixel readout circuits 81 in which transistors of the unit regions 411 are regularly arranged, and a second transistor region in which the first logic circuit 301 is formed by irregularly arranging transistors. The first logic circuit 301 includes at least a histogram generator 334 that generates a histogram of count values ​​based on the detection signal PFout output by the pixel readout circuit 81.

[0108] By arranging the first logic circuit 301, which includes at least the histogram generation unit 334, in the region 82 below the pixel array of the second substrate 52, it is possible to reduce the area of ​​the second logic circuit 311 outside the region 82 below the pixel array, thereby reducing the chip area. By arranging the histogram generation unit 334 in the region 82 below the pixel array, it is possible to ensure a large number of bins in the histogram and a large number of bits in the count value, regardless of the size of the ranging point, thereby enabling the ranging range to be increased.

[0109] Furthermore, by arranging the second logic circuit 311 having multiple TDCs 332 outside the pixel array lower region 82, the size of the ranging points (pixel size) can be reduced, thereby improving the ranging point density. The number of bits of the count value of the TDC 332 can be increased without being restricted by the ranging point size, enabling a longer ranging range. The signal transmission bandwidth can be improved by increasing the wiring width and using wiring layers with low sheet resistance, thereby improving the resolution of the TDC 332 and the ranging accuracy.

[0110] That is, the photodetector 23 including the second substrate 52 allows miniaturization of pixels without increasing the chip area.

[0111] <8. Other configuration examples of pixel readout circuit> Other configuration examples of the pixel readout circuit 81 will be described.

[0112] FIG. 14 is a diagram showing a first modified example of the pixel readout circuit 81. In FIG.

[0113] In the first modified example shown in Fig. 14, a circuit 105 that performs a predetermined function is added to the basic configuration of pixel readout circuit 81 shown in Fig. 3. Circuit 105 is arranged after level-down unit 104. Circuit 105 can be, for example, a buffer circuit or a pulse shortening circuit.

[0114] FIG. 15 is a diagram showing a second modified example of the pixel readout circuit 81. In FIG.

[0115] In the second modified example shown in FIG. 15, a latch circuit 111, an inverter 112, and a switch 113 are added to the basic configuration of the pixel readout circuit 81 shown in FIG.

[0116] The pixel readout circuit 81 of the second modified example is configured so that photon detection can be turned on and off for each pixel.

[0117] The switch 113 has one end connected to the cathode of the SPAD 101, the input terminal of the inverter 103, and the drain of the transistor 102, and the other end connected to ground (GND). The switch 113 can be configured, for example, with an N-type MOS transistor, and is turned on and off in response to a gating inversion signal VG_I ​​obtained by inverting the gating control signal VG, which is the output of the latch circuit 111, by an inverter 112.

[0118] The latch circuit 111 supplies a gating control signal VG, which controls the pixel PX to be either enabled or disabled, to an inverter 112 based on a trigger signal SET and address data DEC supplied from the array drive unit 312. The inverter 112 inverts the gating control signal VG to generate a gating inversion signal VG_I ​​and supplies it to a switch 113.

[0119] The trigger signal SET is a timing signal that indicates the timing for switching the gating control signal VG, and the address data DEC is data that indicates the address of a pixel PX that is to be set as an effective pixel among the multiple pixels PX arranged in a matrix. The trigger signal SET and the address data DEC are supplied from the array driver 312.

[0120] The latch circuit 111 reads address data DEC at a predetermined timing indicated by the trigger signal SET. If the pixel address indicated by the address data DEC includes the pixel address of the latch circuit 111 (of the pixel PX), the latch circuit 111 outputs a gating control signal VG of Hi (1) for setting the pixel PX as a valid pixel. On the other hand, if the pixel address indicated by the address data DEC does not include the pixel address of the latch circuit 111 (of the pixel PX), the latch circuit 111 outputs a gating control signal VG of Lo (0) for setting the pixel PX as an invalid pixel. As a result, when the pixel PX is set as a valid pixel, a gating inversion signal VG_I ​​of Lo (0) inverted by the inverter 112 is supplied to the switch 113. On the other hand, when the pixel PX is set as an invalid pixel, a gating inversion signal VG_I ​​of Hi (1) is supplied to the switch 113. The switch 113 is turned off (disconnected) when the pixel PX is set as a valid pixel, and is turned on (connected) when the pixel PX is set as an invalid pixel. When the switch 113 is turned on and the pixel PX is set as an inactive pixel, the cathode voltage VS of the SPA 101 becomes 0V (GND) and the anode-cathode voltage of the SPAD 101 becomes equal to or lower than the breakdown voltage VBD, so that the SPAD 101 does not react even if a photon enters it.

[0121] <9. Other connection examples between pixel sensor unit and pixel readout circuit> Another example of the connection between the pixel sensor unit 71 and the pixel readout circuit 81 will be described.

[0122] 3, there is a one-to-one correspondence between pixel sensor units 71 and pixel readout circuits 81. However, a configuration in which one pixel readout circuit 81 is provided for a plurality of pixel sensor units 71 may also be used.

[0123] 16 shows a configuration example in which one pixel readout circuit 81 is provided for the SPADs 101 of four pixel sensor units 71. By connecting multiple SPADs 101 to one pixel readout circuit 81, it is possible to reduce variations in the breakdown voltage VBD.

[0124] Alternatively, instead of connecting multiple SPADs 101 to one pixel readout circuit 81 via a single wire as in FIG. 16 , a configuration may be adopted in which multiple SPADs 101 are connected to one pixel readout circuit 81 via multiple wires as shown in FIG. 17 . In FIG. 17 , two SPADs 101 are connected to one wire, and two wires are connected to one pixel readout circuit 81, so that one pixel readout circuit 81 is connected to a total of four SPADs 101. The number of wires connected to the pixel readout circuit 81 may be three or more. The number of SPADs 101 of the pixel sensor unit 71 connected to one wire may be three or more. In this way, by connecting multiple wires to one pixel readout circuit 81 and connecting multiple SPADs 101 to each wire, it is possible to reduce variations in the breakdown voltage VBD and optimize the wiring RC load.

[0125] <10. Example of a three-layer laminated structure> In the above-described example, as shown in FIG. 2, the photodetector 23 is configured to have a laminated structure of two substrates, that is, the first substrate 51 and the second substrate 52 laminated together.

[0126] However, the photodetector 23 may be configured with a stacked structure of three or more substrates.

[0127] FIG. 18 is a perspective view showing an example of a photodetector 23 configured with a stacked structure of three substrates.

[0128] The photodetector 23 is configured by a semiconductor chip having a stacked structure of three substrates, that is, a third substrate 53 in addition to the first substrate 51 and second substrate 52 described above.

[0129] The third substrate 53 has at least a pixel array lower region 92 in which predetermined processing circuits 91 are two-dimensionally arranged in a matrix in the row and column directions. The processing circuits 91 may or may not correspond one-to-one to the pixel sensor units 71 of the first substrate 51 and the pixel readout circuits 81 of the second substrate 52. The processing circuits 91 are electrically connected to the pixel readout circuits 81 above. There are no particular limitations on the type of circuit provided as the processing circuit 91 on the third substrate 53. The third substrate 53 may include a portion of the pixel readout circuit 81 of the second substrate 52, or may include some or all of the first logic circuit 301 and the second logic circuit 311. Furthermore, the third substrate 53 may also include a clock generation unit 314, an I / F unit 315, a memory 316, and the like, in addition to the first logic circuit 301 and the second logic circuit 311.

[0130] By configuring the photodetector 23 with a stacked structure of three substrates, there is more space for circuit layout on the second substrate 52, which makes it possible to reduce the chip area and further increase the distance measurement range.In addition, it becomes possible to further miniaturize the pixels without increasing the chip area.

[0131] <11. Mobile application examples> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0132] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0133] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0134] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0135] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0136] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0137] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0138] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0139] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0140] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0141] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0142] The audio / video output unit 12052 transmits at least one output signal of audio and / or video to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 19, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0143] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031.

[0144] In FIG. 20, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0145] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0146] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0147] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or an imaging element having pixels for detecting a phase difference.

[0148] For example, the microcomputer 12051 can extract, as a preceding vehicle, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher) by calculating the distance to each three-dimensional object within the imaging ranges 12111-12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101-12104. Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which travels autonomously without relying on driver operation.

[0149] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0150] At least one of the image capturing units 12101-12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101-12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101-12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101-12104 and recognizes the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / video output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0151] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the configurations described above. Specifically, the electronic device 1 or the distance measuring device 11 in FIG. 1 can be applied as the imaging unit 12031. The imaging unit 12031 is, for example, a LIDAR, and is used to detect objects around the vehicle 12100 and the distance to the objects. By applying the technology according to the present disclosure to the imaging unit 12031, the accuracy of detecting objects around the vehicle 12100 and the distance to the objects is improved. As a result, for example, a vehicle collision warning can be issued at an appropriate time, making it possible to prevent traffic accidents.

[0152] In the above example, a pixel cross-sectional structure was described in which the first conductivity type was P-type and the second conductivity type was N-type, and electrons were used as signal charges, but the present disclosure can also be applied to a pixel cross-sectional structure in which holes are used as signal charges. That is, the first conductivity type can be N-type and the second conductivity type can be P-type, and the aforementioned semiconductor regions can be configured with semiconductor regions of opposite conductivity types.

[0153] In this specification, a system refers to a collection of multiple components (devices, modules (components), etc.), regardless of whether all the components are contained in the same housing. Therefore, multiple devices housed in separate housings and connected via a network, and a single device housed in a single housing with multiple modules, are both systems.

[0154] The embodiments of the technology of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the technology of the present disclosure.

[0155] The effects described in this specification are merely examples and are not intended to be limiting, and there may be effects other than those described in this specification.

[0156] The technology of the present disclosure can employ the following configurations. (1) The display device is configured by stacking a first substrate having a pixel array region in which light receiving elements are two-dimensionally arranged in a matrix, and a second substrate having a pixel array lower region corresponding to the pixel array region, The region below the pixel array is configured by arranging a plurality of unit regions, each of which is made up of one or more pixels, in a row direction or a column direction, and includes one or more pixel readout circuits having a common circuit layout in the unit regions, and a first logic circuit having a circuit layout across the unit regions. Light detection device. (2) The region below the pixel array includes a first transistor region including a plurality of pixel readout circuits in which transistors are regularly arranged in the unit region, and a second transistor region in which transistors are irregularly arranged and in which the first logic circuit is formed. The photodetector according to (1) above. (3) The first logic circuit includes a histogram generator that generates a histogram of count values ​​based on the detection signal output by the pixel readout circuit. The photodetector according to (1) or (2) above. (4) The first logic circuit further includes a distance calculation unit that calculates a distance to an object based on the histogram. The photodetector according to (3) above. (5) The first logic circuit further includes a control unit that controls the pixel readout circuit or the TDC that generates the count value. The photodetector according to (3) or (4) above. (6) The first logic circuit is arranged outside the pixel array area in addition to the pixel array area. The photodetector according to any one of (1) to (5) above. (7) The pixel array lower region further includes a connection portion electrically connected to the light receiving element of the first substrate. The photodetector according to any one of (1) to (6) above. (8) The connection portion is disposed within the region of the pixel readout circuit. The photodetector according to (7) above. (9) The connection portion is disposed in the center of the pixel region. The photodetector according to (7) or (8) above. (10) The connection portion is disposed within the pixel readout circuit area and in the center of the pixel area. The photodetector according to any one of (7) to (9) above. (11) The second substrate further includes a second logic circuit including at least a TDC that generates a count value indicating a time for which the light receiving element reacts based on the detection signal output by the pixel readout circuit. The photodetector according to any one of (1) to (10) above. (12) The second logic circuit is disposed outside the area under the pixel array. The photodetector according to (11) above. (13) The second logic circuit is disposed in the region below the pixel array. The photodetector according to (11) above. (14) The pixel readout circuit is disposed in the center of the pixel area. The photodetector according to any one of (1) to (13) above. (15) The pixel readout circuits are arranged so that the pixel readout circuits of two adjacent rows are in contact with each other. The photodetector according to any one of (1) to (13) above. (16) The pixel readout circuit is connected to the plurality of light receiving elements. The photodetector according to any one of (1) to (15) above. (17) The pixel readout circuit is connected to a plurality of wirings, and a plurality of the light receiving elements are connected to each wiring. The photodetector according to any one of (1) to (16) above. (18) a light source device that outputs irradiation light; a light detection device that receives reflected light of the irradiated light reflected by an object; Equipped with the photodetector is configured by stacking a first substrate having a pixel array region in which light receiving elements are two-dimensionally arranged in a matrix, and a second substrate having a pixel array lower region corresponding to the pixel array region; The region below the pixel array is configured by arranging a plurality of unit regions, each of which is made up of one or more pixels, in a row direction or a column direction, and includes one or more pixel readout circuits having a common circuit layout in the unit regions, and a first logic circuit having a circuit layout across the unit regions. electronic equipment. [Explanation of symbols]

[0157] 1 electronic device, 11 distance measuring device, 21 control unit, 22 light source device, 23 photodetector, 30 object, 31 irradiated light, 32 reflected light, 51 first substrate, 52 second substrate, 53 third substrate, 71 pixel sensor unit, 72 pixel array area, 81 pixel readout circuit, 82 pixel array lower area, 91 processing circuit, 92 pixel array lower area, 102 transistor, 103 inverter, 104 level down unit, 105 circuit, 111 latch circuit, 112 inverter, 113 switch, 141 semiconductor substrate, 142 wiring layer, 143 on-chip lens, 151 N well, 152 P-type diffusion layer, 153 N-type diffusion layer, 154 hole accumulation layer, 155 high-concentration P-type diffusion layer 156 avalanche multiplication region, 301 (301-1 to 301-R) logic circuit (first logic circuit), 311 logic circuit (second logic circuit), 312 array driving unit, 313 distance measurement control unit, 314 clock generation unit, 315 I / F unit, 316 memory, 317 reference current source, 318 thermometer, 333 TDC result calculation unit, 334 histogram generation unit, 335 distance calculation unit, 336 control unit, 341 metal wiring, 351 decoder unit, 352 counter unit, 353 readout unit, 401 connection unit, 411 repeating unit

Claims

1. The display device is configured by stacking a first substrate having a pixel array region in which light receiving elements are two-dimensionally arranged in a matrix, and a second substrate having a pixel array lower region corresponding to the pixel array region, The region below the pixel array is configured by arranging a plurality of unit regions, each of which is made up of one or more pixels, in a row direction or a column direction, and includes one or more pixel readout circuits having a common circuit layout in the unit regions, and a first logic circuit having a circuit layout across the unit regions. Light detection device.

2. The region below the pixel array includes a first transistor region including a plurality of pixel readout circuits in which transistors of the unit region are regularly arranged, and a second transistor region in which transistors are irregularly arranged and the first logic circuit is formed. The photodetector device according to claim 1 .

3. The first logic circuit includes a histogram generation unit that generates a histogram of count values ​​based on the detection signal output by the pixel readout circuit. The photodetector device according to claim 1 .

4. The first logic circuit further includes a distance calculation unit that calculates a distance to an object based on the histogram. The photodetector device according to claim 3 .

5. The first logic circuit further includes a control unit that controls the pixel readout circuit or the TDC that generates the count value. The photodetector device according to claim 3 .

6. The first logic circuit is arranged outside the pixel array area in addition to the pixel array area. The photodetector device according to claim 1 .

7. The pixel array lower region further includes a connection portion electrically connected to the light receiving element of the first substrate. The photodetector device according to claim 1 .

8. The connection portion is disposed within the region of the pixel readout circuit. The photodetector device according to claim 7 .

9. The connection portion is disposed in the center of the pixel region. The photodetector device according to claim 7 .

10. The connection portion is disposed within the pixel readout circuit area and in the center of the pixel area. The photodetector device according to claim 7 .

11. The second substrate further includes a second logic circuit including at least a TDC that generates a count value indicating a time for which the light receiving element reacts based on the detection signal output by the pixel readout circuit. The photodetector device according to claim 1 .

12. The second logic circuit is disposed outside the area under the pixel array. The optical detection device according to claim 11 .

13. The second logic circuit is disposed in the region below the pixel array. The optical detection device according to claim 11 .

14. The pixel readout circuit is disposed in the center of the pixel area. The photodetector device according to claim 1 .

15. The pixel readout circuits are arranged so that the pixel readout circuits of two adjacent rows are in contact with each other. The photodetector device according to claim 1 .

16. The pixel readout circuit is connected to the plurality of light receiving elements. The photodetector device according to claim 1 .

17. The pixel readout circuit is connected to a plurality of wirings, and a plurality of the light receiving elements are connected to each wiring. The photodetector device according to claim 1 .

18. a light source device that outputs irradiation light; a light detection device that receives reflected light of the irradiated light reflected by an object; Equipped with the photodetector is configured by stacking a first substrate having a pixel array region in which light receiving elements are two-dimensionally arranged in a matrix, and a second substrate having a pixel array lower region corresponding to the pixel array region; The region below the pixel array is configured by arranging a plurality of unit regions, each of which is made up of one or more pixels, in a row direction or a column direction, and includes one or more pixel readout circuits having a common circuit layout in the unit regions, and a first logic circuit having a circuit layout across the unit regions. electronic equipment.

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