Semiconductor device and method for controlling variable resistance element

Abstract

To improve data retention characteristics of a semiconductor device using a variable resistance element.SOLUTION: A semiconductor device includes a variable resistance element whose resistance state changes according to a direction of a voltage applied between two electrodes, and a control circuit. The control circuit applies a plurality of pulses of a first polarity to the variable resistance element in a set sequence for changing the variable resistance element to a low resistance state. M pulses from an X-th pulse to an (X+M-1)-th pulse among the plurality of pulses of the first polarity have a pulse height higher than that of the immediately preceding pulse.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device such as a memory using a resistance change element, a field programmable gate array (FPGA), and the like, and a method for controlling a resistance change element. [Background technology]

[0002] In recent years, memories and field programmable gate arrays have become known that use nonvolatile variable resistance elements whose resistance state transitions between a low resistance state and a high resistance state depending on the direction of the applied voltage and that can retain the set resistance state even when power is not supplied.

[0003] Patent Document 1, Patent Document 2, and Non-Patent Document 1 disclose programmable logic integrated circuits that use variable resistance elements formed in a wiring layer to enable changes to wiring connections after the manufacture of a semiconductor integrated circuit. Such programmable logic integrated circuits make it possible to correct circuit defects after manufacture, change specifications, reduce the area of ​​the semiconductor integrated circuit, improve the power performance ratio, and moreover, omit the operation of reading out circuit configuration information at startup.

[0004] Non-Patent Document 2 discloses a semiconductor memory circuit using a resistance change element formed in a wiring layer. A semiconductor memory circuit using a resistance change element is characterized by a short write time. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-101535 [Patent Document 2] Patent No. 6934258 [Non-patent literature]

[0006] [Non-Patent Document 1] S. Kaeriyama et al., "A Nonvolatile Programmable Solid-Electrolyte Nanometer Switch", IEEE Journal of Solid-State Circuits, Vol. 40(1), pp. 168-176, (2005). [Retrieved February 20, 2024], Internet: URL: https: / / www.researchgate.net / publication / 2982749_A_Nonvolatile_Programmable_Solid-Electrolyte_Nanometer_Switch [Non-patent document 2] M. Tada, "NanoBridge Technology for Embedded Nonvolatile Memory Application", IEEE International Memory Workshop, pp. 101-104., (2022). Summary of the Invention [Problem to be solved by the invention]

[0007] However, there are very rare cases where the resistance change element does not achieve the desired data retention characteristics. To address such retention failures, semiconductor devices are configured to take several measures to meet the desired specifications.

[0008] For example, a known configuration is one in which redundant bits and an error correction circuit are provided, and when a retention failure occurs, the error can be corrected and read. However, if the data retention characteristics of a variable resistance element are poor, the number of redundant bits required to meet specifications tends to increase, resulting in an increase in chip area. Therefore, it is desirable for variable resistance elements to have high data retention characteristics.

[0009] Another possible method is to conduct testing before shipping from the factory to identify bits that are prone to retention failure and replace them with redundant bits, or to discard the chip. However, if the data retention characteristics of the variable resistance element are low, a large number of redundant bits are required to meet the specifications, which poses a problem of increasing the chip area. Alternatively, if the data retention characteristics of the variable resistance element are low, there is a problem of increasing the number of chips that need to be discarded. Therefore, it is desirable for the variable resistance element to have high data retention characteristics.

[0010] Furthermore, when identifying bits that are prone to the above-mentioned retention failure, if the identification accuracy is low, normal bits that do not cause retention failure will also be replaced with redundant bits, resulting in a problem of a larger number of redundant bits required to meet specifications and an increased chip area. Alternatively, when identifying bits that are prone to the above-mentioned retention failure, if the identification accuracy is low, there will be a problem of an increased number of chips to be discarded. Therefore, it is desirable to reduce the false positive rate when predicting variable resistance elements with poor data retention characteristics.

[0011] To begin with, it is not clear how to identify variable resistance elements that are prone to such retention failures. One possible method is to store variable resistance elements in a high-temperature environment after writing data to them, read the data, and identify variable resistance elements that are unable to retain the written data as bits that are prone to retention failures. However, this method has the problem of being difficult to apply after shipment. Therefore, it is desirable to be able to identify variable resistance elements that are prone to retention failures on chips after shipment from the factory.

[0012] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to improve the data retention characteristics of a semiconductor device using a variable resistance element. [Means for solving the problem]

[0013] A semiconductor device according to an embodiment of the present invention comprises a variable resistance element whose resistance state changes depending on the direction of a voltage applied between two electrodes, and a control circuit, wherein the control circuit applies a plurality of pulses of a first polarity to the variable resistance element in a set sequence that sets the variable resistance element to a low resistance state, and among the plurality of pulses of the first polarity, M pulses from the Xth pulse to the X+M-1th pulse have a higher pulse height than the pulse applied immediately before.

[0014] In a control method for a variable resistance element according to an embodiment of the present invention, a computer executes a set sequence for setting a variable resistance element, whose resistance state changes depending on the direction of a voltage applied between two electrodes, to a low resistance state by applying a plurality of pulses of a first polarity to the variable resistance element, and of the plurality of pulses of the first polarity, M pulses from the Xth pulse to the X+M-1th pulse have a higher pulse height than the pulse applied immediately before. [Effects of the Invention]

[0015] According to the present invention, it is possible to improve the data retention characteristics of a semiconductor device using a resistance change element. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram illustrating the structure of a variable resistance element 100. As shown in FIG. [Figure 2] FIG. 2 is a diagram for explaining how the setting operation is performed on the variable resistance element 100. In FIG. [Figure 3] FIG. 3 is a diagram for explaining how the reset operation is performed on the resistance change element 100. In FIG. [Figure 4] FIG. 4 is a graph showing the change in the voltage-current characteristics of the variable resistance element 100. In FIG. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a semiconductor device 200-1 according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing an example of the configuration of the read circuit 45 of the semiconductor device 200-1. [Figure 7A]FIG. 7A is a diagram showing an example of the configuration of the cell array 44. As shown in FIG. [Figure 7B] FIG. 7B is a diagram for explaining the operation of the cell array 44. As shown in FIG. [Figure 7C] FIG. 7C is a diagram for explaining the operation of the cell array 44. As shown in FIG. [Figure 7D] FIG. 7D is a diagram for explaining the operation of the cell array 44. As shown in FIG. [Figure 8] FIG. 8 is a diagram showing an example of a voltage waveform between the terminals of a resistance change element to be written. [Figure 9] FIG. 9 is a diagram showing an example of a voltage waveform between the terminals of a resistance change element to be written. [Figure 10] FIG. 10 is a diagram showing an example of a voltage waveform between terminals of a resistance change element to be written in the semiconductor device of Comparative Example 1. In FIG. [Figure 11] FIG. 11 is a diagram for explaining the retention failure rates in Comparative Example 1, the semiconductor device 200-1 of the first embodiment, and a modified example of the semiconductor device 200-1 of the first embodiment. [Figure 12A] FIG. 12A is a diagram illustrating a set sequence for setting the variable resistance element to a low resistance state. [Figure 12B] FIG. 12B is a diagram illustrating a set sequence for setting the variable resistance element to a low resistance state. [Figure 13A] FIG. 13A is a schematic diagram showing the relationship between the voltage across the terminals of a resistance change element to be written and the current flowing across the terminals of the resistance change element. [Figure 13B] FIG. 13B is a schematic diagram showing the relationship between the conductance of a resistance change element to be written and the power supplied to the resistance change element. [Figure 13C] FIG. 13C is a schematic diagram showing the relationship between the voltage across the terminals of the resistance change element to be written and the current flowing across the terminals of the resistance change element. [Figure 13D] FIG. 13D is a schematic diagram showing the relationship between the conductance of a resistance change element to be written and the power supplied to the resistance change element. [Figure 14]FIG. 14 is a diagram showing an example of the configuration of a semiconductor device 200-2 according to the second embodiment. [Figure 15] FIG. 15 is a diagram showing an example of the configuration of the read circuit 45-2 of the semiconductor device 200-2. [Figure 16] FIG. 16 is a block diagram of a converter 30 and a discriminator 31 included in a semiconductor device 200-2 of the second embodiment. [Figure 17] FIG. 17 is a block diagram of a converter 30A and a discriminator 31A included in the semiconductor device of the first embodiment. [Figure 18] FIG. 18 is a diagram showing an example of a voltage waveform between the terminals of a resistance change element to be written. [Figure 19] FIG. 19 is a diagram showing an example of a voltage waveform between the terminals of a resistance change element to be written. [Figure 20] FIG. 20 is a diagram showing an example of a voltage waveform between the terminals of a resistance change element to be written. [Figure 21] FIG. 21 is a diagram showing an example of a voltage waveform between the terminals of a resistance change element to be written. [Figure 22] FIG. 22 is a block diagram of a converter 30B and a discriminator 31B included in the semiconductor device of the fifth embodiment. [Figure 23] FIG. 23 is a diagram showing an example of a voltage waveform between terminals of a resistance change element to be written in the semiconductor device of Comparative Example 2. In FIG. [Figure 24] FIG. 24 is a diagram showing estimated values ​​of false positive rates when predicting retention failure bits in the semiconductor devices of the first to fifth examples and the comparative example 2. In FIG. [Figure 25] FIG. 25 is a block diagram showing the hardware configuration of the semiconductor devices 200-1 and 200-2 for executing the set sequence. [Figure 26] FIG. 26 is a block diagram showing an example of the functional configuration of the semiconductor devices 200-1 and 200-2 for executing the set sequence. DETAILED DESCRIPTION OF THE INVENTION

[0017] Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[0018] (First embodiment) First, before describing the semiconductor device according to the first embodiment of the present invention, the structure of the resistance change element will be described.

[0019] FIG. 1 is a diagram illustrating the structure of a variable resistance element 100. As shown in FIG. 1, the variable resistance element 100 has a solid electrolyte 93 in which metal ions can freely move due to an electric field or the like, and a first electrode 91 and a second electrode 92 that face each other across the solid electrolyte 93. The first electrode 91 is an active electrode that can supply metal ions to the solid electrolyte 93 and is made of, for example, copper (Cu). The second electrode 92 is an inactive electrode that cannot supply metal ions to the solid electrolyte 93 and is made of, for example, ruthenium (Ru). The first electrode 91 is connected to a first terminal 101, and the second electrode 92 is connected to a second terminal 102.

[0020] FIG. 2 is a diagram illustrating a state in which a set operation is performed on the variable resistance element 100. In this variable resistance element 100, as shown in FIG. 2, when a positive voltage is applied to the first electrode 91 (first terminal 101) side with the second electrode 92 (second terminal 102) at ground potential, copper in the first electrode 91 ionizes, moves into the solid electrolyte 93, and deposits as metal through an electrochemical reaction. The deposited metal forms a metal bridge (also called a filament or conductive path) between the first electrode 91 and the second electrode 92. The voltage at this time is defined as a first threshold voltage or set voltage. As a result, the resistance state of the variable resistance element 100 transitions from a high resistance state (off state) to a low resistance state (on state). This transition of the resistance state from the high resistance state (off state) to the low resistance state (on state) is called a set operation.

[0021] 3 is a diagram for explaining how a reset operation is performed on the variable resistance element 100. Conversely, in this variable resistance element 100, as shown in FIG. 3, when a positive voltage is applied to the second electrode 92 (second terminal 102) side with the first electrode 91 (first terminal 101) at ground potential, the copper atoms that constituted the metal bridge are collected to the first electrode 91 side, which is the copper electrode, and the metal bridge is cut. As a result, the resistance state of the variable resistance element 100 transitions from a low resistance state (on state) to a high resistance state (off state). This transition of the resistance state from the low resistance state (on state) to a high-low resistance state (off state) is called a reset operation.

[0022] Before the electrical connection between the first electrode 91 and the second electrode 92 is completely cut off, changes in electrical characteristics occur, such as an increase in resistance between the first electrode 91 and the second electrode 92 or a change in capacitance, and the electrical connection is finally cut off by a second threshold voltage or a reset voltage. To change from this high-resistance state (off state) to a low-resistance state (on state), the second electrode 92 should be grounded again and a positive voltage should be applied to the first electrode 91 (reset operation).

[0023] Thus, the variable resistance element 100 is composed of a first electrode 91 which is an active electrode, a second electrode 92 which is an inactive electrode, and a variable resistance layer disposed between the first electrode 91 and the second electrode 92 and including a solid electrolyte 93 into which the metal elements constituting the first electrode 91 can diffuse. In the variable resistance element 100, when the potential of the first electrode 91 becomes higher than that of the second electrode 92 by a first threshold voltage, the metal elements constituting the first electrode 91 diffuse into the variable resistance layer, forming a metal bridge, thereby entering a low resistance state. On the other hand, when the potential of the second electrode 92 becomes higher than that of the first electrode 91 by a second threshold voltage, the metal bridge formed in the variable resistance layer is broken, thereby entering a high resistance state.

[0024] The change in voltage-current characteristics of the variable resistance element 100 having such bipolar characteristics is shown in the graph of FIG. 4. FIG. 4 is a graph showing the change in voltage-current characteristics of the variable resistance element 100. As shown in FIG. 4, the variable resistance element 100 can repeatedly change its resistance state simply by changing the direction of voltage application, and is nonvolatile, requiring no power to maintain the on and off states. The variable resistance element 100 has electrical characteristics such as a large difference in on and off resistance, with a resistance value of, for example, 1000 Ω in the on state and, for example, 100 MΩ in the off state. Therefore, the variable resistance element 100 can be used to realize a switching element for switching logic signals or a memory circuit for storing data.

[0025] (First embodiment) Next, a semiconductor device according to a first embodiment of the present invention will be described.

[0026] The semiconductor device of this embodiment is a storage device in which a plurality of memory cells, each of which is made up of a resistance change element and a cell transistor, are arranged at the intersections of bit line pairs and word lines.

[0027] First, the functional configuration of the semiconductor device of this embodiment will be described with reference to the block diagram shown in Fig. 5. Fig. 5 is a diagram showing an example configuration of a semiconductor device 200-1 of the first embodiment. As shown in Fig. 5, the semiconductor device 200-1 of the first embodiment includes a control circuit 41, a row decoder 42, a column decoder 43, a cell array 44, and a read circuit 45.

[0028] (Cell array 44) The cell array 44 is composed of a plurality of memory cells, and is connected to a plurality of bit line pairs BL, BLB and a plurality of word lines WL. Each of the plurality of memory cells is composed of a resistance change element and a cell transistor, and is connected to the bit line pairs BL, BLB and the word lines WL. The configuration of the memory cells will be described in detail later.

[0029] (Column decoder 43) The column decoder 43 is connected to a plurality of bit line pairs BL, BLB. The column decoder 43 selects a specified bit line pair BL, BLB in response to a column selection signal and applies a predetermined voltage to the bit line pair BL, BLB. In other words, the column decoder 43 is arranged to apply a predetermined voltage to the bit line pair BL, BLB selected by the column selection signal.

[0030] (row decoder 42) The row decoder 42 is connected to a plurality of word lines WL. The row decoder 42 selects a specified word line WL in response to a row selection signal and applies a predetermined voltage to the selected word line. That is, the row decoder 42 applies a predetermined voltage to the word line selected by the row selection signal.

[0031] (Control circuit 41) The control circuit 41 receives external control signals such as an address signal A, a write data signal D, and a command signal, and outputs read data Q. In response to the address signal, the control circuit 41 generates a row selection signal and a column selection signal, and outputs them to a row decoder 42 and a column decoder 43, respectively. In response to the external control signals, the control circuit 41 generates internal control signals for performing write operations and read operations.

[0032] (Readout circuit 45) The read circuit 45 is connected to the bit line BL via the column decoder 43 and applies a read voltage to pass a read current through the resistance change element. Since the read current changes depending on the resistance state of the resistance change element, the read circuit 45 determines the resistance state of the resistance change element by comparing the read current value with a reference current. The read circuit 45 outputs the read result to the control circuit 41.

[0033] An example of the configuration of the read circuit 45 will be described with reference to Fig. 6. Fig. 6 is a diagram showing an example of the configuration of the read circuit 45 of the semiconductor device 200-1. The read circuit 45 includes transistors M0 and M1, resistors R0 and R1, a current source CS1, and a differential amplifier AMP1.

[0034] The gate of the transistor M0 is connected to a bias voltage VB. The source of the transistor M0 is connected to a memory cell via a column decoder 43. The drain of the transistor M0 is connected to a resistor R0 and one of the input terminals of a differential amplifier AMP1. The other end of the resistor R0 is connected to a power supply VDD.

[0035] The gate of transistor M1 is connected to a bias voltage VB. The source of transistor M1 is connected to a current source CS1. The drain of transistor M1 is connected to resistor R1 and the other end of the input terminal of differential amplifier AMP1. The other end of resistor R1 is connected to power supply VDD. The other end of current source CS1 is grounded.

[0036] The read circuit 45 applies a read voltage, which is a voltage lower than the bias voltage VB by the threshold voltage of the transistor M0, to the memory cell. As a result, a read current IRD flows. Furthermore, the read circuit 45 converts the read current IRD into a voltage using a resistor R0.

[0037] The read circuit 45 uses a current source CS1 to generate a reference current IREF1, and further uses a resistor R1 to convert the reference current IREF1 into a voltage.

[0038] The read circuit 45 uses a differential amplifier AMP1 to compare the converted voltages and determine the resistance state of the resistance change element.

[0039] Next, the circuit of a memory cell 50 in one row and one column in the cell array 44 is shown in Figure 7A. Figure 7A is a diagram showing an example of the configuration of the cell array 44. As shown in Figure 7A, the cell array 44 is composed of a bit line pair BL0, BLB0 extending in the vertical direction, a word line WL0 extending in the horizontal direction, and a memory cell 50. The memory cell 50 is arranged at the intersection of the bit line pair BL0, BLB0 and the word line WL0.

[0040] The memory cell 50 is composed of a variable resistance element 100 and a cell transistor MC. A first terminal of the variable resistance element 100 is connected to a bit line BL0, and a second terminal of the variable resistance element 100 is connected to one of the source terminal or drain terminal of the cell transistor MC. The other of the source terminal or drain terminal of the cell transistor MC is connected to the other of the bit line pair, BLB0. The gate terminal of the cell transistor MC is connected to a word line WL0.

[0041] The column decoder 43 is composed of a source-side column decoder 43A, a sink-side column decoder 43B, and a read decoder 43C. The source-side column decoder 43A is connected to a write voltage VSET during a set operation and a write voltage VRST during a reset operation, both of which are used to perform a write operation on the resistance change element 100. The sink-side column decoder 43B is connected to a ground voltage VSS, which is lower than the write voltages VSET and VRST. The read decoder 43C is connected to a read circuit 45.

[0042] The source-side column decoder 43A includes two transistors, a transistor M1 and a transistor M101. The source terminal of the transistor M1 is connected to a write voltage VRST during a reset operation, the drain terminal of the transistor M1 is connected to a bit line BLB0, and the gate terminal of the transistor M1 is connected to a column selection signal C0B(RST). The source terminal of the transistor M101 is connected to a write voltage VSET during a set operation, the drain terminal of the transistor M101 is connected to a bit line BL0, and the gate terminal of the transistor M101 is connected to a column selection signal C0B(SET).

[0043] The sink-side column decoder 43B includes two transistors: M0 and M100. The drain terminal of the write transistor M0 is connected to the bit line BL0, the source terminal of the write transistor M0 is connected to the ground voltage VSS, and the gate terminal of the write transistor M0 is connected to the column select signal C0(RST). The drain terminal of the transistor M100 is connected to the bit line BLB0, the source terminal of the transistor M100 is connected to the ground voltage VSS, and the gate terminal of the transistor M100 is connected to the column select signal C0(SET).

[0044] The read decoder 43C includes one transistor M2. The drain terminal of the transistor M2 is connected to the bit line BL0, and the source terminal of the transistor M2 is connected to the read circuit 45. The gate terminal of the transistor M2 is connected to the column selection signal C0B (RD).

[0045] The row decoder 42 is composed of a transistor M4 and a transistor M5. The source terminal of the transistor M4 is connected to the word line voltage VWL, the drain terminal of the transistor M4 is connected to the word line WL0, and the gate terminal of the transistor M4 is connected to the row selection signal R0B. The source terminal of the transistor M5 is connected to the ground voltage VSS, the drain terminal of the transistor M5 is connected to the word line WL0, and the gate terminal of the transistor M5 is connected to the row selection signal R0B.

[0046] During standby, column select signals C0(SET) and C0(RST) turn transistors M0 and M100 on, grounding the bit line pair BL0 and BLB0. Column select signals C0B(SET) and C0B(RST) turn transistors M1 and M101 off. Row select signal R0B turns transistor M5 on and transistor M4 off, grounding the word line WL0.

[0047] When the variable resistance element 100 is selected during a set pulse application operation, the column select signal C0(SET) turns on the transistor M100 and grounds the bit line BLB0. The column select signal C0B(SET) turns on the transistor M101, connecting the bit line BL0 to the write voltage VSET during the set operation. The column select signals C0(RST) and C0B(RST) turn off the transistors M0 and M1. The row select signal R0B turns off the transistor M5 and turns on the transistor M4, connecting the word line WL0 to the word line voltage VWL. As a result, as shown in FIG. 7B, a write current A1 flows from the bit line BL0 to the bit line BLB0 via the variable resistance element 100 and the cell transistor MC.

[0048] When the variable resistance element 100 is selected during a reset pulse application operation, the column selection signal C0(RST) turns on transistor M0 and grounds bit line BL0. Then, the column selection signal C0B(RST) turns on transistor M1 and connects bit line BLB0 to the write voltage VRST during the reset operation. Then, the column selection signals C0(SET) and C0B(SET) turn off transistors M100 and M101. Then, the row selection signal R0B turns off transistor M5 and turns on transistor M4, connecting word line WL0 to word line voltage VWL. As a result, as shown in FIG. 7C, a write current A2 flows from bit line BLB0 to bit line BL0 via the variable resistance element 100 and cell transistor MC.

[0049] During a read operation, when the variable resistance element 100 is selected, the column select signal C0B(RD) turns on transistor M2. The column select signal C0(SET) turns on transistor M100, grounding bit line BLB0. The column select signals C0B(SET), C0(RST), and C0B(RST) turn off transistors M101, M0, and M1. The row select signal R0B turns off transistor M5 and turns on transistor M4, connecting word line WL0 to word line voltage VWL. As a result, a read voltage is applied to bit line BL0, and a read current A3 flows from bit line BL0 through the variable resistance element 100 and cell transistor MC to bit line BLB0, as shown in FIG. 7D.

[0050] A set sequence for setting the variable resistance element to a low resistance state in the semiconductor device 200-1 according to the first embodiment of the present invention will now be described. FIG. 8 is a diagram showing an example of a voltage waveform between the terminals of the variable resistance element to be written. The control circuit 41 sequentially applies nine set pulses S0, S1, S2, S3, S4, S5, S6, S7, and S8, each having a positive polarity, to the variable resistance element to be written. The positive polarity may be interpreted as the first polarity.

[0051] Of the nine set pulses, seven set pulses S2, S3, S4, S5, S6, S7, and S8 have a characteristic that their pulse heights are higher than the pulse applied immediately before. Specifically, of the multiple pulses of the first polarity, M pulses, from the Xth pulse (X is a natural number greater than or equal to 1) to the X+Mth pulse (M is a natural number greater than or equal to 1) - 1, have a pulse height higher than the pulse applied immediately before. X may be interpreted as a natural number greater than or equal to 1. M may be interpreted as a natural number greater than or equal to 1. More specifically, the height of set pulse S2 is higher than the height of set pulse S1. Similarly, the height of set pulse S8 is higher than the height of set pulse S7. This set sequence ultimately transitions the resistance change element to a low-resistance state. The levels of the nine set pulses may be controlled, for example, by the control circuit 41 changing the voltage applied to the word line voltage VWL. Alternatively, the levels of the nine set pulses may be controlled, for example, by the control circuit 41 changing the voltage applied to the write voltage VSET during the set operation. As will be described later, in more detail, the voltage across the terminals of the variable resistance element changes in accordance with the load curve when the resistance state of the variable resistance element changes. From the viewpoint of control, for simplicity, the voltage waveform across the terminals of the variable resistance element in FIG. 8 may be interpreted as a case where the resistance value of the variable resistance element is fixed.

[0052] Next, a set sequence for setting the variable resistance element to a low-resistance state in a modified example of the semiconductor device 200-1 according to the first embodiment of the present invention will be described. FIG. 9 is a diagram showing an example of a voltage waveform between the terminals of the variable resistance element to be written. The control circuit 41 applies a set pulse S0 having a positive polarity followed by a reset pulse RST0 having a negative polarity to the variable resistance element to be written. Specifically, the control circuit 41 applies the reset pulse RST0 to the variable resistance element to be written between the set pulse S0 and the set pulse S1. The negative polarity may be interpreted as a second polarity. The level of the reset pulse may be controlled, for example, by changing the voltage applied by the control circuit 41 to the word line voltage VWL. Alternatively, the level of the reset pulse may be controlled, for example, by changing the voltage applied by the control circuit 41 to the write voltage VRST during the reset operation.

[0053] Furthermore, the control circuit 41 sequentially applies eight set pulses S1, S2, S3, S4, S5, S6, S7, and S8, all of which have positive polarity, to the resistance change element to be written. Of these pulses, seven set pulses S2, S3, S4, S5, S6, S7, and S8 are characterized by having higher pulse heights than the pulse applied immediately before. This set sequence ultimately transitions the resistance change element to a low resistance state.

[0054] The modified example of the semiconductor device 200-1 of the first embodiment differs from the first embodiment only in the set sequence for setting the variable resistance element to the low resistance state, so a description of parts that overlap with the first embodiment will be omitted.

[0055] (Comparative Example 1) Next, a set sequence for setting the variable resistance element to a low resistance state in the semiconductor device of Comparative Example 1 will be described. FIG. 10 is a diagram showing an example of a voltage waveform between the terminals of the variable resistance element to be written in the semiconductor device of Comparative Example 1. The control circuit applies a set pulse S8 having a positive polarity to the variable resistance element to be written. The semiconductor device of Comparative Example 1 differs from this embodiment only in the set sequence for setting the variable resistance element to a low resistance state. Therefore, explanations of parts that overlap with the first embodiment will be omitted.

[0056] (effect) FIG. 11 is a diagram illustrating the retention failure rate in Comparative Example 1, the semiconductor device 200-1 of the first embodiment, and a modified example of the semiconductor device 200-1 of the first embodiment. Here, the above-described set sequence was performed on a variable resistance element whose active electrode was made of copper. Next, the resistance state was read at room temperature. Subsequently, the variable resistance element was stored at a high temperature of 260°C for one hour, and the resistance state was again read at room temperature. Bits in the variable resistance element that were in a low resistance state before high-temperature storage and changed to a high resistance state after high-temperature storage were defined as retention failure bits. The proportion of retention failure bits to the bits to be measured was defined as the retention failure rate. Furthermore, the vertical axis of the graph shown in FIG. 11 was normalized by the retention failure rate of Comparative Example 1.

[0057] The set pulses S0, S1, S2, S3, S4, S5, S6, S7, and S8 of the semiconductor device 200-1 of the first embodiment and the modified example of the semiconductor device 200-1 of the first embodiment have the same pulse height and pulse width.

[0058] Furthermore, the highest height of the set pulse is the same in the semiconductor device 200-1 of the first embodiment, the modified example of the semiconductor device 200-1 of the first embodiment, and the semiconductor device of Comparative Example 1. That is, the height of the set pulse S8 in the semiconductor device of the first embodiment, the height of the set pulse S8 in the modified example of the semiconductor device 200-1 of the first embodiment, and the pulse height of the set pulse S8 in the semiconductor device of Comparative Example 1 are the same.

[0059] Furthermore, if the pulse width of the set pulse S8 of the semiconductor device of Comparative Example 1 is T, the pulse widths of the set pulses S0, S1, S2, S3, S4, S5, S6, S7, and S8 of the semiconductor device of the first embodiment are set to T / 8. Similarly, the pulse widths of the set pulses S0, S1, S2, S3, S4, S5, S6, S7, and S8 of the modified example of the semiconductor device 200-1 of the first embodiment are also set to T / 8.

[0060] 11, it can be seen that the first embodiment and the modified example of the first embodiment have a smaller retention failure rate than Comparative Example 1. Therefore, it can be seen that the semiconductor device 200-1 of this embodiment and the modified example of the semiconductor device 200-1 of this embodiment can improve the data retention characteristics of the resistance change element.

[0061] Furthermore, it can be seen that the retention failure rate in the modified example of the semiconductor device 200-1 of the first embodiment is equivalent to that of the first embodiment. This indicates that the application of a weak reset pulse in the modified example of the first embodiment does not significantly affect the retention characteristics. The fact that a weak reset pulse does not affect the retention characteristics is advantageous in a configuration for identifying defective elements that are prone to data retention failure, as will be described later.

[0062] One possible reason why the semiconductor device 200-1 of this embodiment can improve the data retention characteristics is that the maximum value of the power applied to the resistance change element can be reduced.

[0063] It is thought that by reducing the maximum value of power, which is the product of the current flowing between the terminals of the resistance change element and the voltage between the terminals of the resistance change element, breakdown is suppressed, bridges made up of defects are less likely to form, and retention characteristics are improved.

[0064] Furthermore, if a reset pulse with a high pulse height is applied to intentionally cause dielectric breakdown of the solid electrolyte, the variable resistance element will enter a low-resistance state. It is presumed that the bridges in such variable resistance elements are composed of defects rather than copper. In preliminary experiments, the variable resistance elements in which dielectric breakdown was intentionally caused exhibited poor retention characteristics in the low-resistance state. Specifically, the retention failure rate of the variable resistance elements in which dielectric breakdown was intentionally caused was approximately four times that of Comparative Example 1. Therefore, it is believed that suppressing the formation of bridges composed of defects is important for improving retention characteristics.

[0065] 12A and 12B will be used to describe the set sequence for setting the variable resistance element to the low resistance state in the semiconductor device of Comparative Example 1. Figures 12A and 12B are diagrams for explaining the set sequence for setting the variable resistance element to the low resistance state.

[0066] The following describes the case where one set pulse S8 is applied to a resistance change element to be written. FIG. 12A is a schematic diagram showing the relationship between the voltage between the terminals of the resistance change element to be written and the current flowing between the terminals of the resistance change element. FIG. 12B is a schematic diagram showing the relationship between the conductance of the resistance change element to be written and the power applied to the resistance change element. Points A0, B, C, D, and A in FIG. 12A correspond to A0, B, C, D, and A in FIG. 12B, respectively. The vertical axis of FIG. 12A represents current, and the horizontal axis represents voltage. The vertical axis of FIG. 12B represents power, which is the product of the current flowing between the terminals of the resistance change element and the voltage between the terminals of the resistance change element, and the horizontal axis represents conductance.

[0067] First, the state before the set pulse S8 is applied to the variable resistance element in the high resistance state is point A0. When the set pulse S8 rises, it transitions from point A0 to point B. Then, when the resistance value of the variable resistance element transitions from the high resistance state to the low resistance state, it transitions from point B to point C to point D. Finally, when the set pulse S8 falls, it transitions from point D to point A. The set pulse S8 maximizes the power at point C.

[0068] The set sequence for setting the variable resistance element to a low resistance state in the semiconductor device 200-1 of this embodiment will be described with reference to FIGS. 13A to 13D. For simplicity, the control circuit 41 will be described as applying two set pulses S7 and S8 sequentially to the variable resistance element to be written. Of the two set pulses, the set pulse S8 has a feature that it has a higher pulse height than the pulse S7 applied immediately before. Note that the height of the set pulse S8 in FIGS. 12A and 12B is the same as that of the set pulse S8 in FIGS. 13A to 13D.

[0069] The case where set pulse S7 is applied to a resistance change element to be written will be described. Fig. 13A is a schematic diagram showing the relationship between the voltage between the terminals of the resistance change element to be written and the current flowing between the terminals of the resistance change element. Fig. 13B is a schematic diagram showing the relationship between the conductance of the resistance change element to be written and the power supplied to the resistance change element. The vertical axis of Fig. 13A represents current, and the horizontal axis represents voltage. The vertical axis of Fig. 13B represents power, which is the product of the current flowing between the terminals of the resistance change element and the voltage between the terminals of the resistance change element, and the horizontal axis represents conductance.

[0070] Points A0, B0, C0, D0, and A1 in FIG. 13A correspond to A0, B0, C0, D0, and A1 in FIG. 13B, respectively. First, the state before the set pulse S7 is applied to the variable resistance element in the high resistance state is point A0. When the set pulse S7 rises, the state transitions from point A0 to point B0. Then, when the resistance value of the variable resistance element transitions from the high resistance state to the low resistance state, the state transitions from point B0 to point C0 and then to point D0. Finally, when the set pulse S7 falls, the state transitions from point D0 to point A1. The set pulse S7 maximizes the power at point C0.

[0071] Next, a case where the set pulse S8 is applied to the resistance change element to be written will be described. Fig. 13C is a schematic diagram showing the relationship between the voltage between the terminals of the resistance change element to be written and the current flowing between the terminals of the resistance change element. Fig. 13D is a schematic diagram showing the relationship between the conductance of the resistance change element to be written and the power supplied to the resistance change element. The vertical axis of Fig. 13C represents current, and the horizontal axis represents voltage. The vertical axis of Fig. 13D represents power, which is the product of the current flowing between the terminals of the resistance change element and the voltage between the terminals of the resistance change element, and the horizontal axis represents conductance.

[0072] Points A1, B1, C, D, and A in FIG. 13C correspond to A1, B1, C, D, and A in FIG. 13D, respectively. First, the state before the set pulse S8 is applied to the variable resistance element is point A1. When the set pulse S8 rises, the element transitions from point A1 to point B1. Then, when the resistance value of the variable resistance element transitions from a low-resistance state to an even lower-resistance state, the element transitions from point B1 to point D without passing through point C. Finally, when the set pulse S8 falls, the element transitions from point D to point A. The set pulse S8 maximizes the power at point B1.

[0073] In the semiconductor device of Comparative Example 1, the maximum power applied to the variable resistance element is the power at point C, which is the maximum value on the curve showing the relationship between power and conductance in FIG. 12B. In the semiconductor device 200-1 of this embodiment, the maximum power applied to the variable resistance element is the power at point B1, which is lower than the maximum point C on the curve showing the relationship between power and conductance in FIG. 13D. In other words, the semiconductor device 200-1 of this embodiment can follow a trajectory that avoids the state where the power becomes maximum when transitioning to a desired low resistance state.

[0074] Specifically, for the semiconductor device 200-1 of the present embodiment, it is assumed that when the Nth (N is a natural number greater than or equal to 1) set pulse S(N) is applied, the conductance of the resistive change element becomes G(N), and when the (N + 1)th set pulse S(N + 1) is applied, the conductance of the resistive change element becomes G(N + 1). When the conductance is in the range from 0 to G(N + 1), the conductance at which the power becomes maximum due to the (N + 1)th set pulse S(N + 1) is defined as GMAX(N + 1). By configuring such that GMAX(N + 1) < G(N), the maximum value of the power applied to the resistive change element can be lowered.

[0075] As described above, according to the semiconductor device 200-1 of the present embodiment, by lowering the maximum value of the power applied to the resistive change element, the breakdown (dielectric breakdown) of the solid electrolyte of the resistive change element is suppressed, and it becomes difficult to form a crosslink composed of defects in the resistive change element. Therefore, it becomes possible to improve the data retention characteristics of the semiconductor device 200-1 using the resistive change element.

[0076] (Second Embodiment) Next, a semiconductor device according to the second embodiment of the present invention will be described. FIG. 14 is a diagram showing a configuration example of the semiconductor device 200-2 of the second embodiment. As shown in FIG. 14, the semiconductor device 200-2 of the present embodiment includes a control circuit 41-2, a row decoder 42, a column decoder 43, a cell array 44, and a readout circuit 45-2. The control circuit 41-2 is different from the semiconductor device 200-1 of the first embodiment in that it includes a converter 30 and a discriminator 31. Descriptions of portions overlapping with the first embodiment will be omitted.

[0077] The control circuit 41-2 of this embodiment may apply a set pulse similar to that of the first embodiment in a set sequence that sets the variable resistance element to a low resistance state. The control circuit 41-2 may also apply a set pulse and a reset pulse similar to those in the modification of the first embodiment in a set sequence that sets the variable resistance element to a low resistance state. Furthermore, the control circuit 41-2 applies a read pulse after at least one of these set pulses or reset pulses. Specific examples of the read pulse will be described later (see FIG. 18, etc.).

[0078] The read circuit 45-2 of this embodiment has the same configuration as the read circuit 45 of the first embodiment, and may be configured to output the read result as digital data with a resolution of 1 bit by comparing the read current value, which is analog data, with a reference current.

[0079] Furthermore, the readout circuit 45-2 of this embodiment can be configured to appropriately use an AD converter that converts analog data into digital data. As an example, the readout current value, which is analog data, may be compared with multiple reference currents, and the readout result may be output as digital data with a resolution of multiple bits.

[0080] An example of the read circuit 45-2 is shown in Fig. 15. Fig. 15 is a diagram showing an example of the configuration of the read circuit 45-2 of the semiconductor device 200-2. The read circuit 45-2 includes transistors M0, M1, and M2, resistors R0, R1, and R2, current sources CS1 and CS2, and differential amplifiers AMP1 and AMP2.

[0081] The gate of the transistor M0 is connected to a bias voltage VB. The source of the transistor M0 is connected to the memory cell via the column decoder 43. The drain of the transistor M0 is connected to a resistor R0 and one of the input terminals of the differential amplifiers AMP1 and AMP2. The other end of the resistor R0 is connected to the power supply VDD.

[0082] The gate of transistor M1 is connected to a bias voltage VB. The source of transistor M1 is connected to a current source CS1. The drain of transistor M1 is connected to resistor R1 and the other end of the input terminal of differential amplifier AMP1. The other end of resistor R1 is connected to power supply VDD. The other end of current source CS1 is grounded.

[0083] The gate of transistor M2 is connected to a bias voltage VB. The source of transistor M2 is connected to a current source CS2. The drain of transistor M2 is connected to resistor R2 and the other end of the input terminal of differential amplifier AMP2. The other end of resistor R2 is connected to power supply VDD. The other end of current source CS2 is grounded.

[0084] The read circuit 45-2 applies a read voltage, which is lower than the bias voltage VB by the threshold voltage of the transistor M0, to the memory cell. As a result, a read current IRD flows. Furthermore, the read circuit 45-2 converts the read current IRD into a voltage using a resistor R0.

[0085] The read circuit 45-2 uses a current source CS1 to supply a reference current IREF1, and further uses a resistor R1 to convert the reference current IREF1 into a voltage.

[0086] The read circuit 45-2 uses a current source CS2 to supply a reference current IREF2, and further uses a resistor R2 to convert the reference current IREF2 into a voltage.

[0087] The read circuit 45-2 uses a differential amplifier AMP1 to compare the converted voltages and determine the resistance state of the variable resistance element. The read circuit 45-2 also uses a differential amplifier AMP2 to compare the converted voltages and determine the resistance state of the variable resistance element. By comparing with multiple reference currents in this way, the resolution of the reference current can be improved.

[0088] Next, the converter and the discriminator of the second embodiment will be described with reference to Fig. 16. Fig. 16 is a block diagram of the converter 30 and the discriminator 31 included in the semiconductor device 200-2 of the second embodiment.

[0089] The converter 30 receives the readout result and converter parameters as input, converts the data based on the readout result and the converter parameters, and outputs the converted data to the discriminator 31. The converter 30 may be composed of a converter that calculates the Mahalanobis distance and a converter that normalizes the data.

[0090] The classifier 31 receives the converted data and the classifier parameters as input, and classifies whether the variable resistance element is a retention failure bit or not based on the converted data and the classifier parameters. The classifier 31 may be configured by a classifier using a distance for determining outliers, a support vector machine, a decision tree, or a neural network.

[0091] Incidentally, the parameters for the transformer or the parameters for the discriminator may be determined as follows, for example.

[0092] First, the above-described set sequence is performed on a previously manufactured variable resistance element. Next, the resistance state is read at room temperature. Subsequently, the variable resistance element is stored at a high temperature, and the resistance state is again read at room temperature. Bits that have changed from a low resistance state to a high resistance state due to high-temperature storage are considered retention failure bits.

[0093] Next, a dataset consisting of a matrix is ​​created. Each row consists of information for each bit. Specifically, each row consists of the readout results for each bit and correct data indicating whether the bit is a retention failure or not. This dataset is used as training data for machine learning, and parameters for the transformer and the classifier are determined.

[0094] Alternatively, the data set may be randomly split into training data and test data, with the same number of retained bits in each half. Furthermore, to shorten the learning time, the training data may be subsampled except for the retained bits.

[0095] When determining the parameters for the converter or the classifier, the converter 30 and the classifier 31 may be configured by software that simulates a dedicated circuit on a semiconductor chip. The parameters for the converter or the classifier are determined in a sequence consisting of a learning phase and a test phase.

[0096] In the learning phase, the parameters for the transformer and the classifier are learned using training data.

[0097] In the test phase, the trained parameters for the transformer are used to configure the transformer 30. The trained parameters for the discriminator are also used to configure the discriminator 31.

[0098] Then, using the converter 30 and the discriminator 31, a score that is predicted to result in a retention failure bit is calculated for each bit of the test data, and it is confirmed whether the desired discrimination performance is achieved.

[0099] The parameters for the converter or the parameters for the discriminator may be configured to be supplied from an external interface of the semiconductor device 200-2 or from a storage means within the semiconductor device 200-2.

[0100] Furthermore, the converter parameters and the classifier parameters may be configured to be written to a storage means within the semiconductor device 200-2 from an external interface of the semiconductor device 200-2. This configuration makes it possible to deal with cases where the converter parameters or the classifier parameters need to be corrected due to variations during manufacturing, etc.

[0101] In the semiconductor device 200-2 of this embodiment, the set sequence for setting the variable resistance element to a low resistance state differs from that of the first embodiment in that a read pulse is added. Typically, the read pulse can be set so as not to affect the resistance state, and the data retention characteristics are equivalent to those of the first embodiment. Therefore, according to the semiconductor device 200-2 of this embodiment, it is possible to improve the data retention characteristics of the semiconductor device 200-2 using the variable resistance element.

[0102] Furthermore, according to the semiconductor device 200-2 of this embodiment, it is possible to reduce the false positive rate when predicting a variable resistance element with poor data retention characteristics from the readout result.

[0103] Furthermore, according to the semiconductor device 200-2 of this embodiment, the step of storing the variable resistance elements in a high-temperature environment to identify variable resistance elements prone to retention failure is not required, and the elements can be electrically identified.

[0104] Furthermore, in the semiconductor device 200-2 of this embodiment, the control circuit 41-2 includes a converter 30 and a discriminator 31 for identifying variable resistance elements that are prone to retention failure. Therefore, after shipping from the factory, it is possible to identify variable resistance elements on the chip that are prone to retention failure.

[0105] As described above, according to the semiconductor device 200-2 of this embodiment, it is possible to improve the data retention characteristics of the semiconductor device 200-2 using the resistance change element.

[0106] Specific examples (first to fifth examples) of the second embodiment will be described below.

[0107] (First Example) First, a semiconductor device according to a first embodiment of the present invention will be described. In the semiconductor device according to the first embodiment, the converter and the discriminator are described in detail, unlike in the second embodiment. Also, in the semiconductor device according to the first embodiment, the set sequence for setting the variable resistance element to a low resistance state is described in detail, unlike in the second embodiment. Therefore, the description of the parts of the first embodiment that overlap with the first and second embodiments will be omitted.

[0108] Next, the converter and the classifier of the first embodiment will be described with reference to FIG. 17. FIG. 17 is a block diagram of a converter 30A and a classifier 31A included in the semiconductor device of the first embodiment. The converter 30A receives the read results as variables, and receives the sample mean vector of the variables and the inverse matrix of the sample covariance matrix of the variables as converter parameters. The converter 30A calculates the Mahalanobis distance based on the read results and the converter parameters, and outputs the Mahalanobis distance as conversion data.

[0109] The discriminator 31A receives a threshold as a discriminator parameter, and when the Mahalanobis distance is equal to or greater than the threshold, discriminates whether the resistance change element is a defective element that is likely to cause a data retention failure.

[0110] Next, a set sequence for setting the variable resistance element to a low resistance state in the semiconductor device of the first embodiment will be described. Fig. 18 is a diagram showing an example of a voltage waveform between the terminals of the variable resistance element to be written. The control circuit sequentially applies nine set pulses S0, S1, S2, S3, S4, S5, S6, S7, and S8, each having positive polarity, to the variable resistance element to be written. Of the nine set pulses, seven set pulses S2, S3, S4, S5, S6, S7, and S8 are characterized by having a higher pulse height than the pulse applied immediately before.

[0111] Furthermore, the control circuit applies a read pulse RD9 to the resistance change element to be written. Specifically, for example, of the nine set pulses, the read pulse RD9 is applied after the application of set pulse 8. By this set sequence, the resistance change element finally transitions to a low resistance state.

[0112] (Second Example) Next, a semiconductor device according to a second embodiment of the present invention will be described. The semiconductor device according to the second embodiment has the same converter and discriminator as the first embodiment. The semiconductor device according to the second embodiment differs from the first embodiment only in the set sequence for setting the variable resistance element to a low resistance state. Therefore, explanations of parts that overlap with the first embodiment will be omitted.

[0113] The set sequence for setting the variable resistance element to a low resistance state in the semiconductor device of the second embodiment will now be described. Fig. 19 is a diagram showing an example of a voltage waveform between the terminals of the variable resistance element to be written. The control circuit sequentially applies nine set pulses S0, S1, S2, S3, S4, S5, S6, S7, and S8, each having positive polarity, to the variable resistance element to be written. Of the nine set pulses, seven set pulses S2, S3, S4, S5, S6, S7, and S8 are characterized by having a higher pulse height than the pulse applied immediately before.

[0114] Furthermore, the control circuit applies eight read pulses RD2, RD3, RD4, RD5, RD6, RD7, RD8, and RD9 to the resistance change element to be written. Specifically, the control circuit alternately applies nine set pulses and eight read pulses. More specifically, the control circuit applies the read pulse RD2 after completing the application of the set pulse S1, and applies the set pulse S2 after completing the application of the read pulse RD2. In this way, the control circuit may alternately apply different types of pulses. This set sequence ultimately transitions the resistance change element to a low resistance state.

[0115] (Third Example) Next, a semiconductor device according to a third embodiment of the present invention will be described. The semiconductor device according to the third embodiment has the same converter and discriminator as the first embodiment. The semiconductor device according to the third embodiment differs from the first embodiment only in the set sequence for setting the variable resistance element to a low resistance state. Therefore, explanations of parts that overlap with the first embodiment will be omitted.

[0116] The set sequence for setting the variable resistance element to a low resistance state in the semiconductor device of the third embodiment will now be described. Fig. 20 is a diagram showing an example of a voltage waveform between the terminals of the variable resistance element to be written. The control circuit applies a set pulse S0 having a positive polarity followed by a reset pulse RST0 having a negative polarity to the variable resistance element to be written.

[0117] Furthermore, the control circuit sequentially applies eight set pulses S1, S2, S3, S4, S5, S6, S7, and S8 having positive polarity to the resistance change element to be written. Of these pulses, seven set pulses S2, S3, S4, S5, S6, S7, and S8 are characterized by having a higher pulse height than the pulse applied immediately before.

[0118] Furthermore, the control circuit applies a read pulse RD1 to the resistance change element to be written. Specifically, the control circuit applies the read pulse RD after completing the application of the reset pulse RST0, and applies the set pulse S1 after completing the application of the read pulse RD1. This set sequence ultimately transitions the resistance change element to a low resistance state.

[0119] (Fourth Example) Next, a semiconductor device according to a fourth embodiment of the present invention will be described. The semiconductor device according to the fourth embodiment has the same converter and discriminator as the first embodiment. The semiconductor device according to the fourth embodiment differs from the first embodiment only in the set sequence for setting the variable resistance element to a low resistance state. Therefore, explanations of parts that overlap with the first embodiment will be omitted.

[0120] The set sequence for setting the variable resistance element to a low resistance state in the semiconductor device of the fourth embodiment will now be described. Fig. 21 is a diagram showing an example of a voltage waveform between the terminals of the variable resistance element to be written. The control circuit applies a set pulse S0 having a positive polarity followed by a reset pulse RST0 having a negative polarity to the variable resistance element to be written.

[0121] Furthermore, the control circuit sequentially applies eight set pulses S1, S2, S3, S4, S5, S6, S7, and S8 having positive polarity to the resistance change element to be written. Of these pulses, seven set pulses S2, S3, S4, S5, S6, S7, and S8 are characterized by having a higher pulse height than the pulse applied immediately before.

[0122] Furthermore, the control circuit applies read pulses RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, and RD9 to the resistance change element to be written. Specifically, the control circuit applies the read pulse RD0 after completing the application of the set pulse S0, applies the reset pulse RST0 after completing the application of the read pulse RD0, and applies the read pulse RD1 after completing the application of the reset pulse RST0. The control circuit also applies the set pulse S1 after completing the application of the read pulse RD1, and applies the read pulse RD2 after completing the application of the set pulse S1. This set sequence ultimately transitions the resistance change element to a low resistance state.

[0123] (Fifth Example) Next, a semiconductor device according to a fifth embodiment of the present invention will be described. The semiconductor device according to the fifth embodiment differs from the fourth embodiment only in the converter and the discriminator. Furthermore, the set sequence for setting the variable resistance element to a low resistance state in the semiconductor device according to the fifth embodiment is the same as that in the fourth embodiment. Therefore, explanations of parts that overlap with the fourth embodiment will be omitted.

[0124] Next, the converter and the discriminator of the fifth embodiment will be described with reference to FIG. 22. FIG. 22 is a block diagram of a converter 30B and a discriminator 31B provided in the semiconductor device of the fifth embodiment. Converter 30B uses the read results as variables, and inputs the sample mean vector of the variables and the sample variance vector of the variables as converter parameters. Converter 30B normalizes the read results based on the read results and the converter parameters, and outputs normalized data, which is the normalized data.

[0125] The classifier 31B is configured from a support vector machine, and receives model parameters of the support vector machine and normalized data as parameters for the classifier. Based on the model parameters of the support vector machine and the normalized data, the classifier 31B can identify whether or not the variable resistance element is a defective element that is prone to data retention failure.

[0126] (Comparative Example 2) Next, a semiconductor device according to Comparative Example 2 of the present invention will be described. The semiconductor device according to Comparative Example 2 has the same converter and discriminator as those of the first embodiment. The semiconductor device according to Comparative Example 2 differs from the first embodiment only in the set sequence for setting the variable resistance element to a low resistance state. Therefore, explanations of parts that overlap with those of the first embodiment will be omitted.

[0127] A set sequence for setting the variable resistance element to a low resistance state in the semiconductor device of Comparative Example 2 will be described. FIG. 23 is a diagram showing an example of a voltage waveform between the terminals of the variable resistance element to be written in the semiconductor device of Comparative Example 2. The control circuit applies a set pulse S8 having positive polarity to the variable resistance element to be written. Furthermore, the control circuit applies a read pulse RD9 to the variable resistance element to be written. By this set sequence, the variable resistance element finally transitions to a low resistance state.

[0128] (effect) FIG. 24 is a diagram showing estimated values ​​of false positive rates when predicting retention failure bits in the semiconductor devices of the first to fifth examples and the comparative example 2. In FIG.

[0129] The false positive rate in Figure 24 was calculated using the following procedure. First, the above-mentioned set sequence was performed on a variable resistance element whose active electrode was made of copper. Next, the resistance state was read out at room temperature. Subsequently, the variable resistance element was stored at a high temperature of 260°C for one hour, and the resistance state was again read out at room temperature. Bits in which the variable resistance element was in a low resistance state before high-temperature storage and changed to a high resistance state after high-temperature storage were determined to be retention failure bits.

[0130] Next, we created a dataset consisting of a matrix. Each row consists of information for each bit. Specifically, each row consists of the readout results for each bit and correct data indicating whether the bit is a retention failure or not. We used this dataset as training data for machine learning to determine the parameters for the converter and the classifier.

[0131] The data set was randomly split into half, training data and test data. Furthermore, to shorten the learning time, the training data was subsampled except for the retention failure bits. Since the purpose was to compare the classification methods, the retention failure bits were subsampled so that the same number was included in each example.

[0132] In this estimation, the transformer and classifier were configured in software rather than as dedicated circuits on a semiconductor chip. This estimation was performed using a sequence consisting of a training phase and a test phase.

[0133] In the learning phase, the parameters for the transformer and the classifier were learned using the training data.

[0134] In the test phase, a transformer was constructed using the trained transformer parameters, and a classifier was constructed using the trained classifier parameters.

[0135] Then, using these transformers and classifiers, we calculated a score for each bit of the test data that predicted it would become a retention failure bit.

[0136] The false positive rate in Fig. 24 is the minimum false positive rate at which the true positive rate becomes 100% when the score threshold level is varied. In other words, it is the minimum false positive rate required to identify all retention failure bits. Furthermore, the vertical axis of the graph shown in Fig. 24 is normalized by the false positive rate of Comparative Example 2. In other words, the lower the false positive rate, the higher the ability to identify retention failure bits.

[0137] The effects of each embodiment will be described with reference to FIG.

[0138] The semiconductor device of the first embodiment can reduce the number of reads and shorten the set sequence time. The semiconductor device of the first embodiment and the semiconductor device of Comparative Example 2 use a method for identifying retention-failed bits based on only the result of one read data after the final set pulse.

[0139] The semiconductor device of the second embodiment has a higher read count and a longer set sequence time than the comparative example 2, but has a higher ability to identify retention-failure bits.

[0140] The semiconductor device of the third embodiment can perform fewer read operations than the comparative example 2, shortening the set sequence time, and has a higher ability to identify retention-failure bits than the comparative example 2.

[0141] The semiconductor device of the fourth embodiment has a higher read count than the comparative example 2, but has a higher ability to identify retention-defective bits.

[0142] The semiconductor device of the fifth embodiment has a higher number of reads than the comparative example 2, but has the highest ability to identify retention-failure bits.

[0143] One possible reason why the semiconductor device of this embodiment can improve its ability to identify retention failure bits is that it can identify bridges formed by defects.

[0144] The response of the defect-based bridge to a set pulse is expected to be different from that of the copper-based bridge, as well as the response to a reset pulse.

[0145] For example, Patent Document 2 discloses that a reset pulse causes a variable resistance element to transition to a lower resistance state as a failure mode during reset. It is believed that such variable resistance elements have a locally broken solid electrolyte, resulting in low-resistance areas. It is believed that such low-resistance areas are composed of defects.

[0146] It is presumed that, depending on the state of the bridges formed by defects, a normal reset pulse for placing the variable resistance element in a high-resistance state may cause the variable resistance element to enter a high-resistance state. Once the high-resistance state is reached, it is difficult to distinguish it from the high-resistance state in which the copper bridges are broken. Therefore, the reset pulses in the semiconductor devices of Examples 3 to 5 are set to have a shorter pulse width than normal reset pulses for placing the variable resistance element in a high-resistance state, thereby providing a wider distribution of resistance values ​​between the high-resistance state and the low-resistance state, thereby improving the ability to distinguish between the high-resistance state and the low-resistance state. Alternatively, the reset pulses in the semiconductor devices of Examples 3 to 5 are set to have a shorter pulse height than normal reset pulses for placing the variable resistance element in a high-resistance state, thereby providing a wider distribution of resistance values ​​between the high-resistance state and the low-resistance state, thereby improving the ability to distinguish between the high-resistance state and the low-resistance state.

[0147] As described above, according to the semiconductor device of this embodiment and the present example, it is possible to improve the data retention characteristics of a semiconductor device using a variable resistance element. Furthermore, it is possible to reduce the false positive rate when predicting variable resistance elements with poor data retention characteristics. Furthermore, it is possible to identify variable resistance elements that are prone to retention problems on a chip after shipping from the factory.

[0148] Although the semiconductor device according to one or more aspects of the present disclosure has been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the spirit of the present disclosure, various modifications conceivable by a person skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments may also be included within the scope of one or more aspects of the present disclosure.

[0149] Although the present disclosure has been described using a set sequence that places a variable resistance element in a low resistance state, it may also be applied to a reset sequence that places a variable resistance element in a high resistance state.

[0150] Furthermore, although the present disclosure describes a converter and a discriminator being disposed on a semiconductor device, the converter and discriminator may be disposed on a test device external to the semiconductor device. In this case, rather than identifying variable resistance elements that are prone to retention failure on a chip after shipment from the factory, variable resistance elements that are prone to retention failure on a chip are identified by test equipment in the factory before shipment from the factory. By using such a configuration, it is possible to reduce the circuit area of ​​the converter and discriminator and reduce chip costs.

[0151] 25 is a block diagram showing the hardware configuration of the semiconductor devices 200-1 and 200-2 for executing the set sequence. The semiconductor devices 200-1 and 200-2 may be considered as an example of a computer.

[0152] The semiconductor devices 200-1 and 200-2 may include a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a storage 14, and an external I / F (Interface) 17. Each component is connected to each other via a bus 20 so as to be able to communicate with each other.

[0153] The CPU 11 is a central processing unit that executes various programs and controls each part.

[0154] The ROM 12 stores various programs and various data. The RAM 13 serves as a working area for temporarily storing programs or data.

[0155] The storage 14 is configured by a storage device such as a hard disk drive (HDD), a solid state drive (SSD), or a flash memory, and stores various programs and various data.

[0156] The recording medium 60 may be a CD-ROM (Compact Disk Read Only Memory), a DVD-ROM (Digital Versatile Disk Read Only Memory), a USB (Universal Serial Bus) memory, an SD memory card, etc. The recording medium 60 may store the set sequence program 60A that sets the variable resistance element to the low resistance state, as described above.

[0157] The CPU 11 reads the set sequence program 60A from the recording medium 60 via the external I / F 17 and executes the set sequence program 60A using the RAM 13 as a work area. Note that the set sequence program 60A is not limited to being stored in the recording medium 60, and may be stored in advance in the storage 14 of the semiconductor devices 200-1 and 200-2, or may be downloadable to the semiconductor devices 200-1 and 200-2 via a network.

[0158] 26 is a block diagram showing an example of the functional configuration of semiconductor devices 200-1 and 200-2 for executing a set sequence. The CPU 11 of the semiconductor devices 200-1 and 200-2 may include, as functional components, a pulse application unit 11A and an information input / output unit 11B. The pulse application unit 11A is realized by the CPU 11 reading and executing a set sequence program 60A.

[0159] The pulse application unit 11A may apply a plurality of pulses of a first polarity to the resistance change element in a set sequence that sets the resistance change element to a low resistance state. The pulse application unit 11A may apply one or more pulses of a second polarity opposite to the first polarity to the resistance change element. The information input / output unit 11B may input the set sequence program 60A and output commands to apply these pulses.

[0160] In each of the above embodiments, the hardware structure of the processing unit that executes the processing of the pulse application unit 11A can be any of the following various processors: As described above, the various processors include a CPU, which is a general-purpose processor that executes software (programs) and functions as various processing units, as well as a programmable logic device (PLD), which is a processor whose circuit configuration can be changed after manufacture, such as an FPGA (Field Programmable Gate Array), and a dedicated electrical circuit, such as an ASIC (Application Specific Integrated Circuit), which is a processor having a circuit configuration designed specifically for executing specific processing.

[0161] A single processing unit may be configured with one of these various processors, or may be configured with a combination of two or more processors of the same or different types (for example, a combination of multiple FPGAs or a combination of a CPU and an FPGA). Also, multiple processing units may be configured with a single processor. Examples of multiple processing units configured with a single processor include, first, a configuration in which one processor is configured with a combination of one or more CPUs and software, as typified by client and server computers, and this processor functions as multiple processing units. Second, a configuration in which a processor is used to realize the functions of an entire system including multiple processing units on a single IC (Integrated Circuit) chip, as typified by a System on Chip (SoC). In this way, the various processing units are configured with one or more of the above-mentioned various processors as a hardware structure.

[0162] Furthermore, more specifically, the hardware structure of these various processors can be an electric circuit that combines circuit elements such as semiconductor elements.

[0163] The semiconductor devices 200-1 and 200-2 may be any devices that have the function of applying multiple pulses of a first polarity to the resistance change element in a set sequence that puts the resistance change element into a low resistance state, and may also be interpreted as, for example, a semiconductor circuit or a measurement device.

[0164] In addition, the following supplementary notes are provided in relation to the above description. (Appendix 1) a variable resistance element whose resistance state changes depending on the direction of a voltage applied between two electrodes; a control circuit; The control circuit In a set sequence for setting the variable resistance element to a low resistance state, applying a plurality of pulses of a first polarity to the resistance change element; Among the plurality of pulses of the first polarity, M pulses from the Xth pulse to the X+M-1th pulse have a pulse height higher than that of the pulse applied immediately before. (Appendix 2) The control circuit In the set sequence, 2. The semiconductor device according to claim 1, wherein one or more pulses of a second polarity opposite to the first polarity are applied to the resistance change element. (Appendix 3) A readout circuit is provided, the control circuit comprises a converter and a discriminator; The control circuit In the set sequence, applying a read pulse to the resistance change element after at least one of the plurality of pulses of the first polarity or the one or more pulses of the second polarity; The readout circuit includes: outputting a read result as digital data according to a read current value flowing through the resistance change element; The converter comprises: receiving the readout result and a converter parameter as input, converting data based on the readout result and the converter parameter, and outputting the converted data to the classifier; The classifier is 3. The semiconductor device according to claim 2, wherein the converted data and a parameter for a discriminator are input, and whether the variable resistance element is a defective element prone to data retention failure is discriminated based on the converted data and the parameter for a discriminator. (Appendix 4) The transformer parameters and the classifier parameters are performing the set sequence on the resistance change element that was previously manufactured; Next, by storing the previously manufactured variable resistance element at a high temperature, a bit whose resistance state has changed from a low resistance state to a high resistance state is determined as a retention failure bit, The semiconductor device according to claim 3, wherein the bit is determined by machine learning using a data set consisting of the read result and correct data as to whether the bit is a retention defective bit as training data. (Appendix 5) The converter comprises: The read result is input as a variable, inputting, as parameters for the transformer, a sample mean vector of the variables and an inverse of a sample covariance matrix of the variables; Calculating a Mahalanobis distance based on the readout result and the converter parameters; 5. The semiconductor device according to claim 4, wherein the Mahalanobis distance is output as the conversion data. (Appendix 6) The classifier is Enter the threshold as a parameter for the classifier. 6. The semiconductor device according to claim 5, wherein, when the converted data is equal to or greater than the threshold value, the resistance change element is identified as a defective element that is prone to data retention failure. (Appendix 7) 5. The semiconductor device according to claim 4, wherein the classifier is configured by one or more of a support vector machine, a decision tree, or a neural network. (Appendix 8) 4. The semiconductor device according to claim 3, wherein the parameters for the converter or the parameters for the discriminator are supplied from an external interface of the semiconductor device or from a storage means within the semiconductor device. (Appendix 9) Among the plurality of pulses, assuming that the conductance of the resistance change element becomes G(N) due to the N-th set pulse S(N), assuming that the conductance of the resistance change element becomes G(N + 1) due to the (N + 1)-th set pulse S(N + 1), assuming that the conductance at which the power becomes maximum due to the (N + 1)-th set pulse S(N + 1) in the range where the conductance is from 0 to G(N + 1) is GMAX(N + 1), A semiconductor device according to any one of Appendices 1 to 8, satisfying GMAX(N + 1) < G(N). (Appendix 10) One or more of the pulses of the second polarity have a shorter pulse width than a normal reset pulse for setting the resistance change element to a high resistance state, or One or more of the pulses of the second polarity have a lower pulse height than a normal reset pulse for setting the resistance change element to a high resistance state, the semiconductor device according to Appendix 2. (Appendix 11) In a set sequence for setting a resistance change element, which changes its resistance state according to the direction of the voltage applied between two electrodes, to a low resistance state, a computer executes applying a plurality of pulses of a first polarity to the resistance change element, Among the plurality of pulses of the first polarity, M pulses from the X-th pulse to the (X + M - 1)-th pulse have a higher pulse height than the pulse applied immediately before, a method for controlling a resistance change element. (Appendix 12) The method for controlling a resistance change element according to Appendix 11, wherein the computer applies one or more pulses of a second polarity opposite to the first polarity to the resistance change element in the set sequence. (Appendix 13) The computer applies a read pulse to the resistance change element after at least one of the plurality of pulses of the first polarity or one or more of the pulses of the second polarity in the set sequence, a read circuit that outputs a read result as digital data according to a read current value flowing through the resistance change element; a converter receives the readout result and converter parameters, converts the data based on the readout result and the converter parameters, and outputs the converted data to a classifier; 13. The method for controlling a variable resistance element according to claim 12, wherein the converted data and a parameter for the discriminator are input to the discriminator, and the discriminator discriminates whether the variable resistance element is a defective element prone to data retention failure based on the converted data and the parameter for the discriminator. (Appendix 14) a setting sequence for setting a variable resistance element, the resistance state of which changes depending on the direction of a voltage applied between two electrodes, to a low resistance state, the setting sequence including applying a plurality of pulses of a first polarity to the variable resistance element; A control program for a resistance change element, wherein, of the plurality of pulses of the first polarity, M pulses from the Xth pulse to the X+M-1th pulse have a pulse height higher than that of the pulse applied immediately before. (Appendix 15) 15. The control program for a variable resistance element according to claim 14, which causes the computer to execute control to apply one or more pulses of a second polarity opposite to the first polarity to the variable resistance element in the set sequence. (Appendix 16) causing the computer to execute control to apply a read pulse to the resistance change element after at least one or more pulses of the plurality of pulses of the first polarity or one or more pulses of the second polarity in the set sequence; a read circuit that outputs a read result as digital data according to a read current value flowing through the resistance change element; a converter receives the readout result and converter parameters, converts the data based on the readout result and the converter parameters, and outputs the converted data to a classifier; 16. The control program according to claim 15, wherein the transformed data and a parameter for the discriminator are input to the discriminator, and the discriminator discriminates whether the variable resistance element is a defective element prone to data retention failure based on the transformed data and the parameter for the discriminator. [Explanation of symbols]

[0165] 11 CPU 11A pulse application section 11B Input / output section 12 ROM 13 RAM 14. Storage 17 External I / F 20 Bus 30, 30A, 30B Converter 31, 31A, 31B discriminator 41, 41-2 Control circuit 42 Row decoder 43 Column Decoder 43A Source-side column decoder 43B Sink side column decoder 44 Cell Array 45, 45-2 Readout circuit 50 memory cells 60 Recording Media 60A set sequence program 91 1st electrode 92 2nd electrode 93 Solid electrolyte 100 Resistance change element 101 1st terminal 102 2nd terminal 200-1, 200-2 Semiconductor device

Claims

1. a variable resistance element whose resistance state changes depending on the direction of a voltage applied between two electrodes; a control circuit; The control circuit In a set sequence for setting the variable resistance element to a low resistance state, applying a plurality of pulses of a first polarity to the resistance change element; Among the plurality of pulses of the first polarity, M pulses from an Xth pulse to an X+M-1th pulse have a pulse height higher than that of the pulse applied immediately before.

2. The control circuit In the set sequence, The semiconductor device according to claim 1 , wherein one or more pulses of a second polarity opposite to the first polarity are applied to the resistance change element.

3. A readout circuit is provided, the control circuit comprises a converter and a discriminator; The control circuit In the set sequence, applying a read pulse to the resistance change element after at least one of the plurality of pulses of the first polarity or the one or more pulses of the second polarity; The readout circuit includes: outputting a read result as digital data according to a read current value flowing through the resistance change element; The converter comprises: receiving the readout result and a converter parameter as input, converting data based on the readout result and the converter parameter, and outputting the converted data to the classifier; The classifier is 3. The semiconductor device according to claim 2, wherein the converted data and a parameter for a discriminator are input, and whether or not the variable resistance element is a defective element prone to data retention failure is discriminated based on the converted data and the parameter for the discriminator.

4. The transformer parameters and the classifier parameters are performing the set sequence on the resistance change element that was previously manufactured; Next, by storing the previously manufactured variable resistance element at a high temperature, a bit whose resistance state has changed from a low resistance state to a high resistance state is determined as a retention failure bit, The semiconductor device according to claim 3 , wherein the determination is made by machine learning using a data set made up of the read result and correct data as to whether or not the bit is a retention defective bit as training data.

5. The converter comprises: The read result is input as a variable, inputting, as parameters for the transformer, a sample mean vector of the variables and an inverse of a sample covariance matrix of the variables; Calculating a Mahalanobis distance based on the readout result and the converter parameters; 5. The semiconductor device according to claim 4, wherein the Mahalanobis distance is output as the conversion data.

6. The classifier is Enter the threshold as a parameter for the classifier. The semiconductor device according to claim 5 , wherein when the converted data is equal to or greater than the threshold value, the resistance change element is identified as a defective element that is prone to data retention failure.

7. The semiconductor device according to claim 4 , wherein the classifier is configured by one or more of a support vector machine, a decision tree, and a neural network.

8. 4. The semiconductor device according to claim 3, wherein the transformer parameters or the classifier parameters are supplied from an external interface of the semiconductor device or from a storage means within the semiconductor device.

9. It is assumed that the conductance of the variable resistance element becomes G(N) by an Nth (N is a natural number equal to or greater than 1) set pulse S(N) among the plurality of pulses, Assume that the conductance of the variable resistance element becomes G(N+1) by the N+1th set pulse S(N+1), If the conductance at which the power is maximum due to the N+1-th set pulse S(N+1) in the conductance range from 0 to G(N+1) is denoted by GMAX(N+1), then: The semiconductor device according to claim 1 , wherein GMAX(N+1)<G(N) is satisfied.

10. The one or more pulses of the second polarity have a pulse width shorter than a normal reset pulse for putting the variable resistance element into a high resistance state, or 3 . The semiconductor device according to claim 2 , wherein the one or more pulses of the second polarity have a pulse height lower than a normal reset pulse for putting the variable resistance element into a high resistance state.

11. a set sequence for setting a variable resistance element, the resistance state of which changes depending on the direction of a voltage applied between two electrodes, to a low resistance state, the set sequence comprising: applying a plurality of pulses of a first polarity to the variable resistance element; A method for controlling a resistance change element, wherein, of the plurality of pulses of the first polarity, M pulses from an Xth pulse (X is a natural number equal to or greater than 1) to an X+Mth pulse (M is a natural number equal to or greater than 1) - 1 have a pulse height higher than that of the pulse applied immediately before.

12. The method for controlling a resistance change element according to claim 11 , wherein the computer applies, in the set sequence, one or more pulses of a second polarity opposite to the first polarity to the resistance change element.

13. the computer applies a read pulse to the resistance change element after at least one or more pulses of the plurality of pulses of the first polarity or one or more pulses of the second polarity in the set sequence; a read circuit that outputs a read result as digital data according to a read current value flowing through the resistance change element; a converter receives the readout result and converter parameters, converts the data based on the readout result and the converter parameters, and outputs the converted data to a classifier; 13. The method for controlling a variable resistance element according to claim 12, further comprising inputting the converted data and a parameter for the discriminator to the discriminator, and discriminating whether or not the variable resistance element is a defective element prone to data retention failure based on the converted data and the parameter for the discriminator.

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